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KVM: MMU: mmu_convert_notrap helper
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
4d5c5d0f 33#include <linux/pci.h>
313a3dc7 34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
043405e1 43
313a3dc7 44#define MAX_IO_MSRS 256
a03490ed
CO		 45#define CR0_RESERVED_BITS \
46 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
47 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
48 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
49#define CR4_RESERVED_BITS \
50 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
51 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
52 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
53 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
54
55#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 56/* EFER defaults:
57 * - enable syscall per default because its emulated by KVM
58 * - enable LME and LMA per default on 64 bit KVM
59 */
60#ifdef CONFIG_X86_64
61static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
62#else
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
64#endif
313a3dc7 65
ba1389b7
AK		 66#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
67#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 68
674eea0f
AK		 69static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
70 struct kvm_cpuid_entry2 __user *entries);
71
97896d04 72struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 73EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 74
417bc304 75struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 76 { "pf_fixed", VCPU_STAT(pf_fixed) },
77 { "pf_guest", VCPU_STAT(pf_guest) },
78 { "tlb_flush", VCPU_STAT(tlb_flush) },
79 { "invlpg", VCPU_STAT(invlpg) },
80 { "exits", VCPU_STAT(exits) },
81 { "io_exits", VCPU_STAT(io_exits) },
82 { "mmio_exits", VCPU_STAT(mmio_exits) },
83 { "signal_exits", VCPU_STAT(signal_exits) },
84 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 85 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 86 { "halt_exits", VCPU_STAT(halt_exits) },
87 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 88 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 89 { "request_irq", VCPU_STAT(request_irq_exits) },
90 { "irq_exits", VCPU_STAT(irq_exits) },
91 { "host_state_reload", VCPU_STAT(host_state_reload) },
92 { "efer_reload", VCPU_STAT(efer_reload) },
93 { "fpu_reload", VCPU_STAT(fpu_reload) },
94 { "insn_emulation", VCPU_STAT(insn_emulation) },
95 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 96 { "irq_injections", VCPU_STAT(irq_injections) },
4cee5764
AK		 97 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
98 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
99 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
100 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
101 { "mmu_flooded", VM_STAT(mmu_flooded) },
102 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 103 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 104 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 105 { "largepages", VM_STAT(lpages) },
417bc304
HB		 106 { NULL }
107};
108
ee032c99 109static struct kvm_assigned_dev_kernel *kvm_find_assigned_dev(struct list_head *head,
4d5c5d0f
BAY		 110 int assigned_dev_id)
111{
112 struct list_head *ptr;
113 struct kvm_assigned_dev_kernel *match;
114
115 list_for_each(ptr, head) {
116 match = list_entry(ptr, struct kvm_assigned_dev_kernel, list);
117 if (match->assigned_dev_id == assigned_dev_id)
118 return match;
119 }
120 return NULL;
121}
122
123static void kvm_assigned_dev_interrupt_work_handler(struct work_struct *work)
124{
125 struct kvm_assigned_dev_kernel *assigned_dev;
126
127 assigned_dev = container_of(work, struct kvm_assigned_dev_kernel,
128 interrupt_work);
129
130 /* This is taken to safely inject irq inside the guest. When
131 * the interrupt injection (or the ioapic code) uses a
132 * finer-grained lock, update this
133 */
134 mutex_lock(&assigned_dev->kvm->lock);
135 kvm_set_irq(assigned_dev->kvm,
136 assigned_dev->guest_irq, 1);
137 mutex_unlock(&assigned_dev->kvm->lock);
138 kvm_put_kvm(assigned_dev->kvm);
139}
140
141/* FIXME: Implement the OR logic needed to make shared interrupts on
142 * this line behave properly
143 */
144static irqreturn_t kvm_assigned_dev_intr(int irq, void *dev_id)
145{
146 struct kvm_assigned_dev_kernel *assigned_dev =
147 (struct kvm_assigned_dev_kernel *) dev_id;
148
149 kvm_get_kvm(assigned_dev->kvm);
150 schedule_work(&assigned_dev->interrupt_work);
151 disable_irq_nosync(irq);
152 return IRQ_HANDLED;
153}
154
155/* Ack the irq line for an assigned device */
156static void kvm_assigned_dev_ack_irq(struct kvm_irq_ack_notifier *kian)
157{
158 struct kvm_assigned_dev_kernel *dev;
159
160 if (kian->gsi == -1)
161 return;
162
163 dev = container_of(kian, struct kvm_assigned_dev_kernel,
164 ack_notifier);
165 kvm_set_irq(dev->kvm, dev->guest_irq, 0);
166 enable_irq(dev->host_irq);
167}
168
bfadaded
AS		 169static void kvm_free_assigned_device(struct kvm *kvm,
170 struct kvm_assigned_dev_kernel
171 *assigned_dev)
172{
173 if (irqchip_in_kernel(kvm) && assigned_dev->irq_requested)
174 free_irq(assigned_dev->host_irq, (void *)assigned_dev);
175
176 kvm_unregister_irq_ack_notifier(kvm, &assigned_dev->ack_notifier);
177
178 if (cancel_work_sync(&assigned_dev->interrupt_work))
179 /* We had pending work. That means we will have to take
180 * care of kvm_put_kvm.
181 */
182 kvm_put_kvm(kvm);
183
184 pci_release_regions(assigned_dev->dev);
185 pci_disable_device(assigned_dev->dev);
186 pci_dev_put(assigned_dev->dev);
187
188 list_del(&assigned_dev->list);
189 kfree(assigned_dev);
190}
191
192static void kvm_free_all_assigned_devices(struct kvm *kvm)
193{
194 struct list_head *ptr, *ptr2;
195 struct kvm_assigned_dev_kernel *assigned_dev;
196
197 list_for_each_safe(ptr, ptr2, &kvm->arch.assigned_dev_head) {
198 assigned_dev = list_entry(ptr,
199 struct kvm_assigned_dev_kernel,
200 list);
201
202 kvm_free_assigned_device(kvm, assigned_dev);
203 }
204}
205
4d5c5d0f
BAY		 206static int kvm_vm_ioctl_assign_irq(struct kvm *kvm,
207 struct kvm_assigned_irq
208 *assigned_irq)
209{
210 int r = 0;
211 struct kvm_assigned_dev_kernel *match;
212
213 mutex_lock(&kvm->lock);
214
215 match = kvm_find_assigned_dev(&kvm->arch.assigned_dev_head,
216 assigned_irq->assigned_dev_id);
217 if (!match) {
218 mutex_unlock(&kvm->lock);
219 return -EINVAL;
220 }
221
222 if (match->irq_requested) {
223 match->guest_irq = assigned_irq->guest_irq;
224 match->ack_notifier.gsi = assigned_irq->guest_irq;
225 mutex_unlock(&kvm->lock);
226 return 0;
227 }
228
229 INIT_WORK(&match->interrupt_work,
230 kvm_assigned_dev_interrupt_work_handler);
231
232 if (irqchip_in_kernel(kvm)) {
6762b729 233 if (!capable(CAP_SYS_RAWIO)) {
bfadaded
AS		 234 r = -EPERM;
235 goto out_release;
6762b729
AS		 236 }
237
4d5c5d0f
BAY		 238 if (assigned_irq->host_irq)
239 match->host_irq = assigned_irq->host_irq;
240 else
241 match->host_irq = match->dev->irq;
242 match->guest_irq = assigned_irq->guest_irq;
243 match->ack_notifier.gsi = assigned_irq->guest_irq;
244 match->ack_notifier.irq_acked = kvm_assigned_dev_ack_irq;
245 kvm_register_irq_ack_notifier(kvm, &match->ack_notifier);
246
247 /* Even though this is PCI, we don't want to use shared
248 * interrupts. Sharing host devices with guest-assigned devices
249 * on the same interrupt line is not a happy situation: there
250 * are going to be long delays in accepting, acking, etc.
251 */
252 if (request_irq(match->host_irq, kvm_assigned_dev_intr, 0,
253 "kvm_assigned_device", (void *)match)) {
4d5c5d0f 254 r = -EIO;
bfadaded 255 goto out_release;
4d5c5d0f
BAY		 256 }
257 }
258
259 match->irq_requested = true;
4d5c5d0f
BAY		 260 mutex_unlock(&kvm->lock);
261 return r;
bfadaded
AS		 262out_release:
263 mutex_unlock(&kvm->lock);
264 kvm_free_assigned_device(kvm, match);
265 return r;
4d5c5d0f
BAY		 266}
267
268static int kvm_vm_ioctl_assign_device(struct kvm *kvm,
269 struct kvm_assigned_pci_dev *assigned_dev)
270{
271 int r = 0;
272 struct kvm_assigned_dev_kernel *match;
273 struct pci_dev *dev;
274
275 mutex_lock(&kvm->lock);
276
277 match = kvm_find_assigned_dev(&kvm->arch.assigned_dev_head,
278 assigned_dev->assigned_dev_id);
279 if (match) {
280 /* device already assigned */
281 r = -EINVAL;
282 goto out;
283 }
284
285 match = kzalloc(sizeof(struct kvm_assigned_dev_kernel), GFP_KERNEL);
286 if (match == NULL) {
287 printk(KERN_INFO "%s: Couldn't allocate memory\n",
288 __func__);
289 r = -ENOMEM;
290 goto out;
291 }
292 dev = pci_get_bus_and_slot(assigned_dev->busnr,
293 assigned_dev->devfn);
294 if (!dev) {
295 printk(KERN_INFO "%s: host device not found\n", __func__);
296 r = -EINVAL;
297 goto out_free;
298 }
299 if (pci_enable_device(dev)) {
300 printk(KERN_INFO "%s: Could not enable PCI device\n", __func__);
301 r = -EBUSY;
302 goto out_put;
303 }
304 r = pci_request_regions(dev, "kvm_assigned_device");
305 if (r) {
306 printk(KERN_INFO "%s: Could not get access to device regions\n",
307 __func__);
308 goto out_disable;
309 }
310 match->assigned_dev_id = assigned_dev->assigned_dev_id;
311 match->host_busnr = assigned_dev->busnr;
312 match->host_devfn = assigned_dev->devfn;
313 match->dev = dev;
314
315 match->kvm = kvm;
316
317 list_add(&match->list, &kvm->arch.assigned_dev_head);
318
62c476c7
BAY		 319 if (assigned_dev->flags & KVM_DEV_ASSIGN_ENABLE_IOMMU) {
320 r = kvm_iommu_map_guest(kvm, match);
321 if (r)
322 goto out_list_del;
323 }
324
4d5c5d0f
BAY		 325out:
326 mutex_unlock(&kvm->lock);
327 return r;
62c476c7
BAY		 328out_list_del:
329 list_del(&match->list);
330 pci_release_regions(dev);
4d5c5d0f
BAY		 331out_disable:
332 pci_disable_device(dev);
333out_put:
334 pci_dev_put(dev);
335out_free:
336 kfree(match);
337 mutex_unlock(&kvm->lock);
338 return r;
339}
340
5fb76f9b
CO		 341unsigned long segment_base(u16 selector)
342{
343 struct descriptor_table gdt;
a5f61300 344 struct desc_struct *d;
5fb76f9b
CO		 345 unsigned long table_base;
346 unsigned long v;
347
348 if (selector == 0)
349 return 0;
350
351 asm("sgdt %0" : "=m"(gdt));
352 table_base = gdt.base;
353
354 if (selector & 4) { /* from ldt */
355 u16 ldt_selector;
356
357 asm("sldt %0" : "=g"(ldt_selector));
358 table_base = segment_base(ldt_selector);
359 }
a5f61300
AK		 360 d = (struct desc_struct *)(table_base + (selector & ~7));
361 v = d->base0 | ((unsigned long)d->base1 << 16) |
362 ((unsigned long)d->base2 << 24);
5fb76f9b 363#ifdef CONFIG_X86_64
a5f61300
AK		 364 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
365 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 366#endif
367 return v;
368}
369EXPORT_SYMBOL_GPL(segment_base);
370
6866b83e
CO		 371u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
372{
373 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 374 return vcpu->arch.apic_base;
6866b83e 375 else
ad312c7c 376 return vcpu->arch.apic_base;
6866b83e
CO		 377}
378EXPORT_SYMBOL_GPL(kvm_get_apic_base);
379
380void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
381{
382 /* TODO: reserve bits check */
383 if (irqchip_in_kernel(vcpu->kvm))
384 kvm_lapic_set_base(vcpu, data);
385 else
ad312c7c 386 vcpu->arch.apic_base = data;
6866b83e
CO		 387}
388EXPORT_SYMBOL_GPL(kvm_set_apic_base);
389
298101da
AK		 390void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
391{
ad312c7c
ZX		 392 WARN_ON(vcpu->arch.exception.pending);
393 vcpu->arch.exception.pending = true;
394 vcpu->arch.exception.has_error_code = false;
395 vcpu->arch.exception.nr = nr;
298101da
AK		 396}
397EXPORT_SYMBOL_GPL(kvm_queue_exception);
398
c3c91fee
AK		 399void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
400 u32 error_code)
401{
402 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 403 if (vcpu->arch.exception.pending) {
404 if (vcpu->arch.exception.nr == PF_VECTOR) {
405 printk(KERN_DEBUG "kvm: inject_page_fault:"
406 " double fault 0x%lx\n", addr);
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
410 /* triple fault -> shutdown */
411 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
412 }
c3c91fee
AK		 413 return;
414 }
ad312c7c 415 vcpu->arch.cr2 = addr;
c3c91fee
AK		 416 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
417}
418
3419ffc8
SY		 419void kvm_inject_nmi(struct kvm_vcpu *vcpu)
420{
421 vcpu->arch.nmi_pending = 1;
422}
423EXPORT_SYMBOL_GPL(kvm_inject_nmi);
424
298101da
AK		 425void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
426{
ad312c7c
ZX		 427 WARN_ON(vcpu->arch.exception.pending);
428 vcpu->arch.exception.pending = true;
429 vcpu->arch.exception.has_error_code = true;
430 vcpu->arch.exception.nr = nr;
431 vcpu->arch.exception.error_code = error_code;
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
434
435static void __queue_exception(struct kvm_vcpu *vcpu)
436{
ad312c7c
ZX		 437 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
438 vcpu->arch.exception.has_error_code,
439 vcpu->arch.exception.error_code);
298101da
AK		 440}
441
a03490ed
CO		 442/*
443 * Load the pae pdptrs. Return true is they are all valid.
444 */
445int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
446{
447 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
448 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
449 int i;
450 int ret;
ad312c7c 451 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 452
a03490ed
CO		 453 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
454 offset * sizeof(u64), sizeof(pdpte));
455 if (ret < 0) {
456 ret = 0;
457 goto out;
458 }
459 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
460 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
461 ret = 0;
462 goto out;
463 }
464 }
465 ret = 1;
466
ad312c7c 467 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 468out:
a03490ed
CO		 469
470 return ret;
471}
cc4b6871 472EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 473
d835dfec
AK		 474static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475{
ad312c7c 476 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 477 bool changed = true;
478 int r;
479
480 if (is_long_mode(vcpu) || !is_pae(vcpu))
481 return false;
482
ad312c7c 483 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 484 if (r < 0)
485 goto out;
ad312c7c 486 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 487out:
d835dfec
AK		 488
489 return changed;
490}
491
2d3ad1f4 492void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 493{
494 if (cr0 & CR0_RESERVED_BITS) {
495 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 496 cr0, vcpu->arch.cr0);
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 498 return;
499 }
500
501 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
502 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 504 return;
505 }
506
507 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
508 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
509 "and a clear PE flag\n");
c1a5d4f9 510 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 511 return;
512 }
513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
ad312c7c 516 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
519 if (!is_pae(vcpu)) {
520 printk(KERN_DEBUG "set_cr0: #GP, start paging "
521 "in long mode while PAE is disabled\n");
c1a5d4f9 522 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 523 return;
524 }
525 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
526 if (cs_l) {
527 printk(KERN_DEBUG "set_cr0: #GP, start paging "
528 "in long mode while CS.L == 1\n");
c1a5d4f9 529 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 530 return;
531
532 }
533 } else
534#endif
ad312c7c 535 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 536 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
537 "reserved bits\n");
c1a5d4f9 538 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 539 return;
540 }
541
542 }
543
544 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 545 vcpu->arch.cr0 = cr0;
a03490ed 546
a03490ed 547 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 548 return;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
2d3ad1f4 554 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 555 KVMTRACE_1D(LMSW, vcpu,
556 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
557 handler);
a03490ed 558}
2d3ad1f4 559EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 560
2d3ad1f4 561void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 562{
563 if (cr4 & CR4_RESERVED_BITS) {
564 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 565 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 566 return;
567 }
568
569 if (is_long_mode(vcpu)) {
570 if (!(cr4 & X86_CR4_PAE)) {
571 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
572 "in long mode\n");
c1a5d4f9 573 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 574 return;
575 }
576 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 577 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 578 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 579 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 580 return;
581 }
582
583 if (cr4 & X86_CR4_VMXE) {
584 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 585 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 586 return;
587 }
588 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 589 vcpu->arch.cr4 = cr4;
a03490ed 590 kvm_mmu_reset_context(vcpu);
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 593
2d3ad1f4 594void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 595{
ad312c7c 596 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 597 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 598 kvm_mmu_flush_tlb(vcpu);
599 return;
600 }
601
a03490ed
CO		 602 if (is_long_mode(vcpu)) {
603 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
604 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 605 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 606 return;
607 }
608 } else {
609 if (is_pae(vcpu)) {
610 if (cr3 & CR3_PAE_RESERVED_BITS) {
611 printk(KERN_DEBUG
612 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 613 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 614 return;
615 }
616 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
617 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
618 "reserved bits\n");
c1a5d4f9 619 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 620 return;
621 }
622 }
623 /*
624 * We don't check reserved bits in nonpae mode, because
625 * this isn't enforced, and VMware depends on this.
626 */
627 }
628
a03490ed
CO		 629 /*
630 * Does the new cr3 value map to physical memory? (Note, we
631 * catch an invalid cr3 even in real-mode, because it would
632 * cause trouble later on when we turn on paging anyway.)
633 *
634 * A real CPU would silently accept an invalid cr3 and would
635 * attempt to use it - with largely undefined (and often hard
636 * to debug) behavior on the guest side.
637 */
638 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 639 kvm_inject_gp(vcpu, 0);
a03490ed 640 else {
ad312c7c
ZX		 641 vcpu->arch.cr3 = cr3;
642 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 643 }
a03490ed 644}
2d3ad1f4 645EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 646
2d3ad1f4 647void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 648{
649 if (cr8 & CR8_RESERVED_BITS) {
650 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 651 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 652 return;
653 }
654 if (irqchip_in_kernel(vcpu->kvm))
655 kvm_lapic_set_tpr(vcpu, cr8);
656 else
ad312c7c 657 vcpu->arch.cr8 = cr8;
a03490ed 658}
2d3ad1f4 659EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 660
2d3ad1f4 661unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 662{
663 if (irqchip_in_kernel(vcpu->kvm))
664 return kvm_lapic_get_cr8(vcpu);
665 else
ad312c7c 666 return vcpu->arch.cr8;
a03490ed 667}
2d3ad1f4 668EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 669
043405e1
CO		 670/*
671 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
672 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
673 *
674 * This list is modified at module load time to reflect the
675 * capabilities of the host cpu.
676 */
677static u32 msrs_to_save[] = {
678 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
679 MSR_K6_STAR,
680#ifdef CONFIG_X86_64
681 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
682#endif
18068523 683 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 684 MSR_IA32_PERF_STATUS,
043405e1
CO		 685};
686
687static unsigned num_msrs_to_save;
688
689static u32 emulated_msrs[] = {
690 MSR_IA32_MISC_ENABLE,
691};
692
15c4a640
CO		 693static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
694{
f2b4b7dd 695 if (efer & efer_reserved_bits) {
15c4a640
CO		 696 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
697 efer);
c1a5d4f9 698 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 699 return;
700 }
701
702 if (is_paging(vcpu)
ad312c7c 703 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 704 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 705 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 706 return;
707 }
708
709 kvm_x86_ops->set_efer(vcpu, efer);
710
711 efer &= ~EFER_LMA;
ad312c7c 712 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 713
ad312c7c 714 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 715}
716
f2b4b7dd
JR		 717void kvm_enable_efer_bits(u64 mask)
718{
719 efer_reserved_bits &= ~mask;
720}
721EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
722
723
15c4a640
CO		 724/*
725 * Writes msr value into into the appropriate "register".
726 * Returns 0 on success, non-0 otherwise.
727 * Assumes vcpu_load() was already called.
728 */
729int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
730{
731 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
732}
733
313a3dc7
CO		 734/*
735 * Adapt set_msr() to msr_io()'s calling convention
736 */
737static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
738{
739 return kvm_set_msr(vcpu, index, *data);
740}
741
18068523
GOC		 742static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
743{
744 static int version;
50d0a0f9
GH		 745 struct pvclock_wall_clock wc;
746 struct timespec now, sys, boot;
18068523
GOC		 747
748 if (!wall_clock)
749 return;
750
751 version++;
752
18068523
GOC		 753 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
754
50d0a0f9
GH		 755 /*
756 * The guest calculates current wall clock time by adding
757 * system time (updated by kvm_write_guest_time below) to the
758 * wall clock specified here. guest system time equals host
759 * system time for us, thus we must fill in host boot time here.
760 */
761 now = current_kernel_time();
762 ktime_get_ts(&sys);
763 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
764
765 wc.sec = boot.tv_sec;
766 wc.nsec = boot.tv_nsec;
767 wc.version = version;
18068523
GOC		 768
769 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
770
771 version++;
772 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 773}
774
50d0a0f9
GH		 775static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
776{
777 uint32_t quotient, remainder;
778
779 /* Don't try to replace with do_div(), this one calculates
780 * "(dividend << 32) / divisor" */
781 __asm__ ( "divl %4"
782 : "=a" (quotient), "=d" (remainder)
783 : "0" (0), "1" (dividend), "r" (divisor) );
784 return quotient;
785}
786
787static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
788{
789 uint64_t nsecs = 1000000000LL;
790 int32_t shift = 0;
791 uint64_t tps64;
792 uint32_t tps32;
793
794 tps64 = tsc_khz * 1000LL;
795 while (tps64 > nsecs*2) {
796 tps64 >>= 1;
797 shift--;
798 }
799
800 tps32 = (uint32_t)tps64;
801 while (tps32 <= (uint32_t)nsecs) {
802 tps32 <<= 1;
803 shift++;
804 }
805
806 hv_clock->tsc_shift = shift;
807 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
808
809 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
810 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
811 hv_clock->tsc_to_system_mul);
812}
813
18068523
GOC		 814static void kvm_write_guest_time(struct kvm_vcpu *v)
815{
816 struct timespec ts;
817 unsigned long flags;
818 struct kvm_vcpu_arch *vcpu = &v->arch;
819 void *shared_kaddr;
820
821 if ((!vcpu->time_page))
822 return;
823
50d0a0f9
GH		 824 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
825 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
826 vcpu->hv_clock_tsc_khz = tsc_khz;
827 }
828
18068523
GOC		 829 /* Keep irq disabled to prevent changes to the clock */
830 local_irq_save(flags);
831 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
832 &vcpu->hv_clock.tsc_timestamp);
833 ktime_get_ts(&ts);
834 local_irq_restore(flags);
835
836 /* With all the info we got, fill in the values */
837
838 vcpu->hv_clock.system_time = ts.tv_nsec +
839 (NSEC_PER_SEC * (u64)ts.tv_sec);
840 /*
841 * The interface expects us to write an even number signaling that the
842 * update is finished. Since the guest won't see the intermediate
50d0a0f9 843 * state, we just increase by 2 at the end.
18068523 844 */
50d0a0f9 845 vcpu->hv_clock.version += 2;
18068523
GOC		 846
847 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
848
849 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 850 sizeof(vcpu->hv_clock));
18068523
GOC		 851
852 kunmap_atomic(shared_kaddr, KM_USER0);
853
854 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
855}
856
9ba075a6
AK		 857static bool msr_mtrr_valid(unsigned msr)
858{
859 switch (msr) {
860 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
861 case MSR_MTRRfix64K_00000:
862 case MSR_MTRRfix16K_80000:
863 case MSR_MTRRfix16K_A0000:
864 case MSR_MTRRfix4K_C0000:
865 case MSR_MTRRfix4K_C8000:
866 case MSR_MTRRfix4K_D0000:
867 case MSR_MTRRfix4K_D8000:
868 case MSR_MTRRfix4K_E0000:
869 case MSR_MTRRfix4K_E8000:
870 case MSR_MTRRfix4K_F0000:
871 case MSR_MTRRfix4K_F8000:
872 case MSR_MTRRdefType:
873 case MSR_IA32_CR_PAT:
874 return true;
875 case 0x2f8:
876 return true;
877 }
878 return false;
879}
880
881static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
882{
883 if (!msr_mtrr_valid(msr))
884 return 1;
885
886 vcpu->arch.mtrr[msr - 0x200] = data;
887 return 0;
888}
15c4a640
CO		 889
890int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
891{
892 switch (msr) {
15c4a640
CO		 893 case MSR_EFER:
894 set_efer(vcpu, data);
895 break;
15c4a640
CO		 896 case MSR_IA32_MC0_STATUS:
897 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 898 __func__, data);
15c4a640
CO		 899 break;
900 case MSR_IA32_MCG_STATUS:
901 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 902 __func__, data);
15c4a640 903 break;
c7ac679c
JR		 904 case MSR_IA32_MCG_CTL:
905 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 906 __func__, data);
c7ac679c 907 break;
b5e2fec0
AG		 908 case MSR_IA32_DEBUGCTLMSR:
909 if (!data) {
910 /* We support the non-activated case already */
911 break;
912 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
913 /* Values other than LBR and BTF are vendor-specific,
914 thus reserved and should throw a #GP */
915 return 1;
916 }
917 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
918 __func__, data);
919 break;
15c4a640
CO		 920 case MSR_IA32_UCODE_REV:
921 case MSR_IA32_UCODE_WRITE:
15c4a640 922 break;
9ba075a6
AK		 923 case 0x200 ... 0x2ff:
924 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 925 case MSR_IA32_APICBASE:
926 kvm_set_apic_base(vcpu, data);
927 break;
928 case MSR_IA32_MISC_ENABLE:
ad312c7c 929 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 930 break;
18068523
GOC		 931 case MSR_KVM_WALL_CLOCK:
932 vcpu->kvm->arch.wall_clock = data;
933 kvm_write_wall_clock(vcpu->kvm, data);
934 break;
935 case MSR_KVM_SYSTEM_TIME: {
936 if (vcpu->arch.time_page) {
937 kvm_release_page_dirty(vcpu->arch.time_page);
938 vcpu->arch.time_page = NULL;
939 }
940
941 vcpu->arch.time = data;
942
943 /* we verify if the enable bit is set... */
944 if (!(data & 1))
945 break;
946
947 /* ...but clean it before doing the actual write */
948 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
949
18068523
GOC		 950 vcpu->arch.time_page =
951 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 952
953 if (is_error_page(vcpu->arch.time_page)) {
954 kvm_release_page_clean(vcpu->arch.time_page);
955 vcpu->arch.time_page = NULL;
956 }
957
958 kvm_write_guest_time(vcpu);
959 break;
960 }
15c4a640 961 default:
565f1fbd 962 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 963 return 1;
964 }
965 return 0;
966}
967EXPORT_SYMBOL_GPL(kvm_set_msr_common);
968
969
970/*
971 * Reads an msr value (of 'msr_index') into 'pdata'.
972 * Returns 0 on success, non-0 otherwise.
973 * Assumes vcpu_load() was already called.
974 */
975int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
976{
977 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
978}
979
9ba075a6
AK		 980static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
981{
982 if (!msr_mtrr_valid(msr))
983 return 1;
984
985 *pdata = vcpu->arch.mtrr[msr - 0x200];
986 return 0;
987}
988
15c4a640
CO		 989int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
990{
991 u64 data;
992
993 switch (msr) {
994 case 0xc0010010: /* SYSCFG */
995 case 0xc0010015: /* HWCR */
996 case MSR_IA32_PLATFORM_ID:
997 case MSR_IA32_P5_MC_ADDR:
998 case MSR_IA32_P5_MC_TYPE:
999 case MSR_IA32_MC0_CTL:
1000 case MSR_IA32_MCG_STATUS:
1001 case MSR_IA32_MCG_CAP:
c7ac679c 1002 case MSR_IA32_MCG_CTL:
15c4a640
CO		 1003 case MSR_IA32_MC0_MISC:
1004 case MSR_IA32_MC0_MISC+4:
1005 case MSR_IA32_MC0_MISC+8:
1006 case MSR_IA32_MC0_MISC+12:
1007 case MSR_IA32_MC0_MISC+16:
a89c1ad2 1008 case MSR_IA32_MC0_MISC+20:
15c4a640 1009 case MSR_IA32_UCODE_REV:
15c4a640 1010 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1011 case MSR_IA32_DEBUGCTLMSR:
1012 case MSR_IA32_LASTBRANCHFROMIP:
1013 case MSR_IA32_LASTBRANCHTOIP:
1014 case MSR_IA32_LASTINTFROMIP:
1015 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 1016 data = 0;
1017 break;
9ba075a6
AK		 1018 case MSR_MTRRcap:
1019 data = 0x500 | KVM_NR_VAR_MTRR;
1020 break;
1021 case 0x200 ... 0x2ff:
1022 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1023 case 0xcd: /* fsb frequency */
1024 data = 3;
1025 break;
1026 case MSR_IA32_APICBASE:
1027 data = kvm_get_apic_base(vcpu);
1028 break;
1029 case MSR_IA32_MISC_ENABLE:
ad312c7c 1030 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1031 break;
847f0ad8
AG		 1032 case MSR_IA32_PERF_STATUS:
1033 /* TSC increment by tick */
1034 data = 1000ULL;
1035 /* CPU multiplier */
1036 data |= (((uint64_t)4ULL) << 40);
1037 break;
15c4a640 1038 case MSR_EFER:
ad312c7c 1039 data = vcpu->arch.shadow_efer;
15c4a640 1040 break;
18068523
GOC		 1041 case MSR_KVM_WALL_CLOCK:
1042 data = vcpu->kvm->arch.wall_clock;
1043 break;
1044 case MSR_KVM_SYSTEM_TIME:
1045 data = vcpu->arch.time;
1046 break;
15c4a640
CO		 1047 default:
1048 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1049 return 1;
1050 }
1051 *pdata = data;
1052 return 0;
1053}
1054EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1055
313a3dc7
CO		 1056/*
1057 * Read or write a bunch of msrs. All parameters are kernel addresses.
1058 *
1059 * @return number of msrs set successfully.
1060 */
1061static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1062 struct kvm_msr_entry *entries,
1063 int (*do_msr)(struct kvm_vcpu *vcpu,
1064 unsigned index, u64 *data))
1065{
1066 int i;
1067
1068 vcpu_load(vcpu);
1069
3200f405 1070 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1071 for (i = 0; i < msrs->nmsrs; ++i)
1072 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1073 break;
3200f405 1074 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1075
1076 vcpu_put(vcpu);
1077
1078 return i;
1079}
1080
1081/*
1082 * Read or write a bunch of msrs. Parameters are user addresses.
1083 *
1084 * @return number of msrs set successfully.
1085 */
1086static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1087 int (*do_msr)(struct kvm_vcpu *vcpu,
1088 unsigned index, u64 *data),
1089 int writeback)
1090{
1091 struct kvm_msrs msrs;
1092 struct kvm_msr_entry *entries;
1093 int r, n;
1094 unsigned size;
1095
1096 r = -EFAULT;
1097 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1098 goto out;
1099
1100 r = -E2BIG;
1101 if (msrs.nmsrs >= MAX_IO_MSRS)
1102 goto out;
1103
1104 r = -ENOMEM;
1105 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1106 entries = vmalloc(size);
1107 if (!entries)
1108 goto out;
1109
1110 r = -EFAULT;
1111 if (copy_from_user(entries, user_msrs->entries, size))
1112 goto out_free;
1113
1114 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1115 if (r < 0)
1116 goto out_free;
1117
1118 r = -EFAULT;
1119 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1120 goto out_free;
1121
1122 r = n;
1123
1124out_free:
1125 vfree(entries);
1126out:
1127 return r;
1128}
1129
018d00d2
ZX		 1130int kvm_dev_ioctl_check_extension(long ext)
1131{
1132 int r;
1133
1134 switch (ext) {
1135 case KVM_CAP_IRQCHIP:
1136 case KVM_CAP_HLT:
1137 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1138 case KVM_CAP_USER_MEMORY:
1139 case KVM_CAP_SET_TSS_ADDR:
07716717 1140 case KVM_CAP_EXT_CPUID:
18068523 1141 case KVM_CAP_CLOCKSOURCE:
7837699f 1142 case KVM_CAP_PIT:
a28e4f5a 1143 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1144 case KVM_CAP_MP_STATE:
ed848624 1145 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 1146 r = 1;
1147 break;
542472b5
LV		 1148 case KVM_CAP_COALESCED_MMIO:
1149 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1150 break;
774ead3a
AK		 1151 case KVM_CAP_VAPIC:
1152 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1153 break;
f725230a
AK		 1154 case KVM_CAP_NR_VCPUS:
1155 r = KVM_MAX_VCPUS;
1156 break;
a988b910
AK		 1157 case KVM_CAP_NR_MEMSLOTS:
1158 r = KVM_MEMORY_SLOTS;
1159 break;
2f333bcb
MT		 1160 case KVM_CAP_PV_MMU:
1161 r = !tdp_enabled;
1162 break;
62c476c7
BAY		 1163 case KVM_CAP_IOMMU:
1164 r = intel_iommu_found();
1165 break;
018d00d2
ZX		 1166 default:
1167 r = 0;
1168 break;
1169 }
1170 return r;
1171
1172}
1173
043405e1
CO		 1174long kvm_arch_dev_ioctl(struct file *filp,
1175 unsigned int ioctl, unsigned long arg)
1176{
1177 void __user *argp = (void __user *)arg;
1178 long r;
1179
1180 switch (ioctl) {
1181 case KVM_GET_MSR_INDEX_LIST: {
1182 struct kvm_msr_list __user *user_msr_list = argp;
1183 struct kvm_msr_list msr_list;
1184 unsigned n;
1185
1186 r = -EFAULT;
1187 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1188 goto out;
1189 n = msr_list.nmsrs;
1190 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1191 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1192 goto out;
1193 r = -E2BIG;
1194 if (n < num_msrs_to_save)
1195 goto out;
1196 r = -EFAULT;
1197 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1198 num_msrs_to_save * sizeof(u32)))
1199 goto out;
1200 if (copy_to_user(user_msr_list->indices
1201 + num_msrs_to_save * sizeof(u32),
1202 &emulated_msrs,
1203 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1204 goto out;
1205 r = 0;
1206 break;
1207 }
674eea0f
AK		 1208 case KVM_GET_SUPPORTED_CPUID: {
1209 struct kvm_cpuid2 __user *cpuid_arg = argp;
1210 struct kvm_cpuid2 cpuid;
1211
1212 r = -EFAULT;
1213 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1214 goto out;
1215 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1216 cpuid_arg->entries);
1217 if (r)
1218 goto out;
1219
1220 r = -EFAULT;
1221 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1222 goto out;
1223 r = 0;
1224 break;
1225 }
043405e1
CO		 1226 default:
1227 r = -EINVAL;
1228 }
1229out:
1230 return r;
1231}
1232
313a3dc7
CO		 1233void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1234{
1235 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1236 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1237}
1238
1239void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1240{
1241 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1242 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1243}
1244
07716717 1245static int is_efer_nx(void)
313a3dc7
CO		 1246{
1247 u64 efer;
313a3dc7
CO		 1248
1249 rdmsrl(MSR_EFER, efer);
07716717
DK		 1250 return efer & EFER_NX;
1251}
1252
1253static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1254{
1255 int i;
1256 struct kvm_cpuid_entry2 *e, *entry;
1257
313a3dc7 1258 entry = NULL;
ad312c7c
ZX		 1259 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1260 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1261 if (e->function == 0x80000001) {
1262 entry = e;
1263 break;
1264 }
1265 }
07716717 1266 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1267 entry->edx &= ~(1 << 20);
1268 printk(KERN_INFO "kvm: guest NX capability removed\n");
1269 }
1270}
1271
07716717 1272/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1273static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1274 struct kvm_cpuid *cpuid,
1275 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1276{
1277 int r, i;
1278 struct kvm_cpuid_entry *cpuid_entries;
1279
1280 r = -E2BIG;
1281 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1282 goto out;
1283 r = -ENOMEM;
1284 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1285 if (!cpuid_entries)
1286 goto out;
1287 r = -EFAULT;
1288 if (copy_from_user(cpuid_entries, entries,
1289 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1290 goto out_free;
1291 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1292 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1293 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1294 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1295 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1296 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1297 vcpu->arch.cpuid_entries[i].index = 0;
1298 vcpu->arch.cpuid_entries[i].flags = 0;
1299 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1300 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1301 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1302 }
1303 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1304 cpuid_fix_nx_cap(vcpu);
1305 r = 0;
1306
1307out_free:
1308 vfree(cpuid_entries);
1309out:
1310 return r;
1311}
1312
1313static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1314 struct kvm_cpuid2 *cpuid,
1315 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1316{
1317 int r;
1318
1319 r = -E2BIG;
1320 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1321 goto out;
1322 r = -EFAULT;
ad312c7c 1323 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1324 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1325 goto out;
ad312c7c 1326 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1327 return 0;
1328
1329out:
1330 return r;
1331}
1332
07716717
DK		 1333static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1334 struct kvm_cpuid2 *cpuid,
1335 struct kvm_cpuid_entry2 __user *entries)
1336{
1337 int r;
1338
1339 r = -E2BIG;
ad312c7c 1340 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1341 goto out;
1342 r = -EFAULT;
ad312c7c
ZX		 1343 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1344 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1345 goto out;
1346 return 0;
1347
1348out:
ad312c7c 1349 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1350 return r;
1351}
1352
1353static inline u32 bit(int bitno)
1354{
1355 return 1 << (bitno & 31);
1356}
1357
1358static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1359 u32 index)
1360{
1361 entry->function = function;
1362 entry->index = index;
1363 cpuid_count(entry->function, entry->index,
1364 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1365 entry->flags = 0;
1366}
1367
1368static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1369 u32 index, int *nent, int maxnent)
1370{
1371 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1372 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1373 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1374 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1375 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1376 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1377 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1378 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1379 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1380 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1381 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1382 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1383 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1384 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1385 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1386 bit(X86_FEATURE_PGE) |
1387 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1388 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1389 bit(X86_FEATURE_SYSCALL) |
1390 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1391#ifdef CONFIG_X86_64
1392 bit(X86_FEATURE_LM) |
1393#endif
1394 bit(X86_FEATURE_MMXEXT) |
1395 bit(X86_FEATURE_3DNOWEXT) |
1396 bit(X86_FEATURE_3DNOW);
1397 const u32 kvm_supported_word3_x86_features =
1398 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1399 const u32 kvm_supported_word6_x86_features =
1400 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1401
1402 /* all func 2 cpuid_count() should be called on the same cpu */
1403 get_cpu();
1404 do_cpuid_1_ent(entry, function, index);
1405 ++*nent;
1406
1407 switch (function) {
1408 case 0:
1409 entry->eax = min(entry->eax, (u32)0xb);
1410 break;
1411 case 1:
1412 entry->edx &= kvm_supported_word0_x86_features;
1413 entry->ecx &= kvm_supported_word3_x86_features;
1414 break;
1415 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1416 * may return different values. This forces us to get_cpu() before
1417 * issuing the first command, and also to emulate this annoying behavior
1418 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1419 case 2: {
1420 int t, times = entry->eax & 0xff;
1421
1422 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1423 for (t = 1; t < times && *nent < maxnent; ++t) {
1424 do_cpuid_1_ent(&entry[t], function, 0);
1425 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1426 ++*nent;
1427 }
1428 break;
1429 }
1430 /* function 4 and 0xb have additional index. */
1431 case 4: {
14af3f3c 1432 int i, cache_type;
07716717
DK		 1433
1434 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1435 /* read more entries until cache_type is zero */
14af3f3c
HH		 1436 for (i = 1; *nent < maxnent; ++i) {
1437 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1438 if (!cache_type)
1439 break;
14af3f3c
HH		 1440 do_cpuid_1_ent(&entry[i], function, i);
1441 entry[i].flags |=
07716717
DK		 1442 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1443 ++*nent;
1444 }
1445 break;
1446 }
1447 case 0xb: {
14af3f3c 1448 int i, level_type;
07716717
DK		 1449
1450 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1451 /* read more entries until level_type is zero */
14af3f3c
HH		 1452 for (i = 1; *nent < maxnent; ++i) {
1453 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1454 if (!level_type)
1455 break;
14af3f3c
HH		 1456 do_cpuid_1_ent(&entry[i], function, i);
1457 entry[i].flags |=
07716717
DK		 1458 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1459 ++*nent;
1460 }
1461 break;
1462 }
1463 case 0x80000000:
1464 entry->eax = min(entry->eax, 0x8000001a);
1465 break;
1466 case 0x80000001:
1467 entry->edx &= kvm_supported_word1_x86_features;
1468 entry->ecx &= kvm_supported_word6_x86_features;
1469 break;
1470 }
1471 put_cpu();
1472}
1473
674eea0f 1474static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1475 struct kvm_cpuid_entry2 __user *entries)
1476{
1477 struct kvm_cpuid_entry2 *cpuid_entries;
1478 int limit, nent = 0, r = -E2BIG;
1479 u32 func;
1480
1481 if (cpuid->nent < 1)
1482 goto out;
1483 r = -ENOMEM;
1484 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1485 if (!cpuid_entries)
1486 goto out;
1487
1488 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1489 limit = cpuid_entries[0].eax;
1490 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1491 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1492 &nent, cpuid->nent);
1493 r = -E2BIG;
1494 if (nent >= cpuid->nent)
1495 goto out_free;
1496
1497 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1498 limit = cpuid_entries[nent - 1].eax;
1499 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1500 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1501 &nent, cpuid->nent);
1502 r = -EFAULT;
1503 if (copy_to_user(entries, cpuid_entries,
1504 nent * sizeof(struct kvm_cpuid_entry2)))
1505 goto out_free;
1506 cpuid->nent = nent;
1507 r = 0;
1508
1509out_free:
1510 vfree(cpuid_entries);
1511out:
1512 return r;
1513}
1514
313a3dc7
CO		 1515static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1516 struct kvm_lapic_state *s)
1517{
1518 vcpu_load(vcpu);
ad312c7c 1519 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1520 vcpu_put(vcpu);
1521
1522 return 0;
1523}
1524
1525static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1526 struct kvm_lapic_state *s)
1527{
1528 vcpu_load(vcpu);
ad312c7c 1529 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1530 kvm_apic_post_state_restore(vcpu);
1531 vcpu_put(vcpu);
1532
1533 return 0;
1534}
1535
f77bc6a4
ZX		 1536static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1537 struct kvm_interrupt *irq)
1538{
1539 if (irq->irq < 0 || irq->irq >= 256)
1540 return -EINVAL;
1541 if (irqchip_in_kernel(vcpu->kvm))
1542 return -ENXIO;
1543 vcpu_load(vcpu);
1544
ad312c7c
ZX		 1545 set_bit(irq->irq, vcpu->arch.irq_pending);
1546 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1547
1548 vcpu_put(vcpu);
1549
1550 return 0;
1551}
1552
b209749f
AK		 1553static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1554 struct kvm_tpr_access_ctl *tac)
1555{
1556 if (tac->flags)
1557 return -EINVAL;
1558 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1559 return 0;
1560}
1561
313a3dc7
CO		 1562long kvm_arch_vcpu_ioctl(struct file *filp,
1563 unsigned int ioctl, unsigned long arg)
1564{
1565 struct kvm_vcpu *vcpu = filp->private_data;
1566 void __user *argp = (void __user *)arg;
1567 int r;
b772ff36 1568 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1569
1570 switch (ioctl) {
1571 case KVM_GET_LAPIC: {
b772ff36 1572 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1573
b772ff36
DH		 1574 r = -ENOMEM;
1575 if (!lapic)
1576 goto out;
1577 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1578 if (r)
1579 goto out;
1580 r = -EFAULT;
b772ff36 1581 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1582 goto out;
1583 r = 0;
1584 break;
1585 }
1586 case KVM_SET_LAPIC: {
b772ff36
DH		 1587 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1588 r = -ENOMEM;
1589 if (!lapic)
1590 goto out;
313a3dc7 1591 r = -EFAULT;
b772ff36 1592 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1593 goto out;
b772ff36 1594 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1595 if (r)
1596 goto out;
1597 r = 0;
1598 break;
1599 }
f77bc6a4
ZX		 1600 case KVM_INTERRUPT: {
1601 struct kvm_interrupt irq;
1602
1603 r = -EFAULT;
1604 if (copy_from_user(&irq, argp, sizeof irq))
1605 goto out;
1606 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1607 if (r)
1608 goto out;
1609 r = 0;
1610 break;
1611 }
313a3dc7
CO		 1612 case KVM_SET_CPUID: {
1613 struct kvm_cpuid __user *cpuid_arg = argp;
1614 struct kvm_cpuid cpuid;
1615
1616 r = -EFAULT;
1617 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1618 goto out;
1619 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1620 if (r)
1621 goto out;
1622 break;
1623 }
07716717
DK		 1624 case KVM_SET_CPUID2: {
1625 struct kvm_cpuid2 __user *cpuid_arg = argp;
1626 struct kvm_cpuid2 cpuid;
1627
1628 r = -EFAULT;
1629 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1630 goto out;
1631 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1632 cpuid_arg->entries);
1633 if (r)
1634 goto out;
1635 break;
1636 }
1637 case KVM_GET_CPUID2: {
1638 struct kvm_cpuid2 __user *cpuid_arg = argp;
1639 struct kvm_cpuid2 cpuid;
1640
1641 r = -EFAULT;
1642 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1643 goto out;
1644 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1645 cpuid_arg->entries);
1646 if (r)
1647 goto out;
1648 r = -EFAULT;
1649 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1650 goto out;
1651 r = 0;
1652 break;
1653 }
313a3dc7
CO		 1654 case KVM_GET_MSRS:
1655 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1656 break;
1657 case KVM_SET_MSRS:
1658 r = msr_io(vcpu, argp, do_set_msr, 0);
1659 break;
b209749f
AK		 1660 case KVM_TPR_ACCESS_REPORTING: {
1661 struct kvm_tpr_access_ctl tac;
1662
1663 r = -EFAULT;
1664 if (copy_from_user(&tac, argp, sizeof tac))
1665 goto out;
1666 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1667 if (r)
1668 goto out;
1669 r = -EFAULT;
1670 if (copy_to_user(argp, &tac, sizeof tac))
1671 goto out;
1672 r = 0;
1673 break;
1674 };
b93463aa
AK		 1675 case KVM_SET_VAPIC_ADDR: {
1676 struct kvm_vapic_addr va;
1677
1678 r = -EINVAL;
1679 if (!irqchip_in_kernel(vcpu->kvm))
1680 goto out;
1681 r = -EFAULT;
1682 if (copy_from_user(&va, argp, sizeof va))
1683 goto out;
1684 r = 0;
1685 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1686 break;
1687 }
313a3dc7
CO		 1688 default:
1689 r = -EINVAL;
1690 }
1691out:
b772ff36
DH		 1692 if (lapic)
1693 kfree(lapic);
313a3dc7
CO		 1694 return r;
1695}
1696
1fe779f8
CO		 1697static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1698{
1699 int ret;
1700
1701 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1702 return -1;
1703 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1704 return ret;
1705}
1706
1707static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1708 u32 kvm_nr_mmu_pages)
1709{
1710 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1711 return -EINVAL;
1712
72dc67a6 1713 down_write(&kvm->slots_lock);
1fe779f8
CO		 1714
1715 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1716 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1717
72dc67a6 1718 up_write(&kvm->slots_lock);
1fe779f8
CO		 1719 return 0;
1720}
1721
1722static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1723{
f05e70ac 1724 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1725}
1726
e9f85cde
ZX		 1727gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1728{
1729 int i;
1730 struct kvm_mem_alias *alias;
1731
d69fb81f
ZX		 1732 for (i = 0; i < kvm->arch.naliases; ++i) {
1733 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1734 if (gfn >= alias->base_gfn
1735 && gfn < alias->base_gfn + alias->npages)
1736 return alias->target_gfn + gfn - alias->base_gfn;
1737 }
1738 return gfn;
1739}
1740
1fe779f8
CO		 1741/*
1742 * Set a new alias region. Aliases map a portion of physical memory into
1743 * another portion. This is useful for memory windows, for example the PC
1744 * VGA region.
1745 */
1746static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1747 struct kvm_memory_alias *alias)
1748{
1749 int r, n;
1750 struct kvm_mem_alias *p;
1751
1752 r = -EINVAL;
1753 /* General sanity checks */
1754 if (alias->memory_size & (PAGE_SIZE - 1))
1755 goto out;
1756 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1757 goto out;
1758 if (alias->slot >= KVM_ALIAS_SLOTS)
1759 goto out;
1760 if (alias->guest_phys_addr + alias->memory_size
1761 < alias->guest_phys_addr)
1762 goto out;
1763 if (alias->target_phys_addr + alias->memory_size
1764 < alias->target_phys_addr)
1765 goto out;
1766
72dc67a6 1767 down_write(&kvm->slots_lock);
a1708ce8 1768 spin_lock(&kvm->mmu_lock);
1fe779f8 1769
d69fb81f 1770 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1771 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1772 p->npages = alias->memory_size >> PAGE_SHIFT;
1773 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1774
1775 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1776 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1777 break;
d69fb81f 1778 kvm->arch.naliases = n;
1fe779f8 1779
a1708ce8 1780 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1781 kvm_mmu_zap_all(kvm);
1782
72dc67a6 1783 up_write(&kvm->slots_lock);
1fe779f8
CO		 1784
1785 return 0;
1786
1787out:
1788 return r;
1789}
1790
1791static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1792{
1793 int r;
1794
1795 r = 0;
1796 switch (chip->chip_id) {
1797 case KVM_IRQCHIP_PIC_MASTER:
1798 memcpy(&chip->chip.pic,
1799 &pic_irqchip(kvm)->pics[0],
1800 sizeof(struct kvm_pic_state));
1801 break;
1802 case KVM_IRQCHIP_PIC_SLAVE:
1803 memcpy(&chip->chip.pic,
1804 &pic_irqchip(kvm)->pics[1],
1805 sizeof(struct kvm_pic_state));
1806 break;
1807 case KVM_IRQCHIP_IOAPIC:
1808 memcpy(&chip->chip.ioapic,
1809 ioapic_irqchip(kvm),
1810 sizeof(struct kvm_ioapic_state));
1811 break;
1812 default:
1813 r = -EINVAL;
1814 break;
1815 }
1816 return r;
1817}
1818
1819static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1820{
1821 int r;
1822
1823 r = 0;
1824 switch (chip->chip_id) {
1825 case KVM_IRQCHIP_PIC_MASTER:
1826 memcpy(&pic_irqchip(kvm)->pics[0],
1827 &chip->chip.pic,
1828 sizeof(struct kvm_pic_state));
1829 break;
1830 case KVM_IRQCHIP_PIC_SLAVE:
1831 memcpy(&pic_irqchip(kvm)->pics[1],
1832 &chip->chip.pic,
1833 sizeof(struct kvm_pic_state));
1834 break;
1835 case KVM_IRQCHIP_IOAPIC:
1836 memcpy(ioapic_irqchip(kvm),
1837 &chip->chip.ioapic,
1838 sizeof(struct kvm_ioapic_state));
1839 break;
1840 default:
1841 r = -EINVAL;
1842 break;
1843 }
1844 kvm_pic_update_irq(pic_irqchip(kvm));
1845 return r;
1846}
1847
e0f63cb9
SY		 1848static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1849{
1850 int r = 0;
1851
1852 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1853 return r;
1854}
1855
1856static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1857{
1858 int r = 0;
1859
1860 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1861 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1862 return r;
1863}
1864
5bb064dc
ZX		 1865/*
1866 * Get (and clear) the dirty memory log for a memory slot.
1867 */
1868int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1869 struct kvm_dirty_log *log)
1870{
1871 int r;
1872 int n;
1873 struct kvm_memory_slot *memslot;
1874 int is_dirty = 0;
1875
72dc67a6 1876 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1877
1878 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1879 if (r)
1880 goto out;
1881
1882 /* If nothing is dirty, don't bother messing with page tables. */
1883 if (is_dirty) {
1884 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1885 kvm_flush_remote_tlbs(kvm);
1886 memslot = &kvm->memslots[log->slot];
1887 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1888 memset(memslot->dirty_bitmap, 0, n);
1889 }
1890 r = 0;
1891out:
72dc67a6 1892 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1893 return r;
1894}
1895
1fe779f8
CO		 1896long kvm_arch_vm_ioctl(struct file *filp,
1897 unsigned int ioctl, unsigned long arg)
1898{
1899 struct kvm *kvm = filp->private_data;
1900 void __user *argp = (void __user *)arg;
1901 int r = -EINVAL;
f0d66275
DH		 1902 /*
1903 * This union makes it completely explicit to gcc-3.x
1904 * that these two variables' stack usage should be
1905 * combined, not added together.
1906 */
1907 union {
1908 struct kvm_pit_state ps;
1909 struct kvm_memory_alias alias;
1910 } u;
1fe779f8
CO		 1911
1912 switch (ioctl) {
1913 case KVM_SET_TSS_ADDR:
1914 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1915 if (r < 0)
1916 goto out;
1917 break;
1918 case KVM_SET_MEMORY_REGION: {
1919 struct kvm_memory_region kvm_mem;
1920 struct kvm_userspace_memory_region kvm_userspace_mem;
1921
1922 r = -EFAULT;
1923 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1924 goto out;
1925 kvm_userspace_mem.slot = kvm_mem.slot;
1926 kvm_userspace_mem.flags = kvm_mem.flags;
1927 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1928 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1929 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1930 if (r)
1931 goto out;
1932 break;
1933 }
1934 case KVM_SET_NR_MMU_PAGES:
1935 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1936 if (r)
1937 goto out;
1938 break;
1939 case KVM_GET_NR_MMU_PAGES:
1940 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1941 break;
f0d66275 1942 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1943 r = -EFAULT;
f0d66275 1944 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1945 goto out;
f0d66275 1946 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1947 if (r)
1948 goto out;
1949 break;
1fe779f8
CO		 1950 case KVM_CREATE_IRQCHIP:
1951 r = -ENOMEM;
d7deeeb0
ZX		 1952 kvm->arch.vpic = kvm_create_pic(kvm);
1953 if (kvm->arch.vpic) {
1fe779f8
CO		 1954 r = kvm_ioapic_init(kvm);
1955 if (r) {
d7deeeb0
ZX		 1956 kfree(kvm->arch.vpic);
1957 kvm->arch.vpic = NULL;
1fe779f8
CO		 1958 goto out;
1959 }
1960 } else
1961 goto out;
1962 break;
7837699f
SY		 1963 case KVM_CREATE_PIT:
1964 r = -ENOMEM;
1965 kvm->arch.vpit = kvm_create_pit(kvm);
1966 if (kvm->arch.vpit)
1967 r = 0;
1968 break;
1fe779f8
CO		 1969 case KVM_IRQ_LINE: {
1970 struct kvm_irq_level irq_event;
1971
1972 r = -EFAULT;
1973 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1974 goto out;
1975 if (irqchip_in_kernel(kvm)) {
1976 mutex_lock(&kvm->lock);
29c8fa32 1977 kvm_set_irq(kvm, irq_event.irq, irq_event.level);
1fe779f8
CO		 1978 mutex_unlock(&kvm->lock);
1979 r = 0;
1980 }
1981 break;
1982 }
1983 case KVM_GET_IRQCHIP: {
1984 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1985 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1986
f0d66275
DH		 1987 r = -ENOMEM;
1988 if (!chip)
1fe779f8 1989 goto out;
f0d66275
DH		 1990 r = -EFAULT;
1991 if (copy_from_user(chip, argp, sizeof *chip))
1992 goto get_irqchip_out;
1fe779f8
CO		 1993 r = -ENXIO;
1994 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1995 goto get_irqchip_out;
1996 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1997 if (r)
f0d66275 1998 goto get_irqchip_out;
1fe779f8 1999 r = -EFAULT;
f0d66275
DH		 2000 if (copy_to_user(argp, chip, sizeof *chip))
2001 goto get_irqchip_out;
1fe779f8 2002 r = 0;
f0d66275
DH		 2003 get_irqchip_out:
2004 kfree(chip);
2005 if (r)
2006 goto out;
1fe779f8
CO		 2007 break;
2008 }
2009 case KVM_SET_IRQCHIP: {
2010 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2011 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2012
f0d66275
DH		 2013 r = -ENOMEM;
2014 if (!chip)
1fe779f8 2015 goto out;
f0d66275
DH		 2016 r = -EFAULT;
2017 if (copy_from_user(chip, argp, sizeof *chip))
2018 goto set_irqchip_out;
1fe779f8
CO		 2019 r = -ENXIO;
2020 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2021 goto set_irqchip_out;
2022 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2023 if (r)
f0d66275 2024 goto set_irqchip_out;
1fe779f8 2025 r = 0;
f0d66275
DH		 2026 set_irqchip_out:
2027 kfree(chip);
2028 if (r)
2029 goto out;
1fe779f8
CO		 2030 break;
2031 }
4d5c5d0f
BAY		 2032 case KVM_ASSIGN_PCI_DEVICE: {
2033 struct kvm_assigned_pci_dev assigned_dev;
2034
2035 r = -EFAULT;
2036 if (copy_from_user(&assigned_dev, argp, sizeof assigned_dev))
2037 goto out;
2038 r = kvm_vm_ioctl_assign_device(kvm, &assigned_dev);
2039 if (r)
2040 goto out;
2041 break;
2042 }
2043 case KVM_ASSIGN_IRQ: {
2044 struct kvm_assigned_irq assigned_irq;
2045
2046 r = -EFAULT;
2047 if (copy_from_user(&assigned_irq, argp, sizeof assigned_irq))
2048 goto out;
2049 r = kvm_vm_ioctl_assign_irq(kvm, &assigned_irq);
2050 if (r)
2051 goto out;
2052 break;
2053 }
e0f63cb9 2054 case KVM_GET_PIT: {
e0f63cb9 2055 r = -EFAULT;
f0d66275 2056 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2057 goto out;
2058 r = -ENXIO;
2059 if (!kvm->arch.vpit)
2060 goto out;
f0d66275 2061 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2062 if (r)
2063 goto out;
2064 r = -EFAULT;
f0d66275 2065 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2066 goto out;
2067 r = 0;
2068 break;
2069 }
2070 case KVM_SET_PIT: {
e0f63cb9 2071 r = -EFAULT;
f0d66275 2072 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2073 goto out;
2074 r = -ENXIO;
2075 if (!kvm->arch.vpit)
2076 goto out;
f0d66275 2077 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2078 if (r)
2079 goto out;
2080 r = 0;
2081 break;
2082 }
1fe779f8
CO		 2083 default:
2084 ;
2085 }
2086out:
2087 return r;
2088}
2089
a16b043c 2090static void kvm_init_msr_list(void)
043405e1
CO		 2091{
2092 u32 dummy[2];
2093 unsigned i, j;
2094
2095 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2096 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2097 continue;
2098 if (j < i)
2099 msrs_to_save[j] = msrs_to_save[i];
2100 j++;
2101 }
2102 num_msrs_to_save = j;
2103}
2104
bbd9b64e
CO		 2105/*
2106 * Only apic need an MMIO device hook, so shortcut now..
2107 */
2108static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2109 gpa_t addr, int len,
2110 int is_write)
bbd9b64e
CO		 2111{
2112 struct kvm_io_device *dev;
2113
ad312c7c
ZX		 2114 if (vcpu->arch.apic) {
2115 dev = &vcpu->arch.apic->dev;
92760499 2116 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2117 return dev;
2118 }
2119 return NULL;
2120}
2121
2122
2123static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2124 gpa_t addr, int len,
2125 int is_write)
bbd9b64e
CO		 2126{
2127 struct kvm_io_device *dev;
2128
92760499 2129 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2130 if (dev == NULL)
92760499
LV		 2131 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2132 is_write);
bbd9b64e
CO		 2133 return dev;
2134}
2135
2136int emulator_read_std(unsigned long addr,
2137 void *val,
2138 unsigned int bytes,
2139 struct kvm_vcpu *vcpu)
2140{
2141 void *data = val;
10589a46 2142 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2143
2144 while (bytes) {
ad312c7c 2145 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2146 unsigned offset = addr & (PAGE_SIZE-1);
2147 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
2148 int ret;
2149
10589a46
MT		 2150 if (gpa == UNMAPPED_GVA) {
2151 r = X86EMUL_PROPAGATE_FAULT;
2152 goto out;
2153 }
bbd9b64e 2154 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 2155 if (ret < 0) {
2156 r = X86EMUL_UNHANDLEABLE;
2157 goto out;
2158 }
bbd9b64e
CO		 2159
2160 bytes -= tocopy;
2161 data += tocopy;
2162 addr += tocopy;
2163 }
10589a46 2164out:
10589a46 2165 return r;
bbd9b64e
CO		 2166}
2167EXPORT_SYMBOL_GPL(emulator_read_std);
2168
bbd9b64e
CO		 2169static int emulator_read_emulated(unsigned long addr,
2170 void *val,
2171 unsigned int bytes,
2172 struct kvm_vcpu *vcpu)
2173{
2174 struct kvm_io_device *mmio_dev;
2175 gpa_t gpa;
2176
2177 if (vcpu->mmio_read_completed) {
2178 memcpy(val, vcpu->mmio_data, bytes);
2179 vcpu->mmio_read_completed = 0;
2180 return X86EMUL_CONTINUE;
2181 }
2182
ad312c7c 2183 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2184
2185 /* For APIC access vmexit */
2186 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2187 goto mmio;
2188
2189 if (emulator_read_std(addr, val, bytes, vcpu)
2190 == X86EMUL_CONTINUE)
2191 return X86EMUL_CONTINUE;
2192 if (gpa == UNMAPPED_GVA)
2193 return X86EMUL_PROPAGATE_FAULT;
2194
2195mmio:
2196 /*
2197 * Is this MMIO handled locally?
2198 */
10589a46 2199 mutex_lock(&vcpu->kvm->lock);
92760499 2200 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2201 if (mmio_dev) {
2202 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2203 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2204 return X86EMUL_CONTINUE;
2205 }
10589a46 2206 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2207
2208 vcpu->mmio_needed = 1;
2209 vcpu->mmio_phys_addr = gpa;
2210 vcpu->mmio_size = bytes;
2211 vcpu->mmio_is_write = 0;
2212
2213 return X86EMUL_UNHANDLEABLE;
2214}
2215
3200f405 2216int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2217 const void *val, int bytes)
bbd9b64e
CO		 2218{
2219 int ret;
2220
2221 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2222 if (ret < 0)
bbd9b64e
CO		 2223 return 0;
2224 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
2225 return 1;
2226}
2227
2228static int emulator_write_emulated_onepage(unsigned long addr,
2229 const void *val,
2230 unsigned int bytes,
2231 struct kvm_vcpu *vcpu)
2232{
2233 struct kvm_io_device *mmio_dev;
10589a46
MT		 2234 gpa_t gpa;
2235
10589a46 2236 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2237
2238 if (gpa == UNMAPPED_GVA) {
c3c91fee 2239 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2240 return X86EMUL_PROPAGATE_FAULT;
2241 }
2242
2243 /* For APIC access vmexit */
2244 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2245 goto mmio;
2246
2247 if (emulator_write_phys(vcpu, gpa, val, bytes))
2248 return X86EMUL_CONTINUE;
2249
2250mmio:
2251 /*
2252 * Is this MMIO handled locally?
2253 */
10589a46 2254 mutex_lock(&vcpu->kvm->lock);
92760499 2255 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2256 if (mmio_dev) {
2257 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2258 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2259 return X86EMUL_CONTINUE;
2260 }
10589a46 2261 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2262
2263 vcpu->mmio_needed = 1;
2264 vcpu->mmio_phys_addr = gpa;
2265 vcpu->mmio_size = bytes;
2266 vcpu->mmio_is_write = 1;
2267 memcpy(vcpu->mmio_data, val, bytes);
2268
2269 return X86EMUL_CONTINUE;
2270}
2271
2272int emulator_write_emulated(unsigned long addr,
2273 const void *val,
2274 unsigned int bytes,
2275 struct kvm_vcpu *vcpu)
2276{
2277 /* Crossing a page boundary? */
2278 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2279 int rc, now;
2280
2281 now = -addr & ~PAGE_MASK;
2282 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2283 if (rc != X86EMUL_CONTINUE)
2284 return rc;
2285 addr += now;
2286 val += now;
2287 bytes -= now;
2288 }
2289 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2290}
2291EXPORT_SYMBOL_GPL(emulator_write_emulated);
2292
2293static int emulator_cmpxchg_emulated(unsigned long addr,
2294 const void *old,
2295 const void *new,
2296 unsigned int bytes,
2297 struct kvm_vcpu *vcpu)
2298{
2299 static int reported;
2300
2301 if (!reported) {
2302 reported = 1;
2303 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2304 }
2bacc55c
MT		 2305#ifndef CONFIG_X86_64
2306 /* guests cmpxchg8b have to be emulated atomically */
2307 if (bytes == 8) {
10589a46 2308 gpa_t gpa;
2bacc55c 2309 struct page *page;
c0b49b0d 2310 char *kaddr;
2bacc55c
MT		 2311 u64 val;
2312
10589a46
MT		 2313 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2314
2bacc55c
MT		 2315 if (gpa == UNMAPPED_GVA ||
2316 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2317 goto emul_write;
2318
2319 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2320 goto emul_write;
2321
2322 val = *(u64 *)new;
72dc67a6 2323
2bacc55c 2324 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2325
c0b49b0d
AM		 2326 kaddr = kmap_atomic(page, KM_USER0);
2327 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2328 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2329 kvm_release_page_dirty(page);
2330 }
3200f405 2331emul_write:
2bacc55c
MT		 2332#endif
2333
bbd9b64e
CO		 2334 return emulator_write_emulated(addr, new, bytes, vcpu);
2335}
2336
2337static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2338{
2339 return kvm_x86_ops->get_segment_base(vcpu, seg);
2340}
2341
2342int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2343{
a7052897 2344 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2345 return X86EMUL_CONTINUE;
2346}
2347
2348int emulate_clts(struct kvm_vcpu *vcpu)
2349{
54e445ca 2350 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2351 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2352 return X86EMUL_CONTINUE;
2353}
2354
2355int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2356{
2357 struct kvm_vcpu *vcpu = ctxt->vcpu;
2358
2359 switch (dr) {
2360 case 0 ... 3:
2361 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2362 return X86EMUL_CONTINUE;
2363 default:
b8688d51 2364 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2365 return X86EMUL_UNHANDLEABLE;
2366 }
2367}
2368
2369int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2370{
2371 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2372 int exception;
2373
2374 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2375 if (exception) {
2376 /* FIXME: better handling */
2377 return X86EMUL_UNHANDLEABLE;
2378 }
2379 return X86EMUL_CONTINUE;
2380}
2381
2382void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2383{
bbd9b64e 2384 u8 opcodes[4];
5fdbf976 2385 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2386 unsigned long rip_linear;
2387
f76c710d 2388 if (!printk_ratelimit())
bbd9b64e
CO		 2389 return;
2390
25be4608
GC		 2391 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2392
bbd9b64e
CO		 2393 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2394
2395 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2396 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2397}
2398EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2399
14af3f3c 2400static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2401 .read_std = emulator_read_std,
bbd9b64e
CO		 2402 .read_emulated = emulator_read_emulated,
2403 .write_emulated = emulator_write_emulated,
2404 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2405};
2406
5fdbf976
MT		 2407static void cache_all_regs(struct kvm_vcpu *vcpu)
2408{
2409 kvm_register_read(vcpu, VCPU_REGS_RAX);
2410 kvm_register_read(vcpu, VCPU_REGS_RSP);
2411 kvm_register_read(vcpu, VCPU_REGS_RIP);
2412 vcpu->arch.regs_dirty = ~0;
2413}
2414
bbd9b64e
CO		 2415int emulate_instruction(struct kvm_vcpu *vcpu,
2416 struct kvm_run *run,
2417 unsigned long cr2,
2418 u16 error_code,
571008da 2419 int emulation_type)
bbd9b64e
CO		 2420{
2421 int r;
571008da 2422 struct decode_cache *c;
bbd9b64e 2423
26eef70c 2424 kvm_clear_exception_queue(vcpu);
ad312c7c 2425 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2426 /*
2427 * TODO: fix x86_emulate.c to use guest_read/write_register
2428 * instead of direct ->regs accesses, can save hundred cycles
2429 * on Intel for instructions that don't read/change RSP, for
2430 * for example.
2431 */
2432 cache_all_regs(vcpu);
bbd9b64e
CO		 2433
2434 vcpu->mmio_is_write = 0;
ad312c7c 2435 vcpu->arch.pio.string = 0;
bbd9b64e 2436
571008da 2437 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2438 int cs_db, cs_l;
2439 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2440
ad312c7c
ZX		 2441 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2442 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2443 vcpu->arch.emulate_ctxt.mode =
2444 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2445 ? X86EMUL_MODE_REAL : cs_l
2446 ? X86EMUL_MODE_PROT64 : cs_db
2447 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2448
ad312c7c 2449 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2450
2451 /* Reject the instructions other than VMCALL/VMMCALL when
2452 * try to emulate invalid opcode */
2453 c = &vcpu->arch.emulate_ctxt.decode;
2454 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2455 (!(c->twobyte && c->b == 0x01 &&
2456 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2457 c->modrm_mod == 3 && c->modrm_rm == 1)))
2458 return EMULATE_FAIL;
2459
f2b5756b 2460 ++vcpu->stat.insn_emulation;
bbd9b64e 2461 if (r) {
f2b5756b 2462 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2463 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2464 return EMULATE_DONE;
2465 return EMULATE_FAIL;
2466 }
2467 }
2468
ad312c7c 2469 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2470
ad312c7c 2471 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2472 return EMULATE_DO_MMIO;
2473
2474 if ((r || vcpu->mmio_is_write) && run) {
2475 run->exit_reason = KVM_EXIT_MMIO;
2476 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2477 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2478 run->mmio.len = vcpu->mmio_size;
2479 run->mmio.is_write = vcpu->mmio_is_write;
2480 }
2481
2482 if (r) {
2483 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2484 return EMULATE_DONE;
2485 if (!vcpu->mmio_needed) {
2486 kvm_report_emulation_failure(vcpu, "mmio");
2487 return EMULATE_FAIL;
2488 }
2489 return EMULATE_DO_MMIO;
2490 }
2491
ad312c7c 2492 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2493
2494 if (vcpu->mmio_is_write) {
2495 vcpu->mmio_needed = 0;
2496 return EMULATE_DO_MMIO;
2497 }
2498
2499 return EMULATE_DONE;
2500}
2501EXPORT_SYMBOL_GPL(emulate_instruction);
2502
de7d789a
CO		 2503static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2504{
2505 int i;
2506
ad312c7c
ZX		 2507 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2508 if (vcpu->arch.pio.guest_pages[i]) {
2509 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2510 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2511 }
2512}
2513
2514static int pio_copy_data(struct kvm_vcpu *vcpu)
2515{
ad312c7c 2516 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2517 void *q;
2518 unsigned bytes;
ad312c7c 2519 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2520
ad312c7c 2521 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2522 PAGE_KERNEL);
2523 if (!q) {
2524 free_pio_guest_pages(vcpu);
2525 return -ENOMEM;
2526 }
ad312c7c
ZX		 2527 q += vcpu->arch.pio.guest_page_offset;
2528 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2529 if (vcpu->arch.pio.in)
de7d789a
CO		 2530 memcpy(q, p, bytes);
2531 else
2532 memcpy(p, q, bytes);
ad312c7c 2533 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2534 vunmap(q);
2535 free_pio_guest_pages(vcpu);
2536 return 0;
2537}
2538
2539int complete_pio(struct kvm_vcpu *vcpu)
2540{
ad312c7c 2541 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2542 long delta;
2543 int r;
5fdbf976 2544 unsigned long val;
de7d789a
CO		 2545
2546 if (!io->string) {
5fdbf976
MT		 2547 if (io->in) {
2548 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2549 memcpy(&val, vcpu->arch.pio_data, io->size);
2550 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2551 }
de7d789a
CO		 2552 } else {
2553 if (io->in) {
2554 r = pio_copy_data(vcpu);
5fdbf976 2555 if (r)
de7d789a 2556 return r;
de7d789a
CO		 2557 }
2558
2559 delta = 1;
2560 if (io->rep) {
2561 delta *= io->cur_count;
2562 /*
2563 * The size of the register should really depend on
2564 * current address size.
2565 */
5fdbf976
MT		 2566 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2567 val -= delta;
2568 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2569 }
2570 if (io->down)
2571 delta = -delta;
2572 delta *= io->size;
5fdbf976
MT		 2573 if (io->in) {
2574 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2575 val += delta;
2576 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2577 } else {
2578 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2579 val += delta;
2580 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2581 }
de7d789a
CO		 2582 }
2583
de7d789a
CO		 2584 io->count -= io->cur_count;
2585 io->cur_count = 0;
2586
2587 return 0;
2588}
2589
2590static void kernel_pio(struct kvm_io_device *pio_dev,
2591 struct kvm_vcpu *vcpu,
2592 void *pd)
2593{
2594 /* TODO: String I/O for in kernel device */
2595
2596 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2597 if (vcpu->arch.pio.in)
2598 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2599 vcpu->arch.pio.size,
de7d789a
CO		 2600 pd);
2601 else
ad312c7c
ZX		 2602 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2603 vcpu->arch.pio.size,
de7d789a
CO		 2604 pd);
2605 mutex_unlock(&vcpu->kvm->lock);
2606}
2607
2608static void pio_string_write(struct kvm_io_device *pio_dev,
2609 struct kvm_vcpu *vcpu)
2610{
ad312c7c
ZX		 2611 struct kvm_pio_request *io = &vcpu->arch.pio;
2612 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2613 int i;
2614
2615 mutex_lock(&vcpu->kvm->lock);
2616 for (i = 0; i < io->cur_count; i++) {
2617 kvm_iodevice_write(pio_dev, io->port,
2618 io->size,
2619 pd);
2620 pd += io->size;
2621 }
2622 mutex_unlock(&vcpu->kvm->lock);
2623}
2624
2625static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2626 gpa_t addr, int len,
2627 int is_write)
de7d789a 2628{
92760499 2629 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2630}
2631
2632int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2633 int size, unsigned port)
2634{
2635 struct kvm_io_device *pio_dev;
5fdbf976 2636 unsigned long val;
de7d789a
CO		 2637
2638 vcpu->run->exit_reason = KVM_EXIT_IO;
2639 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2640 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2641 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2642 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2643 vcpu->run->io.port = vcpu->arch.pio.port = port;
2644 vcpu->arch.pio.in = in;
2645 vcpu->arch.pio.string = 0;
2646 vcpu->arch.pio.down = 0;
2647 vcpu->arch.pio.guest_page_offset = 0;
2648 vcpu->arch.pio.rep = 0;
de7d789a 2649
2714d1d3
FEL		 2650 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2651 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2652 handler);
2653 else
2654 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2655 handler);
2656
5fdbf976
MT		 2657 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2658 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a
CO		 2659
2660 kvm_x86_ops->skip_emulated_instruction(vcpu);
2661
92760499 2662 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2663 if (pio_dev) {
ad312c7c 2664 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2665 complete_pio(vcpu);
2666 return 1;
2667 }
2668 return 0;
2669}
2670EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2671
2672int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2673 int size, unsigned long count, int down,
2674 gva_t address, int rep, unsigned port)
2675{
2676 unsigned now, in_page;
2677 int i, ret = 0;
2678 int nr_pages = 1;
2679 struct page *page;
2680 struct kvm_io_device *pio_dev;
2681
2682 vcpu->run->exit_reason = KVM_EXIT_IO;
2683 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2684 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2685 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2686 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2687 vcpu->run->io.port = vcpu->arch.pio.port = port;
2688 vcpu->arch.pio.in = in;
2689 vcpu->arch.pio.string = 1;
2690 vcpu->arch.pio.down = down;
2691 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2692 vcpu->arch.pio.rep = rep;
de7d789a 2693
2714d1d3
FEL		 2694 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2695 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2696 handler);
2697 else
2698 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2699 handler);
2700
de7d789a
CO		 2701 if (!count) {
2702 kvm_x86_ops->skip_emulated_instruction(vcpu);
2703 return 1;
2704 }
2705
2706 if (!down)
2707 in_page = PAGE_SIZE - offset_in_page(address);
2708 else
2709 in_page = offset_in_page(address) + size;
2710 now = min(count, (unsigned long)in_page / size);
2711 if (!now) {
2712 /*
2713 * String I/O straddles page boundary. Pin two guest pages
2714 * so that we satisfy atomicity constraints. Do just one
2715 * transaction to avoid complexity.
2716 */
2717 nr_pages = 2;
2718 now = 1;
2719 }
2720 if (down) {
2721 /*
2722 * String I/O in reverse. Yuck. Kill the guest, fix later.
2723 */
2724 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2725 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2726 return 1;
2727 }
2728 vcpu->run->io.count = now;
ad312c7c 2729 vcpu->arch.pio.cur_count = now;
de7d789a 2730
ad312c7c 2731 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2732 kvm_x86_ops->skip_emulated_instruction(vcpu);
2733
2734 for (i = 0; i < nr_pages; ++i) {
de7d789a 2735 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2736 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2737 if (!page) {
c1a5d4f9 2738 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2739 free_pio_guest_pages(vcpu);
2740 return 1;
2741 }
2742 }
2743
92760499
LV		 2744 pio_dev = vcpu_find_pio_dev(vcpu, port,
2745 vcpu->arch.pio.cur_count,
2746 !vcpu->arch.pio.in);
ad312c7c 2747 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2748 /* string PIO write */
2749 ret = pio_copy_data(vcpu);
2750 if (ret >= 0 && pio_dev) {
2751 pio_string_write(pio_dev, vcpu);
2752 complete_pio(vcpu);
ad312c7c 2753 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2754 ret = 1;
2755 }
2756 } else if (pio_dev)
2757 pr_unimpl(vcpu, "no string pio read support yet, "
2758 "port %x size %d count %ld\n",
2759 port, size, count);
2760
2761 return ret;
2762}
2763EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2764
f8c16bba 2765int kvm_arch_init(void *opaque)
043405e1 2766{
56c6d28a 2767 int r;
f8c16bba
ZX		 2768 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2769
f8c16bba
ZX		 2770 if (kvm_x86_ops) {
2771 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2772 r = -EEXIST;
2773 goto out;
f8c16bba
ZX		 2774 }
2775
2776 if (!ops->cpu_has_kvm_support()) {
2777 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2778 r = -EOPNOTSUPP;
2779 goto out;
f8c16bba
ZX		 2780 }
2781 if (ops->disabled_by_bios()) {
2782 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2783 r = -EOPNOTSUPP;
2784 goto out;
f8c16bba
ZX		 2785 }
2786
97db56ce
AK		 2787 r = kvm_mmu_module_init();
2788 if (r)
2789 goto out;
2790
2791 kvm_init_msr_list();
2792
f8c16bba 2793 kvm_x86_ops = ops;
56c6d28a 2794 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2795 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2796 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2797 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2798 return 0;
56c6d28a
ZX		 2799
2800out:
56c6d28a 2801 return r;
043405e1 2802}
8776e519 2803
f8c16bba
ZX		 2804void kvm_arch_exit(void)
2805{
2806 kvm_x86_ops = NULL;
56c6d28a
ZX		 2807 kvm_mmu_module_exit();
2808}
f8c16bba 2809
8776e519
HB		 2810int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2811{
2812 ++vcpu->stat.halt_exits;
2714d1d3 2813 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2814 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2815 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2816 return 1;
2817 } else {
2818 vcpu->run->exit_reason = KVM_EXIT_HLT;
2819 return 0;
2820 }
2821}
2822EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2823
2f333bcb
MT		 2824static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2825 unsigned long a1)
2826{
2827 if (is_long_mode(vcpu))
2828 return a0;
2829 else
2830 return a0 | ((gpa_t)a1 << 32);
2831}
2832
8776e519
HB		 2833int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2834{
2835 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2836 int r = 1;
8776e519 2837
5fdbf976
MT		 2838 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2839 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2840 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2841 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2842 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2843
2714d1d3
FEL		 2844 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2845
8776e519
HB		 2846 if (!is_long_mode(vcpu)) {
2847 nr &= 0xFFFFFFFF;
2848 a0 &= 0xFFFFFFFF;
2849 a1 &= 0xFFFFFFFF;
2850 a2 &= 0xFFFFFFFF;
2851 a3 &= 0xFFFFFFFF;
2852 }
2853
2854 switch (nr) {
b93463aa
AK		 2855 case KVM_HC_VAPIC_POLL_IRQ:
2856 ret = 0;
2857 break;
2f333bcb
MT		 2858 case KVM_HC_MMU_OP:
2859 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2860 break;
8776e519
HB		 2861 default:
2862 ret = -KVM_ENOSYS;
2863 break;
2864 }
5fdbf976 2865 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2866 ++vcpu->stat.hypercalls;
2f333bcb 2867 return r;
8776e519
HB		 2868}
2869EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2870
2871int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2872{
2873 char instruction[3];
2874 int ret = 0;
5fdbf976 2875 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2876
8776e519
HB		 2877
2878 /*
2879 * Blow out the MMU to ensure that no other VCPU has an active mapping
2880 * to ensure that the updated hypercall appears atomically across all
2881 * VCPUs.
2882 */
2883 kvm_mmu_zap_all(vcpu->kvm);
2884
8776e519 2885 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2886 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2887 != X86EMUL_CONTINUE)
2888 ret = -EFAULT;
2889
8776e519
HB		 2890 return ret;
2891}
2892
2893static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2894{
2895 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2896}
2897
2898void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2899{
2900 struct descriptor_table dt = { limit, base };
2901
2902 kvm_x86_ops->set_gdt(vcpu, &dt);
2903}
2904
2905void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2906{
2907 struct descriptor_table dt = { limit, base };
2908
2909 kvm_x86_ops->set_idt(vcpu, &dt);
2910}
2911
2912void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2913 unsigned long *rflags)
2914{
2d3ad1f4 2915 kvm_lmsw(vcpu, msw);
8776e519
HB		 2916 *rflags = kvm_x86_ops->get_rflags(vcpu);
2917}
2918
2919unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2920{
54e445ca
JR		 2921 unsigned long value;
2922
8776e519
HB		 2923 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2924 switch (cr) {
2925 case 0:
54e445ca
JR		 2926 value = vcpu->arch.cr0;
2927 break;
8776e519 2928 case 2:
54e445ca
JR		 2929 value = vcpu->arch.cr2;
2930 break;
8776e519 2931 case 3:
54e445ca
JR		 2932 value = vcpu->arch.cr3;
2933 break;
8776e519 2934 case 4:
54e445ca
JR		 2935 value = vcpu->arch.cr4;
2936 break;
152ff9be 2937 case 8:
54e445ca
JR		 2938 value = kvm_get_cr8(vcpu);
2939 break;
8776e519 2940 default:
b8688d51 2941 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2942 return 0;
2943 }
54e445ca
JR		 2944 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2945 (u32)((u64)value >> 32), handler);
2946
2947 return value;
8776e519
HB		 2948}
2949
2950void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2951 unsigned long *rflags)
2952{
54e445ca
JR		 2953 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2954 (u32)((u64)val >> 32), handler);
2955
8776e519
HB		 2956 switch (cr) {
2957 case 0:
2d3ad1f4 2958 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2959 *rflags = kvm_x86_ops->get_rflags(vcpu);
2960 break;
2961 case 2:
ad312c7c 2962 vcpu->arch.cr2 = val;
8776e519
HB		 2963 break;
2964 case 3:
2d3ad1f4 2965 kvm_set_cr3(vcpu, val);
8776e519
HB		 2966 break;
2967 case 4:
2d3ad1f4 2968 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2969 break;
152ff9be 2970 case 8:
2d3ad1f4 2971 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2972 break;
8776e519 2973 default:
b8688d51 2974 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2975 }
2976}
2977
07716717
DK		 2978static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2979{
ad312c7c
ZX		 2980 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2981 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2982
2983 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2984 /* when no next entry is found, the current entry[i] is reselected */
2985 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2986 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2987 if (ej->function == e->function) {
2988 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2989 return j;
2990 }
2991 }
2992 return 0; /* silence gcc, even though control never reaches here */
2993}
2994
2995/* find an entry with matching function, matching index (if needed), and that
2996 * should be read next (if it's stateful) */
2997static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2998 u32 function, u32 index)
2999{
3000 if (e->function != function)
3001 return 0;
3002 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3003 return 0;
3004 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3005 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3006 return 0;
3007 return 1;
3008}
3009
8776e519
HB		 3010void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3011{
3012 int i;
07716717
DK		 3013 u32 function, index;
3014 struct kvm_cpuid_entry2 *e, *best;
8776e519 3015
5fdbf976
MT		 3016 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3017 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3018 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3019 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3020 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3021 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
8776e519 3022 best = NULL;
ad312c7c
ZX		 3023 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3024 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3025 if (is_matching_cpuid_entry(e, function, index)) {
3026 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3027 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3028 best = e;
3029 break;
3030 }
3031 /*
3032 * Both basic or both extended?
3033 */
3034 if (((e->function ^ function) & 0x80000000) == 0)
3035 if (!best || e->function > best->function)
3036 best = e;
3037 }
3038 if (best) {
5fdbf976
MT		 3039 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3040 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3041 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3042 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3043 }
8776e519 3044 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3045 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3046 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3047 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3048 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3049 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3050}
3051EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3052
b6c7a5dc
HB		 3053/*
3054 * Check if userspace requested an interrupt window, and that the
3055 * interrupt window is open.
3056 *
3057 * No need to exit to userspace if we already have an interrupt queued.
3058 */
3059static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3060 struct kvm_run *kvm_run)
3061{
ad312c7c 3062 return (!vcpu->arch.irq_summary &&
b6c7a5dc 3063 kvm_run->request_interrupt_window &&
ad312c7c 3064 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 3065 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
3066}
3067
3068static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3069 struct kvm_run *kvm_run)
3070{
3071 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3072 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 3073 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3074 if (irqchip_in_kernel(vcpu->kvm))
3075 kvm_run->ready_for_interrupt_injection = 1;
3076 else
3077 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 3078 (vcpu->arch.interrupt_window_open &&
3079 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 3080}
3081
b93463aa
AK		 3082static void vapic_enter(struct kvm_vcpu *vcpu)
3083{
3084 struct kvm_lapic *apic = vcpu->arch.apic;
3085 struct page *page;
3086
3087 if (!apic || !apic->vapic_addr)
3088 return;
3089
3090 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3091
3092 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3093}
3094
3095static void vapic_exit(struct kvm_vcpu *vcpu)
3096{
3097 struct kvm_lapic *apic = vcpu->arch.apic;
3098
3099 if (!apic || !apic->vapic_addr)
3100 return;
3101
f8b78fa3 3102 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3103 kvm_release_page_dirty(apic->vapic_page);
3104 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3105 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3106}
3107
d7690175 3108static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3109{
3110 int r;
3111
2e53d63a
MT		 3112 if (vcpu->requests)
3113 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3114 kvm_mmu_unload(vcpu);
3115
b6c7a5dc
HB		 3116 r = kvm_mmu_reload(vcpu);
3117 if (unlikely(r))
3118 goto out;
3119
2f52d58c
AK		 3120 if (vcpu->requests) {
3121 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3122 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 3123 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3124 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3125 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3126 &vcpu->requests)) {
3127 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3128 r = 0;
3129 goto out;
3130 }
71c4dfaf
JR		 3131 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3132 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3133 r = 0;
3134 goto out;
3135 }
2f52d58c 3136 }
b93463aa 3137
06e05645 3138 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 3139 kvm_inject_pending_timer_irqs(vcpu);
3140
3141 preempt_disable();
3142
3143 kvm_x86_ops->prepare_guest_switch(vcpu);
3144 kvm_load_guest_fpu(vcpu);
3145
3146 local_irq_disable();
3147
d7690175 3148 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3149 local_irq_enable();
3150 preempt_enable();
3151 r = 1;
3152 goto out;
3153 }
3154
29415c37
MT		 3155 if (vcpu->guest_debug.enabled)
3156 kvm_x86_ops->guest_debug_pre(vcpu);
3157
e9571ed5
MT		 3158 vcpu->guest_mode = 1;
3159 /*
3160 * Make sure that guest_mode assignment won't happen after
3161 * testing the pending IRQ vector bitmap.
3162 */
3163 smp_wmb();
3164
ad312c7c 3165 if (vcpu->arch.exception.pending)
298101da
AK		 3166 __queue_exception(vcpu);
3167 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3168 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3169 else
b6c7a5dc
HB		 3170 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3171
b93463aa
AK		 3172 kvm_lapic_sync_to_vapic(vcpu);
3173
3200f405
MT		 3174 up_read(&vcpu->kvm->slots_lock);
3175
b6c7a5dc
HB		 3176 kvm_guest_enter();
3177
b6c7a5dc 3178
2714d1d3 3179 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3180 kvm_x86_ops->run(vcpu, kvm_run);
3181
3182 vcpu->guest_mode = 0;
3183 local_irq_enable();
3184
3185 ++vcpu->stat.exits;
3186
3187 /*
3188 * We must have an instruction between local_irq_enable() and
3189 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3190 * the interrupt shadow. The stat.exits increment will do nicely.
3191 * But we need to prevent reordering, hence this barrier():
3192 */
3193 barrier();
3194
3195 kvm_guest_exit();
3196
3197 preempt_enable();
3198
3200f405
MT		 3199 down_read(&vcpu->kvm->slots_lock);
3200
b6c7a5dc
HB		 3201 /*
3202 * Profile KVM exit RIPs:
3203 */
3204 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3205 unsigned long rip = kvm_rip_read(vcpu);
3206 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3207 }
3208
ad312c7c
ZX		 3209 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3210 vcpu->arch.exception.pending = false;
298101da 3211
b93463aa
AK		 3212 kvm_lapic_sync_from_vapic(vcpu);
3213
b6c7a5dc 3214 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3215out:
3216 return r;
3217}
b6c7a5dc 3218
d7690175
MT		 3219static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3220{
3221 int r;
3222
3223 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3224 printk("vcpu %d received sipi with vector # %x\n",
3225 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3226 kvm_lapic_reset(vcpu);
3227 r = kvm_x86_ops->vcpu_reset(vcpu);
3228 if (r)
3229 return r;
3230 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3231 }
3232
d7690175
MT		 3233 down_read(&vcpu->kvm->slots_lock);
3234 vapic_enter(vcpu);
3235
3236 r = 1;
3237 while (r > 0) {
af2152f5 3238 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3239 r = vcpu_enter_guest(vcpu, kvm_run);
3240 else {
3241 up_read(&vcpu->kvm->slots_lock);
3242 kvm_vcpu_block(vcpu);
3243 down_read(&vcpu->kvm->slots_lock);
3244 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3245 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3246 vcpu->arch.mp_state =
3247 KVM_MP_STATE_RUNNABLE;
3248 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3249 r = -EINTR;
3250 }
3251
3252 if (r > 0) {
3253 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3254 r = -EINTR;
3255 kvm_run->exit_reason = KVM_EXIT_INTR;
3256 ++vcpu->stat.request_irq_exits;
3257 }
3258 if (signal_pending(current)) {
3259 r = -EINTR;
3260 kvm_run->exit_reason = KVM_EXIT_INTR;
3261 ++vcpu->stat.signal_exits;
3262 }
3263 if (need_resched()) {
3264 up_read(&vcpu->kvm->slots_lock);
3265 kvm_resched(vcpu);
3266 down_read(&vcpu->kvm->slots_lock);
3267 }
3268 }
b6c7a5dc
HB		 3269 }
3270
d7690175 3271 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3272 post_kvm_run_save(vcpu, kvm_run);
3273
b93463aa
AK		 3274 vapic_exit(vcpu);
3275
b6c7a5dc
HB		 3276 return r;
3277}
3278
3279int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3280{
3281 int r;
3282 sigset_t sigsaved;
3283
3284 vcpu_load(vcpu);
3285
ac9f6dc0
AK		 3286 if (vcpu->sigset_active)
3287 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3288
a4535290 3289 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3290 kvm_vcpu_block(vcpu);
d7690175 3291 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3292 r = -EAGAIN;
3293 goto out;
b6c7a5dc
HB		 3294 }
3295
b6c7a5dc
HB		 3296 /* re-sync apic's tpr */
3297 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3298 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3299
ad312c7c 3300 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3301 r = complete_pio(vcpu);
3302 if (r)
3303 goto out;
3304 }
3305#if CONFIG_HAS_IOMEM
3306 if (vcpu->mmio_needed) {
3307 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3308 vcpu->mmio_read_completed = 1;
3309 vcpu->mmio_needed = 0;
3200f405
MT		 3310
3311 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3312 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3313 vcpu->arch.mmio_fault_cr2, 0,
3314 EMULTYPE_NO_DECODE);
3200f405 3315 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3316 if (r == EMULATE_DO_MMIO) {
3317 /*
3318 * Read-modify-write. Back to userspace.
3319 */
3320 r = 0;
3321 goto out;
3322 }
3323 }
3324#endif
5fdbf976
MT		 3325 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3326 kvm_register_write(vcpu, VCPU_REGS_RAX,
3327 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3328
3329 r = __vcpu_run(vcpu, kvm_run);
3330
3331out:
3332 if (vcpu->sigset_active)
3333 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3334
3335 vcpu_put(vcpu);
3336 return r;
3337}
3338
3339int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3340{
3341 vcpu_load(vcpu);
3342
5fdbf976
MT		 3343 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3344 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3345 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3346 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3347 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3348 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3349 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3350 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3351#ifdef CONFIG_X86_64
5fdbf976
MT		 3352 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3353 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3354 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3355 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3356 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3357 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3358 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3359 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3360#endif
3361
5fdbf976 3362 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3363 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3364
3365 /*
3366 * Don't leak debug flags in case they were set for guest debugging
3367 */
3368 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3369 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3370
3371 vcpu_put(vcpu);
3372
3373 return 0;
3374}
3375
3376int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3377{
3378 vcpu_load(vcpu);
3379
5fdbf976
MT		 3380 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3381 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3382 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3383 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3384 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3385 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3386 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3387 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3388#ifdef CONFIG_X86_64
5fdbf976
MT		 3389 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3390 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3391 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3392 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3393 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3394 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3395 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3396 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3397
b6c7a5dc
HB		 3398#endif
3399
5fdbf976 3400 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3401 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3402
b6c7a5dc 3403
b4f14abd
JK		 3404 vcpu->arch.exception.pending = false;
3405
b6c7a5dc
HB		 3406 vcpu_put(vcpu);
3407
3408 return 0;
3409}
3410
3e6e0aab
GT		 3411void kvm_get_segment(struct kvm_vcpu *vcpu,
3412 struct kvm_segment *var, int seg)
b6c7a5dc 3413{
14af3f3c 3414 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3415}
3416
3417void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3418{
3419 struct kvm_segment cs;
3420
3e6e0aab 3421 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3422 *db = cs.db;
3423 *l = cs.l;
3424}
3425EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3426
3427int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3428 struct kvm_sregs *sregs)
3429{
3430 struct descriptor_table dt;
3431 int pending_vec;
3432
3433 vcpu_load(vcpu);
3434
3e6e0aab
GT		 3435 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3436 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3437 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3438 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3439 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3440 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3441
3e6e0aab
GT		 3442 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3443 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3444
3445 kvm_x86_ops->get_idt(vcpu, &dt);
3446 sregs->idt.limit = dt.limit;
3447 sregs->idt.base = dt.base;
3448 kvm_x86_ops->get_gdt(vcpu, &dt);
3449 sregs->gdt.limit = dt.limit;
3450 sregs->gdt.base = dt.base;
3451
3452 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3453 sregs->cr0 = vcpu->arch.cr0;
3454 sregs->cr2 = vcpu->arch.cr2;
3455 sregs->cr3 = vcpu->arch.cr3;
3456 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3457 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3458 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3459 sregs->apic_base = kvm_get_apic_base(vcpu);
3460
3461 if (irqchip_in_kernel(vcpu->kvm)) {
3462 memset(sregs->interrupt_bitmap, 0,
3463 sizeof sregs->interrupt_bitmap);
3464 pending_vec = kvm_x86_ops->get_irq(vcpu);
3465 if (pending_vec >= 0)
3466 set_bit(pending_vec,
3467 (unsigned long *)sregs->interrupt_bitmap);
3468 } else
ad312c7c 3469 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3470 sizeof sregs->interrupt_bitmap);
3471
3472 vcpu_put(vcpu);
3473
3474 return 0;
3475}
3476
62d9f0db
MT		 3477int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3478 struct kvm_mp_state *mp_state)
3479{
3480 vcpu_load(vcpu);
3481 mp_state->mp_state = vcpu->arch.mp_state;
3482 vcpu_put(vcpu);
3483 return 0;
3484}
3485
3486int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3487 struct kvm_mp_state *mp_state)
3488{
3489 vcpu_load(vcpu);
3490 vcpu->arch.mp_state = mp_state->mp_state;
3491 vcpu_put(vcpu);
3492 return 0;
3493}
3494
3e6e0aab 3495static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3496 struct kvm_segment *var, int seg)
3497{
14af3f3c 3498 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3499}
3500
37817f29
IE		 3501static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3502 struct kvm_segment *kvm_desct)
3503{
3504 kvm_desct->base = seg_desc->base0;
3505 kvm_desct->base |= seg_desc->base1 << 16;
3506 kvm_desct->base |= seg_desc->base2 << 24;
3507 kvm_desct->limit = seg_desc->limit0;
3508 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3509 if (seg_desc->g) {
3510 kvm_desct->limit <<= 12;
3511 kvm_desct->limit |= 0xfff;
3512 }
37817f29
IE		 3513 kvm_desct->selector = selector;
3514 kvm_desct->type = seg_desc->type;
3515 kvm_desct->present = seg_desc->p;
3516 kvm_desct->dpl = seg_desc->dpl;
3517 kvm_desct->db = seg_desc->d;
3518 kvm_desct->s = seg_desc->s;
3519 kvm_desct->l = seg_desc->l;
3520 kvm_desct->g = seg_desc->g;
3521 kvm_desct->avl = seg_desc->avl;
3522 if (!selector)
3523 kvm_desct->unusable = 1;
3524 else
3525 kvm_desct->unusable = 0;
3526 kvm_desct->padding = 0;
3527}
3528
3529static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3530 u16 selector,
3531 struct descriptor_table *dtable)
3532{
3533 if (selector & 1 << 2) {
3534 struct kvm_segment kvm_seg;
3535
3e6e0aab 3536 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3537
3538 if (kvm_seg.unusable)
3539 dtable->limit = 0;
3540 else
3541 dtable->limit = kvm_seg.limit;
3542 dtable->base = kvm_seg.base;
3543 }
3544 else
3545 kvm_x86_ops->get_gdt(vcpu, dtable);
3546}
3547
3548/* allowed just for 8 bytes segments */
3549static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3550 struct desc_struct *seg_desc)
3551{
98899aa0 3552 gpa_t gpa;
37817f29
IE		 3553 struct descriptor_table dtable;
3554 u16 index = selector >> 3;
3555
3556 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3557
3558 if (dtable.limit < index * 8 + 7) {
3559 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3560 return 1;
3561 }
98899aa0
MT		 3562 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3563 gpa += index * 8;
3564 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3565}
3566
3567/* allowed just for 8 bytes segments */
3568static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3569 struct desc_struct *seg_desc)
3570{
98899aa0 3571 gpa_t gpa;
37817f29
IE		 3572 struct descriptor_table dtable;
3573 u16 index = selector >> 3;
3574
3575 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3576
3577 if (dtable.limit < index * 8 + 7)
3578 return 1;
98899aa0
MT		 3579 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3580 gpa += index * 8;
3581 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3582}
3583
3584static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3585 struct desc_struct *seg_desc)
3586{
3587 u32 base_addr;
3588
3589 base_addr = seg_desc->base0;
3590 base_addr |= (seg_desc->base1 << 16);
3591 base_addr |= (seg_desc->base2 << 24);
3592
98899aa0 3593 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3594}
3595
37817f29
IE		 3596static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3597{
3598 struct kvm_segment kvm_seg;
3599
3e6e0aab 3600 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3601 return kvm_seg.selector;
3602}
3603
3604static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3605 u16 selector,
3606 struct kvm_segment *kvm_seg)
3607{
3608 struct desc_struct seg_desc;
3609
3610 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3611 return 1;
3612 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3613 return 0;
3614}
3615
2259e3a7 3616static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3617{
3618 struct kvm_segment segvar = {
3619 .base = selector << 4,
3620 .limit = 0xffff,
3621 .selector = selector,
3622 .type = 3,
3623 .present = 1,
3624 .dpl = 3,
3625 .db = 0,
3626 .s = 1,
3627 .l = 0,
3628 .g = 0,
3629 .avl = 0,
3630 .unusable = 0,
3631 };
3632 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3633 return 0;
3634}
3635
3e6e0aab
GT		 3636int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3637 int type_bits, int seg)
37817f29
IE		 3638{
3639 struct kvm_segment kvm_seg;
3640
f4bbd9aa
AK		 3641 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3642 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3643 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3644 return 1;
3645 kvm_seg.type |= type_bits;
3646
3647 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3648 seg != VCPU_SREG_LDTR)
3649 if (!kvm_seg.s)
3650 kvm_seg.unusable = 1;
3651
3e6e0aab 3652 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3653 return 0;
3654}
3655
3656static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3657 struct tss_segment_32 *tss)
3658{
3659 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3660 tss->eip = kvm_rip_read(vcpu);
37817f29 3661 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3662 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3663 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3664 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3665 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3666 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3667 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3668 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3669 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3670 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3671 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3672 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3673 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3674 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3675 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3676 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3677 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3678}
3679
3680static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3681 struct tss_segment_32 *tss)
3682{
3683 kvm_set_cr3(vcpu, tss->cr3);
3684
5fdbf976 3685 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3686 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3687
5fdbf976
MT		 3688 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3689 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3690 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3691 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3692 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3693 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3694 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3695 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3696
3e6e0aab 3697 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3698 return 1;
3699
3e6e0aab 3700 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3701 return 1;
3702
3e6e0aab 3703 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3704 return 1;
3705
3e6e0aab 3706 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3707 return 1;
3708
3e6e0aab 3709 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3710 return 1;
3711
3e6e0aab 3712 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3713 return 1;
3714
3e6e0aab 3715 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3716 return 1;
3717 return 0;
3718}
3719
3720static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3721 struct tss_segment_16 *tss)
3722{
5fdbf976 3723 tss->ip = kvm_rip_read(vcpu);
37817f29 3724 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3725 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3726 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3727 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3728 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3729 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3730 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3731 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3732 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3733
3734 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3735 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3736 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3737 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3738 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3739 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3740}
3741
3742static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3743 struct tss_segment_16 *tss)
3744{
5fdbf976 3745 kvm_rip_write(vcpu, tss->ip);
37817f29 3746 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3747 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3748 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3749 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3750 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3751 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3752 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3753 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3754 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3755
3e6e0aab 3756 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3757 return 1;
3758
3e6e0aab 3759 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3760 return 1;
3761
3e6e0aab 3762 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3763 return 1;
3764
3e6e0aab 3765 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3766 return 1;
3767
3e6e0aab 3768 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3769 return 1;
3770 return 0;
3771}
3772
8b2cf73c 3773static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3774 u32 old_tss_base,
37817f29
IE		 3775 struct desc_struct *nseg_desc)
3776{
3777 struct tss_segment_16 tss_segment_16;
3778 int ret = 0;
3779
34198bf8
MT		 3780 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3781 sizeof tss_segment_16))
37817f29
IE		 3782 goto out;
3783
3784 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3785
34198bf8
MT		 3786 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3787 sizeof tss_segment_16))
37817f29 3788 goto out;
34198bf8
MT		 3789
3790 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3791 &tss_segment_16, sizeof tss_segment_16))
3792 goto out;
3793
37817f29
IE		 3794 if (load_state_from_tss16(vcpu, &tss_segment_16))
3795 goto out;
3796
3797 ret = 1;
3798out:
3799 return ret;
3800}
3801
8b2cf73c 3802static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3803 u32 old_tss_base,
37817f29
IE		 3804 struct desc_struct *nseg_desc)
3805{
3806 struct tss_segment_32 tss_segment_32;
3807 int ret = 0;
3808
34198bf8
MT		 3809 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3810 sizeof tss_segment_32))
37817f29
IE		 3811 goto out;
3812
3813 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3814
34198bf8
MT		 3815 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3816 sizeof tss_segment_32))
3817 goto out;
3818
3819 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3820 &tss_segment_32, sizeof tss_segment_32))
37817f29 3821 goto out;
34198bf8 3822
37817f29
IE		 3823 if (load_state_from_tss32(vcpu, &tss_segment_32))
3824 goto out;
3825
3826 ret = 1;
3827out:
3828 return ret;
3829}
3830
3831int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3832{
3833 struct kvm_segment tr_seg;
3834 struct desc_struct cseg_desc;
3835 struct desc_struct nseg_desc;
3836 int ret = 0;
34198bf8
MT		 3837 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3838 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3839
34198bf8 3840 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3841
34198bf8
MT		 3842 /* FIXME: Handle errors. Failure to read either TSS or their
3843 * descriptors should generate a pagefault.
3844 */
37817f29
IE		 3845 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3846 goto out;
3847
34198bf8 3848 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3849 goto out;
3850
37817f29
IE		 3851 if (reason != TASK_SWITCH_IRET) {
3852 int cpl;
3853
3854 cpl = kvm_x86_ops->get_cpl(vcpu);
3855 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3856 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3857 return 1;
3858 }
3859 }
3860
3861 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3862 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3863 return 1;
3864 }
3865
3866 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3867 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3868 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3869 }
3870
3871 if (reason == TASK_SWITCH_IRET) {
3872 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3873 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3874 }
3875
3876 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3877
3878 if (nseg_desc.type & 8)
34198bf8 3879 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3880 &nseg_desc);
3881 else
34198bf8 3882 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3883 &nseg_desc);
3884
3885 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3886 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3887 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3888 }
3889
3890 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3891 nseg_desc.type |= (1 << 1);
37817f29
IE		 3892 save_guest_segment_descriptor(vcpu, tss_selector,
3893 &nseg_desc);
3894 }
3895
3896 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3897 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3898 tr_seg.type = 11;
3e6e0aab 3899 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3900out:
37817f29
IE		 3901 return ret;
3902}
3903EXPORT_SYMBOL_GPL(kvm_task_switch);
3904
b6c7a5dc
HB		 3905int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3906 struct kvm_sregs *sregs)
3907{
3908 int mmu_reset_needed = 0;
3909 int i, pending_vec, max_bits;
3910 struct descriptor_table dt;
3911
3912 vcpu_load(vcpu);
3913
3914 dt.limit = sregs->idt.limit;
3915 dt.base = sregs->idt.base;
3916 kvm_x86_ops->set_idt(vcpu, &dt);
3917 dt.limit = sregs->gdt.limit;
3918 dt.base = sregs->gdt.base;
3919 kvm_x86_ops->set_gdt(vcpu, &dt);
3920
ad312c7c
ZX		 3921 vcpu->arch.cr2 = sregs->cr2;
3922 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3923 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3924
2d3ad1f4 3925 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3926
ad312c7c 3927 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3928 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3929 kvm_set_apic_base(vcpu, sregs->apic_base);
3930
3931 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3932
ad312c7c 3933 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3934 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3935 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3936
ad312c7c 3937 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3938 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3939 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3940 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3941
3942 if (mmu_reset_needed)
3943 kvm_mmu_reset_context(vcpu);
3944
3945 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3946 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3947 sizeof vcpu->arch.irq_pending);
3948 vcpu->arch.irq_summary = 0;
3949 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3950 if (vcpu->arch.irq_pending[i])
3951 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3952 } else {
3953 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3954 pending_vec = find_first_bit(
3955 (const unsigned long *)sregs->interrupt_bitmap,
3956 max_bits);
3957 /* Only pending external irq is handled here */
3958 if (pending_vec < max_bits) {
3959 kvm_x86_ops->set_irq(vcpu, pending_vec);
3960 pr_debug("Set back pending irq %d\n",
3961 pending_vec);
3962 }
3963 }
3964
3e6e0aab
GT		 3965 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3966 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3967 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3968 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3969 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3970 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3971
3e6e0aab
GT		 3972 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3973 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3974
9c3e4aab
MT		 3975 /* Older userspace won't unhalt the vcpu on reset. */
3976 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3977 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3978 !(vcpu->arch.cr0 & X86_CR0_PE))
3979 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3980
b6c7a5dc
HB		 3981 vcpu_put(vcpu);
3982
3983 return 0;
3984}
3985
3986int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3987 struct kvm_debug_guest *dbg)
3988{
3989 int r;
3990
3991 vcpu_load(vcpu);
3992
3993 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3994
3995 vcpu_put(vcpu);
3996
3997 return r;
3998}
3999
d0752060
HB		 4000/*
4001 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4002 * we have asm/x86/processor.h
4003 */
4004struct fxsave {
4005 u16 cwd;
4006 u16 swd;
4007 u16 twd;
4008 u16 fop;
4009 u64 rip;
4010 u64 rdp;
4011 u32 mxcsr;
4012 u32 mxcsr_mask;
4013 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4014#ifdef CONFIG_X86_64
4015 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4016#else
4017 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4018#endif
4019};
4020
8b006791
ZX		 4021/*
4022 * Translate a guest virtual address to a guest physical address.
4023 */
4024int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4025 struct kvm_translation *tr)
4026{
4027 unsigned long vaddr = tr->linear_address;
4028 gpa_t gpa;
4029
4030 vcpu_load(vcpu);
72dc67a6 4031 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4032 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4033 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4034 tr->physical_address = gpa;
4035 tr->valid = gpa != UNMAPPED_GVA;
4036 tr->writeable = 1;
4037 tr->usermode = 0;
8b006791
ZX		 4038 vcpu_put(vcpu);
4039
4040 return 0;
4041}
4042
d0752060
HB		 4043int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4044{
ad312c7c 4045 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4046
4047 vcpu_load(vcpu);
4048
4049 memcpy(fpu->fpr, fxsave->st_space, 128);
4050 fpu->fcw = fxsave->cwd;
4051 fpu->fsw = fxsave->swd;
4052 fpu->ftwx = fxsave->twd;
4053 fpu->last_opcode = fxsave->fop;
4054 fpu->last_ip = fxsave->rip;
4055 fpu->last_dp = fxsave->rdp;
4056 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4057
4058 vcpu_put(vcpu);
4059
4060 return 0;
4061}
4062
4063int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4064{
ad312c7c 4065 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4066
4067 vcpu_load(vcpu);
4068
4069 memcpy(fxsave->st_space, fpu->fpr, 128);
4070 fxsave->cwd = fpu->fcw;
4071 fxsave->swd = fpu->fsw;
4072 fxsave->twd = fpu->ftwx;
4073 fxsave->fop = fpu->last_opcode;
4074 fxsave->rip = fpu->last_ip;
4075 fxsave->rdp = fpu->last_dp;
4076 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4077
4078 vcpu_put(vcpu);
4079
4080 return 0;
4081}
4082
4083void fx_init(struct kvm_vcpu *vcpu)
4084{
4085 unsigned after_mxcsr_mask;
4086
bc1a34f1
AA		 4087 /*
4088 * Touch the fpu the first time in non atomic context as if
4089 * this is the first fpu instruction the exception handler
4090 * will fire before the instruction returns and it'll have to
4091 * allocate ram with GFP_KERNEL.
4092 */
4093 if (!used_math())
d6e88aec 4094 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4095
d0752060
HB		 4096 /* Initialize guest FPU by resetting ours and saving into guest's */
4097 preempt_disable();
d6e88aec
AK		 4098 kvm_fx_save(&vcpu->arch.host_fx_image);
4099 kvm_fx_finit();
4100 kvm_fx_save(&vcpu->arch.guest_fx_image);
4101 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4102 preempt_enable();
4103
ad312c7c 4104 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4105 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4106 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4107 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4108 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4109}
4110EXPORT_SYMBOL_GPL(fx_init);
4111
4112void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4113{
4114 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4115 return;
4116
4117 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4118 kvm_fx_save(&vcpu->arch.host_fx_image);
4119 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4120}
4121EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4122
4123void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4124{
4125 if (!vcpu->guest_fpu_loaded)
4126 return;
4127
4128 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4129 kvm_fx_save(&vcpu->arch.guest_fx_image);
4130 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4131 ++vcpu->stat.fpu_reload;
d0752060
HB		 4132}
4133EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4134
4135void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4136{
4137 kvm_x86_ops->vcpu_free(vcpu);
4138}
4139
4140struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4141 unsigned int id)
4142{
26e5215f
AK		 4143 return kvm_x86_ops->vcpu_create(kvm, id);
4144}
e9b11c17 4145
26e5215f
AK		 4146int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4147{
4148 int r;
e9b11c17
ZX		 4149
4150 /* We do fxsave: this must be aligned. */
ad312c7c 4151 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 4152
4153 vcpu_load(vcpu);
4154 r = kvm_arch_vcpu_reset(vcpu);
4155 if (r == 0)
4156 r = kvm_mmu_setup(vcpu);
4157 vcpu_put(vcpu);
4158 if (r < 0)
4159 goto free_vcpu;
4160
26e5215f 4161 return 0;
e9b11c17
ZX		 4162free_vcpu:
4163 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4164 return r;
e9b11c17
ZX		 4165}
4166
d40ccc62 4167void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4168{
4169 vcpu_load(vcpu);
4170 kvm_mmu_unload(vcpu);
4171 vcpu_put(vcpu);
4172
4173 kvm_x86_ops->vcpu_free(vcpu);
4174}
4175
4176int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4177{
4178 return kvm_x86_ops->vcpu_reset(vcpu);
4179}
4180
4181void kvm_arch_hardware_enable(void *garbage)
4182{
4183 kvm_x86_ops->hardware_enable(garbage);
4184}
4185
4186void kvm_arch_hardware_disable(void *garbage)
4187{
4188 kvm_x86_ops->hardware_disable(garbage);
4189}
4190
4191int kvm_arch_hardware_setup(void)
4192{
4193 return kvm_x86_ops->hardware_setup();
4194}
4195
4196void kvm_arch_hardware_unsetup(void)
4197{
4198 kvm_x86_ops->hardware_unsetup();
4199}
4200
4201void kvm_arch_check_processor_compat(void *rtn)
4202{
4203 kvm_x86_ops->check_processor_compatibility(rtn);
4204}
4205
4206int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4207{
4208 struct page *page;
4209 struct kvm *kvm;
4210 int r;
4211
4212 BUG_ON(vcpu->kvm == NULL);
4213 kvm = vcpu->kvm;
4214
ad312c7c 4215 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4216 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4217 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4218 else
a4535290 4219 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4220
4221 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4222 if (!page) {
4223 r = -ENOMEM;
4224 goto fail;
4225 }
ad312c7c 4226 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4227
4228 r = kvm_mmu_create(vcpu);
4229 if (r < 0)
4230 goto fail_free_pio_data;
4231
4232 if (irqchip_in_kernel(kvm)) {
4233 r = kvm_create_lapic(vcpu);
4234 if (r < 0)
4235 goto fail_mmu_destroy;
4236 }
4237
4238 return 0;
4239
4240fail_mmu_destroy:
4241 kvm_mmu_destroy(vcpu);
4242fail_free_pio_data:
ad312c7c 4243 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4244fail:
4245 return r;
4246}
4247
4248void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4249{
4250 kvm_free_lapic(vcpu);
3200f405 4251 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4252 kvm_mmu_destroy(vcpu);
3200f405 4253 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4254 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4255}
d19a9cd2
ZX		 4256
4257struct kvm *kvm_arch_create_vm(void)
4258{
4259 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4260
4261 if (!kvm)
4262 return ERR_PTR(-ENOMEM);
4263
f05e70ac 4264 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4265 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2
ZX		 4266
4267 return kvm;
4268}
4269
4270static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4271{
4272 vcpu_load(vcpu);
4273 kvm_mmu_unload(vcpu);
4274 vcpu_put(vcpu);
4275}
4276
4277static void kvm_free_vcpus(struct kvm *kvm)
4278{
4279 unsigned int i;
4280
4281 /*
4282 * Unpin any mmu pages first.
4283 */
4284 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4285 if (kvm->vcpus[i])
4286 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4287 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4288 if (kvm->vcpus[i]) {
4289 kvm_arch_vcpu_free(kvm->vcpus[i]);
4290 kvm->vcpus[i] = NULL;
4291 }
4292 }
4293
4294}
4295
4296void kvm_arch_destroy_vm(struct kvm *kvm)
4297{
62c476c7 4298 kvm_iommu_unmap_guest(kvm);
bfadaded 4299 kvm_free_all_assigned_devices(kvm);
7837699f 4300 kvm_free_pit(kvm);
d7deeeb0
ZX		 4301 kfree(kvm->arch.vpic);
4302 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4303 kvm_free_vcpus(kvm);
4304 kvm_free_physmem(kvm);
3d45830c
AK		 4305 if (kvm->arch.apic_access_page)
4306 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4307 if (kvm->arch.ept_identity_pagetable)
4308 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4309 kfree(kvm);
4310}
0de10343
ZX		 4311
4312int kvm_arch_set_memory_region(struct kvm *kvm,
4313 struct kvm_userspace_memory_region *mem,
4314 struct kvm_memory_slot old,
4315 int user_alloc)
4316{
4317 int npages = mem->memory_size >> PAGE_SHIFT;
4318 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4319
4320 /*To keep backward compatibility with older userspace,
4321 *x86 needs to hanlde !user_alloc case.
4322 */
4323 if (!user_alloc) {
4324 if (npages && !old.rmap) {
604b38ac
AA		 4325 unsigned long userspace_addr;
4326
72dc67a6 4327 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4328 userspace_addr = do_mmap(NULL, 0,
4329 npages * PAGE_SIZE,
4330 PROT_READ | PROT_WRITE,
acee3c04 4331 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4332 0);
72dc67a6 4333 up_write(&current->mm->mmap_sem);
0de10343 4334
604b38ac
AA		 4335 if (IS_ERR((void *)userspace_addr))
4336 return PTR_ERR((void *)userspace_addr);
4337
4338 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4339 spin_lock(&kvm->mmu_lock);
4340 memslot->userspace_addr = userspace_addr;
4341 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4342 } else {
4343 if (!old.user_alloc && old.rmap) {
4344 int ret;
4345
72dc67a6 4346 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4347 ret = do_munmap(current->mm, old.userspace_addr,
4348 old.npages * PAGE_SIZE);
72dc67a6 4349 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4350 if (ret < 0)
4351 printk(KERN_WARNING
4352 "kvm_vm_ioctl_set_memory_region: "
4353 "failed to munmap memory\n");
4354 }
4355 }
4356 }
4357
f05e70ac 4358 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4359 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4360 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4361 }
4362
4363 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4364 kvm_flush_remote_tlbs(kvm);
4365
4366 return 0;
4367}
1d737c8a 4368
34d4cb8f
MT		 4369void kvm_arch_flush_shadow(struct kvm *kvm)
4370{
4371 kvm_mmu_zap_all(kvm);
4372}
4373
1d737c8a
ZX		 4374int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4375{
a4535290
AK		 4376 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4377 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4378}
5736199a
ZX		 4379
4380static void vcpu_kick_intr(void *info)
4381{
4382#ifdef DEBUG
4383 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4384 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4385#endif
4386}
4387
4388void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4389{
4390 int ipi_pcpu = vcpu->cpu;
e9571ed5 4391 int cpu = get_cpu();
5736199a
ZX		 4392
4393 if (waitqueue_active(&vcpu->wq)) {
4394 wake_up_interruptible(&vcpu->wq);
4395 ++vcpu->stat.halt_wakeup;
4396 }
e9571ed5
MT		 4397 /*
4398 * We may be called synchronously with irqs disabled in guest mode,
4399 * So need not to call smp_call_function_single() in that case.
4400 */
4401 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4402 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4403 put_cpu();
5736199a 4404}
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