]> bbs.cooldavid.org Git - net-next-2.6.git/blame - arch/x86/kvm/x86.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: Avoid vmwrite(HOST_RSP) when possible
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
5fdbf976 22#include "kvm_cache_regs.h"
26eef70c 23#include "x86.h"
313a3dc7 24
18068523 25#include <linux/clocksource.h>
313a3dc7
CO		 26#include <linux/kvm.h>
27#include <linux/fs.h>
28#include <linux/vmalloc.h>
5fb76f9b 29#include <linux/module.h>
0de10343 30#include <linux/mman.h>
2bacc55c 31#include <linux/highmem.h>
043405e1
CO		 32
33#include <asm/uaccess.h>
d825ed0a 34#include <asm/msr.h>
a5f61300 35#include <asm/desc.h>
043405e1 36
313a3dc7 37#define MAX_IO_MSRS 256
a03490ed
CO		 38#define CR0_RESERVED_BITS \
39 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
40 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
41 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
42#define CR4_RESERVED_BITS \
43 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
44 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
45 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
46 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
47
48#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 49/* EFER defaults:
50 * - enable syscall per default because its emulated by KVM
51 * - enable LME and LMA per default on 64 bit KVM
52 */
53#ifdef CONFIG_X86_64
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
55#else
56static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
57#endif
313a3dc7 58
ba1389b7
AK		 59#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
60#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 61
674eea0f
AK		 62static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
63 struct kvm_cpuid_entry2 __user *entries);
64
97896d04 65struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 66EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 67
417bc304 68struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 69 { "pf_fixed", VCPU_STAT(pf_fixed) },
70 { "pf_guest", VCPU_STAT(pf_guest) },
71 { "tlb_flush", VCPU_STAT(tlb_flush) },
72 { "invlpg", VCPU_STAT(invlpg) },
73 { "exits", VCPU_STAT(exits) },
74 { "io_exits", VCPU_STAT(io_exits) },
75 { "mmio_exits", VCPU_STAT(mmio_exits) },
76 { "signal_exits", VCPU_STAT(signal_exits) },
77 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 78 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 79 { "halt_exits", VCPU_STAT(halt_exits) },
80 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 81 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 82 { "request_irq", VCPU_STAT(request_irq_exits) },
83 { "irq_exits", VCPU_STAT(irq_exits) },
84 { "host_state_reload", VCPU_STAT(host_state_reload) },
85 { "efer_reload", VCPU_STAT(efer_reload) },
86 { "fpu_reload", VCPU_STAT(fpu_reload) },
87 { "insn_emulation", VCPU_STAT(insn_emulation) },
88 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 89 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
90 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
91 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
92 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
93 { "mmu_flooded", VM_STAT(mmu_flooded) },
94 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 95 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 96 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 97 { "largepages", VM_STAT(lpages) },
417bc304
HB		 98 { NULL }
99};
100
101
5fb76f9b
CO		 102unsigned long segment_base(u16 selector)
103{
104 struct descriptor_table gdt;
a5f61300 105 struct desc_struct *d;
5fb76f9b
CO		 106 unsigned long table_base;
107 unsigned long v;
108
109 if (selector == 0)
110 return 0;
111
112 asm("sgdt %0" : "=m"(gdt));
113 table_base = gdt.base;
114
115 if (selector & 4) { /* from ldt */
116 u16 ldt_selector;
117
118 asm("sldt %0" : "=g"(ldt_selector));
119 table_base = segment_base(ldt_selector);
120 }
a5f61300
AK		 121 d = (struct desc_struct *)(table_base + (selector & ~7));
122 v = d->base0 | ((unsigned long)d->base1 << 16) |
123 ((unsigned long)d->base2 << 24);
5fb76f9b 124#ifdef CONFIG_X86_64
a5f61300
AK		 125 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
126 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 127#endif
128 return v;
129}
130EXPORT_SYMBOL_GPL(segment_base);
131
6866b83e
CO		 132u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
133{
134 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 135 return vcpu->arch.apic_base;
6866b83e 136 else
ad312c7c 137 return vcpu->arch.apic_base;
6866b83e
CO		 138}
139EXPORT_SYMBOL_GPL(kvm_get_apic_base);
140
141void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
142{
143 /* TODO: reserve bits check */
144 if (irqchip_in_kernel(vcpu->kvm))
145 kvm_lapic_set_base(vcpu, data);
146 else
ad312c7c 147 vcpu->arch.apic_base = data;
6866b83e
CO		 148}
149EXPORT_SYMBOL_GPL(kvm_set_apic_base);
150
298101da
AK		 151void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
152{
ad312c7c
ZX		 153 WARN_ON(vcpu->arch.exception.pending);
154 vcpu->arch.exception.pending = true;
155 vcpu->arch.exception.has_error_code = false;
156 vcpu->arch.exception.nr = nr;
298101da
AK		 157}
158EXPORT_SYMBOL_GPL(kvm_queue_exception);
159
c3c91fee
AK		 160void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
161 u32 error_code)
162{
163 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 164 if (vcpu->arch.exception.pending) {
165 if (vcpu->arch.exception.nr == PF_VECTOR) {
166 printk(KERN_DEBUG "kvm: inject_page_fault:"
167 " double fault 0x%lx\n", addr);
168 vcpu->arch.exception.nr = DF_VECTOR;
169 vcpu->arch.exception.error_code = 0;
170 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
171 /* triple fault -> shutdown */
172 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
173 }
c3c91fee
AK		 174 return;
175 }
ad312c7c 176 vcpu->arch.cr2 = addr;
c3c91fee
AK		 177 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
178}
179
3419ffc8
SY		 180void kvm_inject_nmi(struct kvm_vcpu *vcpu)
181{
182 vcpu->arch.nmi_pending = 1;
183}
184EXPORT_SYMBOL_GPL(kvm_inject_nmi);
185
298101da
AK		 186void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
187{
ad312c7c
ZX		 188 WARN_ON(vcpu->arch.exception.pending);
189 vcpu->arch.exception.pending = true;
190 vcpu->arch.exception.has_error_code = true;
191 vcpu->arch.exception.nr = nr;
192 vcpu->arch.exception.error_code = error_code;
298101da
AK		 193}
194EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
195
196static void __queue_exception(struct kvm_vcpu *vcpu)
197{
ad312c7c
ZX		 198 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
199 vcpu->arch.exception.has_error_code,
200 vcpu->arch.exception.error_code);
298101da
AK		 201}
202
a03490ed
CO		 203/*
204 * Load the pae pdptrs. Return true is they are all valid.
205 */
206int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
207{
208 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
209 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
210 int i;
211 int ret;
ad312c7c 212 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 213
a03490ed
CO		 214 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
215 offset * sizeof(u64), sizeof(pdpte));
216 if (ret < 0) {
217 ret = 0;
218 goto out;
219 }
220 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
221 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
222 ret = 0;
223 goto out;
224 }
225 }
226 ret = 1;
227
ad312c7c 228 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 229out:
a03490ed
CO		 230
231 return ret;
232}
cc4b6871 233EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 234
d835dfec
AK		 235static bool pdptrs_changed(struct kvm_vcpu *vcpu)
236{
ad312c7c 237 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 238 bool changed = true;
239 int r;
240
241 if (is_long_mode(vcpu) || !is_pae(vcpu))
242 return false;
243
ad312c7c 244 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 245 if (r < 0)
246 goto out;
ad312c7c 247 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 248out:
d835dfec
AK		 249
250 return changed;
251}
252
2d3ad1f4 253void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 254{
255 if (cr0 & CR0_RESERVED_BITS) {
256 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 257 cr0, vcpu->arch.cr0);
c1a5d4f9 258 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 259 return;
260 }
261
262 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
263 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 264 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 265 return;
266 }
267
268 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
269 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
270 "and a clear PE flag\n");
c1a5d4f9 271 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 272 return;
273 }
274
275 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
276#ifdef CONFIG_X86_64
ad312c7c 277 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 278 int cs_db, cs_l;
279
280 if (!is_pae(vcpu)) {
281 printk(KERN_DEBUG "set_cr0: #GP, start paging "
282 "in long mode while PAE is disabled\n");
c1a5d4f9 283 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 284 return;
285 }
286 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
287 if (cs_l) {
288 printk(KERN_DEBUG "set_cr0: #GP, start paging "
289 "in long mode while CS.L == 1\n");
c1a5d4f9 290 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 291 return;
292
293 }
294 } else
295#endif
ad312c7c 296 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 297 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
298 "reserved bits\n");
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302
303 }
304
305 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 306 vcpu->arch.cr0 = cr0;
a03490ed 307
a03490ed 308 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 309 return;
310}
2d3ad1f4 311EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 312
2d3ad1f4 313void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 314{
2d3ad1f4 315 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 316 KVMTRACE_1D(LMSW, vcpu,
317 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
318 handler);
a03490ed 319}
2d3ad1f4 320EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 321
2d3ad1f4 322void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 323{
324 if (cr4 & CR4_RESERVED_BITS) {
325 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 326 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 327 return;
328 }
329
330 if (is_long_mode(vcpu)) {
331 if (!(cr4 & X86_CR4_PAE)) {
332 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
333 "in long mode\n");
c1a5d4f9 334 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 335 return;
336 }
337 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 338 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 339 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 340 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 341 return;
342 }
343
344 if (cr4 & X86_CR4_VMXE) {
345 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 346 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 347 return;
348 }
349 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 350 vcpu->arch.cr4 = cr4;
a03490ed 351 kvm_mmu_reset_context(vcpu);
a03490ed 352}
2d3ad1f4 353EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 354
2d3ad1f4 355void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 356{
ad312c7c 357 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 358 kvm_mmu_flush_tlb(vcpu);
359 return;
360 }
361
a03490ed
CO		 362 if (is_long_mode(vcpu)) {
363 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368 } else {
369 if (is_pae(vcpu)) {
370 if (cr3 & CR3_PAE_RESERVED_BITS) {
371 printk(KERN_DEBUG
372 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 373 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 374 return;
375 }
376 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
377 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
378 "reserved bits\n");
c1a5d4f9 379 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 380 return;
381 }
382 }
383 /*
384 * We don't check reserved bits in nonpae mode, because
385 * this isn't enforced, and VMware depends on this.
386 */
387 }
388
a03490ed
CO		 389 /*
390 * Does the new cr3 value map to physical memory? (Note, we
391 * catch an invalid cr3 even in real-mode, because it would
392 * cause trouble later on when we turn on paging anyway.)
393 *
394 * A real CPU would silently accept an invalid cr3 and would
395 * attempt to use it - with largely undefined (and often hard
396 * to debug) behavior on the guest side.
397 */
398 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 399 kvm_inject_gp(vcpu, 0);
a03490ed 400 else {
ad312c7c
ZX		 401 vcpu->arch.cr3 = cr3;
402 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 403 }
a03490ed 404}
2d3ad1f4 405EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 406
2d3ad1f4 407void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 408{
409 if (cr8 & CR8_RESERVED_BITS) {
410 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 411 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 412 return;
413 }
414 if (irqchip_in_kernel(vcpu->kvm))
415 kvm_lapic_set_tpr(vcpu, cr8);
416 else
ad312c7c 417 vcpu->arch.cr8 = cr8;
a03490ed 418}
2d3ad1f4 419EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 420
2d3ad1f4 421unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 422{
423 if (irqchip_in_kernel(vcpu->kvm))
424 return kvm_lapic_get_cr8(vcpu);
425 else
ad312c7c 426 return vcpu->arch.cr8;
a03490ed 427}
2d3ad1f4 428EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 429
043405e1
CO		 430/*
431 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
432 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
433 *
434 * This list is modified at module load time to reflect the
435 * capabilities of the host cpu.
436 */
437static u32 msrs_to_save[] = {
438 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
439 MSR_K6_STAR,
440#ifdef CONFIG_X86_64
441 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
442#endif
18068523 443 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 444 MSR_IA32_PERF_STATUS,
043405e1
CO		 445};
446
447static unsigned num_msrs_to_save;
448
449static u32 emulated_msrs[] = {
450 MSR_IA32_MISC_ENABLE,
451};
452
15c4a640
CO		 453static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
454{
f2b4b7dd 455 if (efer & efer_reserved_bits) {
15c4a640
CO		 456 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
457 efer);
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 459 return;
460 }
461
462 if (is_paging(vcpu)
ad312c7c 463 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 464 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 465 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 466 return;
467 }
468
469 kvm_x86_ops->set_efer(vcpu, efer);
470
471 efer &= ~EFER_LMA;
ad312c7c 472 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 473
ad312c7c 474 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 475}
476
f2b4b7dd
JR		 477void kvm_enable_efer_bits(u64 mask)
478{
479 efer_reserved_bits &= ~mask;
480}
481EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
482
483
15c4a640
CO		 484/*
485 * Writes msr value into into the appropriate "register".
486 * Returns 0 on success, non-0 otherwise.
487 * Assumes vcpu_load() was already called.
488 */
489int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
490{
491 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
492}
493
313a3dc7
CO		 494/*
495 * Adapt set_msr() to msr_io()'s calling convention
496 */
497static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
498{
499 return kvm_set_msr(vcpu, index, *data);
500}
501
18068523
GOC		 502static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
503{
504 static int version;
50d0a0f9
GH		 505 struct pvclock_wall_clock wc;
506 struct timespec now, sys, boot;
18068523
GOC		 507
508 if (!wall_clock)
509 return;
510
511 version++;
512
18068523
GOC		 513 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
514
50d0a0f9
GH		 515 /*
516 * The guest calculates current wall clock time by adding
517 * system time (updated by kvm_write_guest_time below) to the
518 * wall clock specified here. guest system time equals host
519 * system time for us, thus we must fill in host boot time here.
520 */
521 now = current_kernel_time();
522 ktime_get_ts(&sys);
523 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
524
525 wc.sec = boot.tv_sec;
526 wc.nsec = boot.tv_nsec;
527 wc.version = version;
18068523
GOC		 528
529 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
530
531 version++;
532 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 533}
534
50d0a0f9
GH		 535static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
536{
537 uint32_t quotient, remainder;
538
539 /* Don't try to replace with do_div(), this one calculates
540 * "(dividend << 32) / divisor" */
541 __asm__ ( "divl %4"
542 : "=a" (quotient), "=d" (remainder)
543 : "0" (0), "1" (dividend), "r" (divisor) );
544 return quotient;
545}
546
547static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
548{
549 uint64_t nsecs = 1000000000LL;
550 int32_t shift = 0;
551 uint64_t tps64;
552 uint32_t tps32;
553
554 tps64 = tsc_khz * 1000LL;
555 while (tps64 > nsecs*2) {
556 tps64 >>= 1;
557 shift--;
558 }
559
560 tps32 = (uint32_t)tps64;
561 while (tps32 <= (uint32_t)nsecs) {
562 tps32 <<= 1;
563 shift++;
564 }
565
566 hv_clock->tsc_shift = shift;
567 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
568
569 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
570 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
571 hv_clock->tsc_to_system_mul);
572}
573
18068523
GOC		 574static void kvm_write_guest_time(struct kvm_vcpu *v)
575{
576 struct timespec ts;
577 unsigned long flags;
578 struct kvm_vcpu_arch *vcpu = &v->arch;
579 void *shared_kaddr;
580
581 if ((!vcpu->time_page))
582 return;
583
50d0a0f9
GH		 584 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
585 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
586 vcpu->hv_clock_tsc_khz = tsc_khz;
587 }
588
18068523
GOC		 589 /* Keep irq disabled to prevent changes to the clock */
590 local_irq_save(flags);
591 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
592 &vcpu->hv_clock.tsc_timestamp);
593 ktime_get_ts(&ts);
594 local_irq_restore(flags);
595
596 /* With all the info we got, fill in the values */
597
598 vcpu->hv_clock.system_time = ts.tv_nsec +
599 (NSEC_PER_SEC * (u64)ts.tv_sec);
600 /*
601 * The interface expects us to write an even number signaling that the
602 * update is finished. Since the guest won't see the intermediate
50d0a0f9 603 * state, we just increase by 2 at the end.
18068523 604 */
50d0a0f9 605 vcpu->hv_clock.version += 2;
18068523
GOC		 606
607 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
608
609 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 610 sizeof(vcpu->hv_clock));
18068523
GOC		 611
612 kunmap_atomic(shared_kaddr, KM_USER0);
613
614 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
615}
616
9ba075a6
AK		 617static bool msr_mtrr_valid(unsigned msr)
618{
619 switch (msr) {
620 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
621 case MSR_MTRRfix64K_00000:
622 case MSR_MTRRfix16K_80000:
623 case MSR_MTRRfix16K_A0000:
624 case MSR_MTRRfix4K_C0000:
625 case MSR_MTRRfix4K_C8000:
626 case MSR_MTRRfix4K_D0000:
627 case MSR_MTRRfix4K_D8000:
628 case MSR_MTRRfix4K_E0000:
629 case MSR_MTRRfix4K_E8000:
630 case MSR_MTRRfix4K_F0000:
631 case MSR_MTRRfix4K_F8000:
632 case MSR_MTRRdefType:
633 case MSR_IA32_CR_PAT:
634 return true;
635 case 0x2f8:
636 return true;
637 }
638 return false;
639}
640
641static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
642{
643 if (!msr_mtrr_valid(msr))
644 return 1;
645
646 vcpu->arch.mtrr[msr - 0x200] = data;
647 return 0;
648}
15c4a640
CO		 649
650int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
651{
652 switch (msr) {
15c4a640
CO		 653 case MSR_EFER:
654 set_efer(vcpu, data);
655 break;
15c4a640
CO		 656 case MSR_IA32_MC0_STATUS:
657 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 658 __func__, data);
15c4a640
CO		 659 break;
660 case MSR_IA32_MCG_STATUS:
661 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 662 __func__, data);
15c4a640 663 break;
c7ac679c
JR		 664 case MSR_IA32_MCG_CTL:
665 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 666 __func__, data);
c7ac679c 667 break;
15c4a640
CO		 668 case MSR_IA32_UCODE_REV:
669 case MSR_IA32_UCODE_WRITE:
15c4a640 670 break;
9ba075a6
AK		 671 case 0x200 ... 0x2ff:
672 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 673 case MSR_IA32_APICBASE:
674 kvm_set_apic_base(vcpu, data);
675 break;
676 case MSR_IA32_MISC_ENABLE:
ad312c7c 677 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 678 break;
18068523
GOC		 679 case MSR_KVM_WALL_CLOCK:
680 vcpu->kvm->arch.wall_clock = data;
681 kvm_write_wall_clock(vcpu->kvm, data);
682 break;
683 case MSR_KVM_SYSTEM_TIME: {
684 if (vcpu->arch.time_page) {
685 kvm_release_page_dirty(vcpu->arch.time_page);
686 vcpu->arch.time_page = NULL;
687 }
688
689 vcpu->arch.time = data;
690
691 /* we verify if the enable bit is set... */
692 if (!(data & 1))
693 break;
694
695 /* ...but clean it before doing the actual write */
696 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
697
18068523 698 down_read(&current->mm->mmap_sem);
18068523
GOC		 699 vcpu->arch.time_page =
700 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 701 up_read(&current->mm->mmap_sem);
702
703 if (is_error_page(vcpu->arch.time_page)) {
704 kvm_release_page_clean(vcpu->arch.time_page);
705 vcpu->arch.time_page = NULL;
706 }
707
708 kvm_write_guest_time(vcpu);
709 break;
710 }
15c4a640 711 default:
565f1fbd 712 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_msr_common);
718
719
720/*
721 * Reads an msr value (of 'msr_index') into 'pdata'.
722 * Returns 0 on success, non-0 otherwise.
723 * Assumes vcpu_load() was already called.
724 */
725int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
726{
727 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
728}
729
9ba075a6
AK		 730static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
731{
732 if (!msr_mtrr_valid(msr))
733 return 1;
734
735 *pdata = vcpu->arch.mtrr[msr - 0x200];
736 return 0;
737}
738
15c4a640
CO		 739int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
740{
741 u64 data;
742
743 switch (msr) {
744 case 0xc0010010: /* SYSCFG */
745 case 0xc0010015: /* HWCR */
746 case MSR_IA32_PLATFORM_ID:
747 case MSR_IA32_P5_MC_ADDR:
748 case MSR_IA32_P5_MC_TYPE:
749 case MSR_IA32_MC0_CTL:
750 case MSR_IA32_MCG_STATUS:
751 case MSR_IA32_MCG_CAP:
c7ac679c 752 case MSR_IA32_MCG_CTL:
15c4a640
CO		 753 case MSR_IA32_MC0_MISC:
754 case MSR_IA32_MC0_MISC+4:
755 case MSR_IA32_MC0_MISC+8:
756 case MSR_IA32_MC0_MISC+12:
757 case MSR_IA32_MC0_MISC+16:
758 case MSR_IA32_UCODE_REV:
15c4a640 759 case MSR_IA32_EBL_CR_POWERON:
15c4a640
CO		 760 data = 0;
761 break;
9ba075a6
AK		 762 case MSR_MTRRcap:
763 data = 0x500 | KVM_NR_VAR_MTRR;
764 break;
765 case 0x200 ... 0x2ff:
766 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 767 case 0xcd: /* fsb frequency */
768 data = 3;
769 break;
770 case MSR_IA32_APICBASE:
771 data = kvm_get_apic_base(vcpu);
772 break;
773 case MSR_IA32_MISC_ENABLE:
ad312c7c 774 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 775 break;
847f0ad8
AG		 776 case MSR_IA32_PERF_STATUS:
777 /* TSC increment by tick */
778 data = 1000ULL;
779 /* CPU multiplier */
780 data |= (((uint64_t)4ULL) << 40);
781 break;
15c4a640 782 case MSR_EFER:
ad312c7c 783 data = vcpu->arch.shadow_efer;
15c4a640 784 break;
18068523
GOC		 785 case MSR_KVM_WALL_CLOCK:
786 data = vcpu->kvm->arch.wall_clock;
787 break;
788 case MSR_KVM_SYSTEM_TIME:
789 data = vcpu->arch.time;
790 break;
15c4a640
CO		 791 default:
792 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
793 return 1;
794 }
795 *pdata = data;
796 return 0;
797}
798EXPORT_SYMBOL_GPL(kvm_get_msr_common);
799
313a3dc7
CO		 800/*
801 * Read or write a bunch of msrs. All parameters are kernel addresses.
802 *
803 * @return number of msrs set successfully.
804 */
805static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
806 struct kvm_msr_entry *entries,
807 int (*do_msr)(struct kvm_vcpu *vcpu,
808 unsigned index, u64 *data))
809{
810 int i;
811
812 vcpu_load(vcpu);
813
3200f405 814 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 815 for (i = 0; i < msrs->nmsrs; ++i)
816 if (do_msr(vcpu, entries[i].index, &entries[i].data))
817 break;
3200f405 818 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 819
820 vcpu_put(vcpu);
821
822 return i;
823}
824
825/*
826 * Read or write a bunch of msrs. Parameters are user addresses.
827 *
828 * @return number of msrs set successfully.
829 */
830static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
831 int (*do_msr)(struct kvm_vcpu *vcpu,
832 unsigned index, u64 *data),
833 int writeback)
834{
835 struct kvm_msrs msrs;
836 struct kvm_msr_entry *entries;
837 int r, n;
838 unsigned size;
839
840 r = -EFAULT;
841 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
842 goto out;
843
844 r = -E2BIG;
845 if (msrs.nmsrs >= MAX_IO_MSRS)
846 goto out;
847
848 r = -ENOMEM;
849 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
850 entries = vmalloc(size);
851 if (!entries)
852 goto out;
853
854 r = -EFAULT;
855 if (copy_from_user(entries, user_msrs->entries, size))
856 goto out_free;
857
858 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
859 if (r < 0)
860 goto out_free;
861
862 r = -EFAULT;
863 if (writeback && copy_to_user(user_msrs->entries, entries, size))
864 goto out_free;
865
866 r = n;
867
868out_free:
869 vfree(entries);
870out:
871 return r;
872}
873
018d00d2
ZX		 874int kvm_dev_ioctl_check_extension(long ext)
875{
876 int r;
877
878 switch (ext) {
879 case KVM_CAP_IRQCHIP:
880 case KVM_CAP_HLT:
881 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
882 case KVM_CAP_USER_MEMORY:
883 case KVM_CAP_SET_TSS_ADDR:
07716717 884 case KVM_CAP_EXT_CPUID:
18068523 885 case KVM_CAP_CLOCKSOURCE:
7837699f 886 case KVM_CAP_PIT:
a28e4f5a 887 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 888 case KVM_CAP_MP_STATE:
ed848624 889 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 890 r = 1;
891 break;
542472b5
LV		 892 case KVM_CAP_COALESCED_MMIO:
893 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
894 break;
774ead3a
AK		 895 case KVM_CAP_VAPIC:
896 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
897 break;
f725230a
AK		 898 case KVM_CAP_NR_VCPUS:
899 r = KVM_MAX_VCPUS;
900 break;
a988b910
AK		 901 case KVM_CAP_NR_MEMSLOTS:
902 r = KVM_MEMORY_SLOTS;
903 break;
2f333bcb
MT		 904 case KVM_CAP_PV_MMU:
905 r = !tdp_enabled;
906 break;
018d00d2
ZX		 907 default:
908 r = 0;
909 break;
910 }
911 return r;
912
913}
914
043405e1
CO		 915long kvm_arch_dev_ioctl(struct file *filp,
916 unsigned int ioctl, unsigned long arg)
917{
918 void __user *argp = (void __user *)arg;
919 long r;
920
921 switch (ioctl) {
922 case KVM_GET_MSR_INDEX_LIST: {
923 struct kvm_msr_list __user *user_msr_list = argp;
924 struct kvm_msr_list msr_list;
925 unsigned n;
926
927 r = -EFAULT;
928 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
929 goto out;
930 n = msr_list.nmsrs;
931 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
932 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
933 goto out;
934 r = -E2BIG;
935 if (n < num_msrs_to_save)
936 goto out;
937 r = -EFAULT;
938 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
939 num_msrs_to_save * sizeof(u32)))
940 goto out;
941 if (copy_to_user(user_msr_list->indices
942 + num_msrs_to_save * sizeof(u32),
943 &emulated_msrs,
944 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
945 goto out;
946 r = 0;
947 break;
948 }
674eea0f
AK		 949 case KVM_GET_SUPPORTED_CPUID: {
950 struct kvm_cpuid2 __user *cpuid_arg = argp;
951 struct kvm_cpuid2 cpuid;
952
953 r = -EFAULT;
954 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
955 goto out;
956 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
957 cpuid_arg->entries);
958 if (r)
959 goto out;
960
961 r = -EFAULT;
962 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
963 goto out;
964 r = 0;
965 break;
966 }
043405e1
CO		 967 default:
968 r = -EINVAL;
969 }
970out:
971 return r;
972}
973
313a3dc7
CO		 974void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
975{
976 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 977 kvm_write_guest_time(vcpu);
313a3dc7
CO		 978}
979
980void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
981{
982 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 983 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 984}
985
07716717 986static int is_efer_nx(void)
313a3dc7
CO		 987{
988 u64 efer;
313a3dc7
CO		 989
990 rdmsrl(MSR_EFER, efer);
07716717
DK		 991 return efer & EFER_NX;
992}
993
994static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
995{
996 int i;
997 struct kvm_cpuid_entry2 *e, *entry;
998
313a3dc7 999 entry = NULL;
ad312c7c
ZX		 1000 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1001 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1002 if (e->function == 0x80000001) {
1003 entry = e;
1004 break;
1005 }
1006 }
07716717 1007 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1008 entry->edx &= ~(1 << 20);
1009 printk(KERN_INFO "kvm: guest NX capability removed\n");
1010 }
1011}
1012
07716717 1013/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1014static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1015 struct kvm_cpuid *cpuid,
1016 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1017{
1018 int r, i;
1019 struct kvm_cpuid_entry *cpuid_entries;
1020
1021 r = -E2BIG;
1022 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1023 goto out;
1024 r = -ENOMEM;
1025 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1026 if (!cpuid_entries)
1027 goto out;
1028 r = -EFAULT;
1029 if (copy_from_user(cpuid_entries, entries,
1030 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1031 goto out_free;
1032 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1033 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1034 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1035 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1036 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1037 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1038 vcpu->arch.cpuid_entries[i].index = 0;
1039 vcpu->arch.cpuid_entries[i].flags = 0;
1040 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1041 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1042 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1043 }
1044 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1045 cpuid_fix_nx_cap(vcpu);
1046 r = 0;
1047
1048out_free:
1049 vfree(cpuid_entries);
1050out:
1051 return r;
1052}
1053
1054static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1055 struct kvm_cpuid2 *cpuid,
1056 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1057{
1058 int r;
1059
1060 r = -E2BIG;
1061 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1062 goto out;
1063 r = -EFAULT;
ad312c7c 1064 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1065 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1066 goto out;
ad312c7c 1067 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1068 return 0;
1069
1070out:
1071 return r;
1072}
1073
07716717
DK		 1074static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1075 struct kvm_cpuid2 *cpuid,
1076 struct kvm_cpuid_entry2 __user *entries)
1077{
1078 int r;
1079
1080 r = -E2BIG;
ad312c7c 1081 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1082 goto out;
1083 r = -EFAULT;
ad312c7c
ZX		 1084 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1085 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1086 goto out;
1087 return 0;
1088
1089out:
ad312c7c 1090 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1091 return r;
1092}
1093
1094static inline u32 bit(int bitno)
1095{
1096 return 1 << (bitno & 31);
1097}
1098
1099static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1100 u32 index)
1101{
1102 entry->function = function;
1103 entry->index = index;
1104 cpuid_count(entry->function, entry->index,
1105 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1106 entry->flags = 0;
1107}
1108
1109static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1110 u32 index, int *nent, int maxnent)
1111{
1112 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1113 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1114 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1115 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1116 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1117 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1118 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1119 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1120 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1121 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1122 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1123 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1124 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1125 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1126 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1127 bit(X86_FEATURE_PGE) |
1128 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1129 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1130 bit(X86_FEATURE_SYSCALL) |
1131 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1132#ifdef CONFIG_X86_64
1133 bit(X86_FEATURE_LM) |
1134#endif
1135 bit(X86_FEATURE_MMXEXT) |
1136 bit(X86_FEATURE_3DNOWEXT) |
1137 bit(X86_FEATURE_3DNOW);
1138 const u32 kvm_supported_word3_x86_features =
1139 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1140 const u32 kvm_supported_word6_x86_features =
1141 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1142
1143 /* all func 2 cpuid_count() should be called on the same cpu */
1144 get_cpu();
1145 do_cpuid_1_ent(entry, function, index);
1146 ++*nent;
1147
1148 switch (function) {
1149 case 0:
1150 entry->eax = min(entry->eax, (u32)0xb);
1151 break;
1152 case 1:
1153 entry->edx &= kvm_supported_word0_x86_features;
1154 entry->ecx &= kvm_supported_word3_x86_features;
1155 break;
1156 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1157 * may return different values. This forces us to get_cpu() before
1158 * issuing the first command, and also to emulate this annoying behavior
1159 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1160 case 2: {
1161 int t, times = entry->eax & 0xff;
1162
1163 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1164 for (t = 1; t < times && *nent < maxnent; ++t) {
1165 do_cpuid_1_ent(&entry[t], function, 0);
1166 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1167 ++*nent;
1168 }
1169 break;
1170 }
1171 /* function 4 and 0xb have additional index. */
1172 case 4: {
14af3f3c 1173 int i, cache_type;
07716717
DK		 1174
1175 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1176 /* read more entries until cache_type is zero */
14af3f3c
HH		 1177 for (i = 1; *nent < maxnent; ++i) {
1178 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1179 if (!cache_type)
1180 break;
14af3f3c
HH		 1181 do_cpuid_1_ent(&entry[i], function, i);
1182 entry[i].flags |=
07716717
DK		 1183 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1184 ++*nent;
1185 }
1186 break;
1187 }
1188 case 0xb: {
14af3f3c 1189 int i, level_type;
07716717
DK		 1190
1191 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1192 /* read more entries until level_type is zero */
14af3f3c
HH		 1193 for (i = 1; *nent < maxnent; ++i) {
1194 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1195 if (!level_type)
1196 break;
14af3f3c
HH		 1197 do_cpuid_1_ent(&entry[i], function, i);
1198 entry[i].flags |=
07716717
DK		 1199 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1200 ++*nent;
1201 }
1202 break;
1203 }
1204 case 0x80000000:
1205 entry->eax = min(entry->eax, 0x8000001a);
1206 break;
1207 case 0x80000001:
1208 entry->edx &= kvm_supported_word1_x86_features;
1209 entry->ecx &= kvm_supported_word6_x86_features;
1210 break;
1211 }
1212 put_cpu();
1213}
1214
674eea0f 1215static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1216 struct kvm_cpuid_entry2 __user *entries)
1217{
1218 struct kvm_cpuid_entry2 *cpuid_entries;
1219 int limit, nent = 0, r = -E2BIG;
1220 u32 func;
1221
1222 if (cpuid->nent < 1)
1223 goto out;
1224 r = -ENOMEM;
1225 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1226 if (!cpuid_entries)
1227 goto out;
1228
1229 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1230 limit = cpuid_entries[0].eax;
1231 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1232 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1233 &nent, cpuid->nent);
1234 r = -E2BIG;
1235 if (nent >= cpuid->nent)
1236 goto out_free;
1237
1238 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1239 limit = cpuid_entries[nent - 1].eax;
1240 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1241 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1242 &nent, cpuid->nent);
1243 r = -EFAULT;
1244 if (copy_to_user(entries, cpuid_entries,
1245 nent * sizeof(struct kvm_cpuid_entry2)))
1246 goto out_free;
1247 cpuid->nent = nent;
1248 r = 0;
1249
1250out_free:
1251 vfree(cpuid_entries);
1252out:
1253 return r;
1254}
1255
313a3dc7
CO		 1256static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1257 struct kvm_lapic_state *s)
1258{
1259 vcpu_load(vcpu);
ad312c7c 1260 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1261 vcpu_put(vcpu);
1262
1263 return 0;
1264}
1265
1266static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1267 struct kvm_lapic_state *s)
1268{
1269 vcpu_load(vcpu);
ad312c7c 1270 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1271 kvm_apic_post_state_restore(vcpu);
1272 vcpu_put(vcpu);
1273
1274 return 0;
1275}
1276
f77bc6a4
ZX		 1277static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1278 struct kvm_interrupt *irq)
1279{
1280 if (irq->irq < 0 || irq->irq >= 256)
1281 return -EINVAL;
1282 if (irqchip_in_kernel(vcpu->kvm))
1283 return -ENXIO;
1284 vcpu_load(vcpu);
1285
ad312c7c
ZX		 1286 set_bit(irq->irq, vcpu->arch.irq_pending);
1287 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1288
1289 vcpu_put(vcpu);
1290
1291 return 0;
1292}
1293
b209749f
AK		 1294static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1295 struct kvm_tpr_access_ctl *tac)
1296{
1297 if (tac->flags)
1298 return -EINVAL;
1299 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1300 return 0;
1301}
1302
313a3dc7
CO		 1303long kvm_arch_vcpu_ioctl(struct file *filp,
1304 unsigned int ioctl, unsigned long arg)
1305{
1306 struct kvm_vcpu *vcpu = filp->private_data;
1307 void __user *argp = (void __user *)arg;
1308 int r;
1309
1310 switch (ioctl) {
1311 case KVM_GET_LAPIC: {
1312 struct kvm_lapic_state lapic;
1313
1314 memset(&lapic, 0, sizeof lapic);
1315 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1316 if (r)
1317 goto out;
1318 r = -EFAULT;
1319 if (copy_to_user(argp, &lapic, sizeof lapic))
1320 goto out;
1321 r = 0;
1322 break;
1323 }
1324 case KVM_SET_LAPIC: {
1325 struct kvm_lapic_state lapic;
1326
1327 r = -EFAULT;
1328 if (copy_from_user(&lapic, argp, sizeof lapic))
1329 goto out;
1330 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1331 if (r)
1332 goto out;
1333 r = 0;
1334 break;
1335 }
f77bc6a4
ZX		 1336 case KVM_INTERRUPT: {
1337 struct kvm_interrupt irq;
1338
1339 r = -EFAULT;
1340 if (copy_from_user(&irq, argp, sizeof irq))
1341 goto out;
1342 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1343 if (r)
1344 goto out;
1345 r = 0;
1346 break;
1347 }
313a3dc7
CO		 1348 case KVM_SET_CPUID: {
1349 struct kvm_cpuid __user *cpuid_arg = argp;
1350 struct kvm_cpuid cpuid;
1351
1352 r = -EFAULT;
1353 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1354 goto out;
1355 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1356 if (r)
1357 goto out;
1358 break;
1359 }
07716717
DK		 1360 case KVM_SET_CPUID2: {
1361 struct kvm_cpuid2 __user *cpuid_arg = argp;
1362 struct kvm_cpuid2 cpuid;
1363
1364 r = -EFAULT;
1365 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1366 goto out;
1367 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1368 cpuid_arg->entries);
1369 if (r)
1370 goto out;
1371 break;
1372 }
1373 case KVM_GET_CPUID2: {
1374 struct kvm_cpuid2 __user *cpuid_arg = argp;
1375 struct kvm_cpuid2 cpuid;
1376
1377 r = -EFAULT;
1378 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1379 goto out;
1380 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1381 cpuid_arg->entries);
1382 if (r)
1383 goto out;
1384 r = -EFAULT;
1385 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1386 goto out;
1387 r = 0;
1388 break;
1389 }
313a3dc7
CO		 1390 case KVM_GET_MSRS:
1391 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1392 break;
1393 case KVM_SET_MSRS:
1394 r = msr_io(vcpu, argp, do_set_msr, 0);
1395 break;
b209749f
AK		 1396 case KVM_TPR_ACCESS_REPORTING: {
1397 struct kvm_tpr_access_ctl tac;
1398
1399 r = -EFAULT;
1400 if (copy_from_user(&tac, argp, sizeof tac))
1401 goto out;
1402 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1403 if (r)
1404 goto out;
1405 r = -EFAULT;
1406 if (copy_to_user(argp, &tac, sizeof tac))
1407 goto out;
1408 r = 0;
1409 break;
1410 };
b93463aa
AK		 1411 case KVM_SET_VAPIC_ADDR: {
1412 struct kvm_vapic_addr va;
1413
1414 r = -EINVAL;
1415 if (!irqchip_in_kernel(vcpu->kvm))
1416 goto out;
1417 r = -EFAULT;
1418 if (copy_from_user(&va, argp, sizeof va))
1419 goto out;
1420 r = 0;
1421 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1422 break;
1423 }
313a3dc7
CO		 1424 default:
1425 r = -EINVAL;
1426 }
1427out:
1428 return r;
1429}
1430
1fe779f8
CO		 1431static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1432{
1433 int ret;
1434
1435 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1436 return -1;
1437 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1438 return ret;
1439}
1440
1441static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1442 u32 kvm_nr_mmu_pages)
1443{
1444 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1445 return -EINVAL;
1446
72dc67a6 1447 down_write(&kvm->slots_lock);
1fe779f8
CO		 1448
1449 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1450 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1451
72dc67a6 1452 up_write(&kvm->slots_lock);
1fe779f8
CO		 1453 return 0;
1454}
1455
1456static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1457{
f05e70ac 1458 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1459}
1460
e9f85cde
ZX		 1461gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1462{
1463 int i;
1464 struct kvm_mem_alias *alias;
1465
d69fb81f
ZX		 1466 for (i = 0; i < kvm->arch.naliases; ++i) {
1467 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1468 if (gfn >= alias->base_gfn
1469 && gfn < alias->base_gfn + alias->npages)
1470 return alias->target_gfn + gfn - alias->base_gfn;
1471 }
1472 return gfn;
1473}
1474
1fe779f8
CO		 1475/*
1476 * Set a new alias region. Aliases map a portion of physical memory into
1477 * another portion. This is useful for memory windows, for example the PC
1478 * VGA region.
1479 */
1480static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1481 struct kvm_memory_alias *alias)
1482{
1483 int r, n;
1484 struct kvm_mem_alias *p;
1485
1486 r = -EINVAL;
1487 /* General sanity checks */
1488 if (alias->memory_size & (PAGE_SIZE - 1))
1489 goto out;
1490 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1491 goto out;
1492 if (alias->slot >= KVM_ALIAS_SLOTS)
1493 goto out;
1494 if (alias->guest_phys_addr + alias->memory_size
1495 < alias->guest_phys_addr)
1496 goto out;
1497 if (alias->target_phys_addr + alias->memory_size
1498 < alias->target_phys_addr)
1499 goto out;
1500
72dc67a6 1501 down_write(&kvm->slots_lock);
a1708ce8 1502 spin_lock(&kvm->mmu_lock);
1fe779f8 1503
d69fb81f 1504 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1505 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1506 p->npages = alias->memory_size >> PAGE_SHIFT;
1507 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1508
1509 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1510 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1511 break;
d69fb81f 1512 kvm->arch.naliases = n;
1fe779f8 1513
a1708ce8 1514 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1515 kvm_mmu_zap_all(kvm);
1516
72dc67a6 1517 up_write(&kvm->slots_lock);
1fe779f8
CO		 1518
1519 return 0;
1520
1521out:
1522 return r;
1523}
1524
1525static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1526{
1527 int r;
1528
1529 r = 0;
1530 switch (chip->chip_id) {
1531 case KVM_IRQCHIP_PIC_MASTER:
1532 memcpy(&chip->chip.pic,
1533 &pic_irqchip(kvm)->pics[0],
1534 sizeof(struct kvm_pic_state));
1535 break;
1536 case KVM_IRQCHIP_PIC_SLAVE:
1537 memcpy(&chip->chip.pic,
1538 &pic_irqchip(kvm)->pics[1],
1539 sizeof(struct kvm_pic_state));
1540 break;
1541 case KVM_IRQCHIP_IOAPIC:
1542 memcpy(&chip->chip.ioapic,
1543 ioapic_irqchip(kvm),
1544 sizeof(struct kvm_ioapic_state));
1545 break;
1546 default:
1547 r = -EINVAL;
1548 break;
1549 }
1550 return r;
1551}
1552
1553static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1554{
1555 int r;
1556
1557 r = 0;
1558 switch (chip->chip_id) {
1559 case KVM_IRQCHIP_PIC_MASTER:
1560 memcpy(&pic_irqchip(kvm)->pics[0],
1561 &chip->chip.pic,
1562 sizeof(struct kvm_pic_state));
1563 break;
1564 case KVM_IRQCHIP_PIC_SLAVE:
1565 memcpy(&pic_irqchip(kvm)->pics[1],
1566 &chip->chip.pic,
1567 sizeof(struct kvm_pic_state));
1568 break;
1569 case KVM_IRQCHIP_IOAPIC:
1570 memcpy(ioapic_irqchip(kvm),
1571 &chip->chip.ioapic,
1572 sizeof(struct kvm_ioapic_state));
1573 break;
1574 default:
1575 r = -EINVAL;
1576 break;
1577 }
1578 kvm_pic_update_irq(pic_irqchip(kvm));
1579 return r;
1580}
1581
e0f63cb9
SY		 1582static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1583{
1584 int r = 0;
1585
1586 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1587 return r;
1588}
1589
1590static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1591{
1592 int r = 0;
1593
1594 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1595 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1596 return r;
1597}
1598
5bb064dc
ZX		 1599/*
1600 * Get (and clear) the dirty memory log for a memory slot.
1601 */
1602int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1603 struct kvm_dirty_log *log)
1604{
1605 int r;
1606 int n;
1607 struct kvm_memory_slot *memslot;
1608 int is_dirty = 0;
1609
72dc67a6 1610 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1611
1612 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1613 if (r)
1614 goto out;
1615
1616 /* If nothing is dirty, don't bother messing with page tables. */
1617 if (is_dirty) {
1618 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1619 kvm_flush_remote_tlbs(kvm);
1620 memslot = &kvm->memslots[log->slot];
1621 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1622 memset(memslot->dirty_bitmap, 0, n);
1623 }
1624 r = 0;
1625out:
72dc67a6 1626 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1627 return r;
1628}
1629
1fe779f8
CO		 1630long kvm_arch_vm_ioctl(struct file *filp,
1631 unsigned int ioctl, unsigned long arg)
1632{
1633 struct kvm *kvm = filp->private_data;
1634 void __user *argp = (void __user *)arg;
1635 int r = -EINVAL;
1636
1637 switch (ioctl) {
1638 case KVM_SET_TSS_ADDR:
1639 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1640 if (r < 0)
1641 goto out;
1642 break;
1643 case KVM_SET_MEMORY_REGION: {
1644 struct kvm_memory_region kvm_mem;
1645 struct kvm_userspace_memory_region kvm_userspace_mem;
1646
1647 r = -EFAULT;
1648 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1649 goto out;
1650 kvm_userspace_mem.slot = kvm_mem.slot;
1651 kvm_userspace_mem.flags = kvm_mem.flags;
1652 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1653 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1654 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1655 if (r)
1656 goto out;
1657 break;
1658 }
1659 case KVM_SET_NR_MMU_PAGES:
1660 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1661 if (r)
1662 goto out;
1663 break;
1664 case KVM_GET_NR_MMU_PAGES:
1665 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1666 break;
1667 case KVM_SET_MEMORY_ALIAS: {
1668 struct kvm_memory_alias alias;
1669
1670 r = -EFAULT;
1671 if (copy_from_user(&alias, argp, sizeof alias))
1672 goto out;
1673 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1674 if (r)
1675 goto out;
1676 break;
1677 }
1678 case KVM_CREATE_IRQCHIP:
1679 r = -ENOMEM;
d7deeeb0
ZX		 1680 kvm->arch.vpic = kvm_create_pic(kvm);
1681 if (kvm->arch.vpic) {
1fe779f8
CO		 1682 r = kvm_ioapic_init(kvm);
1683 if (r) {
d7deeeb0
ZX		 1684 kfree(kvm->arch.vpic);
1685 kvm->arch.vpic = NULL;
1fe779f8
CO		 1686 goto out;
1687 }
1688 } else
1689 goto out;
1690 break;
7837699f
SY		 1691 case KVM_CREATE_PIT:
1692 r = -ENOMEM;
1693 kvm->arch.vpit = kvm_create_pit(kvm);
1694 if (kvm->arch.vpit)
1695 r = 0;
1696 break;
1fe779f8
CO		 1697 case KVM_IRQ_LINE: {
1698 struct kvm_irq_level irq_event;
1699
1700 r = -EFAULT;
1701 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1702 goto out;
1703 if (irqchip_in_kernel(kvm)) {
1704 mutex_lock(&kvm->lock);
1705 if (irq_event.irq < 16)
1706 kvm_pic_set_irq(pic_irqchip(kvm),
1707 irq_event.irq,
1708 irq_event.level);
d7deeeb0 1709 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1710 irq_event.irq,
1711 irq_event.level);
1712 mutex_unlock(&kvm->lock);
1713 r = 0;
1714 }
1715 break;
1716 }
1717 case KVM_GET_IRQCHIP: {
1718 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1719 struct kvm_irqchip chip;
1720
1721 r = -EFAULT;
1722 if (copy_from_user(&chip, argp, sizeof chip))
1723 goto out;
1724 r = -ENXIO;
1725 if (!irqchip_in_kernel(kvm))
1726 goto out;
1727 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1728 if (r)
1729 goto out;
1730 r = -EFAULT;
1731 if (copy_to_user(argp, &chip, sizeof chip))
1732 goto out;
1733 r = 0;
1734 break;
1735 }
1736 case KVM_SET_IRQCHIP: {
1737 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1738 struct kvm_irqchip chip;
1739
1740 r = -EFAULT;
1741 if (copy_from_user(&chip, argp, sizeof chip))
1742 goto out;
1743 r = -ENXIO;
1744 if (!irqchip_in_kernel(kvm))
1745 goto out;
1746 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1747 if (r)
1748 goto out;
1749 r = 0;
1750 break;
1751 }
e0f63cb9
SY		 1752 case KVM_GET_PIT: {
1753 struct kvm_pit_state ps;
1754 r = -EFAULT;
1755 if (copy_from_user(&ps, argp, sizeof ps))
1756 goto out;
1757 r = -ENXIO;
1758 if (!kvm->arch.vpit)
1759 goto out;
1760 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1761 if (r)
1762 goto out;
1763 r = -EFAULT;
1764 if (copy_to_user(argp, &ps, sizeof ps))
1765 goto out;
1766 r = 0;
1767 break;
1768 }
1769 case KVM_SET_PIT: {
1770 struct kvm_pit_state ps;
1771 r = -EFAULT;
1772 if (copy_from_user(&ps, argp, sizeof ps))
1773 goto out;
1774 r = -ENXIO;
1775 if (!kvm->arch.vpit)
1776 goto out;
1777 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1778 if (r)
1779 goto out;
1780 r = 0;
1781 break;
1782 }
1fe779f8
CO		 1783 default:
1784 ;
1785 }
1786out:
1787 return r;
1788}
1789
a16b043c 1790static void kvm_init_msr_list(void)
043405e1
CO		 1791{
1792 u32 dummy[2];
1793 unsigned i, j;
1794
1795 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1796 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1797 continue;
1798 if (j < i)
1799 msrs_to_save[j] = msrs_to_save[i];
1800 j++;
1801 }
1802 num_msrs_to_save = j;
1803}
1804
bbd9b64e
CO		 1805/*
1806 * Only apic need an MMIO device hook, so shortcut now..
1807 */
1808static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1809 gpa_t addr, int len,
1810 int is_write)
bbd9b64e
CO		 1811{
1812 struct kvm_io_device *dev;
1813
ad312c7c
ZX		 1814 if (vcpu->arch.apic) {
1815 dev = &vcpu->arch.apic->dev;
92760499 1816 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1817 return dev;
1818 }
1819 return NULL;
1820}
1821
1822
1823static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1824 gpa_t addr, int len,
1825 int is_write)
bbd9b64e
CO		 1826{
1827 struct kvm_io_device *dev;
1828
92760499 1829 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1830 if (dev == NULL)
92760499
LV		 1831 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1832 is_write);
bbd9b64e
CO		 1833 return dev;
1834}
1835
1836int emulator_read_std(unsigned long addr,
1837 void *val,
1838 unsigned int bytes,
1839 struct kvm_vcpu *vcpu)
1840{
1841 void *data = val;
10589a46 1842 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1843
1844 while (bytes) {
ad312c7c 1845 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1846 unsigned offset = addr & (PAGE_SIZE-1);
1847 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1848 int ret;
1849
10589a46
MT		 1850 if (gpa == UNMAPPED_GVA) {
1851 r = X86EMUL_PROPAGATE_FAULT;
1852 goto out;
1853 }
bbd9b64e 1854 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1855 if (ret < 0) {
1856 r = X86EMUL_UNHANDLEABLE;
1857 goto out;
1858 }
bbd9b64e
CO		 1859
1860 bytes -= tocopy;
1861 data += tocopy;
1862 addr += tocopy;
1863 }
10589a46 1864out:
10589a46 1865 return r;
bbd9b64e
CO		 1866}
1867EXPORT_SYMBOL_GPL(emulator_read_std);
1868
bbd9b64e
CO		 1869static int emulator_read_emulated(unsigned long addr,
1870 void *val,
1871 unsigned int bytes,
1872 struct kvm_vcpu *vcpu)
1873{
1874 struct kvm_io_device *mmio_dev;
1875 gpa_t gpa;
1876
1877 if (vcpu->mmio_read_completed) {
1878 memcpy(val, vcpu->mmio_data, bytes);
1879 vcpu->mmio_read_completed = 0;
1880 return X86EMUL_CONTINUE;
1881 }
1882
ad312c7c 1883 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1884
1885 /* For APIC access vmexit */
1886 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1887 goto mmio;
1888
1889 if (emulator_read_std(addr, val, bytes, vcpu)
1890 == X86EMUL_CONTINUE)
1891 return X86EMUL_CONTINUE;
1892 if (gpa == UNMAPPED_GVA)
1893 return X86EMUL_PROPAGATE_FAULT;
1894
1895mmio:
1896 /*
1897 * Is this MMIO handled locally?
1898 */
10589a46 1899 mutex_lock(&vcpu->kvm->lock);
92760499 1900 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 1901 if (mmio_dev) {
1902 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1903 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1904 return X86EMUL_CONTINUE;
1905 }
10589a46 1906 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1907
1908 vcpu->mmio_needed = 1;
1909 vcpu->mmio_phys_addr = gpa;
1910 vcpu->mmio_size = bytes;
1911 vcpu->mmio_is_write = 0;
1912
1913 return X86EMUL_UNHANDLEABLE;
1914}
1915
3200f405 1916int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1917 const void *val, int bytes)
bbd9b64e
CO		 1918{
1919 int ret;
1920
1921 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1922 if (ret < 0)
bbd9b64e
CO		 1923 return 0;
1924 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1925 return 1;
1926}
1927
1928static int emulator_write_emulated_onepage(unsigned long addr,
1929 const void *val,
1930 unsigned int bytes,
1931 struct kvm_vcpu *vcpu)
1932{
1933 struct kvm_io_device *mmio_dev;
10589a46
MT		 1934 gpa_t gpa;
1935
10589a46 1936 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1937
1938 if (gpa == UNMAPPED_GVA) {
c3c91fee 1939 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1940 return X86EMUL_PROPAGATE_FAULT;
1941 }
1942
1943 /* For APIC access vmexit */
1944 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1945 goto mmio;
1946
1947 if (emulator_write_phys(vcpu, gpa, val, bytes))
1948 return X86EMUL_CONTINUE;
1949
1950mmio:
1951 /*
1952 * Is this MMIO handled locally?
1953 */
10589a46 1954 mutex_lock(&vcpu->kvm->lock);
92760499 1955 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 1956 if (mmio_dev) {
1957 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1958 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1959 return X86EMUL_CONTINUE;
1960 }
10589a46 1961 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1962
1963 vcpu->mmio_needed = 1;
1964 vcpu->mmio_phys_addr = gpa;
1965 vcpu->mmio_size = bytes;
1966 vcpu->mmio_is_write = 1;
1967 memcpy(vcpu->mmio_data, val, bytes);
1968
1969 return X86EMUL_CONTINUE;
1970}
1971
1972int emulator_write_emulated(unsigned long addr,
1973 const void *val,
1974 unsigned int bytes,
1975 struct kvm_vcpu *vcpu)
1976{
1977 /* Crossing a page boundary? */
1978 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1979 int rc, now;
1980
1981 now = -addr & ~PAGE_MASK;
1982 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1983 if (rc != X86EMUL_CONTINUE)
1984 return rc;
1985 addr += now;
1986 val += now;
1987 bytes -= now;
1988 }
1989 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1990}
1991EXPORT_SYMBOL_GPL(emulator_write_emulated);
1992
1993static int emulator_cmpxchg_emulated(unsigned long addr,
1994 const void *old,
1995 const void *new,
1996 unsigned int bytes,
1997 struct kvm_vcpu *vcpu)
1998{
1999 static int reported;
2000
2001 if (!reported) {
2002 reported = 1;
2003 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2004 }
2bacc55c
MT		 2005#ifndef CONFIG_X86_64
2006 /* guests cmpxchg8b have to be emulated atomically */
2007 if (bytes == 8) {
10589a46 2008 gpa_t gpa;
2bacc55c 2009 struct page *page;
c0b49b0d 2010 char *kaddr;
2bacc55c
MT		 2011 u64 val;
2012
10589a46
MT		 2013 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2014
2bacc55c
MT		 2015 if (gpa == UNMAPPED_GVA ||
2016 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2017 goto emul_write;
2018
2019 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2020 goto emul_write;
2021
2022 val = *(u64 *)new;
72dc67a6
IE		 2023
2024 down_read(&current->mm->mmap_sem);
2bacc55c 2025 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 2026 up_read(&current->mm->mmap_sem);
2027
c0b49b0d
AM		 2028 kaddr = kmap_atomic(page, KM_USER0);
2029 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2030 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2031 kvm_release_page_dirty(page);
2032 }
3200f405 2033emul_write:
2bacc55c
MT		 2034#endif
2035
bbd9b64e
CO		 2036 return emulator_write_emulated(addr, new, bytes, vcpu);
2037}
2038
2039static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2040{
2041 return kvm_x86_ops->get_segment_base(vcpu, seg);
2042}
2043
2044int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2045{
2046 return X86EMUL_CONTINUE;
2047}
2048
2049int emulate_clts(struct kvm_vcpu *vcpu)
2050{
54e445ca 2051 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2052 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2053 return X86EMUL_CONTINUE;
2054}
2055
2056int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2057{
2058 struct kvm_vcpu *vcpu = ctxt->vcpu;
2059
2060 switch (dr) {
2061 case 0 ... 3:
2062 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2063 return X86EMUL_CONTINUE;
2064 default:
b8688d51 2065 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2066 return X86EMUL_UNHANDLEABLE;
2067 }
2068}
2069
2070int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2071{
2072 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2073 int exception;
2074
2075 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2076 if (exception) {
2077 /* FIXME: better handling */
2078 return X86EMUL_UNHANDLEABLE;
2079 }
2080 return X86EMUL_CONTINUE;
2081}
2082
2083void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2084{
bbd9b64e 2085 u8 opcodes[4];
5fdbf976 2086 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2087 unsigned long rip_linear;
2088
f76c710d 2089 if (!printk_ratelimit())
bbd9b64e
CO		 2090 return;
2091
25be4608
GC		 2092 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2093
bbd9b64e
CO		 2094 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2095
2096 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2097 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2098}
2099EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2100
14af3f3c 2101static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2102 .read_std = emulator_read_std,
bbd9b64e
CO		 2103 .read_emulated = emulator_read_emulated,
2104 .write_emulated = emulator_write_emulated,
2105 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2106};
2107
5fdbf976
MT		 2108static void cache_all_regs(struct kvm_vcpu *vcpu)
2109{
2110 kvm_register_read(vcpu, VCPU_REGS_RAX);
2111 kvm_register_read(vcpu, VCPU_REGS_RSP);
2112 kvm_register_read(vcpu, VCPU_REGS_RIP);
2113 vcpu->arch.regs_dirty = ~0;
2114}
2115
bbd9b64e
CO		 2116int emulate_instruction(struct kvm_vcpu *vcpu,
2117 struct kvm_run *run,
2118 unsigned long cr2,
2119 u16 error_code,
571008da 2120 int emulation_type)
bbd9b64e
CO		 2121{
2122 int r;
571008da 2123 struct decode_cache *c;
bbd9b64e 2124
26eef70c 2125 kvm_clear_exception_queue(vcpu);
ad312c7c 2126 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2127 /*
2128 * TODO: fix x86_emulate.c to use guest_read/write_register
2129 * instead of direct ->regs accesses, can save hundred cycles
2130 * on Intel for instructions that don't read/change RSP, for
2131 * for example.
2132 */
2133 cache_all_regs(vcpu);
bbd9b64e
CO		 2134
2135 vcpu->mmio_is_write = 0;
ad312c7c 2136 vcpu->arch.pio.string = 0;
bbd9b64e 2137
571008da 2138 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2139 int cs_db, cs_l;
2140 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2141
ad312c7c
ZX		 2142 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2143 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2144 vcpu->arch.emulate_ctxt.mode =
2145 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2146 ? X86EMUL_MODE_REAL : cs_l
2147 ? X86EMUL_MODE_PROT64 : cs_db
2148 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2149
ad312c7c 2150 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2151
2152 /* Reject the instructions other than VMCALL/VMMCALL when
2153 * try to emulate invalid opcode */
2154 c = &vcpu->arch.emulate_ctxt.decode;
2155 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2156 (!(c->twobyte && c->b == 0x01 &&
2157 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2158 c->modrm_mod == 3 && c->modrm_rm == 1)))
2159 return EMULATE_FAIL;
2160
f2b5756b 2161 ++vcpu->stat.insn_emulation;
bbd9b64e 2162 if (r) {
f2b5756b 2163 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2164 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2165 return EMULATE_DONE;
2166 return EMULATE_FAIL;
2167 }
2168 }
2169
ad312c7c 2170 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2171
ad312c7c 2172 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2173 return EMULATE_DO_MMIO;
2174
2175 if ((r || vcpu->mmio_is_write) && run) {
2176 run->exit_reason = KVM_EXIT_MMIO;
2177 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2178 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2179 run->mmio.len = vcpu->mmio_size;
2180 run->mmio.is_write = vcpu->mmio_is_write;
2181 }
2182
2183 if (r) {
2184 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2185 return EMULATE_DONE;
2186 if (!vcpu->mmio_needed) {
2187 kvm_report_emulation_failure(vcpu, "mmio");
2188 return EMULATE_FAIL;
2189 }
2190 return EMULATE_DO_MMIO;
2191 }
2192
ad312c7c 2193 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2194
2195 if (vcpu->mmio_is_write) {
2196 vcpu->mmio_needed = 0;
2197 return EMULATE_DO_MMIO;
2198 }
2199
2200 return EMULATE_DONE;
2201}
2202EXPORT_SYMBOL_GPL(emulate_instruction);
2203
de7d789a
CO		 2204static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2205{
2206 int i;
2207
ad312c7c
ZX		 2208 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2209 if (vcpu->arch.pio.guest_pages[i]) {
2210 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2211 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2212 }
2213}
2214
2215static int pio_copy_data(struct kvm_vcpu *vcpu)
2216{
ad312c7c 2217 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2218 void *q;
2219 unsigned bytes;
ad312c7c 2220 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2221
ad312c7c 2222 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2223 PAGE_KERNEL);
2224 if (!q) {
2225 free_pio_guest_pages(vcpu);
2226 return -ENOMEM;
2227 }
ad312c7c
ZX		 2228 q += vcpu->arch.pio.guest_page_offset;
2229 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2230 if (vcpu->arch.pio.in)
de7d789a
CO		 2231 memcpy(q, p, bytes);
2232 else
2233 memcpy(p, q, bytes);
ad312c7c 2234 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2235 vunmap(q);
2236 free_pio_guest_pages(vcpu);
2237 return 0;
2238}
2239
2240int complete_pio(struct kvm_vcpu *vcpu)
2241{
ad312c7c 2242 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2243 long delta;
2244 int r;
5fdbf976 2245 unsigned long val;
de7d789a
CO		 2246
2247 if (!io->string) {
5fdbf976
MT		 2248 if (io->in) {
2249 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2250 memcpy(&val, vcpu->arch.pio_data, io->size);
2251 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2252 }
de7d789a
CO		 2253 } else {
2254 if (io->in) {
2255 r = pio_copy_data(vcpu);
5fdbf976 2256 if (r)
de7d789a 2257 return r;
de7d789a
CO		 2258 }
2259
2260 delta = 1;
2261 if (io->rep) {
2262 delta *= io->cur_count;
2263 /*
2264 * The size of the register should really depend on
2265 * current address size.
2266 */
5fdbf976
MT		 2267 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2268 val -= delta;
2269 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2270 }
2271 if (io->down)
2272 delta = -delta;
2273 delta *= io->size;
5fdbf976
MT		 2274 if (io->in) {
2275 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2276 val += delta;
2277 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2278 } else {
2279 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2280 val += delta;
2281 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2282 }
de7d789a
CO		 2283 }
2284
de7d789a
CO		 2285 io->count -= io->cur_count;
2286 io->cur_count = 0;
2287
2288 return 0;
2289}
2290
2291static void kernel_pio(struct kvm_io_device *pio_dev,
2292 struct kvm_vcpu *vcpu,
2293 void *pd)
2294{
2295 /* TODO: String I/O for in kernel device */
2296
2297 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2298 if (vcpu->arch.pio.in)
2299 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2300 vcpu->arch.pio.size,
de7d789a
CO		 2301 pd);
2302 else
ad312c7c
ZX		 2303 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2304 vcpu->arch.pio.size,
de7d789a
CO		 2305 pd);
2306 mutex_unlock(&vcpu->kvm->lock);
2307}
2308
2309static void pio_string_write(struct kvm_io_device *pio_dev,
2310 struct kvm_vcpu *vcpu)
2311{
ad312c7c
ZX		 2312 struct kvm_pio_request *io = &vcpu->arch.pio;
2313 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2314 int i;
2315
2316 mutex_lock(&vcpu->kvm->lock);
2317 for (i = 0; i < io->cur_count; i++) {
2318 kvm_iodevice_write(pio_dev, io->port,
2319 io->size,
2320 pd);
2321 pd += io->size;
2322 }
2323 mutex_unlock(&vcpu->kvm->lock);
2324}
2325
2326static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2327 gpa_t addr, int len,
2328 int is_write)
de7d789a 2329{
92760499 2330 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2331}
2332
2333int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2334 int size, unsigned port)
2335{
2336 struct kvm_io_device *pio_dev;
5fdbf976 2337 unsigned long val;
de7d789a
CO		 2338
2339 vcpu->run->exit_reason = KVM_EXIT_IO;
2340 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2341 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2342 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2343 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2344 vcpu->run->io.port = vcpu->arch.pio.port = port;
2345 vcpu->arch.pio.in = in;
2346 vcpu->arch.pio.string = 0;
2347 vcpu->arch.pio.down = 0;
2348 vcpu->arch.pio.guest_page_offset = 0;
2349 vcpu->arch.pio.rep = 0;
de7d789a 2350
2714d1d3
FEL		 2351 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2352 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2353 handler);
2354 else
2355 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2356 handler);
2357
5fdbf976
MT		 2358 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2359 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a
CO		 2360
2361 kvm_x86_ops->skip_emulated_instruction(vcpu);
2362
92760499 2363 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2364 if (pio_dev) {
ad312c7c 2365 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2366 complete_pio(vcpu);
2367 return 1;
2368 }
2369 return 0;
2370}
2371EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2372
2373int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2374 int size, unsigned long count, int down,
2375 gva_t address, int rep, unsigned port)
2376{
2377 unsigned now, in_page;
2378 int i, ret = 0;
2379 int nr_pages = 1;
2380 struct page *page;
2381 struct kvm_io_device *pio_dev;
2382
2383 vcpu->run->exit_reason = KVM_EXIT_IO;
2384 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2385 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2386 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2387 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2388 vcpu->run->io.port = vcpu->arch.pio.port = port;
2389 vcpu->arch.pio.in = in;
2390 vcpu->arch.pio.string = 1;
2391 vcpu->arch.pio.down = down;
2392 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2393 vcpu->arch.pio.rep = rep;
de7d789a 2394
2714d1d3
FEL		 2395 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2396 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2397 handler);
2398 else
2399 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2400 handler);
2401
de7d789a
CO		 2402 if (!count) {
2403 kvm_x86_ops->skip_emulated_instruction(vcpu);
2404 return 1;
2405 }
2406
2407 if (!down)
2408 in_page = PAGE_SIZE - offset_in_page(address);
2409 else
2410 in_page = offset_in_page(address) + size;
2411 now = min(count, (unsigned long)in_page / size);
2412 if (!now) {
2413 /*
2414 * String I/O straddles page boundary. Pin two guest pages
2415 * so that we satisfy atomicity constraints. Do just one
2416 * transaction to avoid complexity.
2417 */
2418 nr_pages = 2;
2419 now = 1;
2420 }
2421 if (down) {
2422 /*
2423 * String I/O in reverse. Yuck. Kill the guest, fix later.
2424 */
2425 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2426 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2427 return 1;
2428 }
2429 vcpu->run->io.count = now;
ad312c7c 2430 vcpu->arch.pio.cur_count = now;
de7d789a 2431
ad312c7c 2432 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2433 kvm_x86_ops->skip_emulated_instruction(vcpu);
2434
2435 for (i = 0; i < nr_pages; ++i) {
de7d789a 2436 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2437 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2438 if (!page) {
c1a5d4f9 2439 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2440 free_pio_guest_pages(vcpu);
2441 return 1;
2442 }
2443 }
2444
92760499
LV		 2445 pio_dev = vcpu_find_pio_dev(vcpu, port,
2446 vcpu->arch.pio.cur_count,
2447 !vcpu->arch.pio.in);
ad312c7c 2448 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2449 /* string PIO write */
2450 ret = pio_copy_data(vcpu);
2451 if (ret >= 0 && pio_dev) {
2452 pio_string_write(pio_dev, vcpu);
2453 complete_pio(vcpu);
ad312c7c 2454 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2455 ret = 1;
2456 }
2457 } else if (pio_dev)
2458 pr_unimpl(vcpu, "no string pio read support yet, "
2459 "port %x size %d count %ld\n",
2460 port, size, count);
2461
2462 return ret;
2463}
2464EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2465
f8c16bba 2466int kvm_arch_init(void *opaque)
043405e1 2467{
56c6d28a 2468 int r;
f8c16bba
ZX		 2469 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2470
f8c16bba
ZX		 2471 if (kvm_x86_ops) {
2472 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2473 r = -EEXIST;
2474 goto out;
f8c16bba
ZX		 2475 }
2476
2477 if (!ops->cpu_has_kvm_support()) {
2478 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2479 r = -EOPNOTSUPP;
2480 goto out;
f8c16bba
ZX		 2481 }
2482 if (ops->disabled_by_bios()) {
2483 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2484 r = -EOPNOTSUPP;
2485 goto out;
f8c16bba
ZX		 2486 }
2487
97db56ce
AK		 2488 r = kvm_mmu_module_init();
2489 if (r)
2490 goto out;
2491
2492 kvm_init_msr_list();
2493
f8c16bba 2494 kvm_x86_ops = ops;
56c6d28a 2495 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2496 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2497 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2498 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2499 return 0;
56c6d28a
ZX		 2500
2501out:
56c6d28a 2502 return r;
043405e1 2503}
8776e519 2504
f8c16bba
ZX		 2505void kvm_arch_exit(void)
2506{
2507 kvm_x86_ops = NULL;
56c6d28a
ZX		 2508 kvm_mmu_module_exit();
2509}
f8c16bba 2510
8776e519
HB		 2511int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2512{
2513 ++vcpu->stat.halt_exits;
2714d1d3 2514 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2515 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2516 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3200f405 2517 up_read(&vcpu->kvm->slots_lock);
8776e519 2518 kvm_vcpu_block(vcpu);
3200f405 2519 down_read(&vcpu->kvm->slots_lock);
a4535290 2520 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
8776e519
HB		 2521 return -EINTR;
2522 return 1;
2523 } else {
2524 vcpu->run->exit_reason = KVM_EXIT_HLT;
2525 return 0;
2526 }
2527}
2528EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2529
2f333bcb
MT		 2530static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2531 unsigned long a1)
2532{
2533 if (is_long_mode(vcpu))
2534 return a0;
2535 else
2536 return a0 | ((gpa_t)a1 << 32);
2537}
2538
8776e519
HB		 2539int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2540{
2541 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2542 int r = 1;
8776e519 2543
5fdbf976
MT		 2544 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2545 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2546 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2547 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2548 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2549
2714d1d3
FEL		 2550 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2551
8776e519
HB		 2552 if (!is_long_mode(vcpu)) {
2553 nr &= 0xFFFFFFFF;
2554 a0 &= 0xFFFFFFFF;
2555 a1 &= 0xFFFFFFFF;
2556 a2 &= 0xFFFFFFFF;
2557 a3 &= 0xFFFFFFFF;
2558 }
2559
2560 switch (nr) {
b93463aa
AK		 2561 case KVM_HC_VAPIC_POLL_IRQ:
2562 ret = 0;
2563 break;
2f333bcb
MT		 2564 case KVM_HC_MMU_OP:
2565 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2566 break;
8776e519
HB		 2567 default:
2568 ret = -KVM_ENOSYS;
2569 break;
2570 }
5fdbf976 2571 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2572 ++vcpu->stat.hypercalls;
2f333bcb 2573 return r;
8776e519
HB		 2574}
2575EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2576
2577int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2578{
2579 char instruction[3];
2580 int ret = 0;
5fdbf976 2581 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2582
8776e519
HB		 2583
2584 /*
2585 * Blow out the MMU to ensure that no other VCPU has an active mapping
2586 * to ensure that the updated hypercall appears atomically across all
2587 * VCPUs.
2588 */
2589 kvm_mmu_zap_all(vcpu->kvm);
2590
8776e519 2591 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2592 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2593 != X86EMUL_CONTINUE)
2594 ret = -EFAULT;
2595
8776e519
HB		 2596 return ret;
2597}
2598
2599static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2600{
2601 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2602}
2603
2604void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2605{
2606 struct descriptor_table dt = { limit, base };
2607
2608 kvm_x86_ops->set_gdt(vcpu, &dt);
2609}
2610
2611void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2612{
2613 struct descriptor_table dt = { limit, base };
2614
2615 kvm_x86_ops->set_idt(vcpu, &dt);
2616}
2617
2618void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2619 unsigned long *rflags)
2620{
2d3ad1f4 2621 kvm_lmsw(vcpu, msw);
8776e519
HB		 2622 *rflags = kvm_x86_ops->get_rflags(vcpu);
2623}
2624
2625unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2626{
54e445ca
JR		 2627 unsigned long value;
2628
8776e519
HB		 2629 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2630 switch (cr) {
2631 case 0:
54e445ca
JR		 2632 value = vcpu->arch.cr0;
2633 break;
8776e519 2634 case 2:
54e445ca
JR		 2635 value = vcpu->arch.cr2;
2636 break;
8776e519 2637 case 3:
54e445ca
JR		 2638 value = vcpu->arch.cr3;
2639 break;
8776e519 2640 case 4:
54e445ca
JR		 2641 value = vcpu->arch.cr4;
2642 break;
152ff9be 2643 case 8:
54e445ca
JR		 2644 value = kvm_get_cr8(vcpu);
2645 break;
8776e519 2646 default:
b8688d51 2647 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2648 return 0;
2649 }
54e445ca
JR		 2650 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2651 (u32)((u64)value >> 32), handler);
2652
2653 return value;
8776e519
HB		 2654}
2655
2656void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2657 unsigned long *rflags)
2658{
54e445ca
JR		 2659 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2660 (u32)((u64)val >> 32), handler);
2661
8776e519
HB		 2662 switch (cr) {
2663 case 0:
2d3ad1f4 2664 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2665 *rflags = kvm_x86_ops->get_rflags(vcpu);
2666 break;
2667 case 2:
ad312c7c 2668 vcpu->arch.cr2 = val;
8776e519
HB		 2669 break;
2670 case 3:
2d3ad1f4 2671 kvm_set_cr3(vcpu, val);
8776e519
HB		 2672 break;
2673 case 4:
2d3ad1f4 2674 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2675 break;
152ff9be 2676 case 8:
2d3ad1f4 2677 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2678 break;
8776e519 2679 default:
b8688d51 2680 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2681 }
2682}
2683
07716717
DK		 2684static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2685{
ad312c7c
ZX		 2686 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2687 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2688
2689 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2690 /* when no next entry is found, the current entry[i] is reselected */
2691 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2692 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2693 if (ej->function == e->function) {
2694 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2695 return j;
2696 }
2697 }
2698 return 0; /* silence gcc, even though control never reaches here */
2699}
2700
2701/* find an entry with matching function, matching index (if needed), and that
2702 * should be read next (if it's stateful) */
2703static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2704 u32 function, u32 index)
2705{
2706 if (e->function != function)
2707 return 0;
2708 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2709 return 0;
2710 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2711 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2712 return 0;
2713 return 1;
2714}
2715
8776e519
HB		 2716void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2717{
2718 int i;
07716717
DK		 2719 u32 function, index;
2720 struct kvm_cpuid_entry2 *e, *best;
8776e519 2721
5fdbf976
MT		 2722 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2723 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2724 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2725 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2726 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2727 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
8776e519 2728 best = NULL;
ad312c7c
ZX		 2729 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2730 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2731 if (is_matching_cpuid_entry(e, function, index)) {
2732 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2733 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2734 best = e;
2735 break;
2736 }
2737 /*
2738 * Both basic or both extended?
2739 */
2740 if (((e->function ^ function) & 0x80000000) == 0)
2741 if (!best || e->function > best->function)
2742 best = e;
2743 }
2744 if (best) {
5fdbf976
MT		 2745 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2746 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2747 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2748 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2749 }
8776e519 2750 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2751 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2752 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2753 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2754 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2755 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2756}
2757EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2758
b6c7a5dc
HB		 2759/*
2760 * Check if userspace requested an interrupt window, and that the
2761 * interrupt window is open.
2762 *
2763 * No need to exit to userspace if we already have an interrupt queued.
2764 */
2765static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2766 struct kvm_run *kvm_run)
2767{
ad312c7c 2768 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2769 kvm_run->request_interrupt_window &&
ad312c7c 2770 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2771 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2772}
2773
2774static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2775 struct kvm_run *kvm_run)
2776{
2777 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2778 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2779 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2780 if (irqchip_in_kernel(vcpu->kvm))
2781 kvm_run->ready_for_interrupt_injection = 1;
2782 else
2783 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2784 (vcpu->arch.interrupt_window_open &&
2785 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2786}
2787
b93463aa
AK		 2788static void vapic_enter(struct kvm_vcpu *vcpu)
2789{
2790 struct kvm_lapic *apic = vcpu->arch.apic;
2791 struct page *page;
2792
2793 if (!apic || !apic->vapic_addr)
2794 return;
2795
10589a46 2796 down_read(&current->mm->mmap_sem);
b93463aa 2797 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2798 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2799
2800 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2801}
2802
2803static void vapic_exit(struct kvm_vcpu *vcpu)
2804{
2805 struct kvm_lapic *apic = vcpu->arch.apic;
2806
2807 if (!apic || !apic->vapic_addr)
2808 return;
2809
f8b78fa3 2810 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2811 kvm_release_page_dirty(apic->vapic_page);
2812 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2813 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2814}
2815
b6c7a5dc
HB		 2816static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2817{
2818 int r;
2819
a4535290 2820 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2821 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2822 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2823 kvm_lapic_reset(vcpu);
2824 r = kvm_x86_ops->vcpu_reset(vcpu);
2825 if (r)
2826 return r;
a4535290 2827 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2828 }
2829
3200f405 2830 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2831 vapic_enter(vcpu);
2832
b6c7a5dc
HB		 2833preempted:
2834 if (vcpu->guest_debug.enabled)
2835 kvm_x86_ops->guest_debug_pre(vcpu);
2836
2837again:
2e53d63a
MT		 2838 if (vcpu->requests)
2839 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2840 kvm_mmu_unload(vcpu);
2841
b6c7a5dc
HB		 2842 r = kvm_mmu_reload(vcpu);
2843 if (unlikely(r))
2844 goto out;
2845
2f52d58c
AK		 2846 if (vcpu->requests) {
2847 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2848 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 2849 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2850 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2851 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2852 &vcpu->requests)) {
2853 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2854 r = 0;
2855 goto out;
2856 }
71c4dfaf
JR		 2857 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2858 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2859 r = 0;
2860 goto out;
2861 }
2f52d58c 2862 }
b93463aa 2863
06e05645 2864 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2865 kvm_inject_pending_timer_irqs(vcpu);
2866
2867 preempt_disable();
2868
2869 kvm_x86_ops->prepare_guest_switch(vcpu);
2870 kvm_load_guest_fpu(vcpu);
2871
2872 local_irq_disable();
2873
d4acf7e7 2874 if (vcpu->requests || need_resched()) {
6c142801
AK		 2875 local_irq_enable();
2876 preempt_enable();
2877 r = 1;
2878 goto out;
2879 }
2880
b6c7a5dc
HB		 2881 if (signal_pending(current)) {
2882 local_irq_enable();
2883 preempt_enable();
2884 r = -EINTR;
2885 kvm_run->exit_reason = KVM_EXIT_INTR;
2886 ++vcpu->stat.signal_exits;
2887 goto out;
2888 }
2889
e9571ed5
MT		 2890 vcpu->guest_mode = 1;
2891 /*
2892 * Make sure that guest_mode assignment won't happen after
2893 * testing the pending IRQ vector bitmap.
2894 */
2895 smp_wmb();
2896
ad312c7c 2897 if (vcpu->arch.exception.pending)
298101da
AK		 2898 __queue_exception(vcpu);
2899 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2900 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2901 else
b6c7a5dc
HB		 2902 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2903
b93463aa
AK		 2904 kvm_lapic_sync_to_vapic(vcpu);
2905
3200f405
MT		 2906 up_read(&vcpu->kvm->slots_lock);
2907
b6c7a5dc
HB		 2908 kvm_guest_enter();
2909
b6c7a5dc 2910
2714d1d3 2911 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 2912 kvm_x86_ops->run(vcpu, kvm_run);
2913
2914 vcpu->guest_mode = 0;
2915 local_irq_enable();
2916
2917 ++vcpu->stat.exits;
2918
2919 /*
2920 * We must have an instruction between local_irq_enable() and
2921 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2922 * the interrupt shadow. The stat.exits increment will do nicely.
2923 * But we need to prevent reordering, hence this barrier():
2924 */
2925 barrier();
2926
2927 kvm_guest_exit();
2928
2929 preempt_enable();
2930
3200f405
MT		 2931 down_read(&vcpu->kvm->slots_lock);
2932
b6c7a5dc
HB		 2933 /*
2934 * Profile KVM exit RIPs:
2935 */
2936 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 2937 unsigned long rip = kvm_rip_read(vcpu);
2938 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 2939 }
2940
ad312c7c
ZX		 2941 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2942 vcpu->arch.exception.pending = false;
298101da 2943
b93463aa
AK		 2944 kvm_lapic_sync_from_vapic(vcpu);
2945
b6c7a5dc
HB		 2946 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2947
2948 if (r > 0) {
2949 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2950 r = -EINTR;
2951 kvm_run->exit_reason = KVM_EXIT_INTR;
2952 ++vcpu->stat.request_irq_exits;
2953 goto out;
2954 }
e1beb1d3 2955 if (!need_resched())
b6c7a5dc 2956 goto again;
b6c7a5dc
HB		 2957 }
2958
2959out:
3200f405 2960 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2961 if (r > 0) {
2962 kvm_resched(vcpu);
3200f405 2963 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2964 goto preempted;
2965 }
2966
2967 post_kvm_run_save(vcpu, kvm_run);
2968
b93463aa
AK		 2969 vapic_exit(vcpu);
2970
b6c7a5dc
HB		 2971 return r;
2972}
2973
2974int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2975{
2976 int r;
2977 sigset_t sigsaved;
2978
2979 vcpu_load(vcpu);
2980
ac9f6dc0
AK		 2981 if (vcpu->sigset_active)
2982 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2983
a4535290 2984 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 2985 kvm_vcpu_block(vcpu);
ac9f6dc0
AK		 2986 r = -EAGAIN;
2987 goto out;
b6c7a5dc
HB		 2988 }
2989
b6c7a5dc
HB		 2990 /* re-sync apic's tpr */
2991 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 2992 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 2993
ad312c7c 2994 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2995 r = complete_pio(vcpu);
2996 if (r)
2997 goto out;
2998 }
2999#if CONFIG_HAS_IOMEM
3000 if (vcpu->mmio_needed) {
3001 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3002 vcpu->mmio_read_completed = 1;
3003 vcpu->mmio_needed = 0;
3200f405
MT		 3004
3005 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3006 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3007 vcpu->arch.mmio_fault_cr2, 0,
3008 EMULTYPE_NO_DECODE);
3200f405 3009 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3010 if (r == EMULATE_DO_MMIO) {
3011 /*
3012 * Read-modify-write. Back to userspace.
3013 */
3014 r = 0;
3015 goto out;
3016 }
3017 }
3018#endif
5fdbf976
MT		 3019 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3020 kvm_register_write(vcpu, VCPU_REGS_RAX,
3021 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3022
3023 r = __vcpu_run(vcpu, kvm_run);
3024
3025out:
3026 if (vcpu->sigset_active)
3027 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3028
3029 vcpu_put(vcpu);
3030 return r;
3031}
3032
3033int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3034{
3035 vcpu_load(vcpu);
3036
5fdbf976
MT		 3037 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3038 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3039 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3040 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3041 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3042 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3043 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3044 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3045#ifdef CONFIG_X86_64
5fdbf976
MT		 3046 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3047 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3048 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3049 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3050 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3051 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3052 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3053 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3054#endif
3055
5fdbf976 3056 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3057 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3058
3059 /*
3060 * Don't leak debug flags in case they were set for guest debugging
3061 */
3062 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3063 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3064
3065 vcpu_put(vcpu);
3066
3067 return 0;
3068}
3069
3070int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3071{
3072 vcpu_load(vcpu);
3073
5fdbf976
MT		 3074 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3075 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3076 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3077 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3078 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3079 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3080 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3081 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3082#ifdef CONFIG_X86_64
5fdbf976
MT		 3083 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3084 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3085 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3086 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3087 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3088 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3089 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3090 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3091
b6c7a5dc
HB		 3092#endif
3093
5fdbf976 3094 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3095 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3096
b6c7a5dc 3097
b4f14abd
JK		 3098 vcpu->arch.exception.pending = false;
3099
b6c7a5dc
HB		 3100 vcpu_put(vcpu);
3101
3102 return 0;
3103}
3104
3e6e0aab
GT		 3105void kvm_get_segment(struct kvm_vcpu *vcpu,
3106 struct kvm_segment *var, int seg)
b6c7a5dc 3107{
14af3f3c 3108 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3109}
3110
3111void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3112{
3113 struct kvm_segment cs;
3114
3e6e0aab 3115 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3116 *db = cs.db;
3117 *l = cs.l;
3118}
3119EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3120
3121int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3122 struct kvm_sregs *sregs)
3123{
3124 struct descriptor_table dt;
3125 int pending_vec;
3126
3127 vcpu_load(vcpu);
3128
3e6e0aab
GT		 3129 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3130 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3131 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3132 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3133 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3134 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3135
3e6e0aab
GT		 3136 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3137 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3138
3139 kvm_x86_ops->get_idt(vcpu, &dt);
3140 sregs->idt.limit = dt.limit;
3141 sregs->idt.base = dt.base;
3142 kvm_x86_ops->get_gdt(vcpu, &dt);
3143 sregs->gdt.limit = dt.limit;
3144 sregs->gdt.base = dt.base;
3145
3146 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3147 sregs->cr0 = vcpu->arch.cr0;
3148 sregs->cr2 = vcpu->arch.cr2;
3149 sregs->cr3 = vcpu->arch.cr3;
3150 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3151 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3152 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3153 sregs->apic_base = kvm_get_apic_base(vcpu);
3154
3155 if (irqchip_in_kernel(vcpu->kvm)) {
3156 memset(sregs->interrupt_bitmap, 0,
3157 sizeof sregs->interrupt_bitmap);
3158 pending_vec = kvm_x86_ops->get_irq(vcpu);
3159 if (pending_vec >= 0)
3160 set_bit(pending_vec,
3161 (unsigned long *)sregs->interrupt_bitmap);
3162 } else
ad312c7c 3163 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3164 sizeof sregs->interrupt_bitmap);
3165
3166 vcpu_put(vcpu);
3167
3168 return 0;
3169}
3170
62d9f0db
MT		 3171int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3172 struct kvm_mp_state *mp_state)
3173{
3174 vcpu_load(vcpu);
3175 mp_state->mp_state = vcpu->arch.mp_state;
3176 vcpu_put(vcpu);
3177 return 0;
3178}
3179
3180int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3181 struct kvm_mp_state *mp_state)
3182{
3183 vcpu_load(vcpu);
3184 vcpu->arch.mp_state = mp_state->mp_state;
3185 vcpu_put(vcpu);
3186 return 0;
3187}
3188
3e6e0aab 3189static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3190 struct kvm_segment *var, int seg)
3191{
14af3f3c 3192 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3193}
3194
37817f29
IE		 3195static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3196 struct kvm_segment *kvm_desct)
3197{
3198 kvm_desct->base = seg_desc->base0;
3199 kvm_desct->base |= seg_desc->base1 << 16;
3200 kvm_desct->base |= seg_desc->base2 << 24;
3201 kvm_desct->limit = seg_desc->limit0;
3202 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3203 if (seg_desc->g) {
3204 kvm_desct->limit <<= 12;
3205 kvm_desct->limit |= 0xfff;
3206 }
37817f29
IE		 3207 kvm_desct->selector = selector;
3208 kvm_desct->type = seg_desc->type;
3209 kvm_desct->present = seg_desc->p;
3210 kvm_desct->dpl = seg_desc->dpl;
3211 kvm_desct->db = seg_desc->d;
3212 kvm_desct->s = seg_desc->s;
3213 kvm_desct->l = seg_desc->l;
3214 kvm_desct->g = seg_desc->g;
3215 kvm_desct->avl = seg_desc->avl;
3216 if (!selector)
3217 kvm_desct->unusable = 1;
3218 else
3219 kvm_desct->unusable = 0;
3220 kvm_desct->padding = 0;
3221}
3222
3223static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3224 u16 selector,
3225 struct descriptor_table *dtable)
3226{
3227 if (selector & 1 << 2) {
3228 struct kvm_segment kvm_seg;
3229
3e6e0aab 3230 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3231
3232 if (kvm_seg.unusable)
3233 dtable->limit = 0;
3234 else
3235 dtable->limit = kvm_seg.limit;
3236 dtable->base = kvm_seg.base;
3237 }
3238 else
3239 kvm_x86_ops->get_gdt(vcpu, dtable);
3240}
3241
3242/* allowed just for 8 bytes segments */
3243static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3244 struct desc_struct *seg_desc)
3245{
98899aa0 3246 gpa_t gpa;
37817f29
IE		 3247 struct descriptor_table dtable;
3248 u16 index = selector >> 3;
3249
3250 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3251
3252 if (dtable.limit < index * 8 + 7) {
3253 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3254 return 1;
3255 }
98899aa0
MT		 3256 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3257 gpa += index * 8;
3258 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3259}
3260
3261/* allowed just for 8 bytes segments */
3262static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3263 struct desc_struct *seg_desc)
3264{
98899aa0 3265 gpa_t gpa;
37817f29
IE		 3266 struct descriptor_table dtable;
3267 u16 index = selector >> 3;
3268
3269 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3270
3271 if (dtable.limit < index * 8 + 7)
3272 return 1;
98899aa0
MT		 3273 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3274 gpa += index * 8;
3275 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3276}
3277
3278static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3279 struct desc_struct *seg_desc)
3280{
3281 u32 base_addr;
3282
3283 base_addr = seg_desc->base0;
3284 base_addr |= (seg_desc->base1 << 16);
3285 base_addr |= (seg_desc->base2 << 24);
3286
98899aa0 3287 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3288}
3289
37817f29
IE		 3290static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3291{
3292 struct kvm_segment kvm_seg;
3293
3e6e0aab 3294 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3295 return kvm_seg.selector;
3296}
3297
3298static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3299 u16 selector,
3300 struct kvm_segment *kvm_seg)
3301{
3302 struct desc_struct seg_desc;
3303
3304 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3305 return 1;
3306 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3307 return 0;
3308}
3309
3e6e0aab
GT		 3310int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3311 int type_bits, int seg)
37817f29
IE		 3312{
3313 struct kvm_segment kvm_seg;
3314
3315 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3316 return 1;
3317 kvm_seg.type |= type_bits;
3318
3319 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3320 seg != VCPU_SREG_LDTR)
3321 if (!kvm_seg.s)
3322 kvm_seg.unusable = 1;
3323
3e6e0aab 3324 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3325 return 0;
3326}
3327
3328static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3329 struct tss_segment_32 *tss)
3330{
3331 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3332 tss->eip = kvm_rip_read(vcpu);
37817f29 3333 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3334 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3335 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3336 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3337 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3338 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3339 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3340 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3341 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3342 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3343 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3344 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3345 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3346 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3347 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3348 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3349 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3350}
3351
3352static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3353 struct tss_segment_32 *tss)
3354{
3355 kvm_set_cr3(vcpu, tss->cr3);
3356
5fdbf976 3357 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3358 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3359
5fdbf976
MT		 3360 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3361 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3362 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3363 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3364 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3365 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3366 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3367 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3368
3e6e0aab 3369 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3370 return 1;
3371
3e6e0aab 3372 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3373 return 1;
3374
3e6e0aab 3375 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3376 return 1;
3377
3e6e0aab 3378 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3379 return 1;
3380
3e6e0aab 3381 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3382 return 1;
3383
3e6e0aab 3384 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3385 return 1;
3386
3e6e0aab 3387 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3388 return 1;
3389 return 0;
3390}
3391
3392static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3393 struct tss_segment_16 *tss)
3394{
5fdbf976 3395 tss->ip = kvm_rip_read(vcpu);
37817f29 3396 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3397 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3398 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3399 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3400 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3401 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3402 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3403 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3404 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3405
3406 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3407 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3408 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3409 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3410 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3411 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3412}
3413
3414static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3415 struct tss_segment_16 *tss)
3416{
5fdbf976 3417 kvm_rip_write(vcpu, tss->ip);
37817f29 3418 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3419 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3420 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3421 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3422 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3423 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3424 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3425 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3426 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3427
3e6e0aab 3428 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3429 return 1;
3430
3e6e0aab 3431 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3432 return 1;
3433
3e6e0aab 3434 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3435 return 1;
3436
3e6e0aab 3437 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3438 return 1;
3439
3e6e0aab 3440 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3441 return 1;
3442 return 0;
3443}
3444
8b2cf73c 3445static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3446 u32 old_tss_base,
37817f29
IE		 3447 struct desc_struct *nseg_desc)
3448{
3449 struct tss_segment_16 tss_segment_16;
3450 int ret = 0;
3451
34198bf8
MT		 3452 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3453 sizeof tss_segment_16))
37817f29
IE		 3454 goto out;
3455
3456 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3457
34198bf8
MT		 3458 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3459 sizeof tss_segment_16))
37817f29 3460 goto out;
34198bf8
MT		 3461
3462 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3463 &tss_segment_16, sizeof tss_segment_16))
3464 goto out;
3465
37817f29
IE		 3466 if (load_state_from_tss16(vcpu, &tss_segment_16))
3467 goto out;
3468
3469 ret = 1;
3470out:
3471 return ret;
3472}
3473
8b2cf73c 3474static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3475 u32 old_tss_base,
37817f29
IE		 3476 struct desc_struct *nseg_desc)
3477{
3478 struct tss_segment_32 tss_segment_32;
3479 int ret = 0;
3480
34198bf8
MT		 3481 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3482 sizeof tss_segment_32))
37817f29
IE		 3483 goto out;
3484
3485 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3486
34198bf8
MT		 3487 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3488 sizeof tss_segment_32))
3489 goto out;
3490
3491 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3492 &tss_segment_32, sizeof tss_segment_32))
37817f29 3493 goto out;
34198bf8 3494
37817f29
IE		 3495 if (load_state_from_tss32(vcpu, &tss_segment_32))
3496 goto out;
3497
3498 ret = 1;
3499out:
3500 return ret;
3501}
3502
3503int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3504{
3505 struct kvm_segment tr_seg;
3506 struct desc_struct cseg_desc;
3507 struct desc_struct nseg_desc;
3508 int ret = 0;
34198bf8
MT		 3509 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3510 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3511
34198bf8 3512 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3513
34198bf8
MT		 3514 /* FIXME: Handle errors. Failure to read either TSS or their
3515 * descriptors should generate a pagefault.
3516 */
37817f29
IE		 3517 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3518 goto out;
3519
34198bf8 3520 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3521 goto out;
3522
37817f29
IE		 3523 if (reason != TASK_SWITCH_IRET) {
3524 int cpl;
3525
3526 cpl = kvm_x86_ops->get_cpl(vcpu);
3527 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3528 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3529 return 1;
3530 }
3531 }
3532
3533 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3534 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3535 return 1;
3536 }
3537
3538 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3539 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3540 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3541 }
3542
3543 if (reason == TASK_SWITCH_IRET) {
3544 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3545 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3546 }
3547
3548 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3549
3550 if (nseg_desc.type & 8)
34198bf8 3551 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3552 &nseg_desc);
3553 else
34198bf8 3554 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3555 &nseg_desc);
3556
3557 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3558 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3559 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3560 }
3561
3562 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3563 nseg_desc.type |= (1 << 1);
37817f29
IE		 3564 save_guest_segment_descriptor(vcpu, tss_selector,
3565 &nseg_desc);
3566 }
3567
3568 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3569 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3570 tr_seg.type = 11;
3e6e0aab 3571 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3572out:
37817f29
IE		 3573 return ret;
3574}
3575EXPORT_SYMBOL_GPL(kvm_task_switch);
3576
b6c7a5dc
HB		 3577int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3578 struct kvm_sregs *sregs)
3579{
3580 int mmu_reset_needed = 0;
3581 int i, pending_vec, max_bits;
3582 struct descriptor_table dt;
3583
3584 vcpu_load(vcpu);
3585
3586 dt.limit = sregs->idt.limit;
3587 dt.base = sregs->idt.base;
3588 kvm_x86_ops->set_idt(vcpu, &dt);
3589 dt.limit = sregs->gdt.limit;
3590 dt.base = sregs->gdt.base;
3591 kvm_x86_ops->set_gdt(vcpu, &dt);
3592
ad312c7c
ZX		 3593 vcpu->arch.cr2 = sregs->cr2;
3594 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3595 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3596
2d3ad1f4 3597 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3598
ad312c7c 3599 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3600 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3601 kvm_set_apic_base(vcpu, sregs->apic_base);
3602
3603 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3604
ad312c7c 3605 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3606 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3607 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3608
ad312c7c 3609 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3610 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3611 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3612 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3613
3614 if (mmu_reset_needed)
3615 kvm_mmu_reset_context(vcpu);
3616
3617 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3618 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3619 sizeof vcpu->arch.irq_pending);
3620 vcpu->arch.irq_summary = 0;
3621 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3622 if (vcpu->arch.irq_pending[i])
3623 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3624 } else {
3625 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3626 pending_vec = find_first_bit(
3627 (const unsigned long *)sregs->interrupt_bitmap,
3628 max_bits);
3629 /* Only pending external irq is handled here */
3630 if (pending_vec < max_bits) {
3631 kvm_x86_ops->set_irq(vcpu, pending_vec);
3632 pr_debug("Set back pending irq %d\n",
3633 pending_vec);
3634 }
3635 }
3636
3e6e0aab
GT		 3637 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3638 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3639 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3640 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3641 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3642 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3643
3e6e0aab
GT		 3644 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3645 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3646
3647 vcpu_put(vcpu);
3648
3649 return 0;
3650}
3651
3652int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3653 struct kvm_debug_guest *dbg)
3654{
3655 int r;
3656
3657 vcpu_load(vcpu);
3658
3659 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3660
3661 vcpu_put(vcpu);
3662
3663 return r;
3664}
3665
d0752060
HB		 3666/*
3667 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3668 * we have asm/x86/processor.h
3669 */
3670struct fxsave {
3671 u16 cwd;
3672 u16 swd;
3673 u16 twd;
3674 u16 fop;
3675 u64 rip;
3676 u64 rdp;
3677 u32 mxcsr;
3678 u32 mxcsr_mask;
3679 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3680#ifdef CONFIG_X86_64
3681 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3682#else
3683 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3684#endif
3685};
3686
8b006791
ZX		 3687/*
3688 * Translate a guest virtual address to a guest physical address.
3689 */
3690int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3691 struct kvm_translation *tr)
3692{
3693 unsigned long vaddr = tr->linear_address;
3694 gpa_t gpa;
3695
3696 vcpu_load(vcpu);
72dc67a6 3697 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3698 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3699 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3700 tr->physical_address = gpa;
3701 tr->valid = gpa != UNMAPPED_GVA;
3702 tr->writeable = 1;
3703 tr->usermode = 0;
8b006791
ZX		 3704 vcpu_put(vcpu);
3705
3706 return 0;
3707}
3708
d0752060
HB		 3709int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3710{
ad312c7c 3711 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3712
3713 vcpu_load(vcpu);
3714
3715 memcpy(fpu->fpr, fxsave->st_space, 128);
3716 fpu->fcw = fxsave->cwd;
3717 fpu->fsw = fxsave->swd;
3718 fpu->ftwx = fxsave->twd;
3719 fpu->last_opcode = fxsave->fop;
3720 fpu->last_ip = fxsave->rip;
3721 fpu->last_dp = fxsave->rdp;
3722 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3723
3724 vcpu_put(vcpu);
3725
3726 return 0;
3727}
3728
3729int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3730{
ad312c7c 3731 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3732
3733 vcpu_load(vcpu);
3734
3735 memcpy(fxsave->st_space, fpu->fpr, 128);
3736 fxsave->cwd = fpu->fcw;
3737 fxsave->swd = fpu->fsw;
3738 fxsave->twd = fpu->ftwx;
3739 fxsave->fop = fpu->last_opcode;
3740 fxsave->rip = fpu->last_ip;
3741 fxsave->rdp = fpu->last_dp;
3742 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3743
3744 vcpu_put(vcpu);
3745
3746 return 0;
3747}
3748
3749void fx_init(struct kvm_vcpu *vcpu)
3750{
3751 unsigned after_mxcsr_mask;
3752
bc1a34f1
AA		 3753 /*
3754 * Touch the fpu the first time in non atomic context as if
3755 * this is the first fpu instruction the exception handler
3756 * will fire before the instruction returns and it'll have to
3757 * allocate ram with GFP_KERNEL.
3758 */
3759 if (!used_math())
d6e88aec 3760 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3761
d0752060
HB		 3762 /* Initialize guest FPU by resetting ours and saving into guest's */
3763 preempt_disable();
d6e88aec
AK		 3764 kvm_fx_save(&vcpu->arch.host_fx_image);
3765 kvm_fx_finit();
3766 kvm_fx_save(&vcpu->arch.guest_fx_image);
3767 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3768 preempt_enable();
3769
ad312c7c 3770 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3771 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3772 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3773 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3774 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3775}
3776EXPORT_SYMBOL_GPL(fx_init);
3777
3778void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3779{
3780 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3781 return;
3782
3783 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 3784 kvm_fx_save(&vcpu->arch.host_fx_image);
3785 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3786}
3787EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3788
3789void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3790{
3791 if (!vcpu->guest_fpu_loaded)
3792 return;
3793
3794 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 3795 kvm_fx_save(&vcpu->arch.guest_fx_image);
3796 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3797 ++vcpu->stat.fpu_reload;
d0752060
HB		 3798}
3799EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3800
3801void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3802{
3803 kvm_x86_ops->vcpu_free(vcpu);
3804}
3805
3806struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3807 unsigned int id)
3808{
26e5215f
AK		 3809 return kvm_x86_ops->vcpu_create(kvm, id);
3810}
e9b11c17 3811
26e5215f
AK		 3812int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3813{
3814 int r;
e9b11c17
ZX		 3815
3816 /* We do fxsave: this must be aligned. */
ad312c7c 3817 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3818
3819 vcpu_load(vcpu);
3820 r = kvm_arch_vcpu_reset(vcpu);
3821 if (r == 0)
3822 r = kvm_mmu_setup(vcpu);
3823 vcpu_put(vcpu);
3824 if (r < 0)
3825 goto free_vcpu;
3826
26e5215f 3827 return 0;
e9b11c17
ZX		 3828free_vcpu:
3829 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3830 return r;
e9b11c17
ZX		 3831}
3832
d40ccc62 3833void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3834{
3835 vcpu_load(vcpu);
3836 kvm_mmu_unload(vcpu);
3837 vcpu_put(vcpu);
3838
3839 kvm_x86_ops->vcpu_free(vcpu);
3840}
3841
3842int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3843{
3844 return kvm_x86_ops->vcpu_reset(vcpu);
3845}
3846
3847void kvm_arch_hardware_enable(void *garbage)
3848{
3849 kvm_x86_ops->hardware_enable(garbage);
3850}
3851
3852void kvm_arch_hardware_disable(void *garbage)
3853{
3854 kvm_x86_ops->hardware_disable(garbage);
3855}
3856
3857int kvm_arch_hardware_setup(void)
3858{
3859 return kvm_x86_ops->hardware_setup();
3860}
3861
3862void kvm_arch_hardware_unsetup(void)
3863{
3864 kvm_x86_ops->hardware_unsetup();
3865}
3866
3867void kvm_arch_check_processor_compat(void *rtn)
3868{
3869 kvm_x86_ops->check_processor_compatibility(rtn);
3870}
3871
3872int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3873{
3874 struct page *page;
3875 struct kvm *kvm;
3876 int r;
3877
3878 BUG_ON(vcpu->kvm == NULL);
3879 kvm = vcpu->kvm;
3880
ad312c7c 3881 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3882 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 3883 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 3884 else
a4535290 3885 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3886
3887 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3888 if (!page) {
3889 r = -ENOMEM;
3890 goto fail;
3891 }
ad312c7c 3892 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3893
3894 r = kvm_mmu_create(vcpu);
3895 if (r < 0)
3896 goto fail_free_pio_data;
3897
3898 if (irqchip_in_kernel(kvm)) {
3899 r = kvm_create_lapic(vcpu);
3900 if (r < 0)
3901 goto fail_mmu_destroy;
3902 }
3903
3904 return 0;
3905
3906fail_mmu_destroy:
3907 kvm_mmu_destroy(vcpu);
3908fail_free_pio_data:
ad312c7c 3909 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3910fail:
3911 return r;
3912}
3913
3914void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3915{
3916 kvm_free_lapic(vcpu);
3200f405 3917 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3918 kvm_mmu_destroy(vcpu);
3200f405 3919 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3920 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3921}
d19a9cd2
ZX		 3922
3923struct kvm *kvm_arch_create_vm(void)
3924{
3925 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3926
3927 if (!kvm)
3928 return ERR_PTR(-ENOMEM);
3929
f05e70ac 3930 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3931
3932 return kvm;
3933}
3934
3935static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3936{
3937 vcpu_load(vcpu);
3938 kvm_mmu_unload(vcpu);
3939 vcpu_put(vcpu);
3940}
3941
3942static void kvm_free_vcpus(struct kvm *kvm)
3943{
3944 unsigned int i;
3945
3946 /*
3947 * Unpin any mmu pages first.
3948 */
3949 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3950 if (kvm->vcpus[i])
3951 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3952 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3953 if (kvm->vcpus[i]) {
3954 kvm_arch_vcpu_free(kvm->vcpus[i]);
3955 kvm->vcpus[i] = NULL;
3956 }
3957 }
3958
3959}
3960
3961void kvm_arch_destroy_vm(struct kvm *kvm)
3962{
7837699f 3963 kvm_free_pit(kvm);
d7deeeb0
ZX		 3964 kfree(kvm->arch.vpic);
3965 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3966 kvm_free_vcpus(kvm);
3967 kvm_free_physmem(kvm);
3d45830c
AK		 3968 if (kvm->arch.apic_access_page)
3969 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 3970 if (kvm->arch.ept_identity_pagetable)
3971 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 3972 kfree(kvm);
3973}
0de10343
ZX		 3974
3975int kvm_arch_set_memory_region(struct kvm *kvm,
3976 struct kvm_userspace_memory_region *mem,
3977 struct kvm_memory_slot old,
3978 int user_alloc)
3979{
3980 int npages = mem->memory_size >> PAGE_SHIFT;
3981 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
3982
3983 /*To keep backward compatibility with older userspace,
3984 *x86 needs to hanlde !user_alloc case.
3985 */
3986 if (!user_alloc) {
3987 if (npages && !old.rmap) {
604b38ac
AA		 3988 unsigned long userspace_addr;
3989
72dc67a6 3990 down_write(&current->mm->mmap_sem);
604b38ac
AA		 3991 userspace_addr = do_mmap(NULL, 0,
3992 npages * PAGE_SIZE,
3993 PROT_READ | PROT_WRITE,
3994 MAP_SHARED | MAP_ANONYMOUS,
3995 0);
72dc67a6 3996 up_write(&current->mm->mmap_sem);
0de10343 3997
604b38ac
AA		 3998 if (IS_ERR((void *)userspace_addr))
3999 return PTR_ERR((void *)userspace_addr);
4000
4001 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4002 spin_lock(&kvm->mmu_lock);
4003 memslot->userspace_addr = userspace_addr;
4004 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4005 } else {
4006 if (!old.user_alloc && old.rmap) {
4007 int ret;
4008
72dc67a6 4009 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4010 ret = do_munmap(current->mm, old.userspace_addr,
4011 old.npages * PAGE_SIZE);
72dc67a6 4012 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4013 if (ret < 0)
4014 printk(KERN_WARNING
4015 "kvm_vm_ioctl_set_memory_region: "
4016 "failed to munmap memory\n");
4017 }
4018 }
4019 }
4020
f05e70ac 4021 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4022 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4023 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4024 }
4025
4026 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4027 kvm_flush_remote_tlbs(kvm);
4028
4029 return 0;
4030}
1d737c8a 4031
34d4cb8f
MT		 4032void kvm_arch_flush_shadow(struct kvm *kvm)
4033{
4034 kvm_mmu_zap_all(kvm);
4035}
4036
1d737c8a
ZX		 4037int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4038{
a4535290
AK		 4039 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4040 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4041}
5736199a
ZX		 4042
4043static void vcpu_kick_intr(void *info)
4044{
4045#ifdef DEBUG
4046 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4047 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4048#endif
4049}
4050
4051void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4052{
4053 int ipi_pcpu = vcpu->cpu;
e9571ed5 4054 int cpu = get_cpu();
5736199a
ZX		 4055
4056 if (waitqueue_active(&vcpu->wq)) {
4057 wake_up_interruptible(&vcpu->wq);
4058 ++vcpu->stat.halt_wakeup;
4059 }
e9571ed5
MT		 4060 /*
4061 * We may be called synchronously with irqs disabled in guest mode,
4062 * So need not to call smp_call_function_single() in that case.
4063 */
4064 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4065 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4066 put_cpu();
5736199a 4067}
Clone of davem's net-next-2.6 tree