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KVM: x86 emulator: Add missing decoder flags for xor instructions
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
0f12244f 417static int __kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
f9a48e6a
AK		 419 cr0 |= X86_CR0_ET;
420
ab344828 421#ifdef CONFIG_X86_64
0f12244f
GN		 422 if (cr0 & 0xffffffff00000000UL)
423 return 1;
ab344828
GN		 424#endif
425
426 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 427
0f12244f
GN		 428 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
429 return 1;
a03490ed 430
0f12244f
GN		 431 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
432 return 1;
a03490ed
CO		 433
434 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
435#ifdef CONFIG_X86_64
f6801dff 436 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 437 int cs_db, cs_l;
438
0f12244f
GN		 439 if (!is_pae(vcpu))
440 return 1;
a03490ed 441 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 442 if (cs_l)
443 return 1;
a03490ed
CO		 444 } else
445#endif
0f12244f
GN		 446 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
447 return 1;
a03490ed
CO		 448 }
449
450 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 451
a03490ed 452 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 453 return 0;
454}
455
456void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
457{
458 if (__kvm_set_cr0(vcpu, cr0))
459 kvm_inject_gp(vcpu, 0);
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 462
2d3ad1f4 463void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 464{
f78e9176 465 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 466}
2d3ad1f4 467EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 468
0f12244f 469int __kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 470{
fc78f519 471 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 472 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
473
0f12244f
GN		 474 if (cr4 & CR4_RESERVED_BITS)
475 return 1;
a03490ed
CO		 476
477 if (is_long_mode(vcpu)) {
0f12244f
GN		 478 if (!(cr4 & X86_CR4_PAE))
479 return 1;
a2edf57f
AK		 480 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
481 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 482 && !load_pdptrs(vcpu, vcpu->arch.cr3))
483 return 1;
484
485 if (cr4 & X86_CR4_VMXE)
486 return 1;
a03490ed 487
a03490ed 488 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 489 vcpu->arch.cr4 = cr4;
a03490ed 490 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 491
492 return 0;
493}
494
495void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
496{
497 if (__kvm_set_cr4(vcpu, cr4))
498 kvm_inject_gp(vcpu, 0);
a03490ed 499}
2d3ad1f4 500EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 501
0f12244f 502static int __kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 503{
ad312c7c 504 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 505 kvm_mmu_sync_roots(vcpu);
d835dfec 506 kvm_mmu_flush_tlb(vcpu);
0f12244f 507 return 0;
d835dfec
AK		 508 }
509
a03490ed 510 if (is_long_mode(vcpu)) {
0f12244f
GN		 511 if (cr3 & CR3_L_MODE_RESERVED_BITS)
512 return 1;
a03490ed
CO		 513 } else {
514 if (is_pae(vcpu)) {
0f12244f
GN		 515 if (cr3 & CR3_PAE_RESERVED_BITS)
516 return 1;
517 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
518 return 1;
a03490ed
CO		 519 }
520 /*
521 * We don't check reserved bits in nonpae mode, because
522 * this isn't enforced, and VMware depends on this.
523 */
524 }
525
a03490ed
CO		 526 /*
527 * Does the new cr3 value map to physical memory? (Note, we
528 * catch an invalid cr3 even in real-mode, because it would
529 * cause trouble later on when we turn on paging anyway.)
530 *
531 * A real CPU would silently accept an invalid cr3 and would
532 * attempt to use it - with largely undefined (and often hard
533 * to debug) behavior on the guest side.
534 */
535 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 536 return 1;
537 vcpu->arch.cr3 = cr3;
538 vcpu->arch.mmu.new_cr3(vcpu);
539 return 0;
540}
541
542void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
543{
544 if (__kvm_set_cr3(vcpu, cr3))
c1a5d4f9 545 kvm_inject_gp(vcpu, 0);
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 548
0f12244f 549int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 550{
0f12244f
GN		 551 if (cr8 & CR8_RESERVED_BITS)
552 return 1;
a03490ed
CO		 553 if (irqchip_in_kernel(vcpu->kvm))
554 kvm_lapic_set_tpr(vcpu, cr8);
555 else
ad312c7c 556 vcpu->arch.cr8 = cr8;
0f12244f
GN		 557 return 0;
558}
559
560void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
561{
562 if (__kvm_set_cr8(vcpu, cr8))
563 kvm_inject_gp(vcpu, 0);
a03490ed 564}
2d3ad1f4 565EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 566
2d3ad1f4 567unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 568{
569 if (irqchip_in_kernel(vcpu->kvm))
570 return kvm_lapic_get_cr8(vcpu);
571 else
ad312c7c 572 return vcpu->arch.cr8;
a03490ed 573}
2d3ad1f4 574EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 575
338dbc97 576static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 577{
578 switch (dr) {
579 case 0 ... 3:
580 vcpu->arch.db[dr] = val;
581 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
582 vcpu->arch.eff_db[dr] = val;
583 break;
584 case 4:
338dbc97
GN		 585 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
586 return 1; /* #UD */
020df079
GN		 587 /* fall through */
588 case 6:
338dbc97
GN		 589 if (val & 0xffffffff00000000ULL)
590 return -1; /* #GP */
020df079
GN		 591 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
592 break;
593 case 5:
338dbc97
GN		 594 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
595 return 1; /* #UD */
020df079
GN		 596 /* fall through */
597 default: /* 7 */
338dbc97
GN		 598 if (val & 0xffffffff00000000ULL)
599 return -1; /* #GP */
020df079
GN		 600 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
601 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
602 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
603 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
604 }
605 break;
606 }
607
608 return 0;
609}
338dbc97
GN		 610
611int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
612{
613 int res;
614
615 res = __kvm_set_dr(vcpu, dr, val);
616 if (res > 0)
617 kvm_queue_exception(vcpu, UD_VECTOR);
618 else if (res < 0)
619 kvm_inject_gp(vcpu, 0);
620
621 return res;
622}
020df079
GN		 623EXPORT_SYMBOL_GPL(kvm_set_dr);
624
338dbc97 625static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 626{
627 switch (dr) {
628 case 0 ... 3:
629 *val = vcpu->arch.db[dr];
630 break;
631 case 4:
338dbc97 632 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 633 return 1;
020df079
GN		 634 /* fall through */
635 case 6:
636 *val = vcpu->arch.dr6;
637 break;
638 case 5:
338dbc97 639 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 640 return 1;
020df079
GN		 641 /* fall through */
642 default: /* 7 */
643 *val = vcpu->arch.dr7;
644 break;
645 }
646
647 return 0;
648}
338dbc97
GN		 649
650int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
651{
652 if (_kvm_get_dr(vcpu, dr, val)) {
653 kvm_queue_exception(vcpu, UD_VECTOR);
654 return 1;
655 }
656 return 0;
657}
020df079
GN		 658EXPORT_SYMBOL_GPL(kvm_get_dr);
659
d8017474
AG		 660static inline u32 bit(int bitno)
661{
662 return 1 << (bitno & 31);
663}
664
043405e1
CO		 665/*
666 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
667 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
668 *
669 * This list is modified at module load time to reflect the
e3267cbb
GC		 670 * capabilities of the host cpu. This capabilities test skips MSRs that are
671 * kvm-specific. Those are put in the beginning of the list.
043405e1 672 */
e3267cbb 673
11c6bffa 674#define KVM_SAVE_MSRS_BEGIN 7
043405e1 675static u32 msrs_to_save[] = {
e3267cbb 676 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 677 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 678 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 679 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 680 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
681 MSR_K6_STAR,
682#ifdef CONFIG_X86_64
683 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
684#endif
e3267cbb 685 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 686};
687
688static unsigned num_msrs_to_save;
689
690static u32 emulated_msrs[] = {
691 MSR_IA32_MISC_ENABLE,
692};
693
b69e8cae 694static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 695{
b69e8cae
RJ		 696 if (efer & efer_reserved_bits)
697 return 1;
15c4a640
CO		 698
699 if (is_paging(vcpu)
b69e8cae
RJ		 700 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
701 return 1;
15c4a640 702
1b2fd70c
AG		 703 if (efer & EFER_FFXSR) {
704 struct kvm_cpuid_entry2 *feat;
705
706 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 707 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
708 return 1;
1b2fd70c
AG		 709 }
710
d8017474
AG		 711 if (efer & EFER_SVME) {
712 struct kvm_cpuid_entry2 *feat;
713
714 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 715 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
716 return 1;
d8017474
AG		 717 }
718
15c4a640 719 efer &= ~EFER_LMA;
f6801dff 720 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 721
a3d204e2
SY		 722 kvm_x86_ops->set_efer(vcpu, efer);
723
f6801dff 724 vcpu->arch.efer = efer;
9645bb56
AK		 725
726 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
727 kvm_mmu_reset_context(vcpu);
b69e8cae
RJ		 728
729 return 0;
15c4a640
CO		 730}
731
f2b4b7dd
JR		 732void kvm_enable_efer_bits(u64 mask)
733{
734 efer_reserved_bits &= ~mask;
735}
736EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
737
738
15c4a640
CO		 739/*
740 * Writes msr value into into the appropriate "register".
741 * Returns 0 on success, non-0 otherwise.
742 * Assumes vcpu_load() was already called.
743 */
744int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
745{
746 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
747}
748
313a3dc7
CO		 749/*
750 * Adapt set_msr() to msr_io()'s calling convention
751 */
752static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
753{
754 return kvm_set_msr(vcpu, index, *data);
755}
756
18068523
GOC		 757static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
758{
9ed3c444
AK		 759 int version;
760 int r;
50d0a0f9 761 struct pvclock_wall_clock wc;
923de3cf 762 struct timespec boot;
18068523
GOC		 763
764 if (!wall_clock)
765 return;
766
9ed3c444
AK		 767 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
768 if (r)
769 return;
770
771 if (version & 1)
772 ++version; /* first time write, random junk */
773
774 ++version;
18068523 775
18068523
GOC		 776 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
777
50d0a0f9
GH		 778 /*
779 * The guest calculates current wall clock time by adding
780 * system time (updated by kvm_write_guest_time below) to the
781 * wall clock specified here. guest system time equals host
782 * system time for us, thus we must fill in host boot time here.
783 */
923de3cf 784 getboottime(&boot);
50d0a0f9
GH		 785
786 wc.sec = boot.tv_sec;
787 wc.nsec = boot.tv_nsec;
788 wc.version = version;
18068523
GOC		 789
790 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
791
792 version++;
793 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 794}
795
50d0a0f9
GH		 796static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
797{
798 uint32_t quotient, remainder;
799
800 /* Don't try to replace with do_div(), this one calculates
801 * "(dividend << 32) / divisor" */
802 __asm__ ( "divl %4"
803 : "=a" (quotient), "=d" (remainder)
804 : "0" (0), "1" (dividend), "r" (divisor) );
805 return quotient;
806}
807
808static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
809{
810 uint64_t nsecs = 1000000000LL;
811 int32_t shift = 0;
812 uint64_t tps64;
813 uint32_t tps32;
814
815 tps64 = tsc_khz * 1000LL;
816 while (tps64 > nsecs*2) {
817 tps64 >>= 1;
818 shift--;
819 }
820
821 tps32 = (uint32_t)tps64;
822 while (tps32 <= (uint32_t)nsecs) {
823 tps32 <<= 1;
824 shift++;
825 }
826
827 hv_clock->tsc_shift = shift;
828 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
829
830 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 831 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 832 hv_clock->tsc_to_system_mul);
833}
834
c8076604
GH		 835static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
836
18068523
GOC		 837static void kvm_write_guest_time(struct kvm_vcpu *v)
838{
839 struct timespec ts;
840 unsigned long flags;
841 struct kvm_vcpu_arch *vcpu = &v->arch;
842 void *shared_kaddr;
463656c0 843 unsigned long this_tsc_khz;
18068523
GOC		 844
845 if ((!vcpu->time_page))
846 return;
847
463656c0
AK		 848 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
849 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
850 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
851 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 852 }
463656c0 853 put_cpu_var(cpu_tsc_khz);
50d0a0f9 854
18068523
GOC		 855 /* Keep irq disabled to prevent changes to the clock */
856 local_irq_save(flags);
af24a4e4 857 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 858 ktime_get_ts(&ts);
923de3cf 859 monotonic_to_bootbased(&ts);
18068523
GOC		 860 local_irq_restore(flags);
861
862 /* With all the info we got, fill in the values */
863
864 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 865 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
866
371bcf64
GC		 867 vcpu->hv_clock.flags = 0;
868
18068523
GOC		 869 /*
870 * The interface expects us to write an even number signaling that the
871 * update is finished. Since the guest won't see the intermediate
50d0a0f9 872 * state, we just increase by 2 at the end.
18068523 873 */
50d0a0f9 874 vcpu->hv_clock.version += 2;
18068523
GOC		 875
876 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
877
878 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 879 sizeof(vcpu->hv_clock));
18068523
GOC		 880
881 kunmap_atomic(shared_kaddr, KM_USER0);
882
883 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
884}
885
c8076604
GH		 886static int kvm_request_guest_time_update(struct kvm_vcpu *v)
887{
888 struct kvm_vcpu_arch *vcpu = &v->arch;
889
890 if (!vcpu->time_page)
891 return 0;
892 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
893 return 1;
894}
895
9ba075a6
AK		 896static bool msr_mtrr_valid(unsigned msr)
897{
898 switch (msr) {
899 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
900 case MSR_MTRRfix64K_00000:
901 case MSR_MTRRfix16K_80000:
902 case MSR_MTRRfix16K_A0000:
903 case MSR_MTRRfix4K_C0000:
904 case MSR_MTRRfix4K_C8000:
905 case MSR_MTRRfix4K_D0000:
906 case MSR_MTRRfix4K_D8000:
907 case MSR_MTRRfix4K_E0000:
908 case MSR_MTRRfix4K_E8000:
909 case MSR_MTRRfix4K_F0000:
910 case MSR_MTRRfix4K_F8000:
911 case MSR_MTRRdefType:
912 case MSR_IA32_CR_PAT:
913 return true;
914 case 0x2f8:
915 return true;
916 }
917 return false;
918}
919
d6289b93
MT		 920static bool valid_pat_type(unsigned t)
921{
922 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
923}
924
925static bool valid_mtrr_type(unsigned t)
926{
927 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
928}
929
930static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
931{
932 int i;
933
934 if (!msr_mtrr_valid(msr))
935 return false;
936
937 if (msr == MSR_IA32_CR_PAT) {
938 for (i = 0; i < 8; i++)
939 if (!valid_pat_type((data >> (i * 8)) & 0xff))
940 return false;
941 return true;
942 } else if (msr == MSR_MTRRdefType) {
943 if (data & ~0xcff)
944 return false;
945 return valid_mtrr_type(data & 0xff);
946 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
947 for (i = 0; i < 8 ; i++)
948 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
949 return false;
950 return true;
951 }
952
953 /* variable MTRRs */
954 return valid_mtrr_type(data & 0xff);
955}
956
9ba075a6
AK		 957static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
958{
0bed3b56
SY		 959 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
960
d6289b93 961 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 962 return 1;
963
0bed3b56
SY		 964 if (msr == MSR_MTRRdefType) {
965 vcpu->arch.mtrr_state.def_type = data;
966 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
967 } else if (msr == MSR_MTRRfix64K_00000)
968 p[0] = data;
969 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
970 p[1 + msr - MSR_MTRRfix16K_80000] = data;
971 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
972 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
973 else if (msr == MSR_IA32_CR_PAT)
974 vcpu->arch.pat = data;
975 else { /* Variable MTRRs */
976 int idx, is_mtrr_mask;
977 u64 *pt;
978
979 idx = (msr - 0x200) / 2;
980 is_mtrr_mask = msr - 0x200 - 2 * idx;
981 if (!is_mtrr_mask)
982 pt =
983 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
984 else
985 pt =
986 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
987 *pt = data;
988 }
989
990 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 991 return 0;
992}
15c4a640 993
890ca9ae 994static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 995{
890ca9ae
HY		 996 u64 mcg_cap = vcpu->arch.mcg_cap;
997 unsigned bank_num = mcg_cap & 0xff;
998
15c4a640 999 switch (msr) {
15c4a640 1000 case MSR_IA32_MCG_STATUS:
890ca9ae 1001 vcpu->arch.mcg_status = data;
15c4a640 1002 break;
c7ac679c 1003 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1004 if (!(mcg_cap & MCG_CTL_P))
1005 return 1;
1006 if (data != 0 && data != ~(u64)0)
1007 return -1;
1008 vcpu->arch.mcg_ctl = data;
1009 break;
1010 default:
1011 if (msr >= MSR_IA32_MC0_CTL &&
1012 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1013 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1014 /* only 0 or all 1s can be written to IA32_MCi_CTL
1015 * some Linux kernels though clear bit 10 in bank 4 to
1016 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1017 * this to avoid an uncatched #GP in the guest
1018 */
890ca9ae 1019 if ((offset & 0x3) == 0 &&
114be429 1020 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1021 return -1;
1022 vcpu->arch.mce_banks[offset] = data;
1023 break;
1024 }
1025 return 1;
1026 }
1027 return 0;
1028}
1029
ffde22ac
ES		 1030static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1031{
1032 struct kvm *kvm = vcpu->kvm;
1033 int lm = is_long_mode(vcpu);
1034 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1035 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1036 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1037 : kvm->arch.xen_hvm_config.blob_size_32;
1038 u32 page_num = data & ~PAGE_MASK;
1039 u64 page_addr = data & PAGE_MASK;
1040 u8 *page;
1041 int r;
1042
1043 r = -E2BIG;
1044 if (page_num >= blob_size)
1045 goto out;
1046 r = -ENOMEM;
1047 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1048 if (!page)
1049 goto out;
1050 r = -EFAULT;
1051 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1052 goto out_free;
1053 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1054 goto out_free;
1055 r = 0;
1056out_free:
1057 kfree(page);
1058out:
1059 return r;
1060}
1061
55cd8e5a
GN		 1062static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1063{
1064 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1065}
1066
1067static bool kvm_hv_msr_partition_wide(u32 msr)
1068{
1069 bool r = false;
1070 switch (msr) {
1071 case HV_X64_MSR_GUEST_OS_ID:
1072 case HV_X64_MSR_HYPERCALL:
1073 r = true;
1074 break;
1075 }
1076
1077 return r;
1078}
1079
1080static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1081{
1082 struct kvm *kvm = vcpu->kvm;
1083
1084 switch (msr) {
1085 case HV_X64_MSR_GUEST_OS_ID:
1086 kvm->arch.hv_guest_os_id = data;
1087 /* setting guest os id to zero disables hypercall page */
1088 if (!kvm->arch.hv_guest_os_id)
1089 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1090 break;
1091 case HV_X64_MSR_HYPERCALL: {
1092 u64 gfn;
1093 unsigned long addr;
1094 u8 instructions[4];
1095
1096 /* if guest os id is not set hypercall should remain disabled */
1097 if (!kvm->arch.hv_guest_os_id)
1098 break;
1099 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1100 kvm->arch.hv_hypercall = data;
1101 break;
1102 }
1103 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1104 addr = gfn_to_hva(kvm, gfn);
1105 if (kvm_is_error_hva(addr))
1106 return 1;
1107 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1108 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1109 if (copy_to_user((void __user *)addr, instructions, 4))
1110 return 1;
1111 kvm->arch.hv_hypercall = data;
1112 break;
1113 }
1114 default:
1115 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1116 "data 0x%llx\n", msr, data);
1117 return 1;
1118 }
1119 return 0;
1120}
1121
1122static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1123{
10388a07
GN		 1124 switch (msr) {
1125 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1126 unsigned long addr;
55cd8e5a 1127
10388a07
GN		 1128 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1129 vcpu->arch.hv_vapic = data;
1130 break;
1131 }
1132 addr = gfn_to_hva(vcpu->kvm, data >>
1133 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1134 if (kvm_is_error_hva(addr))
1135 return 1;
1136 if (clear_user((void __user *)addr, PAGE_SIZE))
1137 return 1;
1138 vcpu->arch.hv_vapic = data;
1139 break;
1140 }
1141 case HV_X64_MSR_EOI:
1142 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1143 case HV_X64_MSR_ICR:
1144 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1145 case HV_X64_MSR_TPR:
1146 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1147 default:
1148 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1149 "data 0x%llx\n", msr, data);
1150 return 1;
1151 }
1152
1153 return 0;
55cd8e5a
GN		 1154}
1155
15c4a640
CO		 1156int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1157{
1158 switch (msr) {
15c4a640 1159 case MSR_EFER:
b69e8cae 1160 return set_efer(vcpu, data);
8f1589d9
AP		 1161 case MSR_K7_HWCR:
1162 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1163 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1164 if (data != 0) {
1165 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1166 data);
1167 return 1;
1168 }
15c4a640 1169 break;
f7c6d140
AP		 1170 case MSR_FAM10H_MMIO_CONF_BASE:
1171 if (data != 0) {
1172 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1173 "0x%llx\n", data);
1174 return 1;
1175 }
15c4a640 1176 break;
c323c0e5 1177 case MSR_AMD64_NB_CFG:
c7ac679c 1178 break;
b5e2fec0
AG		 1179 case MSR_IA32_DEBUGCTLMSR:
1180 if (!data) {
1181 /* We support the non-activated case already */
1182 break;
1183 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1184 /* Values other than LBR and BTF are vendor-specific,
1185 thus reserved and should throw a #GP */
1186 return 1;
1187 }
1188 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1189 __func__, data);
1190 break;
15c4a640
CO		 1191 case MSR_IA32_UCODE_REV:
1192 case MSR_IA32_UCODE_WRITE:
61a6bd67 1193 case MSR_VM_HSAVE_PA:
6098ca93 1194 case MSR_AMD64_PATCH_LOADER:
15c4a640 1195 break;
9ba075a6
AK		 1196 case 0x200 ... 0x2ff:
1197 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1198 case MSR_IA32_APICBASE:
1199 kvm_set_apic_base(vcpu, data);
1200 break;
0105d1a5
GN		 1201 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1202 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1203 case MSR_IA32_MISC_ENABLE:
ad312c7c 1204 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1205 break;
11c6bffa 1206 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1207 case MSR_KVM_WALL_CLOCK:
1208 vcpu->kvm->arch.wall_clock = data;
1209 kvm_write_wall_clock(vcpu->kvm, data);
1210 break;
11c6bffa 1211 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1212 case MSR_KVM_SYSTEM_TIME: {
1213 if (vcpu->arch.time_page) {
1214 kvm_release_page_dirty(vcpu->arch.time_page);
1215 vcpu->arch.time_page = NULL;
1216 }
1217
1218 vcpu->arch.time = data;
1219
1220 /* we verify if the enable bit is set... */
1221 if (!(data & 1))
1222 break;
1223
1224 /* ...but clean it before doing the actual write */
1225 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1226
18068523
GOC		 1227 vcpu->arch.time_page =
1228 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1229
1230 if (is_error_page(vcpu->arch.time_page)) {
1231 kvm_release_page_clean(vcpu->arch.time_page);
1232 vcpu->arch.time_page = NULL;
1233 }
1234
c8076604 1235 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1236 break;
1237 }
890ca9ae
HY		 1238 case MSR_IA32_MCG_CTL:
1239 case MSR_IA32_MCG_STATUS:
1240 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1241 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1242
1243 /* Performance counters are not protected by a CPUID bit,
1244 * so we should check all of them in the generic path for the sake of
1245 * cross vendor migration.
1246 * Writing a zero into the event select MSRs disables them,
1247 * which we perfectly emulate ;-). Any other value should be at least
1248 * reported, some guests depend on them.
1249 */
1250 case MSR_P6_EVNTSEL0:
1251 case MSR_P6_EVNTSEL1:
1252 case MSR_K7_EVNTSEL0:
1253 case MSR_K7_EVNTSEL1:
1254 case MSR_K7_EVNTSEL2:
1255 case MSR_K7_EVNTSEL3:
1256 if (data != 0)
1257 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1258 "0x%x data 0x%llx\n", msr, data);
1259 break;
1260 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1261 * so we ignore writes to make it happy.
1262 */
1263 case MSR_P6_PERFCTR0:
1264 case MSR_P6_PERFCTR1:
1265 case MSR_K7_PERFCTR0:
1266 case MSR_K7_PERFCTR1:
1267 case MSR_K7_PERFCTR2:
1268 case MSR_K7_PERFCTR3:
1269 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1270 "0x%x data 0x%llx\n", msr, data);
1271 break;
55cd8e5a
GN		 1272 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1273 if (kvm_hv_msr_partition_wide(msr)) {
1274 int r;
1275 mutex_lock(&vcpu->kvm->lock);
1276 r = set_msr_hyperv_pw(vcpu, msr, data);
1277 mutex_unlock(&vcpu->kvm->lock);
1278 return r;
1279 } else
1280 return set_msr_hyperv(vcpu, msr, data);
1281 break;
15c4a640 1282 default:
ffde22ac
ES		 1283 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1284 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1285 if (!ignore_msrs) {
1286 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1287 msr, data);
1288 return 1;
1289 } else {
1290 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1291 msr, data);
1292 break;
1293 }
15c4a640
CO		 1294 }
1295 return 0;
1296}
1297EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1298
1299
1300/*
1301 * Reads an msr value (of 'msr_index') into 'pdata'.
1302 * Returns 0 on success, non-0 otherwise.
1303 * Assumes vcpu_load() was already called.
1304 */
1305int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1306{
1307 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1308}
1309
9ba075a6
AK		 1310static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1311{
0bed3b56
SY		 1312 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1313
9ba075a6
AK		 1314 if (!msr_mtrr_valid(msr))
1315 return 1;
1316
0bed3b56
SY		 1317 if (msr == MSR_MTRRdefType)
1318 *pdata = vcpu->arch.mtrr_state.def_type +
1319 (vcpu->arch.mtrr_state.enabled << 10);
1320 else if (msr == MSR_MTRRfix64K_00000)
1321 *pdata = p[0];
1322 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1323 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1324 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1325 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1326 else if (msr == MSR_IA32_CR_PAT)
1327 *pdata = vcpu->arch.pat;
1328 else { /* Variable MTRRs */
1329 int idx, is_mtrr_mask;
1330 u64 *pt;
1331
1332 idx = (msr - 0x200) / 2;
1333 is_mtrr_mask = msr - 0x200 - 2 * idx;
1334 if (!is_mtrr_mask)
1335 pt =
1336 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1337 else
1338 pt =
1339 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1340 *pdata = *pt;
1341 }
1342
9ba075a6
AK		 1343 return 0;
1344}
1345
890ca9ae 1346static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1347{
1348 u64 data;
890ca9ae
HY		 1349 u64 mcg_cap = vcpu->arch.mcg_cap;
1350 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1351
1352 switch (msr) {
15c4a640
CO		 1353 case MSR_IA32_P5_MC_ADDR:
1354 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1355 data = 0;
1356 break;
15c4a640 1357 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1358 data = vcpu->arch.mcg_cap;
1359 break;
c7ac679c 1360 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1361 if (!(mcg_cap & MCG_CTL_P))
1362 return 1;
1363 data = vcpu->arch.mcg_ctl;
1364 break;
1365 case MSR_IA32_MCG_STATUS:
1366 data = vcpu->arch.mcg_status;
1367 break;
1368 default:
1369 if (msr >= MSR_IA32_MC0_CTL &&
1370 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1371 u32 offset = msr - MSR_IA32_MC0_CTL;
1372 data = vcpu->arch.mce_banks[offset];
1373 break;
1374 }
1375 return 1;
1376 }
1377 *pdata = data;
1378 return 0;
1379}
1380
55cd8e5a
GN		 1381static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1382{
1383 u64 data = 0;
1384 struct kvm *kvm = vcpu->kvm;
1385
1386 switch (msr) {
1387 case HV_X64_MSR_GUEST_OS_ID:
1388 data = kvm->arch.hv_guest_os_id;
1389 break;
1390 case HV_X64_MSR_HYPERCALL:
1391 data = kvm->arch.hv_hypercall;
1392 break;
1393 default:
1394 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1395 return 1;
1396 }
1397
1398 *pdata = data;
1399 return 0;
1400}
1401
1402static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1403{
1404 u64 data = 0;
1405
1406 switch (msr) {
1407 case HV_X64_MSR_VP_INDEX: {
1408 int r;
1409 struct kvm_vcpu *v;
1410 kvm_for_each_vcpu(r, v, vcpu->kvm)
1411 if (v == vcpu)
1412 data = r;
1413 break;
1414 }
10388a07
GN		 1415 case HV_X64_MSR_EOI:
1416 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1417 case HV_X64_MSR_ICR:
1418 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1419 case HV_X64_MSR_TPR:
1420 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1421 default:
1422 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1423 return 1;
1424 }
1425 *pdata = data;
1426 return 0;
1427}
1428
890ca9ae
HY		 1429int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1430{
1431 u64 data;
1432
1433 switch (msr) {
890ca9ae 1434 case MSR_IA32_PLATFORM_ID:
15c4a640 1435 case MSR_IA32_UCODE_REV:
15c4a640 1436 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1437 case MSR_IA32_DEBUGCTLMSR:
1438 case MSR_IA32_LASTBRANCHFROMIP:
1439 case MSR_IA32_LASTBRANCHTOIP:
1440 case MSR_IA32_LASTINTFROMIP:
1441 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1442 case MSR_K8_SYSCFG:
1443 case MSR_K7_HWCR:
61a6bd67 1444 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1445 case MSR_P6_PERFCTR0:
1446 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1447 case MSR_P6_EVNTSEL0:
1448 case MSR_P6_EVNTSEL1:
9e699624 1449 case MSR_K7_EVNTSEL0:
1f3ee616 1450 case MSR_K7_PERFCTR0:
1fdbd48c 1451 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1452 case MSR_AMD64_NB_CFG:
f7c6d140 1453 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1454 data = 0;
1455 break;
9ba075a6
AK		 1456 case MSR_MTRRcap:
1457 data = 0x500 | KVM_NR_VAR_MTRR;
1458 break;
1459 case 0x200 ... 0x2ff:
1460 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1461 case 0xcd: /* fsb frequency */
1462 data = 3;
1463 break;
1464 case MSR_IA32_APICBASE:
1465 data = kvm_get_apic_base(vcpu);
1466 break;
0105d1a5
GN		 1467 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1468 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1469 break;
15c4a640 1470 case MSR_IA32_MISC_ENABLE:
ad312c7c 1471 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1472 break;
847f0ad8
AG		 1473 case MSR_IA32_PERF_STATUS:
1474 /* TSC increment by tick */
1475 data = 1000ULL;
1476 /* CPU multiplier */
1477 data |= (((uint64_t)4ULL) << 40);
1478 break;
15c4a640 1479 case MSR_EFER:
f6801dff 1480 data = vcpu->arch.efer;
15c4a640 1481 break;
18068523 1482 case MSR_KVM_WALL_CLOCK:
11c6bffa 1483 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1484 data = vcpu->kvm->arch.wall_clock;
1485 break;
1486 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1487 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1488 data = vcpu->arch.time;
1489 break;
890ca9ae
HY		 1490 case MSR_IA32_P5_MC_ADDR:
1491 case MSR_IA32_P5_MC_TYPE:
1492 case MSR_IA32_MCG_CAP:
1493 case MSR_IA32_MCG_CTL:
1494 case MSR_IA32_MCG_STATUS:
1495 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1496 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1497 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1498 if (kvm_hv_msr_partition_wide(msr)) {
1499 int r;
1500 mutex_lock(&vcpu->kvm->lock);
1501 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1502 mutex_unlock(&vcpu->kvm->lock);
1503 return r;
1504 } else
1505 return get_msr_hyperv(vcpu, msr, pdata);
1506 break;
15c4a640 1507 default:
ed85c068
AP		 1508 if (!ignore_msrs) {
1509 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1510 return 1;
1511 } else {
1512 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1513 data = 0;
1514 }
1515 break;
15c4a640
CO		 1516 }
1517 *pdata = data;
1518 return 0;
1519}
1520EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1521
313a3dc7
CO		 1522/*
1523 * Read or write a bunch of msrs. All parameters are kernel addresses.
1524 *
1525 * @return number of msrs set successfully.
1526 */
1527static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1528 struct kvm_msr_entry *entries,
1529 int (*do_msr)(struct kvm_vcpu *vcpu,
1530 unsigned index, u64 *data))
1531{
f656ce01 1532 int i, idx;
313a3dc7
CO		 1533
1534 vcpu_load(vcpu);
1535
f656ce01 1536 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1537 for (i = 0; i < msrs->nmsrs; ++i)
1538 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1539 break;
f656ce01 1540 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1541
1542 vcpu_put(vcpu);
1543
1544 return i;
1545}
1546
1547/*
1548 * Read or write a bunch of msrs. Parameters are user addresses.
1549 *
1550 * @return number of msrs set successfully.
1551 */
1552static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1553 int (*do_msr)(struct kvm_vcpu *vcpu,
1554 unsigned index, u64 *data),
1555 int writeback)
1556{
1557 struct kvm_msrs msrs;
1558 struct kvm_msr_entry *entries;
1559 int r, n;
1560 unsigned size;
1561
1562 r = -EFAULT;
1563 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1564 goto out;
1565
1566 r = -E2BIG;
1567 if (msrs.nmsrs >= MAX_IO_MSRS)
1568 goto out;
1569
1570 r = -ENOMEM;
1571 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1572 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1573 if (!entries)
1574 goto out;
1575
1576 r = -EFAULT;
1577 if (copy_from_user(entries, user_msrs->entries, size))
1578 goto out_free;
1579
1580 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1581 if (r < 0)
1582 goto out_free;
1583
1584 r = -EFAULT;
1585 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1586 goto out_free;
1587
1588 r = n;
1589
1590out_free:
7a73c028 1591 kfree(entries);
313a3dc7
CO		 1592out:
1593 return r;
1594}
1595
018d00d2
ZX		 1596int kvm_dev_ioctl_check_extension(long ext)
1597{
1598 int r;
1599
1600 switch (ext) {
1601 case KVM_CAP_IRQCHIP:
1602 case KVM_CAP_HLT:
1603 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1604 case KVM_CAP_SET_TSS_ADDR:
07716717 1605 case KVM_CAP_EXT_CPUID:
c8076604 1606 case KVM_CAP_CLOCKSOURCE:
7837699f 1607 case KVM_CAP_PIT:
a28e4f5a 1608 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1609 case KVM_CAP_MP_STATE:
ed848624 1610 case KVM_CAP_SYNC_MMU:
52d939a0 1611 case KVM_CAP_REINJECT_CONTROL:
4925663a 1612 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1613 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1614 case KVM_CAP_IRQFD:
d34e6b17 1615 case KVM_CAP_IOEVENTFD:
c5ff41ce 1616 case KVM_CAP_PIT2:
e9f42757 1617 case KVM_CAP_PIT_STATE2:
b927a3ce 1618 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1619 case KVM_CAP_XEN_HVM:
afbcf7ab 1620 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1621 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1622 case KVM_CAP_HYPERV:
10388a07 1623 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1624 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1625 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1626 case KVM_CAP_DEBUGREGS:
d2be1651 1627 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1628 r = 1;
1629 break;
542472b5
LV		 1630 case KVM_CAP_COALESCED_MMIO:
1631 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1632 break;
774ead3a
AK		 1633 case KVM_CAP_VAPIC:
1634 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1635 break;
f725230a
AK		 1636 case KVM_CAP_NR_VCPUS:
1637 r = KVM_MAX_VCPUS;
1638 break;
a988b910
AK		 1639 case KVM_CAP_NR_MEMSLOTS:
1640 r = KVM_MEMORY_SLOTS;
1641 break;
a68a6a72
MT		 1642 case KVM_CAP_PV_MMU: /* obsolete */
1643 r = 0;
2f333bcb 1644 break;
62c476c7 1645 case KVM_CAP_IOMMU:
19de40a8 1646 r = iommu_found();
62c476c7 1647 break;
890ca9ae
HY		 1648 case KVM_CAP_MCE:
1649 r = KVM_MAX_MCE_BANKS;
1650 break;
018d00d2
ZX		 1651 default:
1652 r = 0;
1653 break;
1654 }
1655 return r;
1656
1657}
1658
043405e1
CO		 1659long kvm_arch_dev_ioctl(struct file *filp,
1660 unsigned int ioctl, unsigned long arg)
1661{
1662 void __user *argp = (void __user *)arg;
1663 long r;
1664
1665 switch (ioctl) {
1666 case KVM_GET_MSR_INDEX_LIST: {
1667 struct kvm_msr_list __user *user_msr_list = argp;
1668 struct kvm_msr_list msr_list;
1669 unsigned n;
1670
1671 r = -EFAULT;
1672 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1673 goto out;
1674 n = msr_list.nmsrs;
1675 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1676 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1677 goto out;
1678 r = -E2BIG;
e125e7b6 1679 if (n < msr_list.nmsrs)
043405e1
CO		 1680 goto out;
1681 r = -EFAULT;
1682 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1683 num_msrs_to_save * sizeof(u32)))
1684 goto out;
e125e7b6 1685 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1686 &emulated_msrs,
1687 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1688 goto out;
1689 r = 0;
1690 break;
1691 }
674eea0f
AK		 1692 case KVM_GET_SUPPORTED_CPUID: {
1693 struct kvm_cpuid2 __user *cpuid_arg = argp;
1694 struct kvm_cpuid2 cpuid;
1695
1696 r = -EFAULT;
1697 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1698 goto out;
1699 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1700 cpuid_arg->entries);
674eea0f
AK		 1701 if (r)
1702 goto out;
1703
1704 r = -EFAULT;
1705 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1706 goto out;
1707 r = 0;
1708 break;
1709 }
890ca9ae
HY		 1710 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1711 u64 mce_cap;
1712
1713 mce_cap = KVM_MCE_CAP_SUPPORTED;
1714 r = -EFAULT;
1715 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1716 goto out;
1717 r = 0;
1718 break;
1719 }
043405e1
CO		 1720 default:
1721 r = -EINVAL;
1722 }
1723out:
1724 return r;
1725}
1726
313a3dc7
CO		 1727void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1728{
1729 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1730 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1731 unsigned long khz = cpufreq_quick_get(cpu);
1732 if (!khz)
1733 khz = tsc_khz;
1734 per_cpu(cpu_tsc_khz, cpu) = khz;
1735 }
c8076604 1736 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1737}
1738
1739void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1740{
02daab21 1741 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1742 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1743}
1744
07716717 1745static int is_efer_nx(void)
313a3dc7 1746{
e286e86e 1747 unsigned long long efer = 0;
313a3dc7 1748
e286e86e 1749 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1750 return efer & EFER_NX;
1751}
1752
1753static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1754{
1755 int i;
1756 struct kvm_cpuid_entry2 *e, *entry;
1757
313a3dc7 1758 entry = NULL;
ad312c7c
ZX		 1759 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1760 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1761 if (e->function == 0x80000001) {
1762 entry = e;
1763 break;
1764 }
1765 }
07716717 1766 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1767 entry->edx &= ~(1 << 20);
1768 printk(KERN_INFO "kvm: guest NX capability removed\n");
1769 }
1770}
1771
07716717 1772/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1773static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1774 struct kvm_cpuid *cpuid,
1775 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1776{
1777 int r, i;
1778 struct kvm_cpuid_entry *cpuid_entries;
1779
1780 r = -E2BIG;
1781 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1782 goto out;
1783 r = -ENOMEM;
1784 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1785 if (!cpuid_entries)
1786 goto out;
1787 r = -EFAULT;
1788 if (copy_from_user(cpuid_entries, entries,
1789 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1790 goto out_free;
fe19c5a4 1791 vcpu_load(vcpu);
07716717 1792 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1793 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1794 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1795 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1796 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1797 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1798 vcpu->arch.cpuid_entries[i].index = 0;
1799 vcpu->arch.cpuid_entries[i].flags = 0;
1800 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1801 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1802 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1803 }
1804 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1805 cpuid_fix_nx_cap(vcpu);
1806 r = 0;
fc61b800 1807 kvm_apic_set_version(vcpu);
0e851880 1808 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1809 vcpu_put(vcpu);
07716717
DK		 1810
1811out_free:
1812 vfree(cpuid_entries);
1813out:
1814 return r;
1815}
1816
1817static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1818 struct kvm_cpuid2 *cpuid,
1819 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1820{
1821 int r;
1822
1823 r = -E2BIG;
1824 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1825 goto out;
1826 r = -EFAULT;
ad312c7c 1827 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1828 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1829 goto out;
fe19c5a4 1830 vcpu_load(vcpu);
ad312c7c 1831 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1832 kvm_apic_set_version(vcpu);
0e851880 1833 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1834 vcpu_put(vcpu);
313a3dc7
CO		 1835 return 0;
1836
1837out:
1838 return r;
1839}
1840
07716717 1841static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1842 struct kvm_cpuid2 *cpuid,
1843 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1844{
1845 int r;
1846
8fbf065d 1847 vcpu_load(vcpu);
07716717 1848 r = -E2BIG;
ad312c7c 1849 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1850 goto out;
1851 r = -EFAULT;
ad312c7c 1852 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1853 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1854 goto out;
1855 return 0;
1856
1857out:
ad312c7c 1858 cpuid->nent = vcpu->arch.cpuid_nent;
8fbf065d 1859 vcpu_put(vcpu);
07716717
DK		 1860 return r;
1861}
1862
07716717 1863static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1864 u32 index)
07716717
DK		 1865{
1866 entry->function = function;
1867 entry->index = index;
1868 cpuid_count(entry->function, entry->index,
19355475 1869 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1870 entry->flags = 0;
1871}
1872
7faa4ee1
AK		 1873#define F(x) bit(X86_FEATURE_##x)
1874
07716717
DK		 1875static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1876 u32 index, int *nent, int maxnent)
1877{
7faa4ee1 1878 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1879#ifdef CONFIG_X86_64
17cc3935
SY		 1880 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1881 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1882 unsigned f_lm = F(LM);
1883#else
17cc3935 1884 unsigned f_gbpages = 0;
7faa4ee1 1885 unsigned f_lm = 0;
07716717 1886#endif
4e47c7a6 1887 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1888
1889 /* cpuid 1.edx */
1890 const u32 kvm_supported_word0_x86_features =
1891 F(FPU) | F(VME) | F(DE) | F(PSE) |
1892 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1893 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1894 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1895 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1896 0 /* Reserved, DS, ACPI */ | F(MMX) |
1897 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1898 0 /* HTT, TM, Reserved, PBE */;
1899 /* cpuid 0x80000001.edx */
1900 const u32 kvm_supported_word1_x86_features =
1901 F(FPU) | F(VME) | F(DE) | F(PSE) |
1902 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1903 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1904 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1905 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1906 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1907 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1908 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1909 /* cpuid 1.ecx */
1910 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1911 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1912 0 /* DS-CPL, VMX, SMX, EST */ |
1913 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1914 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1915 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1916 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1917 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1918 /* cpuid 0x80000001.ecx */
07716717 1919 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1920 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1921 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1922 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1923 0 /* SKINIT */ | 0 /* WDT */;
07716717 1924
19355475 1925 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1926 get_cpu();
1927 do_cpuid_1_ent(entry, function, index);
1928 ++*nent;
1929
1930 switch (function) {
1931 case 0:
1932 entry->eax = min(entry->eax, (u32)0xb);
1933 break;
1934 case 1:
1935 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1936 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1937 /* we support x2apic emulation even if host does not support
1938 * it since we emulate x2apic in software */
1939 entry->ecx |= F(X2APIC);
07716717
DK		 1940 break;
1941 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1942 * may return different values. This forces us to get_cpu() before
1943 * issuing the first command, and also to emulate this annoying behavior
1944 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1945 case 2: {
1946 int t, times = entry->eax & 0xff;
1947
1948 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1949 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1950 for (t = 1; t < times && *nent < maxnent; ++t) {
1951 do_cpuid_1_ent(&entry[t], function, 0);
1952 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1953 ++*nent;
1954 }
1955 break;
1956 }
1957 /* function 4 and 0xb have additional index. */
1958 case 4: {
14af3f3c 1959 int i, cache_type;
07716717
DK		 1960
1961 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1962 /* read more entries until cache_type is zero */
14af3f3c
HH		 1963 for (i = 1; *nent < maxnent; ++i) {
1964 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1965 if (!cache_type)
1966 break;
14af3f3c
HH		 1967 do_cpuid_1_ent(&entry[i], function, i);
1968 entry[i].flags |=
07716717
DK		 1969 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1970 ++*nent;
1971 }
1972 break;
1973 }
1974 case 0xb: {
14af3f3c 1975 int i, level_type;
07716717
DK		 1976
1977 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1978 /* read more entries until level_type is zero */
14af3f3c 1979 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1980 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1981 if (!level_type)
1982 break;
14af3f3c
HH		 1983 do_cpuid_1_ent(&entry[i], function, i);
1984 entry[i].flags |=
07716717
DK		 1985 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1986 ++*nent;
1987 }
1988 break;
1989 }
84478c82
GC		 1990 case KVM_CPUID_SIGNATURE: {
1991 char signature[12] = "KVMKVMKVM\0\0";
1992 u32 *sigptr = (u32 *)signature;
1993 entry->eax = 0;
1994 entry->ebx = sigptr[0];
1995 entry->ecx = sigptr[1];
1996 entry->edx = sigptr[2];
1997 break;
1998 }
1999 case KVM_CPUID_FEATURES:
2000 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2001 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2002 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2003 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2004 entry->ebx = 0;
2005 entry->ecx = 0;
2006 entry->edx = 0;
2007 break;
07716717
DK		 2008 case 0x80000000:
2009 entry->eax = min(entry->eax, 0x8000001a);
2010 break;
2011 case 0x80000001:
2012 entry->edx &= kvm_supported_word1_x86_features;
2013 entry->ecx &= kvm_supported_word6_x86_features;
2014 break;
2015 }
d4330ef2
JR		 2016
2017 kvm_x86_ops->set_supported_cpuid(function, entry);
2018
07716717
DK		 2019 put_cpu();
2020}
2021
7faa4ee1
AK		 2022#undef F
2023
674eea0f 2024static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2025 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2026{
2027 struct kvm_cpuid_entry2 *cpuid_entries;
2028 int limit, nent = 0, r = -E2BIG;
2029 u32 func;
2030
2031 if (cpuid->nent < 1)
2032 goto out;
6a544355
AK		 2033 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2034 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2035 r = -ENOMEM;
2036 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2037 if (!cpuid_entries)
2038 goto out;
2039
2040 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2041 limit = cpuid_entries[0].eax;
2042 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2043 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2044 &nent, cpuid->nent);
07716717
DK		 2045 r = -E2BIG;
2046 if (nent >= cpuid->nent)
2047 goto out_free;
2048
2049 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2050 limit = cpuid_entries[nent - 1].eax;
2051 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2052 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2053 &nent, cpuid->nent);
84478c82
GC		 2054
2055
2056
2057 r = -E2BIG;
2058 if (nent >= cpuid->nent)
2059 goto out_free;
2060
2061 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2062 cpuid->nent);
2063
2064 r = -E2BIG;
2065 if (nent >= cpuid->nent)
2066 goto out_free;
2067
2068 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2069 cpuid->nent);
2070
cb007648
MM		 2071 r = -E2BIG;
2072 if (nent >= cpuid->nent)
2073 goto out_free;
2074
07716717
DK		 2075 r = -EFAULT;
2076 if (copy_to_user(entries, cpuid_entries,
19355475 2077 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2078 goto out_free;
2079 cpuid->nent = nent;
2080 r = 0;
2081
2082out_free:
2083 vfree(cpuid_entries);
2084out:
2085 return r;
2086}
2087
313a3dc7
CO		 2088static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2089 struct kvm_lapic_state *s)
2090{
2091 vcpu_load(vcpu);
ad312c7c 2092 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2093 vcpu_put(vcpu);
2094
2095 return 0;
2096}
2097
2098static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2099 struct kvm_lapic_state *s)
2100{
2101 vcpu_load(vcpu);
ad312c7c 2102 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2103 kvm_apic_post_state_restore(vcpu);
cb142eb7 2104 update_cr8_intercept(vcpu);
313a3dc7
CO		 2105 vcpu_put(vcpu);
2106
2107 return 0;
2108}
2109
f77bc6a4
ZX		 2110static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2111 struct kvm_interrupt *irq)
2112{
2113 if (irq->irq < 0 || irq->irq >= 256)
2114 return -EINVAL;
2115 if (irqchip_in_kernel(vcpu->kvm))
2116 return -ENXIO;
2117 vcpu_load(vcpu);
2118
66fd3f7f 2119 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2120
2121 vcpu_put(vcpu);
2122
2123 return 0;
2124}
2125
c4abb7c9
JK		 2126static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2127{
2128 vcpu_load(vcpu);
2129 kvm_inject_nmi(vcpu);
2130 vcpu_put(vcpu);
2131
2132 return 0;
2133}
2134
b209749f
AK		 2135static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2136 struct kvm_tpr_access_ctl *tac)
2137{
2138 if (tac->flags)
2139 return -EINVAL;
2140 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2141 return 0;
2142}
2143
890ca9ae
HY		 2144static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2145 u64 mcg_cap)
2146{
2147 int r;
2148 unsigned bank_num = mcg_cap & 0xff, bank;
2149
8fbf065d 2150 vcpu_load(vcpu);
890ca9ae 2151 r = -EINVAL;
a9e38c3e 2152 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2153 goto out;
2154 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2155 goto out;
2156 r = 0;
2157 vcpu->arch.mcg_cap = mcg_cap;
2158 /* Init IA32_MCG_CTL to all 1s */
2159 if (mcg_cap & MCG_CTL_P)
2160 vcpu->arch.mcg_ctl = ~(u64)0;
2161 /* Init IA32_MCi_CTL to all 1s */
2162 for (bank = 0; bank < bank_num; bank++)
2163 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2164out:
8fbf065d 2165 vcpu_put(vcpu);
890ca9ae
HY		 2166 return r;
2167}
2168
2169static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2170 struct kvm_x86_mce *mce)
2171{
2172 u64 mcg_cap = vcpu->arch.mcg_cap;
2173 unsigned bank_num = mcg_cap & 0xff;
2174 u64 *banks = vcpu->arch.mce_banks;
2175
2176 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2177 return -EINVAL;
2178 /*
2179 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2180 * reporting is disabled
2181 */
2182 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2183 vcpu->arch.mcg_ctl != ~(u64)0)
2184 return 0;
2185 banks += 4 * mce->bank;
2186 /*
2187 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2188 * reporting is disabled for the bank
2189 */
2190 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2191 return 0;
2192 if (mce->status & MCI_STATUS_UC) {
2193 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2194 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2195 printk(KERN_DEBUG "kvm: set_mce: "
2196 "injects mce exception while "
2197 "previous one is in progress!\n");
2198 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2199 return 0;
2200 }
2201 if (banks[1] & MCI_STATUS_VAL)
2202 mce->status |= MCI_STATUS_OVER;
2203 banks[2] = mce->addr;
2204 banks[3] = mce->misc;
2205 vcpu->arch.mcg_status = mce->mcg_status;
2206 banks[1] = mce->status;
2207 kvm_queue_exception(vcpu, MC_VECTOR);
2208 } else if (!(banks[1] & MCI_STATUS_VAL)
2209 || !(banks[1] & MCI_STATUS_UC)) {
2210 if (banks[1] & MCI_STATUS_VAL)
2211 mce->status |= MCI_STATUS_OVER;
2212 banks[2] = mce->addr;
2213 banks[3] = mce->misc;
2214 banks[1] = mce->status;
2215 } else
2216 banks[1] |= MCI_STATUS_OVER;
2217 return 0;
2218}
2219
3cfc3092
JK		 2220static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2221 struct kvm_vcpu_events *events)
2222{
2223 vcpu_load(vcpu);
2224
03b82a30
JK		 2225 events->exception.injected =
2226 vcpu->arch.exception.pending &&
2227 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2228 events->exception.nr = vcpu->arch.exception.nr;
2229 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2230 events->exception.error_code = vcpu->arch.exception.error_code;
2231
03b82a30
JK		 2232 events->interrupt.injected =
2233 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2234 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2235 events->interrupt.soft = 0;
48005f64
JK		 2236 events->interrupt.shadow =
2237 kvm_x86_ops->get_interrupt_shadow(vcpu,
2238 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2239
2240 events->nmi.injected = vcpu->arch.nmi_injected;
2241 events->nmi.pending = vcpu->arch.nmi_pending;
2242 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2243
2244 events->sipi_vector = vcpu->arch.sipi_vector;
2245
dab4b911 2246 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2247 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2248 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2249
2250 vcpu_put(vcpu);
2251}
2252
2253static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2254 struct kvm_vcpu_events *events)
2255{
dab4b911 2256 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2257 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2258 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2259 return -EINVAL;
2260
2261 vcpu_load(vcpu);
2262
2263 vcpu->arch.exception.pending = events->exception.injected;
2264 vcpu->arch.exception.nr = events->exception.nr;
2265 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2266 vcpu->arch.exception.error_code = events->exception.error_code;
2267
2268 vcpu->arch.interrupt.pending = events->interrupt.injected;
2269 vcpu->arch.interrupt.nr = events->interrupt.nr;
2270 vcpu->arch.interrupt.soft = events->interrupt.soft;
2271 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2272 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2273 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2274 kvm_x86_ops->set_interrupt_shadow(vcpu,
2275 events->interrupt.shadow);
3cfc3092
JK		 2276
2277 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2278 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2279 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2280 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2281
dab4b911
JK		 2282 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2283 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2284
2285 vcpu_put(vcpu);
2286
2287 return 0;
2288}
2289
a1efbe77
JK		 2290static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2291 struct kvm_debugregs *dbgregs)
2292{
2293 vcpu_load(vcpu);
2294
2295 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2296 dbgregs->dr6 = vcpu->arch.dr6;
2297 dbgregs->dr7 = vcpu->arch.dr7;
2298 dbgregs->flags = 0;
2299
2300 vcpu_put(vcpu);
2301}
2302
2303static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2304 struct kvm_debugregs *dbgregs)
2305{
2306 if (dbgregs->flags)
2307 return -EINVAL;
2308
2309 vcpu_load(vcpu);
2310
2311 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2312 vcpu->arch.dr6 = dbgregs->dr6;
2313 vcpu->arch.dr7 = dbgregs->dr7;
2314
2315 vcpu_put(vcpu);
2316
2317 return 0;
2318}
2319
313a3dc7
CO		 2320long kvm_arch_vcpu_ioctl(struct file *filp,
2321 unsigned int ioctl, unsigned long arg)
2322{
2323 struct kvm_vcpu *vcpu = filp->private_data;
2324 void __user *argp = (void __user *)arg;
2325 int r;
b772ff36 2326 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2327
2328 switch (ioctl) {
2329 case KVM_GET_LAPIC: {
2204ae3c
MT		 2330 r = -EINVAL;
2331 if (!vcpu->arch.apic)
2332 goto out;
b772ff36 2333 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2334
b772ff36
DH		 2335 r = -ENOMEM;
2336 if (!lapic)
2337 goto out;
2338 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2339 if (r)
2340 goto out;
2341 r = -EFAULT;
b772ff36 2342 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2343 goto out;
2344 r = 0;
2345 break;
2346 }
2347 case KVM_SET_LAPIC: {
2204ae3c
MT		 2348 r = -EINVAL;
2349 if (!vcpu->arch.apic)
2350 goto out;
b772ff36
DH		 2351 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2352 r = -ENOMEM;
2353 if (!lapic)
2354 goto out;
313a3dc7 2355 r = -EFAULT;
b772ff36 2356 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2357 goto out;
b772ff36 2358 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2359 if (r)
2360 goto out;
2361 r = 0;
2362 break;
2363 }
f77bc6a4
ZX		 2364 case KVM_INTERRUPT: {
2365 struct kvm_interrupt irq;
2366
2367 r = -EFAULT;
2368 if (copy_from_user(&irq, argp, sizeof irq))
2369 goto out;
2370 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2371 if (r)
2372 goto out;
2373 r = 0;
2374 break;
2375 }
c4abb7c9
JK		 2376 case KVM_NMI: {
2377 r = kvm_vcpu_ioctl_nmi(vcpu);
2378 if (r)
2379 goto out;
2380 r = 0;
2381 break;
2382 }
313a3dc7
CO		 2383 case KVM_SET_CPUID: {
2384 struct kvm_cpuid __user *cpuid_arg = argp;
2385 struct kvm_cpuid cpuid;
2386
2387 r = -EFAULT;
2388 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2389 goto out;
2390 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2391 if (r)
2392 goto out;
2393 break;
2394 }
07716717
DK		 2395 case KVM_SET_CPUID2: {
2396 struct kvm_cpuid2 __user *cpuid_arg = argp;
2397 struct kvm_cpuid2 cpuid;
2398
2399 r = -EFAULT;
2400 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2401 goto out;
2402 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2403 cpuid_arg->entries);
07716717
DK		 2404 if (r)
2405 goto out;
2406 break;
2407 }
2408 case KVM_GET_CPUID2: {
2409 struct kvm_cpuid2 __user *cpuid_arg = argp;
2410 struct kvm_cpuid2 cpuid;
2411
2412 r = -EFAULT;
2413 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2414 goto out;
2415 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2416 cpuid_arg->entries);
07716717
DK		 2417 if (r)
2418 goto out;
2419 r = -EFAULT;
2420 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2421 goto out;
2422 r = 0;
2423 break;
2424 }
313a3dc7
CO		 2425 case KVM_GET_MSRS:
2426 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2427 break;
2428 case KVM_SET_MSRS:
2429 r = msr_io(vcpu, argp, do_set_msr, 0);
2430 break;
b209749f
AK		 2431 case KVM_TPR_ACCESS_REPORTING: {
2432 struct kvm_tpr_access_ctl tac;
2433
2434 r = -EFAULT;
2435 if (copy_from_user(&tac, argp, sizeof tac))
2436 goto out;
2437 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2438 if (r)
2439 goto out;
2440 r = -EFAULT;
2441 if (copy_to_user(argp, &tac, sizeof tac))
2442 goto out;
2443 r = 0;
2444 break;
2445 };
b93463aa
AK		 2446 case KVM_SET_VAPIC_ADDR: {
2447 struct kvm_vapic_addr va;
2448
2449 r = -EINVAL;
2450 if (!irqchip_in_kernel(vcpu->kvm))
2451 goto out;
2452 r = -EFAULT;
2453 if (copy_from_user(&va, argp, sizeof va))
2454 goto out;
2455 r = 0;
2456 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2457 break;
2458 }
890ca9ae
HY		 2459 case KVM_X86_SETUP_MCE: {
2460 u64 mcg_cap;
2461
2462 r = -EFAULT;
2463 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2464 goto out;
2465 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2466 break;
2467 }
2468 case KVM_X86_SET_MCE: {
2469 struct kvm_x86_mce mce;
2470
2471 r = -EFAULT;
2472 if (copy_from_user(&mce, argp, sizeof mce))
2473 goto out;
8fbf065d 2474 vcpu_load(vcpu);
890ca9ae 2475 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
8fbf065d 2476 vcpu_put(vcpu);
890ca9ae
HY		 2477 break;
2478 }
3cfc3092
JK		 2479 case KVM_GET_VCPU_EVENTS: {
2480 struct kvm_vcpu_events events;
2481
2482 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2483
2484 r = -EFAULT;
2485 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2486 break;
2487 r = 0;
2488 break;
2489 }
2490 case KVM_SET_VCPU_EVENTS: {
2491 struct kvm_vcpu_events events;
2492
2493 r = -EFAULT;
2494 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2495 break;
2496
2497 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2498 break;
2499 }
a1efbe77
JK		 2500 case KVM_GET_DEBUGREGS: {
2501 struct kvm_debugregs dbgregs;
2502
2503 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2504
2505 r = -EFAULT;
2506 if (copy_to_user(argp, &dbgregs,
2507 sizeof(struct kvm_debugregs)))
2508 break;
2509 r = 0;
2510 break;
2511 }
2512 case KVM_SET_DEBUGREGS: {
2513 struct kvm_debugregs dbgregs;
2514
2515 r = -EFAULT;
2516 if (copy_from_user(&dbgregs, argp,
2517 sizeof(struct kvm_debugregs)))
2518 break;
2519
2520 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2521 break;
2522 }
313a3dc7
CO		 2523 default:
2524 r = -EINVAL;
2525 }
2526out:
7a6ce84c 2527 kfree(lapic);
313a3dc7
CO		 2528 return r;
2529}
2530
1fe779f8
CO		 2531static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2532{
2533 int ret;
2534
2535 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2536 return -1;
2537 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2538 return ret;
2539}
2540
b927a3ce
SY		 2541static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2542 u64 ident_addr)
2543{
2544 kvm->arch.ept_identity_map_addr = ident_addr;
2545 return 0;
2546}
2547
1fe779f8
CO		 2548static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2549 u32 kvm_nr_mmu_pages)
2550{
2551 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2552 return -EINVAL;
2553
79fac95e 2554 mutex_lock(&kvm->slots_lock);
7c8a83b7 2555 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2556
2557 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2558 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2559
7c8a83b7 2560 spin_unlock(&kvm->mmu_lock);
79fac95e 2561 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2562 return 0;
2563}
2564
2565static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2566{
f05e70ac 2567 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2568}
2569
a983fb23
MT		 2570gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2571{
2572 int i;
2573 struct kvm_mem_alias *alias;
2574 struct kvm_mem_aliases *aliases;
2575
90d83dc3 2576 aliases = kvm_aliases(kvm);
a983fb23
MT		 2577
2578 for (i = 0; i < aliases->naliases; ++i) {
2579 alias = &aliases->aliases[i];
2580 if (alias->flags & KVM_ALIAS_INVALID)
2581 continue;
2582 if (gfn >= alias->base_gfn
2583 && gfn < alias->base_gfn + alias->npages)
2584 return alias->target_gfn + gfn - alias->base_gfn;
2585 }
2586 return gfn;
2587}
2588
e9f85cde
ZX		 2589gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2590{
2591 int i;
2592 struct kvm_mem_alias *alias;
a983fb23
MT		 2593 struct kvm_mem_aliases *aliases;
2594
90d83dc3 2595 aliases = kvm_aliases(kvm);
e9f85cde 2596
fef9cce0
MT		 2597 for (i = 0; i < aliases->naliases; ++i) {
2598 alias = &aliases->aliases[i];
e9f85cde
ZX		 2599 if (gfn >= alias->base_gfn
2600 && gfn < alias->base_gfn + alias->npages)
2601 return alias->target_gfn + gfn - alias->base_gfn;
2602 }
2603 return gfn;
2604}
2605
1fe779f8
CO		 2606/*
2607 * Set a new alias region. Aliases map a portion of physical memory into
2608 * another portion. This is useful for memory windows, for example the PC
2609 * VGA region.
2610 */
2611static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2612 struct kvm_memory_alias *alias)
2613{
2614 int r, n;
2615 struct kvm_mem_alias *p;
a983fb23 2616 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2617
2618 r = -EINVAL;
2619 /* General sanity checks */
2620 if (alias->memory_size & (PAGE_SIZE - 1))
2621 goto out;
2622 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2623 goto out;
2624 if (alias->slot >= KVM_ALIAS_SLOTS)
2625 goto out;
2626 if (alias->guest_phys_addr + alias->memory_size
2627 < alias->guest_phys_addr)
2628 goto out;
2629 if (alias->target_phys_addr + alias->memory_size
2630 < alias->target_phys_addr)
2631 goto out;
2632
a983fb23
MT		 2633 r = -ENOMEM;
2634 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2635 if (!aliases)
2636 goto out;
2637
79fac95e 2638 mutex_lock(&kvm->slots_lock);
1fe779f8 2639
a983fb23
MT		 2640 /* invalidate any gfn reference in case of deletion/shrinking */
2641 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2642 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2643 old_aliases = kvm->arch.aliases;
2644 rcu_assign_pointer(kvm->arch.aliases, aliases);
2645 synchronize_srcu_expedited(&kvm->srcu);
2646 kvm_mmu_zap_all(kvm);
2647 kfree(old_aliases);
2648
2649 r = -ENOMEM;
2650 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2651 if (!aliases)
2652 goto out_unlock;
2653
2654 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2655
2656 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2657 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2658 p->npages = alias->memory_size >> PAGE_SHIFT;
2659 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2660 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2661
2662 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2663 if (aliases->aliases[n - 1].npages)
1fe779f8 2664 break;
fef9cce0 2665 aliases->naliases = n;
1fe779f8 2666
a983fb23
MT		 2667 old_aliases = kvm->arch.aliases;
2668 rcu_assign_pointer(kvm->arch.aliases, aliases);
2669 synchronize_srcu_expedited(&kvm->srcu);
2670 kfree(old_aliases);
2671 r = 0;
1fe779f8 2672
a983fb23 2673out_unlock:
79fac95e 2674 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2675out:
2676 return r;
2677}
2678
2679static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2680{
2681 int r;
2682
2683 r = 0;
2684 switch (chip->chip_id) {
2685 case KVM_IRQCHIP_PIC_MASTER:
2686 memcpy(&chip->chip.pic,
2687 &pic_irqchip(kvm)->pics[0],
2688 sizeof(struct kvm_pic_state));
2689 break;
2690 case KVM_IRQCHIP_PIC_SLAVE:
2691 memcpy(&chip->chip.pic,
2692 &pic_irqchip(kvm)->pics[1],
2693 sizeof(struct kvm_pic_state));
2694 break;
2695 case KVM_IRQCHIP_IOAPIC:
eba0226b 2696 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2697 break;
2698 default:
2699 r = -EINVAL;
2700 break;
2701 }
2702 return r;
2703}
2704
2705static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2706{
2707 int r;
2708
2709 r = 0;
2710 switch (chip->chip_id) {
2711 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2712 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2713 memcpy(&pic_irqchip(kvm)->pics[0],
2714 &chip->chip.pic,
2715 sizeof(struct kvm_pic_state));
fa8273e9 2716 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2717 break;
2718 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2719 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2720 memcpy(&pic_irqchip(kvm)->pics[1],
2721 &chip->chip.pic,
2722 sizeof(struct kvm_pic_state));
fa8273e9 2723 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2724 break;
2725 case KVM_IRQCHIP_IOAPIC:
eba0226b 2726 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2727 break;
2728 default:
2729 r = -EINVAL;
2730 break;
2731 }
2732 kvm_pic_update_irq(pic_irqchip(kvm));
2733 return r;
2734}
2735
e0f63cb9
SY		 2736static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2737{
2738 int r = 0;
2739
894a9c55 2740 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2741 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2742 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2743 return r;
2744}
2745
2746static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2747{
2748 int r = 0;
2749
894a9c55 2750 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2751 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2752 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2753 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2754 return r;
2755}
2756
2757static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2758{
2759 int r = 0;
2760
2761 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2762 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2763 sizeof(ps->channels));
2764 ps->flags = kvm->arch.vpit->pit_state.flags;
2765 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2766 return r;
2767}
2768
2769static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2770{
2771 int r = 0, start = 0;
2772 u32 prev_legacy, cur_legacy;
2773 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2774 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2775 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2776 if (!prev_legacy && cur_legacy)
2777 start = 1;
2778 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2779 sizeof(kvm->arch.vpit->pit_state.channels));
2780 kvm->arch.vpit->pit_state.flags = ps->flags;
2781 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2782 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2783 return r;
2784}
2785
52d939a0
MT		 2786static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2787 struct kvm_reinject_control *control)
2788{
2789 if (!kvm->arch.vpit)
2790 return -ENXIO;
894a9c55 2791 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2792 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2793 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2794 return 0;
2795}
2796
5bb064dc
ZX		 2797/*
2798 * Get (and clear) the dirty memory log for a memory slot.
2799 */
2800int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2801 struct kvm_dirty_log *log)
2802{
87bf6e7d 2803 int r, i;
5bb064dc 2804 struct kvm_memory_slot *memslot;
87bf6e7d 2805 unsigned long n;
b050b015 2806 unsigned long is_dirty = 0;
5bb064dc 2807
79fac95e 2808 mutex_lock(&kvm->slots_lock);
5bb064dc 2809
b050b015
MT		 2810 r = -EINVAL;
2811 if (log->slot >= KVM_MEMORY_SLOTS)
2812 goto out;
2813
2814 memslot = &kvm->memslots->memslots[log->slot];
2815 r = -ENOENT;
2816 if (!memslot->dirty_bitmap)
2817 goto out;
2818
87bf6e7d 2819 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2820
b050b015
MT		 2821 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2822 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2823
2824 /* If nothing is dirty, don't bother messing with page tables. */
2825 if (is_dirty) {
b050b015 2826 struct kvm_memslots *slots, *old_slots;
914ebccd 2827 unsigned long *dirty_bitmap;
b050b015 2828
7c8a83b7 2829 spin_lock(&kvm->mmu_lock);
5bb064dc 2830 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2831 spin_unlock(&kvm->mmu_lock);
b050b015 2832
914ebccd
TY		 2833 r = -ENOMEM;
2834 dirty_bitmap = vmalloc(n);
2835 if (!dirty_bitmap)
2836 goto out;
2837 memset(dirty_bitmap, 0, n);
b050b015 2838
914ebccd
TY		 2839 r = -ENOMEM;
2840 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2841 if (!slots) {
2842 vfree(dirty_bitmap);
2843 goto out;
2844 }
b050b015
MT		 2845 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2846 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2847
2848 old_slots = kvm->memslots;
2849 rcu_assign_pointer(kvm->memslots, slots);
2850 synchronize_srcu_expedited(&kvm->srcu);
2851 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2852 kfree(old_slots);
914ebccd
TY		 2853
2854 r = -EFAULT;
2855 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2856 vfree(dirty_bitmap);
2857 goto out;
2858 }
2859 vfree(dirty_bitmap);
2860 } else {
2861 r = -EFAULT;
2862 if (clear_user(log->dirty_bitmap, n))
2863 goto out;
5bb064dc 2864 }
b050b015 2865
5bb064dc
ZX		 2866 r = 0;
2867out:
79fac95e 2868 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2869 return r;
2870}
2871
1fe779f8
CO		 2872long kvm_arch_vm_ioctl(struct file *filp,
2873 unsigned int ioctl, unsigned long arg)
2874{
2875 struct kvm *kvm = filp->private_data;
2876 void __user *argp = (void __user *)arg;
367e1319 2877 int r = -ENOTTY;
f0d66275
DH		 2878 /*
2879 * This union makes it completely explicit to gcc-3.x
2880 * that these two variables' stack usage should be
2881 * combined, not added together.
2882 */
2883 union {
2884 struct kvm_pit_state ps;
e9f42757 2885 struct kvm_pit_state2 ps2;
f0d66275 2886 struct kvm_memory_alias alias;
c5ff41ce 2887 struct kvm_pit_config pit_config;
f0d66275 2888 } u;
1fe779f8
CO		 2889
2890 switch (ioctl) {
2891 case KVM_SET_TSS_ADDR:
2892 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2893 if (r < 0)
2894 goto out;
2895 break;
b927a3ce
SY		 2896 case KVM_SET_IDENTITY_MAP_ADDR: {
2897 u64 ident_addr;
2898
2899 r = -EFAULT;
2900 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2901 goto out;
2902 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2903 if (r < 0)
2904 goto out;
2905 break;
2906 }
1fe779f8
CO		 2907 case KVM_SET_MEMORY_REGION: {
2908 struct kvm_memory_region kvm_mem;
2909 struct kvm_userspace_memory_region kvm_userspace_mem;
2910
2911 r = -EFAULT;
2912 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2913 goto out;
2914 kvm_userspace_mem.slot = kvm_mem.slot;
2915 kvm_userspace_mem.flags = kvm_mem.flags;
2916 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2917 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2918 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2919 if (r)
2920 goto out;
2921 break;
2922 }
2923 case KVM_SET_NR_MMU_PAGES:
2924 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2925 if (r)
2926 goto out;
2927 break;
2928 case KVM_GET_NR_MMU_PAGES:
2929 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2930 break;
f0d66275 2931 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2932 r = -EFAULT;
f0d66275 2933 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2934 goto out;
f0d66275 2935 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2936 if (r)
2937 goto out;
2938 break;
3ddea128
MT		 2939 case KVM_CREATE_IRQCHIP: {
2940 struct kvm_pic *vpic;
2941
2942 mutex_lock(&kvm->lock);
2943 r = -EEXIST;
2944 if (kvm->arch.vpic)
2945 goto create_irqchip_unlock;
1fe779f8 2946 r = -ENOMEM;
3ddea128
MT		 2947 vpic = kvm_create_pic(kvm);
2948 if (vpic) {
1fe779f8
CO		 2949 r = kvm_ioapic_init(kvm);
2950 if (r) {
72bb2fcd
WY		 2951 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2952 &vpic->dev);
3ddea128
MT		 2953 kfree(vpic);
2954 goto create_irqchip_unlock;
1fe779f8
CO		 2955 }
2956 } else
3ddea128
MT		 2957 goto create_irqchip_unlock;
2958 smp_wmb();
2959 kvm->arch.vpic = vpic;
2960 smp_wmb();
399ec807
AK		 2961 r = kvm_setup_default_irq_routing(kvm);
2962 if (r) {
3ddea128 2963 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2964 kvm_ioapic_destroy(kvm);
2965 kvm_destroy_pic(kvm);
3ddea128 2966 mutex_unlock(&kvm->irq_lock);
399ec807 2967 }
3ddea128
MT		 2968 create_irqchip_unlock:
2969 mutex_unlock(&kvm->lock);
1fe779f8 2970 break;
3ddea128 2971 }
7837699f 2972 case KVM_CREATE_PIT:
c5ff41ce
JK		 2973 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2974 goto create_pit;
2975 case KVM_CREATE_PIT2:
2976 r = -EFAULT;
2977 if (copy_from_user(&u.pit_config, argp,
2978 sizeof(struct kvm_pit_config)))
2979 goto out;
2980 create_pit:
79fac95e 2981 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2982 r = -EEXIST;
2983 if (kvm->arch.vpit)
2984 goto create_pit_unlock;
7837699f 2985 r = -ENOMEM;
c5ff41ce 2986 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2987 if (kvm->arch.vpit)
2988 r = 0;
269e05e4 2989 create_pit_unlock:
79fac95e 2990 mutex_unlock(&kvm->slots_lock);
7837699f 2991 break;
4925663a 2992 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2993 case KVM_IRQ_LINE: {
2994 struct kvm_irq_level irq_event;
2995
2996 r = -EFAULT;
2997 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2998 goto out;
160d2f6c 2999 r = -ENXIO;
1fe779f8 3000 if (irqchip_in_kernel(kvm)) {
4925663a 3001 __s32 status;
4925663a
GN		 3002 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3003 irq_event.irq, irq_event.level);
4925663a 3004 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3005 r = -EFAULT;
4925663a
GN		 3006 irq_event.status = status;
3007 if (copy_to_user(argp, &irq_event,
3008 sizeof irq_event))
3009 goto out;
3010 }
1fe779f8
CO		 3011 r = 0;
3012 }
3013 break;
3014 }
3015 case KVM_GET_IRQCHIP: {
3016 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3017 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3018
f0d66275
DH		 3019 r = -ENOMEM;
3020 if (!chip)
1fe779f8 3021 goto out;
f0d66275
DH		 3022 r = -EFAULT;
3023 if (copy_from_user(chip, argp, sizeof *chip))
3024 goto get_irqchip_out;
1fe779f8
CO		 3025 r = -ENXIO;
3026 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3027 goto get_irqchip_out;
3028 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3029 if (r)
f0d66275 3030 goto get_irqchip_out;
1fe779f8 3031 r = -EFAULT;
f0d66275
DH		 3032 if (copy_to_user(argp, chip, sizeof *chip))
3033 goto get_irqchip_out;
1fe779f8 3034 r = 0;
f0d66275
DH		 3035 get_irqchip_out:
3036 kfree(chip);
3037 if (r)
3038 goto out;
1fe779f8
CO		 3039 break;
3040 }
3041 case KVM_SET_IRQCHIP: {
3042 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3043 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3044
f0d66275
DH		 3045 r = -ENOMEM;
3046 if (!chip)
1fe779f8 3047 goto out;
f0d66275
DH		 3048 r = -EFAULT;
3049 if (copy_from_user(chip, argp, sizeof *chip))
3050 goto set_irqchip_out;
1fe779f8
CO		 3051 r = -ENXIO;
3052 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3053 goto set_irqchip_out;
3054 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3055 if (r)
f0d66275 3056 goto set_irqchip_out;
1fe779f8 3057 r = 0;
f0d66275
DH		 3058 set_irqchip_out:
3059 kfree(chip);
3060 if (r)
3061 goto out;
1fe779f8
CO		 3062 break;
3063 }
e0f63cb9 3064 case KVM_GET_PIT: {
e0f63cb9 3065 r = -EFAULT;
f0d66275 3066 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3067 goto out;
3068 r = -ENXIO;
3069 if (!kvm->arch.vpit)
3070 goto out;
f0d66275 3071 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3072 if (r)
3073 goto out;
3074 r = -EFAULT;
f0d66275 3075 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3076 goto out;
3077 r = 0;
3078 break;
3079 }
3080 case KVM_SET_PIT: {
e0f63cb9 3081 r = -EFAULT;
f0d66275 3082 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3083 goto out;
3084 r = -ENXIO;
3085 if (!kvm->arch.vpit)
3086 goto out;
f0d66275 3087 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3088 if (r)
3089 goto out;
3090 r = 0;
3091 break;
3092 }
e9f42757
BK		 3093 case KVM_GET_PIT2: {
3094 r = -ENXIO;
3095 if (!kvm->arch.vpit)
3096 goto out;
3097 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3098 if (r)
3099 goto out;
3100 r = -EFAULT;
3101 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3102 goto out;
3103 r = 0;
3104 break;
3105 }
3106 case KVM_SET_PIT2: {
3107 r = -EFAULT;
3108 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3109 goto out;
3110 r = -ENXIO;
3111 if (!kvm->arch.vpit)
3112 goto out;
3113 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3114 if (r)
3115 goto out;
3116 r = 0;
3117 break;
3118 }
52d939a0
MT		 3119 case KVM_REINJECT_CONTROL: {
3120 struct kvm_reinject_control control;
3121 r = -EFAULT;
3122 if (copy_from_user(&control, argp, sizeof(control)))
3123 goto out;
3124 r = kvm_vm_ioctl_reinject(kvm, &control);
3125 if (r)
3126 goto out;
3127 r = 0;
3128 break;
3129 }
ffde22ac
ES		 3130 case KVM_XEN_HVM_CONFIG: {
3131 r = -EFAULT;
3132 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3133 sizeof(struct kvm_xen_hvm_config)))
3134 goto out;
3135 r = -EINVAL;
3136 if (kvm->arch.xen_hvm_config.flags)
3137 goto out;
3138 r = 0;
3139 break;
3140 }
afbcf7ab
GC		 3141 case KVM_SET_CLOCK: {
3142 struct timespec now;
3143 struct kvm_clock_data user_ns;
3144 u64 now_ns;
3145 s64 delta;
3146
3147 r = -EFAULT;
3148 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3149 goto out;
3150
3151 r = -EINVAL;
3152 if (user_ns.flags)
3153 goto out;
3154
3155 r = 0;
3156 ktime_get_ts(&now);
3157 now_ns = timespec_to_ns(&now);
3158 delta = user_ns.clock - now_ns;
3159 kvm->arch.kvmclock_offset = delta;
3160 break;
3161 }
3162 case KVM_GET_CLOCK: {
3163 struct timespec now;
3164 struct kvm_clock_data user_ns;
3165 u64 now_ns;
3166
3167 ktime_get_ts(&now);
3168 now_ns = timespec_to_ns(&now);
3169 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3170 user_ns.flags = 0;
3171
3172 r = -EFAULT;
3173 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3174 goto out;
3175 r = 0;
3176 break;
3177 }
3178
1fe779f8
CO		 3179 default:
3180 ;
3181 }
3182out:
3183 return r;
3184}
3185
a16b043c 3186static void kvm_init_msr_list(void)
043405e1
CO		 3187{
3188 u32 dummy[2];
3189 unsigned i, j;
3190
e3267cbb
GC		 3191 /* skip the first msrs in the list. KVM-specific */
3192 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3193 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3194 continue;
3195 if (j < i)
3196 msrs_to_save[j] = msrs_to_save[i];
3197 j++;
3198 }
3199 num_msrs_to_save = j;
3200}
3201
bda9020e
MT		 3202static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3203 const void *v)
bbd9b64e 3204{
bda9020e
MT		 3205 if (vcpu->arch.apic &&
3206 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3207 return 0;
bbd9b64e 3208
e93f8a0f 3209 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3210}
3211
bda9020e 3212static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3213{
bda9020e
MT		 3214 if (vcpu->arch.apic &&
3215 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3216 return 0;
bbd9b64e 3217
e93f8a0f 3218 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3219}
3220
2dafc6c2
GN		 3221static void kvm_set_segment(struct kvm_vcpu *vcpu,
3222 struct kvm_segment *var, int seg)
3223{
3224 kvm_x86_ops->set_segment(vcpu, var, seg);
3225}
3226
3227void kvm_get_segment(struct kvm_vcpu *vcpu,
3228 struct kvm_segment *var, int seg)
3229{
3230 kvm_x86_ops->get_segment(vcpu, var, seg);
3231}
3232
1871c602
GN		 3233gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3234{
3235 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3236 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3237}
3238
3239 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3240{
3241 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3242 access |= PFERR_FETCH_MASK;
3243 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3244}
3245
3246gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3247{
3248 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3249 access |= PFERR_WRITE_MASK;
3250 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3251}
3252
3253/* uses this to access any guest's mapped memory without checking CPL */
3254gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3255{
3256 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3257}
3258
3259static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3260 struct kvm_vcpu *vcpu, u32 access,
3261 u32 *error)
bbd9b64e
CO		 3262{
3263 void *data = val;
10589a46 3264 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3265
3266 while (bytes) {
1871c602 3267 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3268 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3269 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3270 int ret;
3271
10589a46
MT		 3272 if (gpa == UNMAPPED_GVA) {
3273 r = X86EMUL_PROPAGATE_FAULT;
3274 goto out;
3275 }
77c2002e 3276 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3277 if (ret < 0) {
c3cd7ffa 3278 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3279 goto out;
3280 }
bbd9b64e 3281
77c2002e
IE		 3282 bytes -= toread;
3283 data += toread;
3284 addr += toread;
bbd9b64e 3285 }
10589a46 3286out:
10589a46 3287 return r;
bbd9b64e 3288}
77c2002e 3289
1871c602
GN		 3290/* used for instruction fetching */
3291static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3292 struct kvm_vcpu *vcpu, u32 *error)
3293{
3294 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3295 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3296 access | PFERR_FETCH_MASK, error);
3297}
3298
3299static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3300 struct kvm_vcpu *vcpu, u32 *error)
3301{
3302 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3303 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3304 error);
3305}
3306
3307static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3308 struct kvm_vcpu *vcpu, u32 *error)
3309{
3310 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3311}
3312
7972995b 3313static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3314 unsigned int bytes,
7972995b 3315 struct kvm_vcpu *vcpu,
2dafc6c2 3316 u32 *error)
77c2002e
IE		 3317{
3318 void *data = val;
3319 int r = X86EMUL_CONTINUE;
3320
3321 while (bytes) {
7972995b
GN		 3322 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3323 PFERR_WRITE_MASK, error);
77c2002e
IE		 3324 unsigned offset = addr & (PAGE_SIZE-1);
3325 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3326 int ret;
3327
3328 if (gpa == UNMAPPED_GVA) {
3329 r = X86EMUL_PROPAGATE_FAULT;
3330 goto out;
3331 }
3332 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3333 if (ret < 0) {
c3cd7ffa 3334 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3335 goto out;
3336 }
3337
3338 bytes -= towrite;
3339 data += towrite;
3340 addr += towrite;
3341 }
3342out:
3343 return r;
3344}
3345
bbd9b64e
CO		 3346static int emulator_read_emulated(unsigned long addr,
3347 void *val,
3348 unsigned int bytes,
8fe681e9 3349 unsigned int *error_code,
bbd9b64e
CO		 3350 struct kvm_vcpu *vcpu)
3351{
bbd9b64e
CO		 3352 gpa_t gpa;
3353
3354 if (vcpu->mmio_read_completed) {
3355 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3356 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3357 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3358 vcpu->mmio_read_completed = 0;
3359 return X86EMUL_CONTINUE;
3360 }
3361
8fe681e9 3362 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3363
8fe681e9 3364 if (gpa == UNMAPPED_GVA)
1871c602 3365 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3366
3367 /* For APIC access vmexit */
3368 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3369 goto mmio;
3370
1871c602 3371 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3372 == X86EMUL_CONTINUE)
bbd9b64e 3373 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3374
3375mmio:
3376 /*
3377 * Is this MMIO handled locally?
3378 */
aec51dc4
AK		 3379 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3380 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3381 return X86EMUL_CONTINUE;
3382 }
aec51dc4
AK		 3383
3384 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3385
3386 vcpu->mmio_needed = 1;
411c35b7
GN		 3387 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3388 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3389 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3390 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3391
c3cd7ffa 3392 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3393}
3394
3200f405 3395int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3396 const void *val, int bytes)
bbd9b64e
CO		 3397{
3398 int ret;
3399
3400 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3401 if (ret < 0)
bbd9b64e 3402 return 0;
ad218f85 3403 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3404 return 1;
3405}
3406
3407static int emulator_write_emulated_onepage(unsigned long addr,
3408 const void *val,
3409 unsigned int bytes,
8fe681e9 3410 unsigned int *error_code,
bbd9b64e
CO		 3411 struct kvm_vcpu *vcpu)
3412{
10589a46
MT		 3413 gpa_t gpa;
3414
8fe681e9 3415 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3416
8fe681e9 3417 if (gpa == UNMAPPED_GVA)
bbd9b64e 3418 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3419
3420 /* For APIC access vmexit */
3421 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3422 goto mmio;
3423
3424 if (emulator_write_phys(vcpu, gpa, val, bytes))
3425 return X86EMUL_CONTINUE;
3426
3427mmio:
aec51dc4 3428 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3429 /*
3430 * Is this MMIO handled locally?
3431 */
bda9020e 3432 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3433 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3434
3435 vcpu->mmio_needed = 1;
411c35b7
GN		 3436 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3437 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3438 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3439 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3440 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3441
3442 return X86EMUL_CONTINUE;
3443}
3444
3445int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3446 const void *val,
3447 unsigned int bytes,
8fe681e9 3448 unsigned int *error_code,
8f6abd06 3449 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3450{
3451 /* Crossing a page boundary? */
3452 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3453 int rc, now;
3454
3455 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3456 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3457 vcpu);
bbd9b64e
CO		 3458 if (rc != X86EMUL_CONTINUE)
3459 return rc;
3460 addr += now;
3461 val += now;
3462 bytes -= now;
3463 }
8fe681e9
GN		 3464 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3465 vcpu);
bbd9b64e 3466}
bbd9b64e 3467
daea3e73
AK		 3468#define CMPXCHG_TYPE(t, ptr, old, new) \
3469 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3470
3471#ifdef CONFIG_X86_64
3472# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3473#else
3474# define CMPXCHG64(ptr, old, new) \
9749a6c0 3475 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3476#endif
3477
bbd9b64e
CO		 3478static int emulator_cmpxchg_emulated(unsigned long addr,
3479 const void *old,
3480 const void *new,
3481 unsigned int bytes,
8fe681e9 3482 unsigned int *error_code,
bbd9b64e
CO		 3483 struct kvm_vcpu *vcpu)
3484{
daea3e73
AK		 3485 gpa_t gpa;
3486 struct page *page;
3487 char *kaddr;
3488 bool exchanged;
2bacc55c 3489
daea3e73
AK		 3490 /* guests cmpxchg8b have to be emulated atomically */
3491 if (bytes > 8 || (bytes & (bytes - 1)))
3492 goto emul_write;
10589a46 3493
daea3e73 3494 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3495
daea3e73
AK		 3496 if (gpa == UNMAPPED_GVA ||
3497 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3498 goto emul_write;
2bacc55c 3499
daea3e73
AK		 3500 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3501 goto emul_write;
72dc67a6 3502
daea3e73 3503 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3504
daea3e73
AK		 3505 kaddr = kmap_atomic(page, KM_USER0);
3506 kaddr += offset_in_page(gpa);
3507 switch (bytes) {
3508 case 1:
3509 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3510 break;
3511 case 2:
3512 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3513 break;
3514 case 4:
3515 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3516 break;
3517 case 8:
3518 exchanged = CMPXCHG64(kaddr, old, new);
3519 break;
3520 default:
3521 BUG();
2bacc55c 3522 }
daea3e73
AK		 3523 kunmap_atomic(kaddr, KM_USER0);
3524 kvm_release_page_dirty(page);
3525
3526 if (!exchanged)
3527 return X86EMUL_CMPXCHG_FAILED;
3528
8f6abd06
GN		 3529 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3530
3531 return X86EMUL_CONTINUE;
4a5f48f6 3532
3200f405 3533emul_write:
daea3e73 3534 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3535
8fe681e9 3536 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3537}
3538
cf8f70bf
GN		 3539static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3540{
3541 /* TODO: String I/O for in kernel device */
3542 int r;
3543
3544 if (vcpu->arch.pio.in)
3545 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3546 vcpu->arch.pio.size, pd);
3547 else
3548 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3549 vcpu->arch.pio.port, vcpu->arch.pio.size,
3550 pd);
3551 return r;
3552}
3553
3554
3555static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3556 unsigned int count, struct kvm_vcpu *vcpu)
3557{
7972995b 3558 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3559 goto data_avail;
3560
3561 trace_kvm_pio(1, port, size, 1);
3562
3563 vcpu->arch.pio.port = port;
3564 vcpu->arch.pio.in = 1;
7972995b 3565 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3566 vcpu->arch.pio.size = size;
3567
3568 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3569 data_avail:
3570 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3571 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3572 return 1;
3573 }
3574
3575 vcpu->run->exit_reason = KVM_EXIT_IO;
3576 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3577 vcpu->run->io.size = size;
3578 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3579 vcpu->run->io.count = count;
3580 vcpu->run->io.port = port;
3581
3582 return 0;
3583}
3584
3585static int emulator_pio_out_emulated(int size, unsigned short port,
3586 const void *val, unsigned int count,
3587 struct kvm_vcpu *vcpu)
3588{
3589 trace_kvm_pio(0, port, size, 1);
3590
3591 vcpu->arch.pio.port = port;
3592 vcpu->arch.pio.in = 0;
7972995b 3593 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3594 vcpu->arch.pio.size = size;
3595
3596 memcpy(vcpu->arch.pio_data, val, size * count);
3597
3598 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3599 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3600 return 1;
3601 }
3602
3603 vcpu->run->exit_reason = KVM_EXIT_IO;
3604 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3605 vcpu->run->io.size = size;
3606 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3607 vcpu->run->io.count = count;
3608 vcpu->run->io.port = port;
3609
3610 return 0;
3611}
3612
bbd9b64e
CO		 3613static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3614{
3615 return kvm_x86_ops->get_segment_base(vcpu, seg);
3616}
3617
3618int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3619{
a7052897 3620 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3621 return X86EMUL_CONTINUE;
3622}
3623
3624int emulate_clts(struct kvm_vcpu *vcpu)
3625{
4d4ec087 3626 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3627 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3628 return X86EMUL_CONTINUE;
3629}
3630
35aa5375 3631int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3632{
338dbc97 3633 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3634}
3635
35aa5375 3636int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3637{
338dbc97
GN		 3638
3639 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3640}
3641
52a46617 3642static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3643{
52a46617 3644 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3645}
3646
52a46617 3647static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3648{
52a46617
GN		 3649 unsigned long value;
3650
3651 switch (cr) {
3652 case 0:
3653 value = kvm_read_cr0(vcpu);
3654 break;
3655 case 2:
3656 value = vcpu->arch.cr2;
3657 break;
3658 case 3:
3659 value = vcpu->arch.cr3;
3660 break;
3661 case 4:
3662 value = kvm_read_cr4(vcpu);
3663 break;
3664 case 8:
3665 value = kvm_get_cr8(vcpu);
3666 break;
3667 default:
3668 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3669 return 0;
3670 }
3671
3672 return value;
3673}
3674
0f12244f 3675static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3676{
0f12244f
GN		 3677 int res = 0;
3678
52a46617
GN		 3679 switch (cr) {
3680 case 0:
0f12244f 3681 res = __kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3682 break;
3683 case 2:
3684 vcpu->arch.cr2 = val;
3685 break;
3686 case 3:
0f12244f 3687 res = __kvm_set_cr3(vcpu, val);
52a46617
GN		 3688 break;
3689 case 4:
0f12244f 3690 res = __kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3691 break;
3692 case 8:
0f12244f 3693 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3694 break;
3695 default:
3696 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3697 res = -1;
52a46617 3698 }
0f12244f
GN		 3699
3700 return res;
52a46617
GN		 3701}
3702
9c537244
GN		 3703static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3704{
3705 return kvm_x86_ops->get_cpl(vcpu);
3706}
3707
2dafc6c2
GN		 3708static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3709{
3710 kvm_x86_ops->get_gdt(vcpu, dt);
3711}
3712
5951c442
GN		 3713static unsigned long emulator_get_cached_segment_base(int seg,
3714 struct kvm_vcpu *vcpu)
3715{
3716 return get_segment_base(vcpu, seg);
3717}
3718
2dafc6c2
GN		 3719static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3720 struct kvm_vcpu *vcpu)
3721{
3722 struct kvm_segment var;
3723
3724 kvm_get_segment(vcpu, &var, seg);
3725
3726 if (var.unusable)
3727 return false;
3728
3729 if (var.g)
3730 var.limit >>= 12;
3731 set_desc_limit(desc, var.limit);
3732 set_desc_base(desc, (unsigned long)var.base);
3733 desc->type = var.type;
3734 desc->s = var.s;
3735 desc->dpl = var.dpl;
3736 desc->p = var.present;
3737 desc->avl = var.avl;
3738 desc->l = var.l;
3739 desc->d = var.db;
3740 desc->g = var.g;
3741
3742 return true;
3743}
3744
3745static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3746 struct kvm_vcpu *vcpu)
3747{
3748 struct kvm_segment var;
3749
3750 /* needed to preserve selector */
3751 kvm_get_segment(vcpu, &var, seg);
3752
3753 var.base = get_desc_base(desc);
3754 var.limit = get_desc_limit(desc);
3755 if (desc->g)
3756 var.limit = (var.limit << 12) | 0xfff;
3757 var.type = desc->type;
3758 var.present = desc->p;
3759 var.dpl = desc->dpl;
3760 var.db = desc->d;
3761 var.s = desc->s;
3762 var.l = desc->l;
3763 var.g = desc->g;
3764 var.avl = desc->avl;
3765 var.present = desc->p;
3766 var.unusable = !var.present;
3767 var.padding = 0;
3768
3769 kvm_set_segment(vcpu, &var, seg);
3770 return;
3771}
3772
3773static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3774{
3775 struct kvm_segment kvm_seg;
3776
3777 kvm_get_segment(vcpu, &kvm_seg, seg);
3778 return kvm_seg.selector;
3779}
3780
3781static void emulator_set_segment_selector(u16 sel, int seg,
3782 struct kvm_vcpu *vcpu)
3783{
3784 struct kvm_segment kvm_seg;
3785
3786 kvm_get_segment(vcpu, &kvm_seg, seg);
3787 kvm_seg.selector = sel;
3788 kvm_set_segment(vcpu, &kvm_seg, seg);
3789}
3790
14af3f3c 3791static struct x86_emulate_ops emulate_ops = {
1871c602 3792 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3793 .write_std = kvm_write_guest_virt_system,
1871c602 3794 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3795 .read_emulated = emulator_read_emulated,
3796 .write_emulated = emulator_write_emulated,
3797 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3798 .pio_in_emulated = emulator_pio_in_emulated,
3799 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3800 .get_cached_descriptor = emulator_get_cached_descriptor,
3801 .set_cached_descriptor = emulator_set_cached_descriptor,
3802 .get_segment_selector = emulator_get_segment_selector,
3803 .set_segment_selector = emulator_set_segment_selector,
5951c442 3804 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3805 .get_gdt = emulator_get_gdt,
52a46617
GN		 3806 .get_cr = emulator_get_cr,
3807 .set_cr = emulator_set_cr,
9c537244 3808 .cpl = emulator_get_cpl,
35aa5375
GN		 3809 .get_dr = emulator_get_dr,
3810 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3811 .set_msr = kvm_set_msr,
3812 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3813};
3814
5fdbf976
MT		 3815static void cache_all_regs(struct kvm_vcpu *vcpu)
3816{
3817 kvm_register_read(vcpu, VCPU_REGS_RAX);
3818 kvm_register_read(vcpu, VCPU_REGS_RSP);
3819 kvm_register_read(vcpu, VCPU_REGS_RIP);
3820 vcpu->arch.regs_dirty = ~0;
3821}
3822
95cb2295
GN		 3823static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3824{
3825 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3826 /*
3827 * an sti; sti; sequence only disable interrupts for the first
3828 * instruction. So, if the last instruction, be it emulated or
3829 * not, left the system with the INT_STI flag enabled, it
3830 * means that the last instruction is an sti. We should not
3831 * leave the flag on in this case. The same goes for mov ss
3832 */
3833 if (!(int_shadow & mask))
3834 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3835}
3836
54b8486f
GN		 3837static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3838{
3839 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3840 if (ctxt->exception == PF_VECTOR)
3841 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3842 else if (ctxt->error_code_valid)
3843 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3844 else
3845 kvm_queue_exception(vcpu, ctxt->exception);
3846}
3847
6d77dbfc
GN		 3848static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3849{
3850 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3851
3852 ++vcpu->stat.insn_emulation_fail;
3853 trace_kvm_emulate_insn_failed(vcpu);
3854 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3855 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3856 vcpu->run->internal.ndata = 0;
3857 kvm_queue_exception(vcpu, UD_VECTOR);
3858 return EMULATE_FAIL;
3859}
3860
bbd9b64e 3861int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3862 unsigned long cr2,
3863 u16 error_code,
571008da 3864 int emulation_type)
bbd9b64e 3865{
95cb2295 3866 int r;
4d2179e1 3867 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3868
26eef70c 3869 kvm_clear_exception_queue(vcpu);
ad312c7c 3870 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3871 /*
56e82318 3872 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3873 * instead of direct ->regs accesses, can save hundred cycles
3874 * on Intel for instructions that don't read/change RSP, for
3875 * for example.
3876 */
3877 cache_all_regs(vcpu);
bbd9b64e 3878
571008da 3879 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3880 int cs_db, cs_l;
3881 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3882
ad312c7c 3883 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3884 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3885 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3886 vcpu->arch.emulate_ctxt.mode =
a0044755 3887 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3888 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3889 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3890 ? X86EMUL_MODE_PROT64 : cs_db
3891 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3892 memset(c, 0, sizeof(struct decode_cache));
3893 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3894 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3895 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3896
ad312c7c 3897 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3898 trace_kvm_emulate_insn_start(vcpu);
571008da 3899
0cb5762e
AP		 3900 /* Only allow emulation of specific instructions on #UD
3901 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 3902 if (emulation_type & EMULTYPE_TRAP_UD) {
3903 if (!c->twobyte)
3904 return EMULATE_FAIL;
3905 switch (c->b) {
3906 case 0x01: /* VMMCALL */
3907 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3908 return EMULATE_FAIL;
3909 break;
3910 case 0x34: /* sysenter */
3911 case 0x35: /* sysexit */
3912 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3913 return EMULATE_FAIL;
3914 break;
3915 case 0x05: /* syscall */
3916 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3917 return EMULATE_FAIL;
3918 break;
3919 default:
3920 return EMULATE_FAIL;
3921 }
3922
3923 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3924 return EMULATE_FAIL;
3925 }
571008da 3926
f2b5756b 3927 ++vcpu->stat.insn_emulation;
bbd9b64e
CO		 3928 if (r) {
3929 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3930 return EMULATE_DONE;
6d77dbfc
GN		 3931 if (emulation_type & EMULTYPE_SKIP)
3932 return EMULATE_FAIL;
3933 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3934 }
3935 }
3936
ba8afb6b
GN		 3937 if (emulation_type & EMULTYPE_SKIP) {
3938 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3939 return EMULATE_DONE;
3940 }
3941
4d2179e1
GN		 3942 /* this is needed for vmware backdor interface to work since it
3943 changes registers values during IO operation */
3944 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
3945
5cd21917 3946restart:
ad312c7c 3947 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 3948
c3cd7ffa
GN		 3949 if (r) { /* emulation failed */
3950 /*
3951 * if emulation was due to access to shadowed page table
3952 * and it failed try to unshadow page and re-entetr the
3953 * guest to let CPU execute the instruction.
3954 */
3955 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3956 return EMULATE_DONE;
3957
6d77dbfc 3958 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3959 }
3960
95cb2295 3961 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 3962 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 3963 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 3964 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 3965
54b8486f
GN		 3966 if (vcpu->arch.emulate_ctxt.exception >= 0) {
3967 inject_emulated_exception(vcpu);
3968 return EMULATE_DONE;
3969 }
3970
3457e419
GN		 3971 if (vcpu->arch.pio.count) {
3972 if (!vcpu->arch.pio.in)
3973 vcpu->arch.pio.count = 0;
3974 return EMULATE_DO_MMIO;
3975 }
3976
3977 if (vcpu->mmio_needed) {
3978 if (vcpu->mmio_is_write)
3979 vcpu->mmio_needed = 0;
3980 return EMULATE_DO_MMIO;
3981 }
3982
5cd21917
GN		 3983 if (vcpu->arch.emulate_ctxt.restart)
3984 goto restart;
f850e2e6 3985
bbd9b64e 3986 return EMULATE_DONE;
de7d789a 3987}
bbd9b64e 3988EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 3989
cf8f70bf 3990int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 3991{
cf8f70bf
GN		 3992 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3993 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3994 /* do not return to emulator after return from userspace */
7972995b 3995 vcpu->arch.pio.count = 0;
de7d789a
CO		 3996 return ret;
3997}
cf8f70bf 3998EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 3999
c8076604
GH		 4000static void bounce_off(void *info)
4001{
4002 /* nothing */
4003}
4004
c8076604
GH		 4005static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4006 void *data)
4007{
4008 struct cpufreq_freqs *freq = data;
4009 struct kvm *kvm;
4010 struct kvm_vcpu *vcpu;
4011 int i, send_ipi = 0;
4012
c8076604
GH		 4013 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4014 return 0;
4015 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4016 return 0;
0cca7907 4017 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 4018
4019 spin_lock(&kvm_lock);
4020 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4021 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4022 if (vcpu->cpu != freq->cpu)
4023 continue;
4024 if (!kvm_request_guest_time_update(vcpu))
4025 continue;
4026 if (vcpu->cpu != smp_processor_id())
4027 send_ipi++;
4028 }
4029 }
4030 spin_unlock(&kvm_lock);
4031
4032 if (freq->old < freq->new && send_ipi) {
4033 /*
4034 * We upscale the frequency. Must make the guest
4035 * doesn't see old kvmclock values while running with
4036 * the new frequency, otherwise we risk the guest sees
4037 * time go backwards.
4038 *
4039 * In case we update the frequency for another cpu
4040 * (which might be in guest context) send an interrupt
4041 * to kick the cpu out of guest context. Next time
4042 * guest context is entered kvmclock will be updated,
4043 * so the guest will not see stale values.
4044 */
4045 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4046 }
4047 return 0;
4048}
4049
4050static struct notifier_block kvmclock_cpufreq_notifier_block = {
4051 .notifier_call = kvmclock_cpufreq_notifier
4052};
4053
b820cc0c
ZA		 4054static void kvm_timer_init(void)
4055{
4056 int cpu;
4057
b820cc0c 4058 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4059 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4060 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4061 for_each_online_cpu(cpu) {
4062 unsigned long khz = cpufreq_get(cpu);
4063 if (!khz)
4064 khz = tsc_khz;
4065 per_cpu(cpu_tsc_khz, cpu) = khz;
4066 }
0cca7907
ZA		 4067 } else {
4068 for_each_possible_cpu(cpu)
4069 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4070 }
4071}
4072
ff9d07a0
ZY		 4073static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4074
4075static int kvm_is_in_guest(void)
4076{
4077 return percpu_read(current_vcpu) != NULL;
4078}
4079
4080static int kvm_is_user_mode(void)
4081{
4082 int user_mode = 3;
dcf46b94 4083
ff9d07a0
ZY		 4084 if (percpu_read(current_vcpu))
4085 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4086
ff9d07a0
ZY		 4087 return user_mode != 0;
4088}
4089
4090static unsigned long kvm_get_guest_ip(void)
4091{
4092 unsigned long ip = 0;
dcf46b94 4093
ff9d07a0
ZY		 4094 if (percpu_read(current_vcpu))
4095 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4096
ff9d07a0
ZY		 4097 return ip;
4098}
4099
4100static struct perf_guest_info_callbacks kvm_guest_cbs = {
4101 .is_in_guest = kvm_is_in_guest,
4102 .is_user_mode = kvm_is_user_mode,
4103 .get_guest_ip = kvm_get_guest_ip,
4104};
4105
4106void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4107{
4108 percpu_write(current_vcpu, vcpu);
4109}
4110EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4111
4112void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4113{
4114 percpu_write(current_vcpu, NULL);
4115}
4116EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4117
f8c16bba 4118int kvm_arch_init(void *opaque)
043405e1 4119{
b820cc0c 4120 int r;
f8c16bba
ZX		 4121 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4122
f8c16bba
ZX		 4123 if (kvm_x86_ops) {
4124 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4125 r = -EEXIST;
4126 goto out;
f8c16bba
ZX		 4127 }
4128
4129 if (!ops->cpu_has_kvm_support()) {
4130 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4131 r = -EOPNOTSUPP;
4132 goto out;
f8c16bba
ZX		 4133 }
4134 if (ops->disabled_by_bios()) {
4135 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4136 r = -EOPNOTSUPP;
4137 goto out;
f8c16bba
ZX		 4138 }
4139
97db56ce
AK		 4140 r = kvm_mmu_module_init();
4141 if (r)
4142 goto out;
4143
4144 kvm_init_msr_list();
4145
f8c16bba 4146 kvm_x86_ops = ops;
56c6d28a 4147 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4148 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4149 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4150 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4151
b820cc0c 4152 kvm_timer_init();
c8076604 4153
ff9d07a0
ZY		 4154 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4155
f8c16bba 4156 return 0;
56c6d28a
ZX		 4157
4158out:
56c6d28a 4159 return r;
043405e1 4160}
8776e519 4161
f8c16bba
ZX		 4162void kvm_arch_exit(void)
4163{
ff9d07a0
ZY		 4164 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4165
888d256e
JK		 4166 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4167 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4168 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4169 kvm_x86_ops = NULL;
56c6d28a
ZX		 4170 kvm_mmu_module_exit();
4171}
f8c16bba 4172
8776e519
HB		 4173int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4174{
4175 ++vcpu->stat.halt_exits;
4176 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4177 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4178 return 1;
4179 } else {
4180 vcpu->run->exit_reason = KVM_EXIT_HLT;
4181 return 0;
4182 }
4183}
4184EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4185
2f333bcb
MT		 4186static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4187 unsigned long a1)
4188{
4189 if (is_long_mode(vcpu))
4190 return a0;
4191 else
4192 return a0 | ((gpa_t)a1 << 32);
4193}
4194
55cd8e5a
GN		 4195int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4196{
4197 u64 param, ingpa, outgpa, ret;
4198 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4199 bool fast, longmode;
4200 int cs_db, cs_l;
4201
4202 /*
4203 * hypercall generates UD from non zero cpl and real mode
4204 * per HYPER-V spec
4205 */
3eeb3288 4206 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4207 kvm_queue_exception(vcpu, UD_VECTOR);
4208 return 0;
4209 }
4210
4211 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4212 longmode = is_long_mode(vcpu) && cs_l == 1;
4213
4214 if (!longmode) {
ccd46936
GN		 4215 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4216 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4217 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4218 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4219 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4220 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4221 }
4222#ifdef CONFIG_X86_64
4223 else {
4224 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4225 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4226 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4227 }
4228#endif
4229
4230 code = param & 0xffff;
4231 fast = (param >> 16) & 0x1;
4232 rep_cnt = (param >> 32) & 0xfff;
4233 rep_idx = (param >> 48) & 0xfff;
4234
4235 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4236
c25bc163
GN		 4237 switch (code) {
4238 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4239 kvm_vcpu_on_spin(vcpu);
4240 break;
4241 default:
4242 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4243 break;
4244 }
55cd8e5a
GN		 4245
4246 ret = res | (((u64)rep_done & 0xfff) << 32);
4247 if (longmode) {
4248 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4249 } else {
4250 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4251 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4252 }
4253
4254 return 1;
4255}
4256
8776e519
HB		 4257int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4258{
4259 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4260 int r = 1;
8776e519 4261
55cd8e5a
GN		 4262 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4263 return kvm_hv_hypercall(vcpu);
4264
5fdbf976
MT		 4265 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4266 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4267 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4268 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4269 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4270
229456fc 4271 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4272
8776e519
HB		 4273 if (!is_long_mode(vcpu)) {
4274 nr &= 0xFFFFFFFF;
4275 a0 &= 0xFFFFFFFF;
4276 a1 &= 0xFFFFFFFF;
4277 a2 &= 0xFFFFFFFF;
4278 a3 &= 0xFFFFFFFF;
4279 }
4280
07708c4a
JK		 4281 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4282 ret = -KVM_EPERM;
4283 goto out;
4284 }
4285
8776e519 4286 switch (nr) {
b93463aa
AK		 4287 case KVM_HC_VAPIC_POLL_IRQ:
4288 ret = 0;
4289 break;
2f333bcb
MT		 4290 case KVM_HC_MMU_OP:
4291 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4292 break;
8776e519
HB		 4293 default:
4294 ret = -KVM_ENOSYS;
4295 break;
4296 }
07708c4a 4297out:
5fdbf976 4298 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4299 ++vcpu->stat.hypercalls;
2f333bcb 4300 return r;
8776e519
HB		 4301}
4302EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4303
4304int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4305{
4306 char instruction[3];
5fdbf976 4307 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4308
8776e519
HB		 4309 /*
4310 * Blow out the MMU to ensure that no other VCPU has an active mapping
4311 * to ensure that the updated hypercall appears atomically across all
4312 * VCPUs.
4313 */
4314 kvm_mmu_zap_all(vcpu->kvm);
4315
8776e519 4316 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4317
8fe681e9 4318 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4319}
4320
8776e519
HB		 4321void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4322{
89a27f4d 4323 struct desc_ptr dt = { limit, base };
8776e519
HB		 4324
4325 kvm_x86_ops->set_gdt(vcpu, &dt);
4326}
4327
4328void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4329{
89a27f4d 4330 struct desc_ptr dt = { limit, base };
8776e519
HB		 4331
4332 kvm_x86_ops->set_idt(vcpu, &dt);
4333}
4334
07716717
DK		 4335static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4336{
ad312c7c
ZX		 4337 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4338 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4339
4340 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4341 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4342 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4343 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4344 if (ej->function == e->function) {
4345 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4346 return j;
4347 }
4348 }
4349 return 0; /* silence gcc, even though control never reaches here */
4350}
4351
4352/* find an entry with matching function, matching index (if needed), and that
4353 * should be read next (if it's stateful) */
4354static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4355 u32 function, u32 index)
4356{
4357 if (e->function != function)
4358 return 0;
4359 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4360 return 0;
4361 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4362 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4363 return 0;
4364 return 1;
4365}
4366
d8017474
AG		 4367struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4368 u32 function, u32 index)
8776e519
HB		 4369{
4370 int i;
d8017474 4371 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4372
ad312c7c 4373 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4374 struct kvm_cpuid_entry2 *e;
4375
ad312c7c 4376 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4377 if (is_matching_cpuid_entry(e, function, index)) {
4378 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4379 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4380 best = e;
4381 break;
4382 }
4383 /*
4384 * Both basic or both extended?
4385 */
4386 if (((e->function ^ function) & 0x80000000) == 0)
4387 if (!best || e->function > best->function)
4388 best = e;
4389 }
d8017474
AG		 4390 return best;
4391}
0e851880 4392EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4393
82725b20
DE		 4394int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4395{
4396 struct kvm_cpuid_entry2 *best;
4397
f7a71197
AK		 4398 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4399 if (!best || best->eax < 0x80000008)
4400 goto not_found;
82725b20
DE		 4401 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4402 if (best)
4403 return best->eax & 0xff;
f7a71197 4404not_found:
82725b20
DE		 4405 return 36;
4406}
4407
d8017474
AG		 4408void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4409{
4410 u32 function, index;
4411 struct kvm_cpuid_entry2 *best;
4412
4413 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4414 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4415 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4416 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4417 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4418 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4419 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4420 if (best) {
5fdbf976
MT		 4421 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4422 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4423 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4424 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4425 }
8776e519 4426 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4427 trace_kvm_cpuid(function,
4428 kvm_register_read(vcpu, VCPU_REGS_RAX),
4429 kvm_register_read(vcpu, VCPU_REGS_RBX),
4430 kvm_register_read(vcpu, VCPU_REGS_RCX),
4431 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4432}
4433EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4434
b6c7a5dc
HB		 4435/*
4436 * Check if userspace requested an interrupt window, and that the
4437 * interrupt window is open.
4438 *
4439 * No need to exit to userspace if we already have an interrupt queued.
4440 */
851ba692 4441static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4442{
8061823a 4443 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4444 vcpu->run->request_interrupt_window &&
5df56646 4445 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4446}
4447
851ba692 4448static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4449{
851ba692
AK		 4450 struct kvm_run *kvm_run = vcpu->run;
4451
91586a3b 4452 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4453 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4454 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4455 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4456 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4457 else
b6c7a5dc 4458 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4459 kvm_arch_interrupt_allowed(vcpu) &&
4460 !kvm_cpu_has_interrupt(vcpu) &&
4461 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4462}
4463
b93463aa
AK		 4464static void vapic_enter(struct kvm_vcpu *vcpu)
4465{
4466 struct kvm_lapic *apic = vcpu->arch.apic;
4467 struct page *page;
4468
4469 if (!apic || !apic->vapic_addr)
4470 return;
4471
4472 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4473
4474 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4475}
4476
4477static void vapic_exit(struct kvm_vcpu *vcpu)
4478{
4479 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4480 int idx;
b93463aa
AK		 4481
4482 if (!apic || !apic->vapic_addr)
4483 return;
4484
f656ce01 4485 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4486 kvm_release_page_dirty(apic->vapic_page);
4487 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4488 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4489}
4490
95ba8273
GN		 4491static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4492{
4493 int max_irr, tpr;
4494
4495 if (!kvm_x86_ops->update_cr8_intercept)
4496 return;
4497
88c808fd
AK		 4498 if (!vcpu->arch.apic)
4499 return;
4500
8db3baa2
GN		 4501 if (!vcpu->arch.apic->vapic_addr)
4502 max_irr = kvm_lapic_find_highest_irr(vcpu);
4503 else
4504 max_irr = -1;
95ba8273
GN		 4505
4506 if (max_irr != -1)
4507 max_irr >>= 4;
4508
4509 tpr = kvm_lapic_get_cr8(vcpu);
4510
4511 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4512}
4513
851ba692 4514static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4515{
4516 /* try to reinject previous events if any */
b59bb7bd 4517 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4518 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4519 vcpu->arch.exception.has_error_code,
4520 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4521 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4522 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4523 vcpu->arch.exception.error_code,
4524 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4525 return;
4526 }
4527
95ba8273
GN		 4528 if (vcpu->arch.nmi_injected) {
4529 kvm_x86_ops->set_nmi(vcpu);
4530 return;
4531 }
4532
4533 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4534 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4535 return;
4536 }
4537
4538 /* try to inject new event if pending */
4539 if (vcpu->arch.nmi_pending) {
4540 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4541 vcpu->arch.nmi_pending = false;
4542 vcpu->arch.nmi_injected = true;
4543 kvm_x86_ops->set_nmi(vcpu);
4544 }
4545 } else if (kvm_cpu_has_interrupt(vcpu)) {
4546 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4547 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4548 false);
4549 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4550 }
4551 }
4552}
4553
851ba692 4554static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4555{
4556 int r;
6a8b1d13 4557 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4558 vcpu->run->request_interrupt_window;
b6c7a5dc 4559
2e53d63a
MT		 4560 if (vcpu->requests)
4561 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4562 kvm_mmu_unload(vcpu);
4563
b6c7a5dc
HB		 4564 r = kvm_mmu_reload(vcpu);
4565 if (unlikely(r))
4566 goto out;
4567
2f52d58c
AK		 4568 if (vcpu->requests) {
4569 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4570 __kvm_migrate_timers(vcpu);
c8076604
GH		 4571 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4572 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4573 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4574 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4575 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4576 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4577 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4578 &vcpu->requests)) {
851ba692 4579 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4580 r = 0;
4581 goto out;
4582 }
71c4dfaf 4583 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4584 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4585 r = 0;
4586 goto out;
4587 }
02daab21
AK		 4588 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4589 vcpu->fpu_active = 0;
4590 kvm_x86_ops->fpu_deactivate(vcpu);
4591 }
2f52d58c 4592 }
b93463aa 4593
b6c7a5dc
HB		 4594 preempt_disable();
4595
4596 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4597 if (vcpu->fpu_active)
4598 kvm_load_guest_fpu(vcpu);
b6c7a5dc 4599
d94e1dc9
AK		 4600 atomic_set(&vcpu->guest_mode, 1);
4601 smp_wmb();
b6c7a5dc 4602
d94e1dc9 4603 local_irq_disable();
32f88400 4604
d94e1dc9
AK		 4605 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4606 || need_resched() || signal_pending(current)) {
4607 atomic_set(&vcpu->guest_mode, 0);
4608 smp_wmb();
6c142801
AK		 4609 local_irq_enable();
4610 preempt_enable();
4611 r = 1;
4612 goto out;
4613 }
4614
851ba692 4615 inject_pending_event(vcpu);
b6c7a5dc 4616
6a8b1d13
GN		 4617 /* enable NMI/IRQ window open exits if needed */
4618 if (vcpu->arch.nmi_pending)
4619 kvm_x86_ops->enable_nmi_window(vcpu);
4620 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4621 kvm_x86_ops->enable_irq_window(vcpu);
4622
95ba8273 4623 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4624 update_cr8_intercept(vcpu);
4625 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4626 }
b93463aa 4627
f656ce01 4628 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4629
b6c7a5dc
HB		 4630 kvm_guest_enter();
4631
42dbaa5a 4632 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4633 set_debugreg(0, 7);
4634 set_debugreg(vcpu->arch.eff_db[0], 0);
4635 set_debugreg(vcpu->arch.eff_db[1], 1);
4636 set_debugreg(vcpu->arch.eff_db[2], 2);
4637 set_debugreg(vcpu->arch.eff_db[3], 3);
4638 }
b6c7a5dc 4639
229456fc 4640 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4641 kvm_x86_ops->run(vcpu);
b6c7a5dc 4642
24f1e32c
FW		 4643 /*
4644 * If the guest has used debug registers, at least dr7
4645 * will be disabled while returning to the host.
4646 * If we don't have active breakpoints in the host, we don't
4647 * care about the messed up debug address registers. But if
4648 * we have some of them active, restore the old state.
4649 */
59d8eb53 4650 if (hw_breakpoint_active())
24f1e32c 4651 hw_breakpoint_restore();
42dbaa5a 4652
d94e1dc9
AK		 4653 atomic_set(&vcpu->guest_mode, 0);
4654 smp_wmb();
b6c7a5dc
HB		 4655 local_irq_enable();
4656
4657 ++vcpu->stat.exits;
4658
4659 /*
4660 * We must have an instruction between local_irq_enable() and
4661 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4662 * the interrupt shadow. The stat.exits increment will do nicely.
4663 * But we need to prevent reordering, hence this barrier():
4664 */
4665 barrier();
4666
4667 kvm_guest_exit();
4668
4669 preempt_enable();
4670
f656ce01 4671 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4672
b6c7a5dc
HB		 4673 /*
4674 * Profile KVM exit RIPs:
4675 */
4676 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4677 unsigned long rip = kvm_rip_read(vcpu);
4678 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4679 }
4680
298101da 4681
b93463aa
AK		 4682 kvm_lapic_sync_from_vapic(vcpu);
4683
851ba692 4684 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4685out:
4686 return r;
4687}
b6c7a5dc 4688
09cec754 4689
851ba692 4690static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4691{
4692 int r;
f656ce01 4693 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4694
4695 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4696 pr_debug("vcpu %d received sipi with vector # %x\n",
4697 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4698 kvm_lapic_reset(vcpu);
5f179287 4699 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4700 if (r)
4701 return r;
4702 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4703 }
4704
f656ce01 4705 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4706 vapic_enter(vcpu);
4707
4708 r = 1;
4709 while (r > 0) {
af2152f5 4710 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4711 r = vcpu_enter_guest(vcpu);
d7690175 4712 else {
f656ce01 4713 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4714 kvm_vcpu_block(vcpu);
f656ce01 4715 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4716 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4717 {
4718 switch(vcpu->arch.mp_state) {
4719 case KVM_MP_STATE_HALTED:
d7690175 4720 vcpu->arch.mp_state =
09cec754
GN		 4721 KVM_MP_STATE_RUNNABLE;
4722 case KVM_MP_STATE_RUNNABLE:
4723 break;
4724 case KVM_MP_STATE_SIPI_RECEIVED:
4725 default:
4726 r = -EINTR;
4727 break;
4728 }
4729 }
d7690175
MT		 4730 }
4731
09cec754
GN		 4732 if (r <= 0)
4733 break;
4734
4735 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4736 if (kvm_cpu_has_pending_timer(vcpu))
4737 kvm_inject_pending_timer_irqs(vcpu);
4738
851ba692 4739 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4740 r = -EINTR;
851ba692 4741 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4742 ++vcpu->stat.request_irq_exits;
4743 }
4744 if (signal_pending(current)) {
4745 r = -EINTR;
851ba692 4746 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4747 ++vcpu->stat.signal_exits;
4748 }
4749 if (need_resched()) {
f656ce01 4750 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4751 kvm_resched(vcpu);
f656ce01 4752 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4753 }
b6c7a5dc
HB		 4754 }
4755
f656ce01 4756 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4757
b93463aa
AK		 4758 vapic_exit(vcpu);
4759
b6c7a5dc
HB		 4760 return r;
4761}
4762
4763int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4764{
4765 int r;
4766 sigset_t sigsaved;
4767
4768 vcpu_load(vcpu);
4769
ac9f6dc0
AK		 4770 if (vcpu->sigset_active)
4771 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4772
a4535290 4773 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4774 kvm_vcpu_block(vcpu);
d7690175 4775 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4776 r = -EAGAIN;
4777 goto out;
b6c7a5dc
HB		 4778 }
4779
b6c7a5dc
HB		 4780 /* re-sync apic's tpr */
4781 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4782 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4783
92bf9748
GN		 4784 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4785 vcpu->arch.emulate_ctxt.restart) {
4786 if (vcpu->mmio_needed) {
4787 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4788 vcpu->mmio_read_completed = 1;
4789 vcpu->mmio_needed = 0;
b6c7a5dc 4790 }
f656ce01 4791 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4792 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4793 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4794 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4795 r = 0;
4796 goto out;
4797 }
4798 }
5fdbf976
MT		 4799 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4800 kvm_register_write(vcpu, VCPU_REGS_RAX,
4801 kvm_run->hypercall.ret);
b6c7a5dc 4802
851ba692 4803 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4804
4805out:
f1d86e46 4806 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4807 if (vcpu->sigset_active)
4808 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4809
4810 vcpu_put(vcpu);
4811 return r;
4812}
4813
4814int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4815{
4816 vcpu_load(vcpu);
4817
5fdbf976
MT		 4818 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4819 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4820 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4821 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4822 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4823 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4824 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4825 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4826#ifdef CONFIG_X86_64
5fdbf976
MT		 4827 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4828 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4829 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4830 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4831 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4832 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4833 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4834 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4835#endif
4836
5fdbf976 4837 regs->rip = kvm_rip_read(vcpu);
91586a3b 4838 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4839
4840 vcpu_put(vcpu);
4841
4842 return 0;
4843}
4844
4845int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4846{
4847 vcpu_load(vcpu);
4848
5fdbf976
MT		 4849 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4850 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4851 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4852 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4853 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4854 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4855 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4856 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4857#ifdef CONFIG_X86_64
5fdbf976
MT		 4858 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4859 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4860 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4861 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4862 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4863 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4864 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4865 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4866#endif
4867
5fdbf976 4868 kvm_rip_write(vcpu, regs->rip);
91586a3b 4869 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4870
b4f14abd
JK		 4871 vcpu->arch.exception.pending = false;
4872
b6c7a5dc
HB		 4873 vcpu_put(vcpu);
4874
4875 return 0;
4876}
4877
b6c7a5dc
HB		 4878void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4879{
4880 struct kvm_segment cs;
4881
3e6e0aab 4882 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4883 *db = cs.db;
4884 *l = cs.l;
4885}
4886EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4887
4888int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4889 struct kvm_sregs *sregs)
4890{
89a27f4d 4891 struct desc_ptr dt;
b6c7a5dc
HB		 4892
4893 vcpu_load(vcpu);
4894
3e6e0aab
GT		 4895 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4896 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4897 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4898 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4899 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4900 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4901
3e6e0aab
GT		 4902 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4903 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4904
4905 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4906 sregs->idt.limit = dt.size;
4907 sregs->idt.base = dt.address;
b6c7a5dc 4908 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4909 sregs->gdt.limit = dt.size;
4910 sregs->gdt.base = dt.address;
b6c7a5dc 4911
4d4ec087 4912 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4913 sregs->cr2 = vcpu->arch.cr2;
4914 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4915 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4916 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4917 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4918 sregs->apic_base = kvm_get_apic_base(vcpu);
4919
923c61bb 4920 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4921
36752c9b 4922 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4923 set_bit(vcpu->arch.interrupt.nr,
4924 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4925
b6c7a5dc
HB		 4926 vcpu_put(vcpu);
4927
4928 return 0;
4929}
4930
62d9f0db
MT		 4931int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4932 struct kvm_mp_state *mp_state)
4933{
4934 vcpu_load(vcpu);
4935 mp_state->mp_state = vcpu->arch.mp_state;
4936 vcpu_put(vcpu);
4937 return 0;
4938}
4939
4940int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4941 struct kvm_mp_state *mp_state)
4942{
4943 vcpu_load(vcpu);
4944 vcpu->arch.mp_state = mp_state->mp_state;
4945 vcpu_put(vcpu);
4946 return 0;
4947}
4948
e269fb21
JK		 4949int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4950 bool has_error_code, u32 error_code)
b6c7a5dc 4951{
4d2179e1 4952 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 4953 int cs_db, cs_l, ret;
4954 cache_all_regs(vcpu);
37817f29 4955
ceffb459 4956 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4957
ceffb459
GN		 4958 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4959 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4960 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4961 vcpu->arch.emulate_ctxt.mode =
4962 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4963 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4964 ? X86EMUL_MODE_VM86 : cs_l
4965 ? X86EMUL_MODE_PROT64 : cs_db
4966 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 4967 memset(c, 0, sizeof(struct decode_cache));
4968 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 4969
ceffb459 4970 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4971 tss_selector, reason, has_error_code,
4972 error_code);
c697518a 4973
c697518a 4974 if (ret)
19d04437 4975 return EMULATE_FAIL;
37817f29 4976
4d2179e1 4977 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4978 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 4979 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4980 return EMULATE_DONE;
37817f29
IE		 4981}
4982EXPORT_SYMBOL_GPL(kvm_task_switch);
4983
b6c7a5dc
HB		 4984int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4985 struct kvm_sregs *sregs)
4986{
4987 int mmu_reset_needed = 0;
923c61bb 4988 int pending_vec, max_bits;
89a27f4d 4989 struct desc_ptr dt;
b6c7a5dc
HB		 4990
4991 vcpu_load(vcpu);
4992
89a27f4d
GN		 4993 dt.size = sregs->idt.limit;
4994 dt.address = sregs->idt.base;
b6c7a5dc 4995 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4996 dt.size = sregs->gdt.limit;
4997 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4998 kvm_x86_ops->set_gdt(vcpu, &dt);
4999
ad312c7c
ZX		 5000 vcpu->arch.cr2 = sregs->cr2;
5001 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5002 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5003
2d3ad1f4 5004 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5005
f6801dff 5006 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5007 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5008 kvm_set_apic_base(vcpu, sregs->apic_base);
5009
4d4ec087 5010 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5011 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5012 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5013
fc78f519 5014 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5015 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5016 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5017 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5018 mmu_reset_needed = 1;
5019 }
b6c7a5dc
HB		 5020
5021 if (mmu_reset_needed)
5022 kvm_mmu_reset_context(vcpu);
5023
923c61bb
GN		 5024 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5025 pending_vec = find_first_bit(
5026 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5027 if (pending_vec < max_bits) {
66fd3f7f 5028 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5029 pr_debug("Set back pending irq %d\n", pending_vec);
5030 if (irqchip_in_kernel(vcpu->kvm))
5031 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5032 }
5033
3e6e0aab
GT		 5034 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5035 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5036 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5037 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5038 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5039 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5040
3e6e0aab
GT		 5041 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5042 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5043
5f0269f5
ME		 5044 update_cr8_intercept(vcpu);
5045
9c3e4aab 5046 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5047 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5048 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5049 !is_protmode(vcpu))
9c3e4aab
MT		 5050 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5051
b6c7a5dc
HB		 5052 vcpu_put(vcpu);
5053
5054 return 0;
5055}
5056
d0bfb940
JK		 5057int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5058 struct kvm_guest_debug *dbg)
b6c7a5dc 5059{
355be0b9 5060 unsigned long rflags;
ae675ef0 5061 int i, r;
b6c7a5dc
HB		 5062
5063 vcpu_load(vcpu);
5064
4f926bf2
JK		 5065 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5066 r = -EBUSY;
5067 if (vcpu->arch.exception.pending)
5068 goto unlock_out;
5069 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5070 kvm_queue_exception(vcpu, DB_VECTOR);
5071 else
5072 kvm_queue_exception(vcpu, BP_VECTOR);
5073 }
5074
91586a3b
JK		 5075 /*
5076 * Read rflags as long as potentially injected trace flags are still
5077 * filtered out.
5078 */
5079 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5080
5081 vcpu->guest_debug = dbg->control;
5082 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5083 vcpu->guest_debug = 0;
5084
5085 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5086 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5087 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5088 vcpu->arch.switch_db_regs =
5089 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5090 } else {
5091 for (i = 0; i < KVM_NR_DB_REGS; i++)
5092 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5093 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5094 }
5095
f92653ee
JK		 5096 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5097 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5098 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5099
91586a3b
JK		 5100 /*
5101 * Trigger an rflags update that will inject or remove the trace
5102 * flags.
5103 */
5104 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5105
355be0b9 5106 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5107
4f926bf2 5108 r = 0;
d0bfb940 5109
4f926bf2 5110unlock_out:
b6c7a5dc
HB		 5111 vcpu_put(vcpu);
5112
5113 return r;
5114}
5115
d0752060
HB		 5116/*
5117 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5118 * we have asm/x86/processor.h
5119 */
5120struct fxsave {
5121 u16 cwd;
5122 u16 swd;
5123 u16 twd;
5124 u16 fop;
5125 u64 rip;
5126 u64 rdp;
5127 u32 mxcsr;
5128 u32 mxcsr_mask;
5129 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5130#ifdef CONFIG_X86_64
5131 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5132#else
5133 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5134#endif
5135};
5136
8b006791
ZX		 5137/*
5138 * Translate a guest virtual address to a guest physical address.
5139 */
5140int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5141 struct kvm_translation *tr)
5142{
5143 unsigned long vaddr = tr->linear_address;
5144 gpa_t gpa;
f656ce01 5145 int idx;
8b006791
ZX		 5146
5147 vcpu_load(vcpu);
f656ce01 5148 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5149 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5150 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5151 tr->physical_address = gpa;
5152 tr->valid = gpa != UNMAPPED_GVA;
5153 tr->writeable = 1;
5154 tr->usermode = 0;
8b006791
ZX		 5155 vcpu_put(vcpu);
5156
5157 return 0;
5158}
5159
d0752060
HB		 5160int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5161{
ad312c7c 5162 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5163
5164 vcpu_load(vcpu);
5165
5166 memcpy(fpu->fpr, fxsave->st_space, 128);
5167 fpu->fcw = fxsave->cwd;
5168 fpu->fsw = fxsave->swd;
5169 fpu->ftwx = fxsave->twd;
5170 fpu->last_opcode = fxsave->fop;
5171 fpu->last_ip = fxsave->rip;
5172 fpu->last_dp = fxsave->rdp;
5173 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5174
5175 vcpu_put(vcpu);
5176
5177 return 0;
5178}
5179
5180int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5181{
ad312c7c 5182 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5183
5184 vcpu_load(vcpu);
5185
5186 memcpy(fxsave->st_space, fpu->fpr, 128);
5187 fxsave->cwd = fpu->fcw;
5188 fxsave->swd = fpu->fsw;
5189 fxsave->twd = fpu->ftwx;
5190 fxsave->fop = fpu->last_opcode;
5191 fxsave->rip = fpu->last_ip;
5192 fxsave->rdp = fpu->last_dp;
5193 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5194
5195 vcpu_put(vcpu);
5196
5197 return 0;
5198}
5199
5200void fx_init(struct kvm_vcpu *vcpu)
5201{
5202 unsigned after_mxcsr_mask;
5203
bc1a34f1
AA		 5204 /*
5205 * Touch the fpu the first time in non atomic context as if
5206 * this is the first fpu instruction the exception handler
5207 * will fire before the instruction returns and it'll have to
5208 * allocate ram with GFP_KERNEL.
5209 */
5210 if (!used_math())
d6e88aec 5211 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5212
d0752060
HB		 5213 /* Initialize guest FPU by resetting ours and saving into guest's */
5214 preempt_disable();
d6e88aec
AK		 5215 kvm_fx_save(&vcpu->arch.host_fx_image);
5216 kvm_fx_finit();
5217 kvm_fx_save(&vcpu->arch.guest_fx_image);
5218 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5219 preempt_enable();
5220
ad312c7c 5221 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5222 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5223 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5224 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5225 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5226}
5227EXPORT_SYMBOL_GPL(fx_init);
5228
5229void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5230{
2608d7a1 5231 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5232 return;
5233
5234 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5235 kvm_fx_save(&vcpu->arch.host_fx_image);
5236 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5237 trace_kvm_fpu(1);
d0752060 5238}
d0752060
HB		 5239
5240void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5241{
5242 if (!vcpu->guest_fpu_loaded)
5243 return;
5244
5245 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5246 kvm_fx_save(&vcpu->arch.guest_fx_image);
5247 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5248 ++vcpu->stat.fpu_reload;
02daab21 5249 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5250 trace_kvm_fpu(0);
d0752060 5251}
e9b11c17
ZX		 5252
5253void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5254{
7f1ea208
JR		 5255 if (vcpu->arch.time_page) {
5256 kvm_release_page_dirty(vcpu->arch.time_page);
5257 vcpu->arch.time_page = NULL;
5258 }
5259
e9b11c17
ZX		 5260 kvm_x86_ops->vcpu_free(vcpu);
5261}
5262
5263struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5264 unsigned int id)
5265{
26e5215f
AK		 5266 return kvm_x86_ops->vcpu_create(kvm, id);
5267}
e9b11c17 5268
26e5215f
AK		 5269int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5270{
5271 int r;
e9b11c17
ZX		 5272
5273 /* We do fxsave: this must be aligned. */
ad312c7c 5274 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5275
0bed3b56 5276 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5277 vcpu_load(vcpu);
5278 r = kvm_arch_vcpu_reset(vcpu);
5279 if (r == 0)
5280 r = kvm_mmu_setup(vcpu);
5281 vcpu_put(vcpu);
5282 if (r < 0)
5283 goto free_vcpu;
5284
26e5215f 5285 return 0;
e9b11c17
ZX		 5286free_vcpu:
5287 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5288 return r;
e9b11c17
ZX		 5289}
5290
d40ccc62 5291void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5292{
5293 vcpu_load(vcpu);
5294 kvm_mmu_unload(vcpu);
5295 vcpu_put(vcpu);
5296
5297 kvm_x86_ops->vcpu_free(vcpu);
5298}
5299
5300int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5301{
448fa4a9
JK		 5302 vcpu->arch.nmi_pending = false;
5303 vcpu->arch.nmi_injected = false;
5304
42dbaa5a
JK		 5305 vcpu->arch.switch_db_regs = 0;
5306 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5307 vcpu->arch.dr6 = DR6_FIXED_1;
5308 vcpu->arch.dr7 = DR7_FIXED_1;
5309
e9b11c17
ZX		 5310 return kvm_x86_ops->vcpu_reset(vcpu);
5311}
5312
10474ae8 5313int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5314{
0cca7907
ZA		 5315 /*
5316 * Since this may be called from a hotplug notifcation,
5317 * we can't get the CPU frequency directly.
5318 */
5319 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5320 int cpu = raw_smp_processor_id();
5321 per_cpu(cpu_tsc_khz, cpu) = 0;
5322 }
18863bdd
AK		 5323
5324 kvm_shared_msr_cpu_online();
5325
10474ae8 5326 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5327}
5328
5329void kvm_arch_hardware_disable(void *garbage)
5330{
5331 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5332 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5333}
5334
5335int kvm_arch_hardware_setup(void)
5336{
5337 return kvm_x86_ops->hardware_setup();
5338}
5339
5340void kvm_arch_hardware_unsetup(void)
5341{
5342 kvm_x86_ops->hardware_unsetup();
5343}
5344
5345void kvm_arch_check_processor_compat(void *rtn)
5346{
5347 kvm_x86_ops->check_processor_compatibility(rtn);
5348}
5349
5350int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5351{
5352 struct page *page;
5353 struct kvm *kvm;
5354 int r;
5355
5356 BUG_ON(vcpu->kvm == NULL);
5357 kvm = vcpu->kvm;
5358
ad312c7c 5359 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5360 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5361 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5362 else
a4535290 5363 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5364
5365 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5366 if (!page) {
5367 r = -ENOMEM;
5368 goto fail;
5369 }
ad312c7c 5370 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5371
5372 r = kvm_mmu_create(vcpu);
5373 if (r < 0)
5374 goto fail_free_pio_data;
5375
5376 if (irqchip_in_kernel(kvm)) {
5377 r = kvm_create_lapic(vcpu);
5378 if (r < 0)
5379 goto fail_mmu_destroy;
5380 }
5381
890ca9ae
HY		 5382 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5383 GFP_KERNEL);
5384 if (!vcpu->arch.mce_banks) {
5385 r = -ENOMEM;
443c39bc 5386 goto fail_free_lapic;
890ca9ae
HY		 5387 }
5388 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5389
e9b11c17 5390 return 0;
443c39bc
WY		 5391fail_free_lapic:
5392 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5393fail_mmu_destroy:
5394 kvm_mmu_destroy(vcpu);
5395fail_free_pio_data:
ad312c7c 5396 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5397fail:
5398 return r;
5399}
5400
5401void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5402{
f656ce01
MT		 5403 int idx;
5404
36cb93fd 5405 kfree(vcpu->arch.mce_banks);
e9b11c17 5406 kvm_free_lapic(vcpu);
f656ce01 5407 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5408 kvm_mmu_destroy(vcpu);
f656ce01 5409 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5410 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5411}
d19a9cd2
ZX		 5412
5413struct kvm *kvm_arch_create_vm(void)
5414{
5415 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5416
5417 if (!kvm)
5418 return ERR_PTR(-ENOMEM);
5419
fef9cce0
MT		 5420 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5421 if (!kvm->arch.aliases) {
5422 kfree(kvm);
5423 return ERR_PTR(-ENOMEM);
5424 }
5425
f05e70ac 5426 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5427 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5428
5550af4d
SY		 5429 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5430 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5431
53f658b3
MT		 5432 rdtscll(kvm->arch.vm_init_tsc);
5433
d19a9cd2
ZX		 5434 return kvm;
5435}
5436
5437static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5438{
5439 vcpu_load(vcpu);
5440 kvm_mmu_unload(vcpu);
5441 vcpu_put(vcpu);
5442}
5443
5444static void kvm_free_vcpus(struct kvm *kvm)
5445{
5446 unsigned int i;
988a2cae 5447 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5448
5449 /*
5450 * Unpin any mmu pages first.
5451 */
988a2cae
GN		 5452 kvm_for_each_vcpu(i, vcpu, kvm)
5453 kvm_unload_vcpu_mmu(vcpu);
5454 kvm_for_each_vcpu(i, vcpu, kvm)
5455 kvm_arch_vcpu_free(vcpu);
5456
5457 mutex_lock(&kvm->lock);
5458 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5459 kvm->vcpus[i] = NULL;
d19a9cd2 5460
988a2cae
GN		 5461 atomic_set(&kvm->online_vcpus, 0);
5462 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5463}
5464
ad8ba2cd
SY		 5465void kvm_arch_sync_events(struct kvm *kvm)
5466{
ba4cef31 5467 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5468}
5469
d19a9cd2
ZX		 5470void kvm_arch_destroy_vm(struct kvm *kvm)
5471{
6eb55818 5472 kvm_iommu_unmap_guest(kvm);
7837699f 5473 kvm_free_pit(kvm);
d7deeeb0
ZX		 5474 kfree(kvm->arch.vpic);
5475 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5476 kvm_free_vcpus(kvm);
5477 kvm_free_physmem(kvm);
3d45830c
AK		 5478 if (kvm->arch.apic_access_page)
5479 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5480 if (kvm->arch.ept_identity_pagetable)
5481 put_page(kvm->arch.ept_identity_pagetable);
64749204 5482 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5483 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5484 kfree(kvm);
5485}
0de10343 5486
f7784b8e
MT		 5487int kvm_arch_prepare_memory_region(struct kvm *kvm,
5488 struct kvm_memory_slot *memslot,
0de10343 5489 struct kvm_memory_slot old,
f7784b8e 5490 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5491 int user_alloc)
5492{
f7784b8e 5493 int npages = memslot->npages;
0de10343
ZX		 5494
5495 /*To keep backward compatibility with older userspace,
5496 *x86 needs to hanlde !user_alloc case.
5497 */
5498 if (!user_alloc) {
5499 if (npages && !old.rmap) {
604b38ac
AA		 5500 unsigned long userspace_addr;
5501
72dc67a6 5502 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5503 userspace_addr = do_mmap(NULL, 0,
5504 npages * PAGE_SIZE,
5505 PROT_READ | PROT_WRITE,
acee3c04 5506 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5507 0);
72dc67a6 5508 up_write(&current->mm->mmap_sem);
0de10343 5509
604b38ac
AA		 5510 if (IS_ERR((void *)userspace_addr))
5511 return PTR_ERR((void *)userspace_addr);
5512
604b38ac 5513 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5514 }
5515 }
5516
f7784b8e
MT		 5517
5518 return 0;
5519}
5520
5521void kvm_arch_commit_memory_region(struct kvm *kvm,
5522 struct kvm_userspace_memory_region *mem,
5523 struct kvm_memory_slot old,
5524 int user_alloc)
5525{
5526
5527 int npages = mem->memory_size >> PAGE_SHIFT;
5528
5529 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5530 int ret;
5531
5532 down_write(&current->mm->mmap_sem);
5533 ret = do_munmap(current->mm, old.userspace_addr,
5534 old.npages * PAGE_SIZE);
5535 up_write(&current->mm->mmap_sem);
5536 if (ret < 0)
5537 printk(KERN_WARNING
5538 "kvm_vm_ioctl_set_memory_region: "
5539 "failed to munmap memory\n");
5540 }
5541
7c8a83b7 5542 spin_lock(&kvm->mmu_lock);
f05e70ac 5543 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5544 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5545 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5546 }
5547
5548 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5549 spin_unlock(&kvm->mmu_lock);
0de10343 5550}
1d737c8a 5551
34d4cb8f
MT		 5552void kvm_arch_flush_shadow(struct kvm *kvm)
5553{
5554 kvm_mmu_zap_all(kvm);
8986ecc0 5555 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5556}
5557
1d737c8a
ZX		 5558int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5559{
a4535290 5560 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5561 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5562 || vcpu->arch.nmi_pending ||
5563 (kvm_arch_interrupt_allowed(vcpu) &&
5564 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5565}
5736199a 5566
5736199a
ZX		 5567void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5568{
32f88400
MT		 5569 int me;
5570 int cpu = vcpu->cpu;
5736199a
ZX		 5571
5572 if (waitqueue_active(&vcpu->wq)) {
5573 wake_up_interruptible(&vcpu->wq);
5574 ++vcpu->stat.halt_wakeup;
5575 }
32f88400
MT		 5576
5577 me = get_cpu();
5578 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5579 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5580 smp_send_reschedule(cpu);
e9571ed5 5581 put_cpu();
5736199a 5582}
78646121
GN		 5583
5584int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5585{
5586 return kvm_x86_ops->interrupt_allowed(vcpu);
5587}
229456fc 5588
f92653ee
JK		 5589bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5590{
5591 unsigned long current_rip = kvm_rip_read(vcpu) +
5592 get_segment_base(vcpu, VCPU_SREG_CS);
5593
5594 return current_rip == linear_rip;
5595}
5596EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5597
94fe45da
JK		 5598unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5599{
5600 unsigned long rflags;
5601
5602 rflags = kvm_x86_ops->get_rflags(vcpu);
5603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5604 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5605 return rflags;
5606}
5607EXPORT_SYMBOL_GPL(kvm_get_rflags);
5608
5609void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5610{
5611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5612 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5613 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5614 kvm_x86_ops->set_rflags(vcpu, rflags);
5615}
5616EXPORT_SYMBOL_GPL(kvm_set_rflags);
5617
229456fc
MT		 5618EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5619EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5620EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5621EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5622EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5623EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5624EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5625EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5626EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5627EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5628EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5629EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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