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KVM: Add HYPER-V header file
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
aec51dc4
AK		 42#include <trace/events/kvm.h>
43#undef TRACE_INCLUDE_FILE
229456fc
MT		 44#define CREATE_TRACE_POINTS
45#include "trace.h"
043405e1 46
24f1e32c 47#include <asm/debugreg.h>
043405e1 48#include <asm/uaccess.h>
d825ed0a 49#include <asm/msr.h>
a5f61300 50#include <asm/desc.h>
0bed3b56 51#include <asm/mtrr.h>
890ca9ae 52#include <asm/mce.h>
043405e1 53
313a3dc7 54#define MAX_IO_MSRS 256
a03490ed
CO		 55#define CR0_RESERVED_BITS \
56 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
57 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
58 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
59#define CR4_RESERVED_BITS \
60 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
61 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
62 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
63 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
64
65#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 66
67#define KVM_MAX_MCE_BANKS 32
68#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
76#else
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
18863bdd
AK		 93#define KVM_NR_SHARED_MSRS 16
94
95struct kvm_shared_msrs_global {
96 int nr;
2bf78fa7 97 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 98};
99
100struct kvm_shared_msrs {
101 struct user_return_notifier urn;
102 bool registered;
2bf78fa7
SY		 103 struct kvm_shared_msr_values {
104 u64 host;
105 u64 curr;
106 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
110static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
111
417bc304 112struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 113 { "pf_fixed", VCPU_STAT(pf_fixed) },
114 { "pf_guest", VCPU_STAT(pf_guest) },
115 { "tlb_flush", VCPU_STAT(tlb_flush) },
116 { "invlpg", VCPU_STAT(invlpg) },
117 { "exits", VCPU_STAT(exits) },
118 { "io_exits", VCPU_STAT(io_exits) },
119 { "mmio_exits", VCPU_STAT(mmio_exits) },
120 { "signal_exits", VCPU_STAT(signal_exits) },
121 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 122 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 123 { "halt_exits", VCPU_STAT(halt_exits) },
124 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 125 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 126 { "request_irq", VCPU_STAT(request_irq_exits) },
127 { "irq_exits", VCPU_STAT(irq_exits) },
128 { "host_state_reload", VCPU_STAT(host_state_reload) },
129 { "efer_reload", VCPU_STAT(efer_reload) },
130 { "fpu_reload", VCPU_STAT(fpu_reload) },
131 { "insn_emulation", VCPU_STAT(insn_emulation) },
132 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 133 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 134 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 135 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
136 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
137 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
138 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
139 { "mmu_flooded", VM_STAT(mmu_flooded) },
140 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 141 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 142 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 143 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 144 { "largepages", VM_STAT(lpages) },
417bc304
HB		 145 { NULL }
146};
147
18863bdd
AK		 148static void kvm_on_user_return(struct user_return_notifier *urn)
149{
150 unsigned slot;
18863bdd
AK		 151 struct kvm_shared_msrs *locals
152 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 153 struct kvm_shared_msr_values *values;
18863bdd
AK		 154
155 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 156 values = &locals->values[slot];
157 if (values->host != values->curr) {
158 wrmsrl(shared_msrs_global.msrs[slot], values->host);
159 values->curr = values->host;
18863bdd
AK		 160 }
161 }
162 locals->registered = false;
163 user_return_notifier_unregister(urn);
164}
165
2bf78fa7 166static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 167{
2bf78fa7 168 struct kvm_shared_msrs *smsr;
18863bdd
AK		 169 u64 value;
170
2bf78fa7
SY		 171 smsr = &__get_cpu_var(shared_msrs);
172 /* only read, and nobody should modify it at this time,
173 * so don't need lock */
174 if (slot >= shared_msrs_global.nr) {
175 printk(KERN_ERR "kvm: invalid MSR slot!");
176 return;
177 }
178 rdmsrl_safe(msr, &value);
179 smsr->values[slot].host = value;
180 smsr->values[slot].curr = value;
181}
182
183void kvm_define_shared_msr(unsigned slot, u32 msr)
184{
18863bdd
AK		 185 if (slot >= shared_msrs_global.nr)
186 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 187 shared_msrs_global.msrs[slot] = msr;
188 /* we need ensured the shared_msr_global have been updated */
189 smp_wmb();
18863bdd
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
192
193static void kvm_shared_msr_cpu_online(void)
194{
195 unsigned i;
18863bdd
AK		 196
197 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 198 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 199}
200
d5696725 201void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 202{
203 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
204
2bf78fa7 205 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 206 return;
2bf78fa7
SY		 207 smsr->values[slot].curr = value;
208 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 209 if (!smsr->registered) {
210 smsr->urn.on_user_return = kvm_on_user_return;
211 user_return_notifier_register(&smsr->urn);
212 smsr->registered = true;
213 }
214}
215EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
216
3548bab5
AK		 217static void drop_user_return_notifiers(void *ignore)
218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
221 if (smsr->registered)
222 kvm_on_user_return(&smsr->urn);
223}
224
5fb76f9b
CO		 225unsigned long segment_base(u16 selector)
226{
227 struct descriptor_table gdt;
a5f61300 228 struct desc_struct *d;
5fb76f9b
CO		 229 unsigned long table_base;
230 unsigned long v;
231
232 if (selector == 0)
233 return 0;
234
b792c344 235 kvm_get_gdt(&gdt);
5fb76f9b
CO		 236 table_base = gdt.base;
237
238 if (selector & 4) { /* from ldt */
b792c344 239 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 240
5fb76f9b
CO		 241 table_base = segment_base(ldt_selector);
242 }
a5f61300 243 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 244 v = get_desc_base(d);
5fb76f9b 245#ifdef CONFIG_X86_64
a5f61300
AK		 246 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
247 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 248#endif
249 return v;
250}
251EXPORT_SYMBOL_GPL(segment_base);
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
255 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 256 return vcpu->arch.apic_base;
6866b83e 257 else
ad312c7c 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
262void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
263{
264 /* TODO: reserve bits check */
265 if (irqchip_in_kernel(vcpu->kvm))
266 kvm_lapic_set_base(vcpu, data);
267 else
ad312c7c 268 vcpu->arch.apic_base = data;
6866b83e
CO		 269}
270EXPORT_SYMBOL_GPL(kvm_set_apic_base);
271
3fd28fce
ED		 272#define EXCPT_BENIGN 0
273#define EXCPT_CONTRIBUTORY 1
274#define EXCPT_PF 2
275
276static int exception_class(int vector)
277{
278 switch (vector) {
279 case PF_VECTOR:
280 return EXCPT_PF;
281 case DE_VECTOR:
282 case TS_VECTOR:
283 case NP_VECTOR:
284 case SS_VECTOR:
285 case GP_VECTOR:
286 return EXCPT_CONTRIBUTORY;
287 default:
288 break;
289 }
290 return EXCPT_BENIGN;
291}
292
293static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
294 unsigned nr, bool has_error, u32 error_code)
295{
296 u32 prev_nr;
297 int class1, class2;
298
299 if (!vcpu->arch.exception.pending) {
300 queue:
301 vcpu->arch.exception.pending = true;
302 vcpu->arch.exception.has_error_code = has_error;
303 vcpu->arch.exception.nr = nr;
304 vcpu->arch.exception.error_code = error_code;
305 return;
306 }
307
308 /* to check exception */
309 prev_nr = vcpu->arch.exception.nr;
310 if (prev_nr == DF_VECTOR) {
311 /* triple fault -> shutdown */
312 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
313 return;
314 }
315 class1 = exception_class(prev_nr);
316 class2 = exception_class(nr);
317 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
318 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
319 /* generate double fault per SDM Table 5-5 */
320 vcpu->arch.exception.pending = true;
321 vcpu->arch.exception.has_error_code = true;
322 vcpu->arch.exception.nr = DF_VECTOR;
323 vcpu->arch.exception.error_code = 0;
324 } else
325 /* replace previous exception with a new one in a hope
326 that instruction re-execution will regenerate lost
327 exception */
328 goto queue;
329}
330
298101da
AK		 331void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
3fd28fce 333 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 334}
335EXPORT_SYMBOL_GPL(kvm_queue_exception);
336
c3c91fee
AK		 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
338 u32 error_code)
339{
340 ++vcpu->stat.pf_guest;
ad312c7c 341 vcpu->arch.cr2 = addr;
c3c91fee
AK		 342 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
343}
344
3419ffc8
SY		 345void kvm_inject_nmi(struct kvm_vcpu *vcpu)
346{
347 vcpu->arch.nmi_pending = 1;
348}
349EXPORT_SYMBOL_GPL(kvm_inject_nmi);
350
298101da
AK		 351void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
352{
3fd28fce 353 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 354}
355EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
356
0a79b009
AK		 357/*
358 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
359 * a #GP and return false.
360 */
361bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 362{
0a79b009
AK		 363 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
364 return true;
365 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
366 return false;
298101da 367}
0a79b009 368EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 369
a03490ed
CO		 370/*
371 * Load the pae pdptrs. Return true is they are all valid.
372 */
373int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
374{
375 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
376 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
377 int i;
378 int ret;
ad312c7c 379 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 380
a03490ed
CO		 381 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
382 offset * sizeof(u64), sizeof(pdpte));
383 if (ret < 0) {
384 ret = 0;
385 goto out;
386 }
387 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 388 if (is_present_gpte(pdpte[i]) &&
20c466b5 389 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 390 ret = 0;
391 goto out;
392 }
393 }
394 ret = 1;
395
ad312c7c 396 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 397 __set_bit(VCPU_EXREG_PDPTR,
398 (unsigned long *)&vcpu->arch.regs_avail);
399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 401out:
a03490ed
CO		 402
403 return ret;
404}
cc4b6871 405EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 406
d835dfec
AK		 407static bool pdptrs_changed(struct kvm_vcpu *vcpu)
408{
ad312c7c 409 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 410 bool changed = true;
411 int r;
412
413 if (is_long_mode(vcpu) || !is_pae(vcpu))
414 return false;
415
6de4f3ad
AK		 416 if (!test_bit(VCPU_EXREG_PDPTR,
417 (unsigned long *)&vcpu->arch.regs_avail))
418 return true;
419
ad312c7c 420 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 421 if (r < 0)
422 goto out;
ad312c7c 423 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 424out:
d835dfec
AK		 425
426 return changed;
427}
428
2d3ad1f4 429void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 430{
f9a48e6a
AK		 431 cr0 |= X86_CR0_ET;
432
a03490ed
CO		 433 if (cr0 & CR0_RESERVED_BITS) {
434 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
4d4ec087 435 cr0, kvm_read_cr0(vcpu));
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
439
440 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
441 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 442 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 443 return;
444 }
445
446 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
447 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
448 "and a clear PE flag\n");
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
ad312c7c 455 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
459 printk(KERN_DEBUG "set_cr0: #GP, start paging "
460 "in long mode while PAE is disabled\n");
c1a5d4f9 461 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 462 return;
463 }
464 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
465 if (cs_l) {
466 printk(KERN_DEBUG "set_cr0: #GP, start paging "
467 "in long mode while CS.L == 1\n");
c1a5d4f9 468 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 469 return;
470
471 }
472 } else
473#endif
ad312c7c 474 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 475 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
476 "reserved bits\n");
c1a5d4f9 477 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 478 return;
479 }
480
481 }
482
483 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 484 vcpu->arch.cr0 = cr0;
a03490ed 485
a03490ed 486 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 487 return;
488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 490
2d3ad1f4 491void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 492{
4d4ec087 493 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 494}
2d3ad1f4 495EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 496
2d3ad1f4 497void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 498{
fc78f519 499 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 500 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
501
a03490ed
CO		 502 if (cr4 & CR4_RESERVED_BITS) {
503 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 504 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 505 return;
506 }
507
508 if (is_long_mode(vcpu)) {
509 if (!(cr4 & X86_CR4_PAE)) {
510 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
511 "in long mode\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 513 return;
514 }
a2edf57f
AK		 515 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
516 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 517 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 518 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 519 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 520 return;
521 }
522
523 if (cr4 & X86_CR4_VMXE) {
524 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 529 vcpu->arch.cr4 = cr4;
5a41accd 530 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 531 kvm_mmu_reset_context(vcpu);
a03490ed 532}
2d3ad1f4 533EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 534
2d3ad1f4 535void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 536{
ad312c7c 537 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 538 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 539 kvm_mmu_flush_tlb(vcpu);
540 return;
541 }
542
a03490ed
CO		 543 if (is_long_mode(vcpu)) {
544 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
545 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 546 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 547 return;
548 }
549 } else {
550 if (is_pae(vcpu)) {
551 if (cr3 & CR3_PAE_RESERVED_BITS) {
552 printk(KERN_DEBUG
553 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 554 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 555 return;
556 }
557 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
558 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
559 "reserved bits\n");
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 }
564 /*
565 * We don't check reserved bits in nonpae mode, because
566 * this isn't enforced, and VMware depends on this.
567 */
568 }
569
a03490ed
CO		 570 /*
571 * Does the new cr3 value map to physical memory? (Note, we
572 * catch an invalid cr3 even in real-mode, because it would
573 * cause trouble later on when we turn on paging anyway.)
574 *
575 * A real CPU would silently accept an invalid cr3 and would
576 * attempt to use it - with largely undefined (and often hard
577 * to debug) behavior on the guest side.
578 */
579 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 580 kvm_inject_gp(vcpu, 0);
a03490ed 581 else {
ad312c7c
ZX		 582 vcpu->arch.cr3 = cr3;
583 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 584 }
a03490ed 585}
2d3ad1f4 586EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 587
2d3ad1f4 588void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 589{
590 if (cr8 & CR8_RESERVED_BITS) {
591 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 592 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 593 return;
594 }
595 if (irqchip_in_kernel(vcpu->kvm))
596 kvm_lapic_set_tpr(vcpu, cr8);
597 else
ad312c7c 598 vcpu->arch.cr8 = cr8;
a03490ed 599}
2d3ad1f4 600EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 601
2d3ad1f4 602unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 603{
604 if (irqchip_in_kernel(vcpu->kvm))
605 return kvm_lapic_get_cr8(vcpu);
606 else
ad312c7c 607 return vcpu->arch.cr8;
a03490ed 608}
2d3ad1f4 609EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 610
d8017474
AG		 611static inline u32 bit(int bitno)
612{
613 return 1 << (bitno & 31);
614}
615
043405e1
CO		 616/*
617 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
618 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
619 *
620 * This list is modified at module load time to reflect the
e3267cbb
GC		 621 * capabilities of the host cpu. This capabilities test skips MSRs that are
622 * kvm-specific. Those are put in the beginning of the list.
043405e1 623 */
e3267cbb
GC		 624
625#define KVM_SAVE_MSRS_BEGIN 2
043405e1 626static u32 msrs_to_save[] = {
e3267cbb 627 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 628 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
629 MSR_K6_STAR,
630#ifdef CONFIG_X86_64
631 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
632#endif
e3267cbb 633 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 634};
635
636static unsigned num_msrs_to_save;
637
638static u32 emulated_msrs[] = {
639 MSR_IA32_MISC_ENABLE,
640};
641
15c4a640
CO		 642static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
643{
f2b4b7dd 644 if (efer & efer_reserved_bits) {
15c4a640
CO		 645 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
646 efer);
c1a5d4f9 647 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 648 return;
649 }
650
651 if (is_paging(vcpu)
ad312c7c 652 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 653 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 654 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 655 return;
656 }
657
1b2fd70c
AG		 658 if (efer & EFER_FFXSR) {
659 struct kvm_cpuid_entry2 *feat;
660
661 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
662 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
663 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
664 kvm_inject_gp(vcpu, 0);
665 return;
666 }
667 }
668
d8017474
AG		 669 if (efer & EFER_SVME) {
670 struct kvm_cpuid_entry2 *feat;
671
672 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
673 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
674 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
675 kvm_inject_gp(vcpu, 0);
676 return;
677 }
678 }
679
15c4a640
CO		 680 kvm_x86_ops->set_efer(vcpu, efer);
681
682 efer &= ~EFER_LMA;
ad312c7c 683 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 684
ad312c7c 685 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 686
687 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
688 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 689}
690
f2b4b7dd
JR		 691void kvm_enable_efer_bits(u64 mask)
692{
693 efer_reserved_bits &= ~mask;
694}
695EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
696
697
15c4a640
CO		 698/*
699 * Writes msr value into into the appropriate "register".
700 * Returns 0 on success, non-0 otherwise.
701 * Assumes vcpu_load() was already called.
702 */
703int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
704{
705 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
706}
707
313a3dc7
CO		 708/*
709 * Adapt set_msr() to msr_io()'s calling convention
710 */
711static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
712{
713 return kvm_set_msr(vcpu, index, *data);
714}
715
18068523
GOC		 716static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
717{
718 static int version;
50d0a0f9 719 struct pvclock_wall_clock wc;
923de3cf 720 struct timespec boot;
18068523
GOC		 721
722 if (!wall_clock)
723 return;
724
725 version++;
726
18068523
GOC		 727 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
728
50d0a0f9
GH		 729 /*
730 * The guest calculates current wall clock time by adding
731 * system time (updated by kvm_write_guest_time below) to the
732 * wall clock specified here. guest system time equals host
733 * system time for us, thus we must fill in host boot time here.
734 */
923de3cf 735 getboottime(&boot);
50d0a0f9
GH		 736
737 wc.sec = boot.tv_sec;
738 wc.nsec = boot.tv_nsec;
739 wc.version = version;
18068523
GOC		 740
741 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
742
743 version++;
744 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 745}
746
50d0a0f9
GH		 747static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
748{
749 uint32_t quotient, remainder;
750
751 /* Don't try to replace with do_div(), this one calculates
752 * "(dividend << 32) / divisor" */
753 __asm__ ( "divl %4"
754 : "=a" (quotient), "=d" (remainder)
755 : "0" (0), "1" (dividend), "r" (divisor) );
756 return quotient;
757}
758
759static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
760{
761 uint64_t nsecs = 1000000000LL;
762 int32_t shift = 0;
763 uint64_t tps64;
764 uint32_t tps32;
765
766 tps64 = tsc_khz * 1000LL;
767 while (tps64 > nsecs*2) {
768 tps64 >>= 1;
769 shift--;
770 }
771
772 tps32 = (uint32_t)tps64;
773 while (tps32 <= (uint32_t)nsecs) {
774 tps32 <<= 1;
775 shift++;
776 }
777
778 hv_clock->tsc_shift = shift;
779 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
780
781 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 782 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 783 hv_clock->tsc_to_system_mul);
784}
785
c8076604
GH		 786static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
787
18068523
GOC		 788static void kvm_write_guest_time(struct kvm_vcpu *v)
789{
790 struct timespec ts;
791 unsigned long flags;
792 struct kvm_vcpu_arch *vcpu = &v->arch;
793 void *shared_kaddr;
463656c0 794 unsigned long this_tsc_khz;
18068523
GOC		 795
796 if ((!vcpu->time_page))
797 return;
798
463656c0
AK		 799 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
800 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
801 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
802 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 803 }
463656c0 804 put_cpu_var(cpu_tsc_khz);
50d0a0f9 805
18068523
GOC		 806 /* Keep irq disabled to prevent changes to the clock */
807 local_irq_save(flags);
af24a4e4 808 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 809 ktime_get_ts(&ts);
923de3cf 810 monotonic_to_bootbased(&ts);
18068523
GOC		 811 local_irq_restore(flags);
812
813 /* With all the info we got, fill in the values */
814
815 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 816 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
817
18068523
GOC		 818 /*
819 * The interface expects us to write an even number signaling that the
820 * update is finished. Since the guest won't see the intermediate
50d0a0f9 821 * state, we just increase by 2 at the end.
18068523 822 */
50d0a0f9 823 vcpu->hv_clock.version += 2;
18068523
GOC		 824
825 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
826
827 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 828 sizeof(vcpu->hv_clock));
18068523
GOC		 829
830 kunmap_atomic(shared_kaddr, KM_USER0);
831
832 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
833}
834
c8076604
GH		 835static int kvm_request_guest_time_update(struct kvm_vcpu *v)
836{
837 struct kvm_vcpu_arch *vcpu = &v->arch;
838
839 if (!vcpu->time_page)
840 return 0;
841 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
842 return 1;
843}
844
9ba075a6
AK		 845static bool msr_mtrr_valid(unsigned msr)
846{
847 switch (msr) {
848 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
849 case MSR_MTRRfix64K_00000:
850 case MSR_MTRRfix16K_80000:
851 case MSR_MTRRfix16K_A0000:
852 case MSR_MTRRfix4K_C0000:
853 case MSR_MTRRfix4K_C8000:
854 case MSR_MTRRfix4K_D0000:
855 case MSR_MTRRfix4K_D8000:
856 case MSR_MTRRfix4K_E0000:
857 case MSR_MTRRfix4K_E8000:
858 case MSR_MTRRfix4K_F0000:
859 case MSR_MTRRfix4K_F8000:
860 case MSR_MTRRdefType:
861 case MSR_IA32_CR_PAT:
862 return true;
863 case 0x2f8:
864 return true;
865 }
866 return false;
867}
868
d6289b93
MT		 869static bool valid_pat_type(unsigned t)
870{
871 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
872}
873
874static bool valid_mtrr_type(unsigned t)
875{
876 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
877}
878
879static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
880{
881 int i;
882
883 if (!msr_mtrr_valid(msr))
884 return false;
885
886 if (msr == MSR_IA32_CR_PAT) {
887 for (i = 0; i < 8; i++)
888 if (!valid_pat_type((data >> (i * 8)) & 0xff))
889 return false;
890 return true;
891 } else if (msr == MSR_MTRRdefType) {
892 if (data & ~0xcff)
893 return false;
894 return valid_mtrr_type(data & 0xff);
895 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
896 for (i = 0; i < 8 ; i++)
897 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
898 return false;
899 return true;
900 }
901
902 /* variable MTRRs */
903 return valid_mtrr_type(data & 0xff);
904}
905
9ba075a6
AK		 906static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
907{
0bed3b56
SY		 908 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
909
d6289b93 910 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 911 return 1;
912
0bed3b56
SY		 913 if (msr == MSR_MTRRdefType) {
914 vcpu->arch.mtrr_state.def_type = data;
915 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
916 } else if (msr == MSR_MTRRfix64K_00000)
917 p[0] = data;
918 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
919 p[1 + msr - MSR_MTRRfix16K_80000] = data;
920 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
921 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
922 else if (msr == MSR_IA32_CR_PAT)
923 vcpu->arch.pat = data;
924 else { /* Variable MTRRs */
925 int idx, is_mtrr_mask;
926 u64 *pt;
927
928 idx = (msr - 0x200) / 2;
929 is_mtrr_mask = msr - 0x200 - 2 * idx;
930 if (!is_mtrr_mask)
931 pt =
932 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
933 else
934 pt =
935 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
936 *pt = data;
937 }
938
939 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 940 return 0;
941}
15c4a640 942
890ca9ae 943static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 944{
890ca9ae
HY		 945 u64 mcg_cap = vcpu->arch.mcg_cap;
946 unsigned bank_num = mcg_cap & 0xff;
947
15c4a640 948 switch (msr) {
15c4a640 949 case MSR_IA32_MCG_STATUS:
890ca9ae 950 vcpu->arch.mcg_status = data;
15c4a640 951 break;
c7ac679c 952 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 953 if (!(mcg_cap & MCG_CTL_P))
954 return 1;
955 if (data != 0 && data != ~(u64)0)
956 return -1;
957 vcpu->arch.mcg_ctl = data;
958 break;
959 default:
960 if (msr >= MSR_IA32_MC0_CTL &&
961 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
962 u32 offset = msr - MSR_IA32_MC0_CTL;
963 /* only 0 or all 1s can be written to IA32_MCi_CTL */
964 if ((offset & 0x3) == 0 &&
965 data != 0 && data != ~(u64)0)
966 return -1;
967 vcpu->arch.mce_banks[offset] = data;
968 break;
969 }
970 return 1;
971 }
972 return 0;
973}
974
ffde22ac
ES		 975static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
976{
977 struct kvm *kvm = vcpu->kvm;
978 int lm = is_long_mode(vcpu);
979 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
980 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
981 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
982 : kvm->arch.xen_hvm_config.blob_size_32;
983 u32 page_num = data & ~PAGE_MASK;
984 u64 page_addr = data & PAGE_MASK;
985 u8 *page;
986 int r;
987
988 r = -E2BIG;
989 if (page_num >= blob_size)
990 goto out;
991 r = -ENOMEM;
992 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
993 if (!page)
994 goto out;
995 r = -EFAULT;
996 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
997 goto out_free;
998 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
999 goto out_free;
1000 r = 0;
1001out_free:
1002 kfree(page);
1003out:
1004 return r;
1005}
1006
15c4a640
CO		 1007int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1008{
1009 switch (msr) {
15c4a640
CO		 1010 case MSR_EFER:
1011 set_efer(vcpu, data);
1012 break;
8f1589d9
AP		 1013 case MSR_K7_HWCR:
1014 data &= ~(u64)0x40; /* ignore flush filter disable */
1015 if (data != 0) {
1016 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1017 data);
1018 return 1;
1019 }
15c4a640 1020 break;
f7c6d140
AP		 1021 case MSR_FAM10H_MMIO_CONF_BASE:
1022 if (data != 0) {
1023 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1024 "0x%llx\n", data);
1025 return 1;
1026 }
15c4a640 1027 break;
c323c0e5 1028 case MSR_AMD64_NB_CFG:
c7ac679c 1029 break;
b5e2fec0
AG		 1030 case MSR_IA32_DEBUGCTLMSR:
1031 if (!data) {
1032 /* We support the non-activated case already */
1033 break;
1034 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1035 /* Values other than LBR and BTF are vendor-specific,
1036 thus reserved and should throw a #GP */
1037 return 1;
1038 }
1039 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1040 __func__, data);
1041 break;
15c4a640
CO		 1042 case MSR_IA32_UCODE_REV:
1043 case MSR_IA32_UCODE_WRITE:
61a6bd67 1044 case MSR_VM_HSAVE_PA:
6098ca93 1045 case MSR_AMD64_PATCH_LOADER:
15c4a640 1046 break;
9ba075a6
AK		 1047 case 0x200 ... 0x2ff:
1048 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1049 case MSR_IA32_APICBASE:
1050 kvm_set_apic_base(vcpu, data);
1051 break;
0105d1a5
GN		 1052 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1053 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1054 case MSR_IA32_MISC_ENABLE:
ad312c7c 1055 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1056 break;
18068523
GOC		 1057 case MSR_KVM_WALL_CLOCK:
1058 vcpu->kvm->arch.wall_clock = data;
1059 kvm_write_wall_clock(vcpu->kvm, data);
1060 break;
1061 case MSR_KVM_SYSTEM_TIME: {
1062 if (vcpu->arch.time_page) {
1063 kvm_release_page_dirty(vcpu->arch.time_page);
1064 vcpu->arch.time_page = NULL;
1065 }
1066
1067 vcpu->arch.time = data;
1068
1069 /* we verify if the enable bit is set... */
1070 if (!(data & 1))
1071 break;
1072
1073 /* ...but clean it before doing the actual write */
1074 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1075
18068523
GOC		 1076 vcpu->arch.time_page =
1077 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1078
1079 if (is_error_page(vcpu->arch.time_page)) {
1080 kvm_release_page_clean(vcpu->arch.time_page);
1081 vcpu->arch.time_page = NULL;
1082 }
1083
c8076604 1084 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1085 break;
1086 }
890ca9ae
HY		 1087 case MSR_IA32_MCG_CTL:
1088 case MSR_IA32_MCG_STATUS:
1089 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1090 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1091
1092 /* Performance counters are not protected by a CPUID bit,
1093 * so we should check all of them in the generic path for the sake of
1094 * cross vendor migration.
1095 * Writing a zero into the event select MSRs disables them,
1096 * which we perfectly emulate ;-). Any other value should be at least
1097 * reported, some guests depend on them.
1098 */
1099 case MSR_P6_EVNTSEL0:
1100 case MSR_P6_EVNTSEL1:
1101 case MSR_K7_EVNTSEL0:
1102 case MSR_K7_EVNTSEL1:
1103 case MSR_K7_EVNTSEL2:
1104 case MSR_K7_EVNTSEL3:
1105 if (data != 0)
1106 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1107 "0x%x data 0x%llx\n", msr, data);
1108 break;
1109 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1110 * so we ignore writes to make it happy.
1111 */
1112 case MSR_P6_PERFCTR0:
1113 case MSR_P6_PERFCTR1:
1114 case MSR_K7_PERFCTR0:
1115 case MSR_K7_PERFCTR1:
1116 case MSR_K7_PERFCTR2:
1117 case MSR_K7_PERFCTR3:
1118 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1119 "0x%x data 0x%llx\n", msr, data);
1120 break;
15c4a640 1121 default:
ffde22ac
ES		 1122 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1123 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1124 if (!ignore_msrs) {
1125 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1126 msr, data);
1127 return 1;
1128 } else {
1129 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1130 msr, data);
1131 break;
1132 }
15c4a640
CO		 1133 }
1134 return 0;
1135}
1136EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1137
1138
1139/*
1140 * Reads an msr value (of 'msr_index') into 'pdata'.
1141 * Returns 0 on success, non-0 otherwise.
1142 * Assumes vcpu_load() was already called.
1143 */
1144int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1145{
1146 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1147}
1148
9ba075a6
AK		 1149static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1150{
0bed3b56
SY		 1151 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1152
9ba075a6
AK		 1153 if (!msr_mtrr_valid(msr))
1154 return 1;
1155
0bed3b56
SY		 1156 if (msr == MSR_MTRRdefType)
1157 *pdata = vcpu->arch.mtrr_state.def_type +
1158 (vcpu->arch.mtrr_state.enabled << 10);
1159 else if (msr == MSR_MTRRfix64K_00000)
1160 *pdata = p[0];
1161 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1162 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1163 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1164 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1165 else if (msr == MSR_IA32_CR_PAT)
1166 *pdata = vcpu->arch.pat;
1167 else { /* Variable MTRRs */
1168 int idx, is_mtrr_mask;
1169 u64 *pt;
1170
1171 idx = (msr - 0x200) / 2;
1172 is_mtrr_mask = msr - 0x200 - 2 * idx;
1173 if (!is_mtrr_mask)
1174 pt =
1175 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1176 else
1177 pt =
1178 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1179 *pdata = *pt;
1180 }
1181
9ba075a6
AK		 1182 return 0;
1183}
1184
890ca9ae 1185static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1186{
1187 u64 data;
890ca9ae
HY		 1188 u64 mcg_cap = vcpu->arch.mcg_cap;
1189 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1190
1191 switch (msr) {
15c4a640
CO		 1192 case MSR_IA32_P5_MC_ADDR:
1193 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1194 data = 0;
1195 break;
15c4a640 1196 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1197 data = vcpu->arch.mcg_cap;
1198 break;
c7ac679c 1199 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1200 if (!(mcg_cap & MCG_CTL_P))
1201 return 1;
1202 data = vcpu->arch.mcg_ctl;
1203 break;
1204 case MSR_IA32_MCG_STATUS:
1205 data = vcpu->arch.mcg_status;
1206 break;
1207 default:
1208 if (msr >= MSR_IA32_MC0_CTL &&
1209 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1210 u32 offset = msr - MSR_IA32_MC0_CTL;
1211 data = vcpu->arch.mce_banks[offset];
1212 break;
1213 }
1214 return 1;
1215 }
1216 *pdata = data;
1217 return 0;
1218}
1219
1220int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1221{
1222 u64 data;
1223
1224 switch (msr) {
890ca9ae 1225 case MSR_IA32_PLATFORM_ID:
15c4a640 1226 case MSR_IA32_UCODE_REV:
15c4a640 1227 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1228 case MSR_IA32_DEBUGCTLMSR:
1229 case MSR_IA32_LASTBRANCHFROMIP:
1230 case MSR_IA32_LASTBRANCHTOIP:
1231 case MSR_IA32_LASTINTFROMIP:
1232 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1233 case MSR_K8_SYSCFG:
1234 case MSR_K7_HWCR:
61a6bd67 1235 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1236 case MSR_P6_PERFCTR0:
1237 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1238 case MSR_P6_EVNTSEL0:
1239 case MSR_P6_EVNTSEL1:
9e699624 1240 case MSR_K7_EVNTSEL0:
1f3ee616 1241 case MSR_K7_PERFCTR0:
1fdbd48c 1242 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1243 case MSR_AMD64_NB_CFG:
f7c6d140 1244 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1245 data = 0;
1246 break;
9ba075a6
AK		 1247 case MSR_MTRRcap:
1248 data = 0x500 | KVM_NR_VAR_MTRR;
1249 break;
1250 case 0x200 ... 0x2ff:
1251 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1252 case 0xcd: /* fsb frequency */
1253 data = 3;
1254 break;
1255 case MSR_IA32_APICBASE:
1256 data = kvm_get_apic_base(vcpu);
1257 break;
0105d1a5
GN		 1258 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1259 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1260 break;
15c4a640 1261 case MSR_IA32_MISC_ENABLE:
ad312c7c 1262 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1263 break;
847f0ad8
AG		 1264 case MSR_IA32_PERF_STATUS:
1265 /* TSC increment by tick */
1266 data = 1000ULL;
1267 /* CPU multiplier */
1268 data |= (((uint64_t)4ULL) << 40);
1269 break;
15c4a640 1270 case MSR_EFER:
ad312c7c 1271 data = vcpu->arch.shadow_efer;
15c4a640 1272 break;
18068523
GOC		 1273 case MSR_KVM_WALL_CLOCK:
1274 data = vcpu->kvm->arch.wall_clock;
1275 break;
1276 case MSR_KVM_SYSTEM_TIME:
1277 data = vcpu->arch.time;
1278 break;
890ca9ae
HY		 1279 case MSR_IA32_P5_MC_ADDR:
1280 case MSR_IA32_P5_MC_TYPE:
1281 case MSR_IA32_MCG_CAP:
1282 case MSR_IA32_MCG_CTL:
1283 case MSR_IA32_MCG_STATUS:
1284 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1285 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1286 default:
ed85c068
AP		 1287 if (!ignore_msrs) {
1288 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1289 return 1;
1290 } else {
1291 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1292 data = 0;
1293 }
1294 break;
15c4a640
CO		 1295 }
1296 *pdata = data;
1297 return 0;
1298}
1299EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1300
313a3dc7
CO		 1301/*
1302 * Read or write a bunch of msrs. All parameters are kernel addresses.
1303 *
1304 * @return number of msrs set successfully.
1305 */
1306static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1307 struct kvm_msr_entry *entries,
1308 int (*do_msr)(struct kvm_vcpu *vcpu,
1309 unsigned index, u64 *data))
1310{
f656ce01 1311 int i, idx;
313a3dc7
CO		 1312
1313 vcpu_load(vcpu);
1314
f656ce01 1315 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1316 for (i = 0; i < msrs->nmsrs; ++i)
1317 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1318 break;
f656ce01 1319 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1320
1321 vcpu_put(vcpu);
1322
1323 return i;
1324}
1325
1326/*
1327 * Read or write a bunch of msrs. Parameters are user addresses.
1328 *
1329 * @return number of msrs set successfully.
1330 */
1331static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1332 int (*do_msr)(struct kvm_vcpu *vcpu,
1333 unsigned index, u64 *data),
1334 int writeback)
1335{
1336 struct kvm_msrs msrs;
1337 struct kvm_msr_entry *entries;
1338 int r, n;
1339 unsigned size;
1340
1341 r = -EFAULT;
1342 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1343 goto out;
1344
1345 r = -E2BIG;
1346 if (msrs.nmsrs >= MAX_IO_MSRS)
1347 goto out;
1348
1349 r = -ENOMEM;
1350 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1351 entries = vmalloc(size);
1352 if (!entries)
1353 goto out;
1354
1355 r = -EFAULT;
1356 if (copy_from_user(entries, user_msrs->entries, size))
1357 goto out_free;
1358
1359 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1360 if (r < 0)
1361 goto out_free;
1362
1363 r = -EFAULT;
1364 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1365 goto out_free;
1366
1367 r = n;
1368
1369out_free:
1370 vfree(entries);
1371out:
1372 return r;
1373}
1374
018d00d2
ZX		 1375int kvm_dev_ioctl_check_extension(long ext)
1376{
1377 int r;
1378
1379 switch (ext) {
1380 case KVM_CAP_IRQCHIP:
1381 case KVM_CAP_HLT:
1382 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1383 case KVM_CAP_SET_TSS_ADDR:
07716717 1384 case KVM_CAP_EXT_CPUID:
c8076604 1385 case KVM_CAP_CLOCKSOURCE:
7837699f 1386 case KVM_CAP_PIT:
a28e4f5a 1387 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1388 case KVM_CAP_MP_STATE:
ed848624 1389 case KVM_CAP_SYNC_MMU:
52d939a0 1390 case KVM_CAP_REINJECT_CONTROL:
4925663a 1391 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1392 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1393 case KVM_CAP_IRQFD:
d34e6b17 1394 case KVM_CAP_IOEVENTFD:
c5ff41ce 1395 case KVM_CAP_PIT2:
e9f42757 1396 case KVM_CAP_PIT_STATE2:
b927a3ce 1397 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1398 case KVM_CAP_XEN_HVM:
afbcf7ab 1399 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1400 case KVM_CAP_VCPU_EVENTS:
018d00d2
ZX		 1401 r = 1;
1402 break;
542472b5
LV		 1403 case KVM_CAP_COALESCED_MMIO:
1404 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1405 break;
774ead3a
AK		 1406 case KVM_CAP_VAPIC:
1407 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1408 break;
f725230a
AK		 1409 case KVM_CAP_NR_VCPUS:
1410 r = KVM_MAX_VCPUS;
1411 break;
a988b910
AK		 1412 case KVM_CAP_NR_MEMSLOTS:
1413 r = KVM_MEMORY_SLOTS;
1414 break;
a68a6a72
MT		 1415 case KVM_CAP_PV_MMU: /* obsolete */
1416 r = 0;
2f333bcb 1417 break;
62c476c7 1418 case KVM_CAP_IOMMU:
19de40a8 1419 r = iommu_found();
62c476c7 1420 break;
890ca9ae
HY		 1421 case KVM_CAP_MCE:
1422 r = KVM_MAX_MCE_BANKS;
1423 break;
018d00d2
ZX		 1424 default:
1425 r = 0;
1426 break;
1427 }
1428 return r;
1429
1430}
1431
043405e1
CO		 1432long kvm_arch_dev_ioctl(struct file *filp,
1433 unsigned int ioctl, unsigned long arg)
1434{
1435 void __user *argp = (void __user *)arg;
1436 long r;
1437
1438 switch (ioctl) {
1439 case KVM_GET_MSR_INDEX_LIST: {
1440 struct kvm_msr_list __user *user_msr_list = argp;
1441 struct kvm_msr_list msr_list;
1442 unsigned n;
1443
1444 r = -EFAULT;
1445 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1446 goto out;
1447 n = msr_list.nmsrs;
1448 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1449 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1450 goto out;
1451 r = -E2BIG;
e125e7b6 1452 if (n < msr_list.nmsrs)
043405e1
CO		 1453 goto out;
1454 r = -EFAULT;
1455 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1456 num_msrs_to_save * sizeof(u32)))
1457 goto out;
e125e7b6 1458 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1459 &emulated_msrs,
1460 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1461 goto out;
1462 r = 0;
1463 break;
1464 }
674eea0f
AK		 1465 case KVM_GET_SUPPORTED_CPUID: {
1466 struct kvm_cpuid2 __user *cpuid_arg = argp;
1467 struct kvm_cpuid2 cpuid;
1468
1469 r = -EFAULT;
1470 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1471 goto out;
1472 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1473 cpuid_arg->entries);
674eea0f
AK		 1474 if (r)
1475 goto out;
1476
1477 r = -EFAULT;
1478 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1479 goto out;
1480 r = 0;
1481 break;
1482 }
890ca9ae
HY		 1483 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1484 u64 mce_cap;
1485
1486 mce_cap = KVM_MCE_CAP_SUPPORTED;
1487 r = -EFAULT;
1488 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1489 goto out;
1490 r = 0;
1491 break;
1492 }
043405e1
CO		 1493 default:
1494 r = -EINVAL;
1495 }
1496out:
1497 return r;
1498}
1499
313a3dc7
CO		 1500void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1501{
1502 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1503 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1504 unsigned long khz = cpufreq_quick_get(cpu);
1505 if (!khz)
1506 khz = tsc_khz;
1507 per_cpu(cpu_tsc_khz, cpu) = khz;
1508 }
c8076604 1509 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1510}
1511
1512void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1513{
9327fd11 1514 kvm_put_guest_fpu(vcpu);
02daab21 1515 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1516}
1517
07716717 1518static int is_efer_nx(void)
313a3dc7 1519{
e286e86e 1520 unsigned long long efer = 0;
313a3dc7 1521
e286e86e 1522 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1523 return efer & EFER_NX;
1524}
1525
1526static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1527{
1528 int i;
1529 struct kvm_cpuid_entry2 *e, *entry;
1530
313a3dc7 1531 entry = NULL;
ad312c7c
ZX		 1532 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1533 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1534 if (e->function == 0x80000001) {
1535 entry = e;
1536 break;
1537 }
1538 }
07716717 1539 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1540 entry->edx &= ~(1 << 20);
1541 printk(KERN_INFO "kvm: guest NX capability removed\n");
1542 }
1543}
1544
07716717 1545/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1546static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1547 struct kvm_cpuid *cpuid,
1548 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1549{
1550 int r, i;
1551 struct kvm_cpuid_entry *cpuid_entries;
1552
1553 r = -E2BIG;
1554 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1555 goto out;
1556 r = -ENOMEM;
1557 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1558 if (!cpuid_entries)
1559 goto out;
1560 r = -EFAULT;
1561 if (copy_from_user(cpuid_entries, entries,
1562 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1563 goto out_free;
1564 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1565 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1566 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1567 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1568 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1569 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1570 vcpu->arch.cpuid_entries[i].index = 0;
1571 vcpu->arch.cpuid_entries[i].flags = 0;
1572 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1573 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1574 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1575 }
1576 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1577 cpuid_fix_nx_cap(vcpu);
1578 r = 0;
fc61b800 1579 kvm_apic_set_version(vcpu);
0e851880 1580 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1581
1582out_free:
1583 vfree(cpuid_entries);
1584out:
1585 return r;
1586}
1587
1588static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1589 struct kvm_cpuid2 *cpuid,
1590 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1591{
1592 int r;
1593
1594 r = -E2BIG;
1595 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1596 goto out;
1597 r = -EFAULT;
ad312c7c 1598 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1599 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1600 goto out;
ad312c7c 1601 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1602 kvm_apic_set_version(vcpu);
0e851880 1603 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1604 return 0;
1605
1606out:
1607 return r;
1608}
1609
07716717 1610static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1611 struct kvm_cpuid2 *cpuid,
1612 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1613{
1614 int r;
1615
1616 r = -E2BIG;
ad312c7c 1617 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1618 goto out;
1619 r = -EFAULT;
ad312c7c 1620 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1621 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1622 goto out;
1623 return 0;
1624
1625out:
ad312c7c 1626 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1627 return r;
1628}
1629
07716717 1630static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1631 u32 index)
07716717
DK		 1632{
1633 entry->function = function;
1634 entry->index = index;
1635 cpuid_count(entry->function, entry->index,
19355475 1636 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1637 entry->flags = 0;
1638}
1639
7faa4ee1
AK		 1640#define F(x) bit(X86_FEATURE_##x)
1641
07716717
DK		 1642static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1643 u32 index, int *nent, int maxnent)
1644{
7faa4ee1 1645 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1646#ifdef CONFIG_X86_64
17cc3935
SY		 1647 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1648 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1649 unsigned f_lm = F(LM);
1650#else
17cc3935 1651 unsigned f_gbpages = 0;
7faa4ee1 1652 unsigned f_lm = 0;
07716717 1653#endif
4e47c7a6 1654 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1655
1656 /* cpuid 1.edx */
1657 const u32 kvm_supported_word0_x86_features =
1658 F(FPU) | F(VME) | F(DE) | F(PSE) |
1659 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1660 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1661 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1662 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1663 0 /* Reserved, DS, ACPI */ | F(MMX) |
1664 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1665 0 /* HTT, TM, Reserved, PBE */;
1666 /* cpuid 0x80000001.edx */
1667 const u32 kvm_supported_word1_x86_features =
1668 F(FPU) | F(VME) | F(DE) | F(PSE) |
1669 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1670 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1671 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1672 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1673 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1674 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1675 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1676 /* cpuid 1.ecx */
1677 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1678 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1679 0 /* DS-CPL, VMX, SMX, EST */ |
1680 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1681 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1682 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1683 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1684 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1685 /* cpuid 0x80000001.ecx */
07716717 1686 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1687 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1688 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1689 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1690 0 /* SKINIT */ | 0 /* WDT */;
07716717 1691
19355475 1692 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1693 get_cpu();
1694 do_cpuid_1_ent(entry, function, index);
1695 ++*nent;
1696
1697 switch (function) {
1698 case 0:
1699 entry->eax = min(entry->eax, (u32)0xb);
1700 break;
1701 case 1:
1702 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1703 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1704 /* we support x2apic emulation even if host does not support
1705 * it since we emulate x2apic in software */
1706 entry->ecx |= F(X2APIC);
07716717
DK		 1707 break;
1708 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1709 * may return different values. This forces us to get_cpu() before
1710 * issuing the first command, and also to emulate this annoying behavior
1711 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1712 case 2: {
1713 int t, times = entry->eax & 0xff;
1714
1715 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1716 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1717 for (t = 1; t < times && *nent < maxnent; ++t) {
1718 do_cpuid_1_ent(&entry[t], function, 0);
1719 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1720 ++*nent;
1721 }
1722 break;
1723 }
1724 /* function 4 and 0xb have additional index. */
1725 case 4: {
14af3f3c 1726 int i, cache_type;
07716717
DK		 1727
1728 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1729 /* read more entries until cache_type is zero */
14af3f3c
HH		 1730 for (i = 1; *nent < maxnent; ++i) {
1731 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1732 if (!cache_type)
1733 break;
14af3f3c
HH		 1734 do_cpuid_1_ent(&entry[i], function, i);
1735 entry[i].flags |=
07716717
DK		 1736 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1737 ++*nent;
1738 }
1739 break;
1740 }
1741 case 0xb: {
14af3f3c 1742 int i, level_type;
07716717
DK		 1743
1744 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1745 /* read more entries until level_type is zero */
14af3f3c 1746 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1747 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1748 if (!level_type)
1749 break;
14af3f3c
HH		 1750 do_cpuid_1_ent(&entry[i], function, i);
1751 entry[i].flags |=
07716717
DK		 1752 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1753 ++*nent;
1754 }
1755 break;
1756 }
1757 case 0x80000000:
1758 entry->eax = min(entry->eax, 0x8000001a);
1759 break;
1760 case 0x80000001:
1761 entry->edx &= kvm_supported_word1_x86_features;
1762 entry->ecx &= kvm_supported_word6_x86_features;
1763 break;
1764 }
1765 put_cpu();
1766}
1767
7faa4ee1
AK		 1768#undef F
1769
674eea0f 1770static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1771 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1772{
1773 struct kvm_cpuid_entry2 *cpuid_entries;
1774 int limit, nent = 0, r = -E2BIG;
1775 u32 func;
1776
1777 if (cpuid->nent < 1)
1778 goto out;
6a544355
AK		 1779 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1780 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1781 r = -ENOMEM;
1782 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1783 if (!cpuid_entries)
1784 goto out;
1785
1786 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1787 limit = cpuid_entries[0].eax;
1788 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1789 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1790 &nent, cpuid->nent);
07716717
DK		 1791 r = -E2BIG;
1792 if (nent >= cpuid->nent)
1793 goto out_free;
1794
1795 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1796 limit = cpuid_entries[nent - 1].eax;
1797 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1798 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1799 &nent, cpuid->nent);
cb007648
MM		 1800 r = -E2BIG;
1801 if (nent >= cpuid->nent)
1802 goto out_free;
1803
07716717
DK		 1804 r = -EFAULT;
1805 if (copy_to_user(entries, cpuid_entries,
19355475 1806 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1807 goto out_free;
1808 cpuid->nent = nent;
1809 r = 0;
1810
1811out_free:
1812 vfree(cpuid_entries);
1813out:
1814 return r;
1815}
1816
313a3dc7
CO		 1817static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1818 struct kvm_lapic_state *s)
1819{
1820 vcpu_load(vcpu);
ad312c7c 1821 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1822 vcpu_put(vcpu);
1823
1824 return 0;
1825}
1826
1827static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1828 struct kvm_lapic_state *s)
1829{
1830 vcpu_load(vcpu);
ad312c7c 1831 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1832 kvm_apic_post_state_restore(vcpu);
cb142eb7 1833 update_cr8_intercept(vcpu);
313a3dc7
CO		 1834 vcpu_put(vcpu);
1835
1836 return 0;
1837}
1838
f77bc6a4
ZX		 1839static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1840 struct kvm_interrupt *irq)
1841{
1842 if (irq->irq < 0 || irq->irq >= 256)
1843 return -EINVAL;
1844 if (irqchip_in_kernel(vcpu->kvm))
1845 return -ENXIO;
1846 vcpu_load(vcpu);
1847
66fd3f7f 1848 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1849
1850 vcpu_put(vcpu);
1851
1852 return 0;
1853}
1854
c4abb7c9
JK		 1855static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1856{
1857 vcpu_load(vcpu);
1858 kvm_inject_nmi(vcpu);
1859 vcpu_put(vcpu);
1860
1861 return 0;
1862}
1863
b209749f
AK		 1864static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1865 struct kvm_tpr_access_ctl *tac)
1866{
1867 if (tac->flags)
1868 return -EINVAL;
1869 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1870 return 0;
1871}
1872
890ca9ae
HY		 1873static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1874 u64 mcg_cap)
1875{
1876 int r;
1877 unsigned bank_num = mcg_cap & 0xff, bank;
1878
1879 r = -EINVAL;
a9e38c3e 1880 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1881 goto out;
1882 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1883 goto out;
1884 r = 0;
1885 vcpu->arch.mcg_cap = mcg_cap;
1886 /* Init IA32_MCG_CTL to all 1s */
1887 if (mcg_cap & MCG_CTL_P)
1888 vcpu->arch.mcg_ctl = ~(u64)0;
1889 /* Init IA32_MCi_CTL to all 1s */
1890 for (bank = 0; bank < bank_num; bank++)
1891 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1892out:
1893 return r;
1894}
1895
1896static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1897 struct kvm_x86_mce *mce)
1898{
1899 u64 mcg_cap = vcpu->arch.mcg_cap;
1900 unsigned bank_num = mcg_cap & 0xff;
1901 u64 *banks = vcpu->arch.mce_banks;
1902
1903 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1904 return -EINVAL;
1905 /*
1906 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1907 * reporting is disabled
1908 */
1909 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1910 vcpu->arch.mcg_ctl != ~(u64)0)
1911 return 0;
1912 banks += 4 * mce->bank;
1913 /*
1914 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1915 * reporting is disabled for the bank
1916 */
1917 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1918 return 0;
1919 if (mce->status & MCI_STATUS_UC) {
1920 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 1921 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 1922 printk(KERN_DEBUG "kvm: set_mce: "
1923 "injects mce exception while "
1924 "previous one is in progress!\n");
1925 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1926 return 0;
1927 }
1928 if (banks[1] & MCI_STATUS_VAL)
1929 mce->status |= MCI_STATUS_OVER;
1930 banks[2] = mce->addr;
1931 banks[3] = mce->misc;
1932 vcpu->arch.mcg_status = mce->mcg_status;
1933 banks[1] = mce->status;
1934 kvm_queue_exception(vcpu, MC_VECTOR);
1935 } else if (!(banks[1] & MCI_STATUS_VAL)
1936 || !(banks[1] & MCI_STATUS_UC)) {
1937 if (banks[1] & MCI_STATUS_VAL)
1938 mce->status |= MCI_STATUS_OVER;
1939 banks[2] = mce->addr;
1940 banks[3] = mce->misc;
1941 banks[1] = mce->status;
1942 } else
1943 banks[1] |= MCI_STATUS_OVER;
1944 return 0;
1945}
1946
3cfc3092
JK		 1947static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1948 struct kvm_vcpu_events *events)
1949{
1950 vcpu_load(vcpu);
1951
1952 events->exception.injected = vcpu->arch.exception.pending;
1953 events->exception.nr = vcpu->arch.exception.nr;
1954 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1955 events->exception.error_code = vcpu->arch.exception.error_code;
1956
1957 events->interrupt.injected = vcpu->arch.interrupt.pending;
1958 events->interrupt.nr = vcpu->arch.interrupt.nr;
1959 events->interrupt.soft = vcpu->arch.interrupt.soft;
1960
1961 events->nmi.injected = vcpu->arch.nmi_injected;
1962 events->nmi.pending = vcpu->arch.nmi_pending;
1963 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1964
1965 events->sipi_vector = vcpu->arch.sipi_vector;
1966
dab4b911
JK		 1967 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
1968 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 1969
1970 vcpu_put(vcpu);
1971}
1972
1973static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1974 struct kvm_vcpu_events *events)
1975{
dab4b911
JK		 1976 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
1977 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 1978 return -EINVAL;
1979
1980 vcpu_load(vcpu);
1981
1982 vcpu->arch.exception.pending = events->exception.injected;
1983 vcpu->arch.exception.nr = events->exception.nr;
1984 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1985 vcpu->arch.exception.error_code = events->exception.error_code;
1986
1987 vcpu->arch.interrupt.pending = events->interrupt.injected;
1988 vcpu->arch.interrupt.nr = events->interrupt.nr;
1989 vcpu->arch.interrupt.soft = events->interrupt.soft;
1990 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1991 kvm_pic_clear_isr_ack(vcpu->kvm);
1992
1993 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 1994 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
1995 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 1996 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1997
dab4b911
JK		 1998 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
1999 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2000
2001 vcpu_put(vcpu);
2002
2003 return 0;
2004}
2005
313a3dc7
CO		 2006long kvm_arch_vcpu_ioctl(struct file *filp,
2007 unsigned int ioctl, unsigned long arg)
2008{
2009 struct kvm_vcpu *vcpu = filp->private_data;
2010 void __user *argp = (void __user *)arg;
2011 int r;
b772ff36 2012 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2013
2014 switch (ioctl) {
2015 case KVM_GET_LAPIC: {
2204ae3c
MT		 2016 r = -EINVAL;
2017 if (!vcpu->arch.apic)
2018 goto out;
b772ff36 2019 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2020
b772ff36
DH		 2021 r = -ENOMEM;
2022 if (!lapic)
2023 goto out;
2024 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2025 if (r)
2026 goto out;
2027 r = -EFAULT;
b772ff36 2028 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2029 goto out;
2030 r = 0;
2031 break;
2032 }
2033 case KVM_SET_LAPIC: {
2204ae3c
MT		 2034 r = -EINVAL;
2035 if (!vcpu->arch.apic)
2036 goto out;
b772ff36
DH		 2037 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2038 r = -ENOMEM;
2039 if (!lapic)
2040 goto out;
313a3dc7 2041 r = -EFAULT;
b772ff36 2042 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2043 goto out;
b772ff36 2044 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2045 if (r)
2046 goto out;
2047 r = 0;
2048 break;
2049 }
f77bc6a4
ZX		 2050 case KVM_INTERRUPT: {
2051 struct kvm_interrupt irq;
2052
2053 r = -EFAULT;
2054 if (copy_from_user(&irq, argp, sizeof irq))
2055 goto out;
2056 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2057 if (r)
2058 goto out;
2059 r = 0;
2060 break;
2061 }
c4abb7c9
JK		 2062 case KVM_NMI: {
2063 r = kvm_vcpu_ioctl_nmi(vcpu);
2064 if (r)
2065 goto out;
2066 r = 0;
2067 break;
2068 }
313a3dc7
CO		 2069 case KVM_SET_CPUID: {
2070 struct kvm_cpuid __user *cpuid_arg = argp;
2071 struct kvm_cpuid cpuid;
2072
2073 r = -EFAULT;
2074 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2075 goto out;
2076 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2077 if (r)
2078 goto out;
2079 break;
2080 }
07716717
DK		 2081 case KVM_SET_CPUID2: {
2082 struct kvm_cpuid2 __user *cpuid_arg = argp;
2083 struct kvm_cpuid2 cpuid;
2084
2085 r = -EFAULT;
2086 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2087 goto out;
2088 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2089 cpuid_arg->entries);
07716717
DK		 2090 if (r)
2091 goto out;
2092 break;
2093 }
2094 case KVM_GET_CPUID2: {
2095 struct kvm_cpuid2 __user *cpuid_arg = argp;
2096 struct kvm_cpuid2 cpuid;
2097
2098 r = -EFAULT;
2099 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2100 goto out;
2101 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2102 cpuid_arg->entries);
07716717
DK		 2103 if (r)
2104 goto out;
2105 r = -EFAULT;
2106 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2107 goto out;
2108 r = 0;
2109 break;
2110 }
313a3dc7
CO		 2111 case KVM_GET_MSRS:
2112 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2113 break;
2114 case KVM_SET_MSRS:
2115 r = msr_io(vcpu, argp, do_set_msr, 0);
2116 break;
b209749f
AK		 2117 case KVM_TPR_ACCESS_REPORTING: {
2118 struct kvm_tpr_access_ctl tac;
2119
2120 r = -EFAULT;
2121 if (copy_from_user(&tac, argp, sizeof tac))
2122 goto out;
2123 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2124 if (r)
2125 goto out;
2126 r = -EFAULT;
2127 if (copy_to_user(argp, &tac, sizeof tac))
2128 goto out;
2129 r = 0;
2130 break;
2131 };
b93463aa
AK		 2132 case KVM_SET_VAPIC_ADDR: {
2133 struct kvm_vapic_addr va;
2134
2135 r = -EINVAL;
2136 if (!irqchip_in_kernel(vcpu->kvm))
2137 goto out;
2138 r = -EFAULT;
2139 if (copy_from_user(&va, argp, sizeof va))
2140 goto out;
2141 r = 0;
2142 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2143 break;
2144 }
890ca9ae
HY		 2145 case KVM_X86_SETUP_MCE: {
2146 u64 mcg_cap;
2147
2148 r = -EFAULT;
2149 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2150 goto out;
2151 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2152 break;
2153 }
2154 case KVM_X86_SET_MCE: {
2155 struct kvm_x86_mce mce;
2156
2157 r = -EFAULT;
2158 if (copy_from_user(&mce, argp, sizeof mce))
2159 goto out;
2160 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2161 break;
2162 }
3cfc3092
JK		 2163 case KVM_GET_VCPU_EVENTS: {
2164 struct kvm_vcpu_events events;
2165
2166 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2167
2168 r = -EFAULT;
2169 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2170 break;
2171 r = 0;
2172 break;
2173 }
2174 case KVM_SET_VCPU_EVENTS: {
2175 struct kvm_vcpu_events events;
2176
2177 r = -EFAULT;
2178 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2179 break;
2180
2181 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2182 break;
2183 }
313a3dc7
CO		 2184 default:
2185 r = -EINVAL;
2186 }
2187out:
7a6ce84c 2188 kfree(lapic);
313a3dc7
CO		 2189 return r;
2190}
2191
1fe779f8
CO		 2192static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2193{
2194 int ret;
2195
2196 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2197 return -1;
2198 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2199 return ret;
2200}
2201
b927a3ce
SY		 2202static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2203 u64 ident_addr)
2204{
2205 kvm->arch.ept_identity_map_addr = ident_addr;
2206 return 0;
2207}
2208
1fe779f8
CO		 2209static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2210 u32 kvm_nr_mmu_pages)
2211{
2212 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2213 return -EINVAL;
2214
79fac95e 2215 mutex_lock(&kvm->slots_lock);
7c8a83b7 2216 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2217
2218 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2219 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2220
7c8a83b7 2221 spin_unlock(&kvm->mmu_lock);
79fac95e 2222 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2223 return 0;
2224}
2225
2226static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2227{
f05e70ac 2228 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2229}
2230
a983fb23
MT		 2231gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2232{
2233 int i;
2234 struct kvm_mem_alias *alias;
2235 struct kvm_mem_aliases *aliases;
2236
2237 aliases = rcu_dereference(kvm->arch.aliases);
2238
2239 for (i = 0; i < aliases->naliases; ++i) {
2240 alias = &aliases->aliases[i];
2241 if (alias->flags & KVM_ALIAS_INVALID)
2242 continue;
2243 if (gfn >= alias->base_gfn
2244 && gfn < alias->base_gfn + alias->npages)
2245 return alias->target_gfn + gfn - alias->base_gfn;
2246 }
2247 return gfn;
2248}
2249
e9f85cde
ZX		 2250gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2251{
2252 int i;
2253 struct kvm_mem_alias *alias;
a983fb23
MT		 2254 struct kvm_mem_aliases *aliases;
2255
2256 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2257
fef9cce0
MT		 2258 for (i = 0; i < aliases->naliases; ++i) {
2259 alias = &aliases->aliases[i];
e9f85cde
ZX		 2260 if (gfn >= alias->base_gfn
2261 && gfn < alias->base_gfn + alias->npages)
2262 return alias->target_gfn + gfn - alias->base_gfn;
2263 }
2264 return gfn;
2265}
2266
1fe779f8
CO		 2267/*
2268 * Set a new alias region. Aliases map a portion of physical memory into
2269 * another portion. This is useful for memory windows, for example the PC
2270 * VGA region.
2271 */
2272static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2273 struct kvm_memory_alias *alias)
2274{
2275 int r, n;
2276 struct kvm_mem_alias *p;
a983fb23 2277 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2278
2279 r = -EINVAL;
2280 /* General sanity checks */
2281 if (alias->memory_size & (PAGE_SIZE - 1))
2282 goto out;
2283 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2284 goto out;
2285 if (alias->slot >= KVM_ALIAS_SLOTS)
2286 goto out;
2287 if (alias->guest_phys_addr + alias->memory_size
2288 < alias->guest_phys_addr)
2289 goto out;
2290 if (alias->target_phys_addr + alias->memory_size
2291 < alias->target_phys_addr)
2292 goto out;
2293
a983fb23
MT		 2294 r = -ENOMEM;
2295 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2296 if (!aliases)
2297 goto out;
2298
79fac95e 2299 mutex_lock(&kvm->slots_lock);
1fe779f8 2300
a983fb23
MT		 2301 /* invalidate any gfn reference in case of deletion/shrinking */
2302 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2303 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2304 old_aliases = kvm->arch.aliases;
2305 rcu_assign_pointer(kvm->arch.aliases, aliases);
2306 synchronize_srcu_expedited(&kvm->srcu);
2307 kvm_mmu_zap_all(kvm);
2308 kfree(old_aliases);
2309
2310 r = -ENOMEM;
2311 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2312 if (!aliases)
2313 goto out_unlock;
2314
2315 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2316
2317 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2318 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2319 p->npages = alias->memory_size >> PAGE_SHIFT;
2320 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2321 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2322
2323 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2324 if (aliases->aliases[n - 1].npages)
1fe779f8 2325 break;
fef9cce0 2326 aliases->naliases = n;
1fe779f8 2327
a983fb23
MT		 2328 old_aliases = kvm->arch.aliases;
2329 rcu_assign_pointer(kvm->arch.aliases, aliases);
2330 synchronize_srcu_expedited(&kvm->srcu);
2331 kfree(old_aliases);
2332 r = 0;
1fe779f8 2333
a983fb23 2334out_unlock:
79fac95e 2335 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2336out:
2337 return r;
2338}
2339
2340static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2341{
2342 int r;
2343
2344 r = 0;
2345 switch (chip->chip_id) {
2346 case KVM_IRQCHIP_PIC_MASTER:
2347 memcpy(&chip->chip.pic,
2348 &pic_irqchip(kvm)->pics[0],
2349 sizeof(struct kvm_pic_state));
2350 break;
2351 case KVM_IRQCHIP_PIC_SLAVE:
2352 memcpy(&chip->chip.pic,
2353 &pic_irqchip(kvm)->pics[1],
2354 sizeof(struct kvm_pic_state));
2355 break;
2356 case KVM_IRQCHIP_IOAPIC:
eba0226b 2357 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2358 break;
2359 default:
2360 r = -EINVAL;
2361 break;
2362 }
2363 return r;
2364}
2365
2366static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2367{
2368 int r;
2369
2370 r = 0;
2371 switch (chip->chip_id) {
2372 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2373 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2374 memcpy(&pic_irqchip(kvm)->pics[0],
2375 &chip->chip.pic,
2376 sizeof(struct kvm_pic_state));
894a9c55 2377 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2378 break;
2379 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2380 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2381 memcpy(&pic_irqchip(kvm)->pics[1],
2382 &chip->chip.pic,
2383 sizeof(struct kvm_pic_state));
894a9c55 2384 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2385 break;
2386 case KVM_IRQCHIP_IOAPIC:
eba0226b 2387 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2388 break;
2389 default:
2390 r = -EINVAL;
2391 break;
2392 }
2393 kvm_pic_update_irq(pic_irqchip(kvm));
2394 return r;
2395}
2396
e0f63cb9
SY		 2397static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2398{
2399 int r = 0;
2400
894a9c55 2401 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2402 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2403 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2404 return r;
2405}
2406
2407static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2408{
2409 int r = 0;
2410
894a9c55 2411 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2412 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2413 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2414 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2415 return r;
2416}
2417
2418static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2419{
2420 int r = 0;
2421
2422 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2423 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2424 sizeof(ps->channels));
2425 ps->flags = kvm->arch.vpit->pit_state.flags;
2426 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2427 return r;
2428}
2429
2430static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2431{
2432 int r = 0, start = 0;
2433 u32 prev_legacy, cur_legacy;
2434 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2435 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2436 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2437 if (!prev_legacy && cur_legacy)
2438 start = 1;
2439 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2440 sizeof(kvm->arch.vpit->pit_state.channels));
2441 kvm->arch.vpit->pit_state.flags = ps->flags;
2442 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2443 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2444 return r;
2445}
2446
52d939a0
MT		 2447static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2448 struct kvm_reinject_control *control)
2449{
2450 if (!kvm->arch.vpit)
2451 return -ENXIO;
894a9c55 2452 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2453 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2454 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2455 return 0;
2456}
2457
5bb064dc
ZX		 2458/*
2459 * Get (and clear) the dirty memory log for a memory slot.
2460 */
2461int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2462 struct kvm_dirty_log *log)
2463{
b050b015 2464 int r, n, i;
5bb064dc 2465 struct kvm_memory_slot *memslot;
b050b015
MT		 2466 unsigned long is_dirty = 0;
2467 unsigned long *dirty_bitmap = NULL;
5bb064dc 2468
79fac95e 2469 mutex_lock(&kvm->slots_lock);
5bb064dc 2470
b050b015
MT		 2471 r = -EINVAL;
2472 if (log->slot >= KVM_MEMORY_SLOTS)
2473 goto out;
2474
2475 memslot = &kvm->memslots->memslots[log->slot];
2476 r = -ENOENT;
2477 if (!memslot->dirty_bitmap)
2478 goto out;
2479
2480 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2481
2482 r = -ENOMEM;
2483 dirty_bitmap = vmalloc(n);
2484 if (!dirty_bitmap)
5bb064dc 2485 goto out;
b050b015
MT		 2486 memset(dirty_bitmap, 0, n);
2487
2488 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2489 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2490
2491 /* If nothing is dirty, don't bother messing with page tables. */
2492 if (is_dirty) {
b050b015
MT		 2493 struct kvm_memslots *slots, *old_slots;
2494
7c8a83b7 2495 spin_lock(&kvm->mmu_lock);
5bb064dc 2496 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2497 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2498
2499 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2500 if (!slots)
2501 goto out_free;
2502
2503 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2504 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2505
2506 old_slots = kvm->memslots;
2507 rcu_assign_pointer(kvm->memslots, slots);
2508 synchronize_srcu_expedited(&kvm->srcu);
2509 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2510 kfree(old_slots);
5bb064dc 2511 }
b050b015 2512
5bb064dc 2513 r = 0;
b050b015
MT		 2514 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2515 r = -EFAULT;
2516out_free:
2517 vfree(dirty_bitmap);
5bb064dc 2518out:
79fac95e 2519 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2520 return r;
2521}
2522
1fe779f8
CO		 2523long kvm_arch_vm_ioctl(struct file *filp,
2524 unsigned int ioctl, unsigned long arg)
2525{
2526 struct kvm *kvm = filp->private_data;
2527 void __user *argp = (void __user *)arg;
367e1319 2528 int r = -ENOTTY;
f0d66275
DH		 2529 /*
2530 * This union makes it completely explicit to gcc-3.x
2531 * that these two variables' stack usage should be
2532 * combined, not added together.
2533 */
2534 union {
2535 struct kvm_pit_state ps;
e9f42757 2536 struct kvm_pit_state2 ps2;
f0d66275 2537 struct kvm_memory_alias alias;
c5ff41ce 2538 struct kvm_pit_config pit_config;
f0d66275 2539 } u;
1fe779f8
CO		 2540
2541 switch (ioctl) {
2542 case KVM_SET_TSS_ADDR:
2543 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2544 if (r < 0)
2545 goto out;
2546 break;
b927a3ce
SY		 2547 case KVM_SET_IDENTITY_MAP_ADDR: {
2548 u64 ident_addr;
2549
2550 r = -EFAULT;
2551 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2552 goto out;
2553 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2554 if (r < 0)
2555 goto out;
2556 break;
2557 }
1fe779f8
CO		 2558 case KVM_SET_MEMORY_REGION: {
2559 struct kvm_memory_region kvm_mem;
2560 struct kvm_userspace_memory_region kvm_userspace_mem;
2561
2562 r = -EFAULT;
2563 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2564 goto out;
2565 kvm_userspace_mem.slot = kvm_mem.slot;
2566 kvm_userspace_mem.flags = kvm_mem.flags;
2567 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2568 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2569 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2570 if (r)
2571 goto out;
2572 break;
2573 }
2574 case KVM_SET_NR_MMU_PAGES:
2575 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2576 if (r)
2577 goto out;
2578 break;
2579 case KVM_GET_NR_MMU_PAGES:
2580 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2581 break;
f0d66275 2582 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2583 r = -EFAULT;
f0d66275 2584 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2585 goto out;
f0d66275 2586 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2587 if (r)
2588 goto out;
2589 break;
3ddea128
MT		 2590 case KVM_CREATE_IRQCHIP: {
2591 struct kvm_pic *vpic;
2592
2593 mutex_lock(&kvm->lock);
2594 r = -EEXIST;
2595 if (kvm->arch.vpic)
2596 goto create_irqchip_unlock;
1fe779f8 2597 r = -ENOMEM;
3ddea128
MT		 2598 vpic = kvm_create_pic(kvm);
2599 if (vpic) {
1fe779f8
CO		 2600 r = kvm_ioapic_init(kvm);
2601 if (r) {
3ddea128
MT		 2602 kfree(vpic);
2603 goto create_irqchip_unlock;
1fe779f8
CO		 2604 }
2605 } else
3ddea128
MT		 2606 goto create_irqchip_unlock;
2607 smp_wmb();
2608 kvm->arch.vpic = vpic;
2609 smp_wmb();
399ec807
AK		 2610 r = kvm_setup_default_irq_routing(kvm);
2611 if (r) {
3ddea128 2612 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2613 kfree(kvm->arch.vpic);
2614 kfree(kvm->arch.vioapic);
3ddea128
MT		 2615 kvm->arch.vpic = NULL;
2616 kvm->arch.vioapic = NULL;
2617 mutex_unlock(&kvm->irq_lock);
399ec807 2618 }
3ddea128
MT		 2619 create_irqchip_unlock:
2620 mutex_unlock(&kvm->lock);
1fe779f8 2621 break;
3ddea128 2622 }
7837699f 2623 case KVM_CREATE_PIT:
c5ff41ce
JK		 2624 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2625 goto create_pit;
2626 case KVM_CREATE_PIT2:
2627 r = -EFAULT;
2628 if (copy_from_user(&u.pit_config, argp,
2629 sizeof(struct kvm_pit_config)))
2630 goto out;
2631 create_pit:
79fac95e 2632 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2633 r = -EEXIST;
2634 if (kvm->arch.vpit)
2635 goto create_pit_unlock;
7837699f 2636 r = -ENOMEM;
c5ff41ce 2637 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2638 if (kvm->arch.vpit)
2639 r = 0;
269e05e4 2640 create_pit_unlock:
79fac95e 2641 mutex_unlock(&kvm->slots_lock);
7837699f 2642 break;
4925663a 2643 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2644 case KVM_IRQ_LINE: {
2645 struct kvm_irq_level irq_event;
2646
2647 r = -EFAULT;
2648 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2649 goto out;
2650 if (irqchip_in_kernel(kvm)) {
4925663a 2651 __s32 status;
4925663a
GN		 2652 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2653 irq_event.irq, irq_event.level);
4925663a
GN		 2654 if (ioctl == KVM_IRQ_LINE_STATUS) {
2655 irq_event.status = status;
2656 if (copy_to_user(argp, &irq_event,
2657 sizeof irq_event))
2658 goto out;
2659 }
1fe779f8
CO		 2660 r = 0;
2661 }
2662 break;
2663 }
2664 case KVM_GET_IRQCHIP: {
2665 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2666 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2667
f0d66275
DH		 2668 r = -ENOMEM;
2669 if (!chip)
1fe779f8 2670 goto out;
f0d66275
DH		 2671 r = -EFAULT;
2672 if (copy_from_user(chip, argp, sizeof *chip))
2673 goto get_irqchip_out;
1fe779f8
CO		 2674 r = -ENXIO;
2675 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2676 goto get_irqchip_out;
2677 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2678 if (r)
f0d66275 2679 goto get_irqchip_out;
1fe779f8 2680 r = -EFAULT;
f0d66275
DH		 2681 if (copy_to_user(argp, chip, sizeof *chip))
2682 goto get_irqchip_out;
1fe779f8 2683 r = 0;
f0d66275
DH		 2684 get_irqchip_out:
2685 kfree(chip);
2686 if (r)
2687 goto out;
1fe779f8
CO		 2688 break;
2689 }
2690 case KVM_SET_IRQCHIP: {
2691 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2692 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2693
f0d66275
DH		 2694 r = -ENOMEM;
2695 if (!chip)
1fe779f8 2696 goto out;
f0d66275
DH		 2697 r = -EFAULT;
2698 if (copy_from_user(chip, argp, sizeof *chip))
2699 goto set_irqchip_out;
1fe779f8
CO		 2700 r = -ENXIO;
2701 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2702 goto set_irqchip_out;
2703 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2704 if (r)
f0d66275 2705 goto set_irqchip_out;
1fe779f8 2706 r = 0;
f0d66275
DH		 2707 set_irqchip_out:
2708 kfree(chip);
2709 if (r)
2710 goto out;
1fe779f8
CO		 2711 break;
2712 }
e0f63cb9 2713 case KVM_GET_PIT: {
e0f63cb9 2714 r = -EFAULT;
f0d66275 2715 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2716 goto out;
2717 r = -ENXIO;
2718 if (!kvm->arch.vpit)
2719 goto out;
f0d66275 2720 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2721 if (r)
2722 goto out;
2723 r = -EFAULT;
f0d66275 2724 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2725 goto out;
2726 r = 0;
2727 break;
2728 }
2729 case KVM_SET_PIT: {
e0f63cb9 2730 r = -EFAULT;
f0d66275 2731 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2732 goto out;
2733 r = -ENXIO;
2734 if (!kvm->arch.vpit)
2735 goto out;
f0d66275 2736 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2737 if (r)
2738 goto out;
2739 r = 0;
2740 break;
2741 }
e9f42757
BK		 2742 case KVM_GET_PIT2: {
2743 r = -ENXIO;
2744 if (!kvm->arch.vpit)
2745 goto out;
2746 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2747 if (r)
2748 goto out;
2749 r = -EFAULT;
2750 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2751 goto out;
2752 r = 0;
2753 break;
2754 }
2755 case KVM_SET_PIT2: {
2756 r = -EFAULT;
2757 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2758 goto out;
2759 r = -ENXIO;
2760 if (!kvm->arch.vpit)
2761 goto out;
2762 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2763 if (r)
2764 goto out;
2765 r = 0;
2766 break;
2767 }
52d939a0
MT		 2768 case KVM_REINJECT_CONTROL: {
2769 struct kvm_reinject_control control;
2770 r = -EFAULT;
2771 if (copy_from_user(&control, argp, sizeof(control)))
2772 goto out;
2773 r = kvm_vm_ioctl_reinject(kvm, &control);
2774 if (r)
2775 goto out;
2776 r = 0;
2777 break;
2778 }
ffde22ac
ES		 2779 case KVM_XEN_HVM_CONFIG: {
2780 r = -EFAULT;
2781 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2782 sizeof(struct kvm_xen_hvm_config)))
2783 goto out;
2784 r = -EINVAL;
2785 if (kvm->arch.xen_hvm_config.flags)
2786 goto out;
2787 r = 0;
2788 break;
2789 }
afbcf7ab
GC		 2790 case KVM_SET_CLOCK: {
2791 struct timespec now;
2792 struct kvm_clock_data user_ns;
2793 u64 now_ns;
2794 s64 delta;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2798 goto out;
2799
2800 r = -EINVAL;
2801 if (user_ns.flags)
2802 goto out;
2803
2804 r = 0;
2805 ktime_get_ts(&now);
2806 now_ns = timespec_to_ns(&now);
2807 delta = user_ns.clock - now_ns;
2808 kvm->arch.kvmclock_offset = delta;
2809 break;
2810 }
2811 case KVM_GET_CLOCK: {
2812 struct timespec now;
2813 struct kvm_clock_data user_ns;
2814 u64 now_ns;
2815
2816 ktime_get_ts(&now);
2817 now_ns = timespec_to_ns(&now);
2818 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2819 user_ns.flags = 0;
2820
2821 r = -EFAULT;
2822 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2823 goto out;
2824 r = 0;
2825 break;
2826 }
2827
1fe779f8
CO		 2828 default:
2829 ;
2830 }
2831out:
2832 return r;
2833}
2834
a16b043c 2835static void kvm_init_msr_list(void)
043405e1
CO		 2836{
2837 u32 dummy[2];
2838 unsigned i, j;
2839
e3267cbb
GC		 2840 /* skip the first msrs in the list. KVM-specific */
2841 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2842 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2843 continue;
2844 if (j < i)
2845 msrs_to_save[j] = msrs_to_save[i];
2846 j++;
2847 }
2848 num_msrs_to_save = j;
2849}
2850
bda9020e
MT		 2851static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2852 const void *v)
bbd9b64e 2853{
bda9020e
MT		 2854 if (vcpu->arch.apic &&
2855 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2856 return 0;
bbd9b64e 2857
e93f8a0f 2858 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2859}
2860
bda9020e 2861static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2862{
bda9020e
MT		 2863 if (vcpu->arch.apic &&
2864 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2865 return 0;
bbd9b64e 2866
e93f8a0f 2867 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2868}
2869
cded19f3
HE		 2870static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2871 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2872{
2873 void *data = val;
10589a46 2874 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2875
2876 while (bytes) {
ad312c7c 2877 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2878 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2879 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2880 int ret;
2881
10589a46
MT		 2882 if (gpa == UNMAPPED_GVA) {
2883 r = X86EMUL_PROPAGATE_FAULT;
2884 goto out;
2885 }
77c2002e 2886 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2887 if (ret < 0) {
2888 r = X86EMUL_UNHANDLEABLE;
2889 goto out;
2890 }
bbd9b64e 2891
77c2002e
IE		 2892 bytes -= toread;
2893 data += toread;
2894 addr += toread;
bbd9b64e 2895 }
10589a46 2896out:
10589a46 2897 return r;
bbd9b64e 2898}
77c2002e 2899
cded19f3
HE		 2900static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2901 struct kvm_vcpu *vcpu)
77c2002e
IE		 2902{
2903 void *data = val;
2904 int r = X86EMUL_CONTINUE;
2905
2906 while (bytes) {
2907 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2908 unsigned offset = addr & (PAGE_SIZE-1);
2909 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2910 int ret;
2911
2912 if (gpa == UNMAPPED_GVA) {
2913 r = X86EMUL_PROPAGATE_FAULT;
2914 goto out;
2915 }
2916 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2917 if (ret < 0) {
2918 r = X86EMUL_UNHANDLEABLE;
2919 goto out;
2920 }
2921
2922 bytes -= towrite;
2923 data += towrite;
2924 addr += towrite;
2925 }
2926out:
2927 return r;
2928}
2929
bbd9b64e 2930
bbd9b64e
CO		 2931static int emulator_read_emulated(unsigned long addr,
2932 void *val,
2933 unsigned int bytes,
2934 struct kvm_vcpu *vcpu)
2935{
bbd9b64e
CO		 2936 gpa_t gpa;
2937
2938 if (vcpu->mmio_read_completed) {
2939 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2940 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2941 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2942 vcpu->mmio_read_completed = 0;
2943 return X86EMUL_CONTINUE;
2944 }
2945
ad312c7c 2946 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2947
2948 /* For APIC access vmexit */
2949 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2950 goto mmio;
2951
77c2002e
IE		 2952 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2953 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2954 return X86EMUL_CONTINUE;
2955 if (gpa == UNMAPPED_GVA)
2956 return X86EMUL_PROPAGATE_FAULT;
2957
2958mmio:
2959 /*
2960 * Is this MMIO handled locally?
2961 */
aec51dc4
AK		 2962 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2963 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2964 return X86EMUL_CONTINUE;
2965 }
aec51dc4
AK		 2966
2967 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2968
2969 vcpu->mmio_needed = 1;
2970 vcpu->mmio_phys_addr = gpa;
2971 vcpu->mmio_size = bytes;
2972 vcpu->mmio_is_write = 0;
2973
2974 return X86EMUL_UNHANDLEABLE;
2975}
2976
3200f405 2977int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2978 const void *val, int bytes)
bbd9b64e
CO		 2979{
2980 int ret;
2981
2982 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2983 if (ret < 0)
bbd9b64e 2984 return 0;
ad218f85 2985 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2986 return 1;
2987}
2988
2989static int emulator_write_emulated_onepage(unsigned long addr,
2990 const void *val,
2991 unsigned int bytes,
2992 struct kvm_vcpu *vcpu)
2993{
10589a46
MT		 2994 gpa_t gpa;
2995
10589a46 2996 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2997
2998 if (gpa == UNMAPPED_GVA) {
c3c91fee 2999 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 3000 return X86EMUL_PROPAGATE_FAULT;
3001 }
3002
3003 /* For APIC access vmexit */
3004 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3005 goto mmio;
3006
3007 if (emulator_write_phys(vcpu, gpa, val, bytes))
3008 return X86EMUL_CONTINUE;
3009
3010mmio:
aec51dc4 3011 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3012 /*
3013 * Is this MMIO handled locally?
3014 */
bda9020e 3015 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3016 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3017
3018 vcpu->mmio_needed = 1;
3019 vcpu->mmio_phys_addr = gpa;
3020 vcpu->mmio_size = bytes;
3021 vcpu->mmio_is_write = 1;
3022 memcpy(vcpu->mmio_data, val, bytes);
3023
3024 return X86EMUL_CONTINUE;
3025}
3026
3027int emulator_write_emulated(unsigned long addr,
3028 const void *val,
3029 unsigned int bytes,
3030 struct kvm_vcpu *vcpu)
3031{
3032 /* Crossing a page boundary? */
3033 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3034 int rc, now;
3035
3036 now = -addr & ~PAGE_MASK;
3037 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3038 if (rc != X86EMUL_CONTINUE)
3039 return rc;
3040 addr += now;
3041 val += now;
3042 bytes -= now;
3043 }
3044 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3045}
3046EXPORT_SYMBOL_GPL(emulator_write_emulated);
3047
3048static int emulator_cmpxchg_emulated(unsigned long addr,
3049 const void *old,
3050 const void *new,
3051 unsigned int bytes,
3052 struct kvm_vcpu *vcpu)
3053{
9f51e24e 3054 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3055#ifndef CONFIG_X86_64
3056 /* guests cmpxchg8b have to be emulated atomically */
3057 if (bytes == 8) {
10589a46 3058 gpa_t gpa;
2bacc55c 3059 struct page *page;
c0b49b0d 3060 char *kaddr;
2bacc55c
MT		 3061 u64 val;
3062
10589a46
MT		 3063 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
3064
2bacc55c
MT		 3065 if (gpa == UNMAPPED_GVA ||
3066 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3067 goto emul_write;
3068
3069 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3070 goto emul_write;
3071
3072 val = *(u64 *)new;
72dc67a6 3073
2bacc55c 3074 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3075
c0b49b0d
AM		 3076 kaddr = kmap_atomic(page, KM_USER0);
3077 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3078 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3079 kvm_release_page_dirty(page);
3080 }
3200f405 3081emul_write:
2bacc55c
MT		 3082#endif
3083
bbd9b64e
CO		 3084 return emulator_write_emulated(addr, new, bytes, vcpu);
3085}
3086
3087static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3088{
3089 return kvm_x86_ops->get_segment_base(vcpu, seg);
3090}
3091
3092int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3093{
a7052897 3094 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3095 return X86EMUL_CONTINUE;
3096}
3097
3098int emulate_clts(struct kvm_vcpu *vcpu)
3099{
4d4ec087 3100 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
bbd9b64e
CO		 3101 return X86EMUL_CONTINUE;
3102}
3103
3104int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3105{
3106 struct kvm_vcpu *vcpu = ctxt->vcpu;
3107
3108 switch (dr) {
3109 case 0 ... 3:
3110 *dest = kvm_x86_ops->get_dr(vcpu, dr);
3111 return X86EMUL_CONTINUE;
3112 default:
b8688d51 3113 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 3114 return X86EMUL_UNHANDLEABLE;
3115 }
3116}
3117
3118int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3119{
3120 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
3121 int exception;
3122
3123 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
3124 if (exception) {
3125 /* FIXME: better handling */
3126 return X86EMUL_UNHANDLEABLE;
3127 }
3128 return X86EMUL_CONTINUE;
3129}
3130
3131void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3132{
bbd9b64e 3133 u8 opcodes[4];
5fdbf976 3134 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3135 unsigned long rip_linear;
3136
f76c710d 3137 if (!printk_ratelimit())
bbd9b64e
CO		 3138 return;
3139
25be4608
GC		 3140 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3141
77c2002e 3142 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3143
3144 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3145 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3146}
3147EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3148
14af3f3c 3149static struct x86_emulate_ops emulate_ops = {
77c2002e 3150 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3151 .read_emulated = emulator_read_emulated,
3152 .write_emulated = emulator_write_emulated,
3153 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3154};
3155
5fdbf976
MT		 3156static void cache_all_regs(struct kvm_vcpu *vcpu)
3157{
3158 kvm_register_read(vcpu, VCPU_REGS_RAX);
3159 kvm_register_read(vcpu, VCPU_REGS_RSP);
3160 kvm_register_read(vcpu, VCPU_REGS_RIP);
3161 vcpu->arch.regs_dirty = ~0;
3162}
3163
bbd9b64e 3164int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3165 unsigned long cr2,
3166 u16 error_code,
571008da 3167 int emulation_type)
bbd9b64e 3168{
310b5d30 3169 int r, shadow_mask;
571008da 3170 struct decode_cache *c;
851ba692 3171 struct kvm_run *run = vcpu->run;
bbd9b64e 3172
26eef70c 3173 kvm_clear_exception_queue(vcpu);
ad312c7c 3174 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3175 /*
56e82318 3176 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3177 * instead of direct ->regs accesses, can save hundred cycles
3178 * on Intel for instructions that don't read/change RSP, for
3179 * for example.
3180 */
3181 cache_all_regs(vcpu);
bbd9b64e
CO		 3182
3183 vcpu->mmio_is_write = 0;
ad312c7c 3184 vcpu->arch.pio.string = 0;
bbd9b64e 3185
571008da 3186 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3187 int cs_db, cs_l;
3188 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3189
ad312c7c 3190 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3191 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3192 vcpu->arch.emulate_ctxt.mode =
3193 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3194 ? X86EMUL_MODE_REAL : cs_l
3195 ? X86EMUL_MODE_PROT64 : cs_db
3196 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3197
ad312c7c 3198 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3199
0cb5762e
AP		 3200 /* Only allow emulation of specific instructions on #UD
3201 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3202 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3203 if (emulation_type & EMULTYPE_TRAP_UD) {
3204 if (!c->twobyte)
3205 return EMULATE_FAIL;
3206 switch (c->b) {
3207 case 0x01: /* VMMCALL */
3208 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3209 return EMULATE_FAIL;
3210 break;
3211 case 0x34: /* sysenter */
3212 case 0x35: /* sysexit */
3213 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3214 return EMULATE_FAIL;
3215 break;
3216 case 0x05: /* syscall */
3217 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3218 return EMULATE_FAIL;
3219 break;
3220 default:
3221 return EMULATE_FAIL;
3222 }
3223
3224 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3225 return EMULATE_FAIL;
3226 }
571008da 3227
f2b5756b 3228 ++vcpu->stat.insn_emulation;
bbd9b64e 3229 if (r) {
f2b5756b 3230 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3231 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3232 return EMULATE_DONE;
3233 return EMULATE_FAIL;
3234 }
3235 }
3236
ba8afb6b
GN		 3237 if (emulation_type & EMULTYPE_SKIP) {
3238 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3239 return EMULATE_DONE;
3240 }
3241
ad312c7c 3242 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3243 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3244
3245 if (r == 0)
3246 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3247
ad312c7c 3248 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3249 return EMULATE_DO_MMIO;
3250
3251 if ((r || vcpu->mmio_is_write) && run) {
3252 run->exit_reason = KVM_EXIT_MMIO;
3253 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3254 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3255 run->mmio.len = vcpu->mmio_size;
3256 run->mmio.is_write = vcpu->mmio_is_write;
3257 }
3258
3259 if (r) {
3260 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3261 return EMULATE_DONE;
3262 if (!vcpu->mmio_needed) {
3263 kvm_report_emulation_failure(vcpu, "mmio");
3264 return EMULATE_FAIL;
3265 }
3266 return EMULATE_DO_MMIO;
3267 }
3268
91586a3b 3269 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3270
3271 if (vcpu->mmio_is_write) {
3272 vcpu->mmio_needed = 0;
3273 return EMULATE_DO_MMIO;
3274 }
3275
3276 return EMULATE_DONE;
3277}
3278EXPORT_SYMBOL_GPL(emulate_instruction);
3279
de7d789a
CO		 3280static int pio_copy_data(struct kvm_vcpu *vcpu)
3281{
ad312c7c 3282 void *p = vcpu->arch.pio_data;
0f346074 3283 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3284 unsigned bytes;
0f346074 3285 int ret;
de7d789a 3286
ad312c7c
ZX		 3287 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3288 if (vcpu->arch.pio.in)
0f346074 3289 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3290 else
0f346074
IE		 3291 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3292 return ret;
de7d789a
CO		 3293}
3294
3295int complete_pio(struct kvm_vcpu *vcpu)
3296{
ad312c7c 3297 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3298 long delta;
3299 int r;
5fdbf976 3300 unsigned long val;
de7d789a
CO		 3301
3302 if (!io->string) {
5fdbf976
MT		 3303 if (io->in) {
3304 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3305 memcpy(&val, vcpu->arch.pio_data, io->size);
3306 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3307 }
de7d789a
CO		 3308 } else {
3309 if (io->in) {
3310 r = pio_copy_data(vcpu);
5fdbf976 3311 if (r)
de7d789a 3312 return r;
de7d789a
CO		 3313 }
3314
3315 delta = 1;
3316 if (io->rep) {
3317 delta *= io->cur_count;
3318 /*
3319 * The size of the register should really depend on
3320 * current address size.
3321 */
5fdbf976
MT		 3322 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3323 val -= delta;
3324 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3325 }
3326 if (io->down)
3327 delta = -delta;
3328 delta *= io->size;
5fdbf976
MT		 3329 if (io->in) {
3330 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3331 val += delta;
3332 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3333 } else {
3334 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3335 val += delta;
3336 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3337 }
de7d789a
CO		 3338 }
3339
de7d789a
CO		 3340 io->count -= io->cur_count;
3341 io->cur_count = 0;
3342
3343 return 0;
3344}
3345
bda9020e 3346static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3347{
3348 /* TODO: String I/O for in kernel device */
bda9020e 3349 int r;
de7d789a 3350
ad312c7c 3351 if (vcpu->arch.pio.in)
e93f8a0f 3352 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3353 vcpu->arch.pio.size, pd);
de7d789a 3354 else
e93f8a0f
MT		 3355 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3356 vcpu->arch.pio.port, vcpu->arch.pio.size,
3357 pd);
bda9020e 3358 return r;
de7d789a
CO		 3359}
3360
bda9020e 3361static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3362{
ad312c7c
ZX		 3363 struct kvm_pio_request *io = &vcpu->arch.pio;
3364 void *pd = vcpu->arch.pio_data;
bda9020e 3365 int i, r = 0;
de7d789a 3366
de7d789a 3367 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3368 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3369 io->port, io->size, pd)) {
3370 r = -EOPNOTSUPP;
3371 break;
3372 }
de7d789a
CO		 3373 pd += io->size;
3374 }
bda9020e 3375 return r;
de7d789a
CO		 3376}
3377
851ba692 3378int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3379{
5fdbf976 3380 unsigned long val;
de7d789a
CO		 3381
3382 vcpu->run->exit_reason = KVM_EXIT_IO;
3383 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3384 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3385 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3386 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3387 vcpu->run->io.port = vcpu->arch.pio.port = port;
3388 vcpu->arch.pio.in = in;
3389 vcpu->arch.pio.string = 0;
3390 vcpu->arch.pio.down = 0;
ad312c7c 3391 vcpu->arch.pio.rep = 0;
de7d789a 3392
229456fc
MT		 3393 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3394 size, 1);
2714d1d3 3395
5fdbf976
MT		 3396 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3397 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3398
bda9020e 3399 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3400 complete_pio(vcpu);
3401 return 1;
3402 }
3403 return 0;
3404}
3405EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3406
851ba692 3407int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3408 int size, unsigned long count, int down,
3409 gva_t address, int rep, unsigned port)
3410{
3411 unsigned now, in_page;
0f346074 3412 int ret = 0;
de7d789a
CO		 3413
3414 vcpu->run->exit_reason = KVM_EXIT_IO;
3415 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3416 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3417 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3418 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3419 vcpu->run->io.port = vcpu->arch.pio.port = port;
3420 vcpu->arch.pio.in = in;
3421 vcpu->arch.pio.string = 1;
3422 vcpu->arch.pio.down = down;
ad312c7c 3423 vcpu->arch.pio.rep = rep;
de7d789a 3424
229456fc
MT		 3425 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3426 size, count);
2714d1d3 3427
de7d789a
CO		 3428 if (!count) {
3429 kvm_x86_ops->skip_emulated_instruction(vcpu);
3430 return 1;
3431 }
3432
3433 if (!down)
3434 in_page = PAGE_SIZE - offset_in_page(address);
3435 else
3436 in_page = offset_in_page(address) + size;
3437 now = min(count, (unsigned long)in_page / size);
0f346074 3438 if (!now)
de7d789a 3439 now = 1;
de7d789a
CO		 3440 if (down) {
3441 /*
3442 * String I/O in reverse. Yuck. Kill the guest, fix later.
3443 */
3444 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3445 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3446 return 1;
3447 }
3448 vcpu->run->io.count = now;
ad312c7c 3449 vcpu->arch.pio.cur_count = now;
de7d789a 3450
ad312c7c 3451 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3452 kvm_x86_ops->skip_emulated_instruction(vcpu);
3453
0f346074 3454 vcpu->arch.pio.guest_gva = address;
de7d789a 3455
ad312c7c 3456 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3457 /* string PIO write */
3458 ret = pio_copy_data(vcpu);
0f346074
IE		 3459 if (ret == X86EMUL_PROPAGATE_FAULT) {
3460 kvm_inject_gp(vcpu, 0);
3461 return 1;
3462 }
bda9020e 3463 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3464 complete_pio(vcpu);
ad312c7c 3465 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3466 ret = 1;
3467 }
bda9020e
MT		 3468 }
3469 /* no string PIO read support yet */
de7d789a
CO		 3470
3471 return ret;
3472}
3473EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3474
c8076604
GH		 3475static void bounce_off(void *info)
3476{
3477 /* nothing */
3478}
3479
c8076604
GH		 3480static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3481 void *data)
3482{
3483 struct cpufreq_freqs *freq = data;
3484 struct kvm *kvm;
3485 struct kvm_vcpu *vcpu;
3486 int i, send_ipi = 0;
3487
c8076604
GH		 3488 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3489 return 0;
3490 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3491 return 0;
0cca7907 3492 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3493
3494 spin_lock(&kvm_lock);
3495 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3496 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3497 if (vcpu->cpu != freq->cpu)
3498 continue;
3499 if (!kvm_request_guest_time_update(vcpu))
3500 continue;
3501 if (vcpu->cpu != smp_processor_id())
3502 send_ipi++;
3503 }
3504 }
3505 spin_unlock(&kvm_lock);
3506
3507 if (freq->old < freq->new && send_ipi) {
3508 /*
3509 * We upscale the frequency. Must make the guest
3510 * doesn't see old kvmclock values while running with
3511 * the new frequency, otherwise we risk the guest sees
3512 * time go backwards.
3513 *
3514 * In case we update the frequency for another cpu
3515 * (which might be in guest context) send an interrupt
3516 * to kick the cpu out of guest context. Next time
3517 * guest context is entered kvmclock will be updated,
3518 * so the guest will not see stale values.
3519 */
3520 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3521 }
3522 return 0;
3523}
3524
3525static struct notifier_block kvmclock_cpufreq_notifier_block = {
3526 .notifier_call = kvmclock_cpufreq_notifier
3527};
3528
b820cc0c
ZA		 3529static void kvm_timer_init(void)
3530{
3531 int cpu;
3532
b820cc0c 3533 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3534 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3535 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3536 for_each_online_cpu(cpu) {
3537 unsigned long khz = cpufreq_get(cpu);
3538 if (!khz)
3539 khz = tsc_khz;
3540 per_cpu(cpu_tsc_khz, cpu) = khz;
3541 }
0cca7907
ZA		 3542 } else {
3543 for_each_possible_cpu(cpu)
3544 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3545 }
3546}
3547
f8c16bba 3548int kvm_arch_init(void *opaque)
043405e1 3549{
b820cc0c 3550 int r;
f8c16bba
ZX		 3551 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3552
f8c16bba
ZX		 3553 if (kvm_x86_ops) {
3554 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3555 r = -EEXIST;
3556 goto out;
f8c16bba
ZX		 3557 }
3558
3559 if (!ops->cpu_has_kvm_support()) {
3560 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3561 r = -EOPNOTSUPP;
3562 goto out;
f8c16bba
ZX		 3563 }
3564 if (ops->disabled_by_bios()) {
3565 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3566 r = -EOPNOTSUPP;
3567 goto out;
f8c16bba
ZX		 3568 }
3569
97db56ce
AK		 3570 r = kvm_mmu_module_init();
3571 if (r)
3572 goto out;
3573
3574 kvm_init_msr_list();
3575
f8c16bba 3576 kvm_x86_ops = ops;
56c6d28a 3577 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3578 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3579 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3580 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3581
b820cc0c 3582 kvm_timer_init();
c8076604 3583
f8c16bba 3584 return 0;
56c6d28a
ZX		 3585
3586out:
56c6d28a 3587 return r;
043405e1 3588}
8776e519 3589
f8c16bba
ZX		 3590void kvm_arch_exit(void)
3591{
888d256e
JK		 3592 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3593 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3594 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3595 kvm_x86_ops = NULL;
56c6d28a
ZX		 3596 kvm_mmu_module_exit();
3597}
f8c16bba 3598
8776e519
HB		 3599int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3600{
3601 ++vcpu->stat.halt_exits;
3602 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3603 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3604 return 1;
3605 } else {
3606 vcpu->run->exit_reason = KVM_EXIT_HLT;
3607 return 0;
3608 }
3609}
3610EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3611
2f333bcb
MT		 3612static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3613 unsigned long a1)
3614{
3615 if (is_long_mode(vcpu))
3616 return a0;
3617 else
3618 return a0 | ((gpa_t)a1 << 32);
3619}
3620
8776e519
HB		 3621int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3622{
3623 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3624 int r = 1;
8776e519 3625
5fdbf976
MT		 3626 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3627 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3628 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3629 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3630 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3631
229456fc 3632 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3633
8776e519
HB		 3634 if (!is_long_mode(vcpu)) {
3635 nr &= 0xFFFFFFFF;
3636 a0 &= 0xFFFFFFFF;
3637 a1 &= 0xFFFFFFFF;
3638 a2 &= 0xFFFFFFFF;
3639 a3 &= 0xFFFFFFFF;
3640 }
3641
07708c4a
JK		 3642 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3643 ret = -KVM_EPERM;
3644 goto out;
3645 }
3646
8776e519 3647 switch (nr) {
b93463aa
AK		 3648 case KVM_HC_VAPIC_POLL_IRQ:
3649 ret = 0;
3650 break;
2f333bcb
MT		 3651 case KVM_HC_MMU_OP:
3652 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3653 break;
8776e519
HB		 3654 default:
3655 ret = -KVM_ENOSYS;
3656 break;
3657 }
07708c4a 3658out:
5fdbf976 3659 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3660 ++vcpu->stat.hypercalls;
2f333bcb 3661 return r;
8776e519
HB		 3662}
3663EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3664
3665int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3666{
3667 char instruction[3];
3668 int ret = 0;
5fdbf976 3669 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3670
8776e519
HB		 3671
3672 /*
3673 * Blow out the MMU to ensure that no other VCPU has an active mapping
3674 * to ensure that the updated hypercall appears atomically across all
3675 * VCPUs.
3676 */
3677 kvm_mmu_zap_all(vcpu->kvm);
3678
8776e519 3679 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3680 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3681 != X86EMUL_CONTINUE)
3682 ret = -EFAULT;
3683
8776e519
HB		 3684 return ret;
3685}
3686
3687static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3688{
3689 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3690}
3691
3692void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3693{
3694 struct descriptor_table dt = { limit, base };
3695
3696 kvm_x86_ops->set_gdt(vcpu, &dt);
3697}
3698
3699void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3700{
3701 struct descriptor_table dt = { limit, base };
3702
3703 kvm_x86_ops->set_idt(vcpu, &dt);
3704}
3705
3706void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3707 unsigned long *rflags)
3708{
2d3ad1f4 3709 kvm_lmsw(vcpu, msw);
91586a3b 3710 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3711}
3712
3713unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3714{
54e445ca
JR		 3715 unsigned long value;
3716
8776e519
HB		 3717 switch (cr) {
3718 case 0:
4d4ec087 3719 value = kvm_read_cr0(vcpu);
54e445ca 3720 break;
8776e519 3721 case 2:
54e445ca
JR		 3722 value = vcpu->arch.cr2;
3723 break;
8776e519 3724 case 3:
54e445ca
JR		 3725 value = vcpu->arch.cr3;
3726 break;
8776e519 3727 case 4:
fc78f519 3728 value = kvm_read_cr4(vcpu);
54e445ca 3729 break;
152ff9be 3730 case 8:
54e445ca
JR		 3731 value = kvm_get_cr8(vcpu);
3732 break;
8776e519 3733 default:
b8688d51 3734 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3735 return 0;
3736 }
54e445ca
JR		 3737
3738 return value;
8776e519
HB		 3739}
3740
3741void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3742 unsigned long *rflags)
3743{
3744 switch (cr) {
3745 case 0:
4d4ec087 3746 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 3747 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3748 break;
3749 case 2:
ad312c7c 3750 vcpu->arch.cr2 = val;
8776e519
HB		 3751 break;
3752 case 3:
2d3ad1f4 3753 kvm_set_cr3(vcpu, val);
8776e519
HB		 3754 break;
3755 case 4:
fc78f519 3756 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 3757 break;
152ff9be 3758 case 8:
2d3ad1f4 3759 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3760 break;
8776e519 3761 default:
b8688d51 3762 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3763 }
3764}
3765
07716717
DK		 3766static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3767{
ad312c7c
ZX		 3768 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3769 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3770
3771 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3772 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3773 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3774 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3775 if (ej->function == e->function) {
3776 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3777 return j;
3778 }
3779 }
3780 return 0; /* silence gcc, even though control never reaches here */
3781}
3782
3783/* find an entry with matching function, matching index (if needed), and that
3784 * should be read next (if it's stateful) */
3785static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3786 u32 function, u32 index)
3787{
3788 if (e->function != function)
3789 return 0;
3790 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3791 return 0;
3792 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3793 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3794 return 0;
3795 return 1;
3796}
3797
d8017474
AG		 3798struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3799 u32 function, u32 index)
8776e519
HB		 3800{
3801 int i;
d8017474 3802 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3803
ad312c7c 3804 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3805 struct kvm_cpuid_entry2 *e;
3806
ad312c7c 3807 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3808 if (is_matching_cpuid_entry(e, function, index)) {
3809 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3810 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3811 best = e;
3812 break;
3813 }
3814 /*
3815 * Both basic or both extended?
3816 */
3817 if (((e->function ^ function) & 0x80000000) == 0)
3818 if (!best || e->function > best->function)
3819 best = e;
3820 }
d8017474
AG		 3821 return best;
3822}
0e851880 3823EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 3824
82725b20
DE		 3825int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3826{
3827 struct kvm_cpuid_entry2 *best;
3828
3829 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3830 if (best)
3831 return best->eax & 0xff;
3832 return 36;
3833}
3834
d8017474
AG		 3835void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3836{
3837 u32 function, index;
3838 struct kvm_cpuid_entry2 *best;
3839
3840 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3841 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3842 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3843 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3844 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3845 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3846 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3847 if (best) {
5fdbf976
MT		 3848 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3849 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3850 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3851 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3852 }
8776e519 3853 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3854 trace_kvm_cpuid(function,
3855 kvm_register_read(vcpu, VCPU_REGS_RAX),
3856 kvm_register_read(vcpu, VCPU_REGS_RBX),
3857 kvm_register_read(vcpu, VCPU_REGS_RCX),
3858 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3859}
3860EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3861
b6c7a5dc
HB		 3862/*
3863 * Check if userspace requested an interrupt window, and that the
3864 * interrupt window is open.
3865 *
3866 * No need to exit to userspace if we already have an interrupt queued.
3867 */
851ba692 3868static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3869{
8061823a 3870 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3871 vcpu->run->request_interrupt_window &&
5df56646 3872 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3873}
3874
851ba692 3875static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3876{
851ba692
AK		 3877 struct kvm_run *kvm_run = vcpu->run;
3878
91586a3b 3879 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3880 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3881 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3882 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3883 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3884 else
b6c7a5dc 3885 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3886 kvm_arch_interrupt_allowed(vcpu) &&
3887 !kvm_cpu_has_interrupt(vcpu) &&
3888 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3889}
3890
b93463aa
AK		 3891static void vapic_enter(struct kvm_vcpu *vcpu)
3892{
3893 struct kvm_lapic *apic = vcpu->arch.apic;
3894 struct page *page;
3895
3896 if (!apic || !apic->vapic_addr)
3897 return;
3898
3899 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3900
3901 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3902}
3903
3904static void vapic_exit(struct kvm_vcpu *vcpu)
3905{
3906 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 3907 int idx;
b93463aa
AK		 3908
3909 if (!apic || !apic->vapic_addr)
3910 return;
3911
f656ce01 3912 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 3913 kvm_release_page_dirty(apic->vapic_page);
3914 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 3915 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3916}
3917
95ba8273
GN		 3918static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3919{
3920 int max_irr, tpr;
3921
3922 if (!kvm_x86_ops->update_cr8_intercept)
3923 return;
3924
88c808fd
AK		 3925 if (!vcpu->arch.apic)
3926 return;
3927
8db3baa2
GN		 3928 if (!vcpu->arch.apic->vapic_addr)
3929 max_irr = kvm_lapic_find_highest_irr(vcpu);
3930 else
3931 max_irr = -1;
95ba8273
GN		 3932
3933 if (max_irr != -1)
3934 max_irr >>= 4;
3935
3936 tpr = kvm_lapic_get_cr8(vcpu);
3937
3938 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3939}
3940
851ba692 3941static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3942{
3943 /* try to reinject previous events if any */
b59bb7bd
GN		 3944 if (vcpu->arch.exception.pending) {
3945 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3946 vcpu->arch.exception.has_error_code,
3947 vcpu->arch.exception.error_code);
3948 return;
3949 }
3950
95ba8273
GN		 3951 if (vcpu->arch.nmi_injected) {
3952 kvm_x86_ops->set_nmi(vcpu);
3953 return;
3954 }
3955
3956 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3957 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3958 return;
3959 }
3960
3961 /* try to inject new event if pending */
3962 if (vcpu->arch.nmi_pending) {
3963 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3964 vcpu->arch.nmi_pending = false;
3965 vcpu->arch.nmi_injected = true;
3966 kvm_x86_ops->set_nmi(vcpu);
3967 }
3968 } else if (kvm_cpu_has_interrupt(vcpu)) {
3969 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3970 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3971 false);
3972 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3973 }
3974 }
3975}
3976
851ba692 3977static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3978{
3979 int r;
6a8b1d13 3980 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3981 vcpu->run->request_interrupt_window;
b6c7a5dc 3982
2e53d63a
MT		 3983 if (vcpu->requests)
3984 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3985 kvm_mmu_unload(vcpu);
3986
b6c7a5dc
HB		 3987 r = kvm_mmu_reload(vcpu);
3988 if (unlikely(r))
3989 goto out;
3990
2f52d58c
AK		 3991 if (vcpu->requests) {
3992 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3993 __kvm_migrate_timers(vcpu);
c8076604
GH		 3994 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3995 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3996 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3997 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3998 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3999 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4000 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4001 &vcpu->requests)) {
851ba692 4002 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4003 r = 0;
4004 goto out;
4005 }
71c4dfaf 4006 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4007 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4008 r = 0;
4009 goto out;
4010 }
02daab21
AK		 4011 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4012 vcpu->fpu_active = 0;
4013 kvm_x86_ops->fpu_deactivate(vcpu);
4014 }
2f52d58c 4015 }
b93463aa 4016
b6c7a5dc
HB		 4017 preempt_disable();
4018
4019 kvm_x86_ops->prepare_guest_switch(vcpu);
4020 kvm_load_guest_fpu(vcpu);
4021
4022 local_irq_disable();
4023
32f88400
MT		 4024 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4025 smp_mb__after_clear_bit();
4026
d7690175 4027 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4028 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4029 local_irq_enable();
4030 preempt_enable();
4031 r = 1;
4032 goto out;
4033 }
4034
851ba692 4035 inject_pending_event(vcpu);
b6c7a5dc 4036
6a8b1d13
GN		 4037 /* enable NMI/IRQ window open exits if needed */
4038 if (vcpu->arch.nmi_pending)
4039 kvm_x86_ops->enable_nmi_window(vcpu);
4040 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4041 kvm_x86_ops->enable_irq_window(vcpu);
4042
95ba8273 4043 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4044 update_cr8_intercept(vcpu);
4045 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4046 }
b93463aa 4047
f656ce01 4048 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4049
b6c7a5dc
HB		 4050 kvm_guest_enter();
4051
42dbaa5a 4052 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4053 set_debugreg(0, 7);
4054 set_debugreg(vcpu->arch.eff_db[0], 0);
4055 set_debugreg(vcpu->arch.eff_db[1], 1);
4056 set_debugreg(vcpu->arch.eff_db[2], 2);
4057 set_debugreg(vcpu->arch.eff_db[3], 3);
4058 }
b6c7a5dc 4059
229456fc 4060 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4061 kvm_x86_ops->run(vcpu);
b6c7a5dc 4062
24f1e32c
FW		 4063 /*
4064 * If the guest has used debug registers, at least dr7
4065 * will be disabled while returning to the host.
4066 * If we don't have active breakpoints in the host, we don't
4067 * care about the messed up debug address registers. But if
4068 * we have some of them active, restore the old state.
4069 */
59d8eb53 4070 if (hw_breakpoint_active())
24f1e32c 4071 hw_breakpoint_restore();
42dbaa5a 4072
32f88400 4073 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4074 local_irq_enable();
4075
4076 ++vcpu->stat.exits;
4077
4078 /*
4079 * We must have an instruction between local_irq_enable() and
4080 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4081 * the interrupt shadow. The stat.exits increment will do nicely.
4082 * But we need to prevent reordering, hence this barrier():
4083 */
4084 barrier();
4085
4086 kvm_guest_exit();
4087
4088 preempt_enable();
4089
f656ce01 4090 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4091
b6c7a5dc
HB		 4092 /*
4093 * Profile KVM exit RIPs:
4094 */
4095 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4096 unsigned long rip = kvm_rip_read(vcpu);
4097 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4098 }
4099
298101da 4100
b93463aa
AK		 4101 kvm_lapic_sync_from_vapic(vcpu);
4102
851ba692 4103 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4104out:
4105 return r;
4106}
b6c7a5dc 4107
09cec754 4108
851ba692 4109static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4110{
4111 int r;
f656ce01 4112 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4113
4114 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4115 pr_debug("vcpu %d received sipi with vector # %x\n",
4116 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4117 kvm_lapic_reset(vcpu);
5f179287 4118 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4119 if (r)
4120 return r;
4121 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4122 }
4123
f656ce01 4124 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4125 vapic_enter(vcpu);
4126
4127 r = 1;
4128 while (r > 0) {
af2152f5 4129 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4130 r = vcpu_enter_guest(vcpu);
d7690175 4131 else {
f656ce01 4132 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4133 kvm_vcpu_block(vcpu);
f656ce01 4134 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4135 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4136 {
4137 switch(vcpu->arch.mp_state) {
4138 case KVM_MP_STATE_HALTED:
d7690175 4139 vcpu->arch.mp_state =
09cec754
GN		 4140 KVM_MP_STATE_RUNNABLE;
4141 case KVM_MP_STATE_RUNNABLE:
4142 break;
4143 case KVM_MP_STATE_SIPI_RECEIVED:
4144 default:
4145 r = -EINTR;
4146 break;
4147 }
4148 }
d7690175
MT		 4149 }
4150
09cec754
GN		 4151 if (r <= 0)
4152 break;
4153
4154 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4155 if (kvm_cpu_has_pending_timer(vcpu))
4156 kvm_inject_pending_timer_irqs(vcpu);
4157
851ba692 4158 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4159 r = -EINTR;
851ba692 4160 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4161 ++vcpu->stat.request_irq_exits;
4162 }
4163 if (signal_pending(current)) {
4164 r = -EINTR;
851ba692 4165 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4166 ++vcpu->stat.signal_exits;
4167 }
4168 if (need_resched()) {
f656ce01 4169 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4170 kvm_resched(vcpu);
f656ce01 4171 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4172 }
b6c7a5dc
HB		 4173 }
4174
f656ce01 4175 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4176 post_kvm_run_save(vcpu);
b6c7a5dc 4177
b93463aa
AK		 4178 vapic_exit(vcpu);
4179
b6c7a5dc
HB		 4180 return r;
4181}
4182
4183int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4184{
4185 int r;
4186 sigset_t sigsaved;
4187
4188 vcpu_load(vcpu);
4189
ac9f6dc0
AK		 4190 if (vcpu->sigset_active)
4191 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4192
a4535290 4193 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4194 kvm_vcpu_block(vcpu);
d7690175 4195 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4196 r = -EAGAIN;
4197 goto out;
b6c7a5dc
HB		 4198 }
4199
b6c7a5dc
HB		 4200 /* re-sync apic's tpr */
4201 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4202 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4203
ad312c7c 4204 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4205 r = complete_pio(vcpu);
4206 if (r)
4207 goto out;
4208 }
b6c7a5dc
HB		 4209 if (vcpu->mmio_needed) {
4210 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4211 vcpu->mmio_read_completed = 1;
4212 vcpu->mmio_needed = 0;
3200f405 4213
f656ce01 4214 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4215 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4216 EMULTYPE_NO_DECODE);
f656ce01 4217 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4218 if (r == EMULATE_DO_MMIO) {
4219 /*
4220 * Read-modify-write. Back to userspace.
4221 */
4222 r = 0;
4223 goto out;
4224 }
4225 }
5fdbf976
MT		 4226 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4227 kvm_register_write(vcpu, VCPU_REGS_RAX,
4228 kvm_run->hypercall.ret);
b6c7a5dc 4229
851ba692 4230 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4231
4232out:
4233 if (vcpu->sigset_active)
4234 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4235
4236 vcpu_put(vcpu);
4237 return r;
4238}
4239
4240int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4241{
4242 vcpu_load(vcpu);
4243
5fdbf976
MT		 4244 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4245 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4246 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4247 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4248 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4249 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4250 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4251 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4252#ifdef CONFIG_X86_64
5fdbf976
MT		 4253 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4254 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4255 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4256 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4257 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4258 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4259 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4260 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4261#endif
4262
5fdbf976 4263 regs->rip = kvm_rip_read(vcpu);
91586a3b 4264 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4265
4266 vcpu_put(vcpu);
4267
4268 return 0;
4269}
4270
4271int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4272{
4273 vcpu_load(vcpu);
4274
5fdbf976
MT		 4275 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4276 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4277 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4278 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4279 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4280 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4281 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4282 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4283#ifdef CONFIG_X86_64
5fdbf976
MT		 4284 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4285 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4286 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4287 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4288 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4289 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4290 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4291 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4292#endif
4293
5fdbf976 4294 kvm_rip_write(vcpu, regs->rip);
91586a3b 4295 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4296
b4f14abd
JK		 4297 vcpu->arch.exception.pending = false;
4298
b6c7a5dc
HB		 4299 vcpu_put(vcpu);
4300
4301 return 0;
4302}
4303
3e6e0aab
GT		 4304void kvm_get_segment(struct kvm_vcpu *vcpu,
4305 struct kvm_segment *var, int seg)
b6c7a5dc 4306{
14af3f3c 4307 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4308}
4309
4310void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4311{
4312 struct kvm_segment cs;
4313
3e6e0aab 4314 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4315 *db = cs.db;
4316 *l = cs.l;
4317}
4318EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4319
4320int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4321 struct kvm_sregs *sregs)
4322{
4323 struct descriptor_table dt;
b6c7a5dc
HB		 4324
4325 vcpu_load(vcpu);
4326
3e6e0aab
GT		 4327 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4328 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4329 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4330 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4331 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4332 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4333
3e6e0aab
GT		 4334 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4335 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4336
4337 kvm_x86_ops->get_idt(vcpu, &dt);
4338 sregs->idt.limit = dt.limit;
4339 sregs->idt.base = dt.base;
4340 kvm_x86_ops->get_gdt(vcpu, &dt);
4341 sregs->gdt.limit = dt.limit;
4342 sregs->gdt.base = dt.base;
4343
4d4ec087 4344 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4345 sregs->cr2 = vcpu->arch.cr2;
4346 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4347 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4348 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4349 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4350 sregs->apic_base = kvm_get_apic_base(vcpu);
4351
923c61bb 4352 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4353
36752c9b 4354 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4355 set_bit(vcpu->arch.interrupt.nr,
4356 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4357
b6c7a5dc
HB		 4358 vcpu_put(vcpu);
4359
4360 return 0;
4361}
4362
62d9f0db
MT		 4363int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4364 struct kvm_mp_state *mp_state)
4365{
4366 vcpu_load(vcpu);
4367 mp_state->mp_state = vcpu->arch.mp_state;
4368 vcpu_put(vcpu);
4369 return 0;
4370}
4371
4372int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4373 struct kvm_mp_state *mp_state)
4374{
4375 vcpu_load(vcpu);
4376 vcpu->arch.mp_state = mp_state->mp_state;
4377 vcpu_put(vcpu);
4378 return 0;
4379}
4380
3e6e0aab 4381static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4382 struct kvm_segment *var, int seg)
4383{
14af3f3c 4384 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4385}
4386
37817f29
IE		 4387static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4388 struct kvm_segment *kvm_desct)
4389{
46a359e7
AM		 4390 kvm_desct->base = get_desc_base(seg_desc);
4391 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4392 if (seg_desc->g) {
4393 kvm_desct->limit <<= 12;
4394 kvm_desct->limit |= 0xfff;
4395 }
37817f29
IE		 4396 kvm_desct->selector = selector;
4397 kvm_desct->type = seg_desc->type;
4398 kvm_desct->present = seg_desc->p;
4399 kvm_desct->dpl = seg_desc->dpl;
4400 kvm_desct->db = seg_desc->d;
4401 kvm_desct->s = seg_desc->s;
4402 kvm_desct->l = seg_desc->l;
4403 kvm_desct->g = seg_desc->g;
4404 kvm_desct->avl = seg_desc->avl;
4405 if (!selector)
4406 kvm_desct->unusable = 1;
4407 else
4408 kvm_desct->unusable = 0;
4409 kvm_desct->padding = 0;
4410}
4411
b8222ad2
AS		 4412static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4413 u16 selector,
4414 struct descriptor_table *dtable)
37817f29
IE		 4415{
4416 if (selector & 1 << 2) {
4417 struct kvm_segment kvm_seg;
4418
3e6e0aab 4419 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4420
4421 if (kvm_seg.unusable)
4422 dtable->limit = 0;
4423 else
4424 dtable->limit = kvm_seg.limit;
4425 dtable->base = kvm_seg.base;
4426 }
4427 else
4428 kvm_x86_ops->get_gdt(vcpu, dtable);
4429}
4430
4431/* allowed just for 8 bytes segments */
4432static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4433 struct desc_struct *seg_desc)
4434{
4435 struct descriptor_table dtable;
4436 u16 index = selector >> 3;
4437
b8222ad2 4438 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4439
4440 if (dtable.limit < index * 8 + 7) {
4441 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4442 return 1;
4443 }
d9048d32 4444 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4445}
4446
4447/* allowed just for 8 bytes segments */
4448static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4449 struct desc_struct *seg_desc)
4450{
4451 struct descriptor_table dtable;
4452 u16 index = selector >> 3;
4453
b8222ad2 4454 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4455
4456 if (dtable.limit < index * 8 + 7)
4457 return 1;
d9048d32 4458 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4459}
4460
abb39119 4461static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4462 struct desc_struct *seg_desc)
4463{
46a359e7 4464 u32 base_addr = get_desc_base(seg_desc);
37817f29 4465
98899aa0 4466 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4467}
4468
37817f29
IE		 4469static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4470{
4471 struct kvm_segment kvm_seg;
4472
3e6e0aab 4473 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4474 return kvm_seg.selector;
4475}
4476
4477static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4478 u16 selector,
4479 struct kvm_segment *kvm_seg)
4480{
4481 struct desc_struct seg_desc;
4482
4483 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4484 return 1;
4485 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4486 return 0;
4487}
4488
2259e3a7 4489static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4490{
4491 struct kvm_segment segvar = {
4492 .base = selector << 4,
4493 .limit = 0xffff,
4494 .selector = selector,
4495 .type = 3,
4496 .present = 1,
4497 .dpl = 3,
4498 .db = 0,
4499 .s = 1,
4500 .l = 0,
4501 .g = 0,
4502 .avl = 0,
4503 .unusable = 0,
4504 };
4505 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4506 return 0;
4507}
4508
c0c7c04b
AL		 4509static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4510{
4511 return (seg != VCPU_SREG_LDTR) &&
4512 (seg != VCPU_SREG_TR) &&
91586a3b 4513 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4514}
4515
cb84b55f
MT		 4516static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg,
4517 u16 selector)
4518{
4519 /* NULL selector is not valid for CS and SS */
4520 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4521 if (!selector)
4522 kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3);
4523}
4524
3e6e0aab
GT		 4525int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4526 int type_bits, int seg)
37817f29
IE		 4527{
4528 struct kvm_segment kvm_seg;
4529
4d4ec087 4530 if (is_vm86_segment(vcpu, seg) || !(kvm_read_cr0_bits(vcpu, X86_CR0_PE)))
f4bbd9aa 4531 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4532 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4533 return 1;
cb84b55f
MT		 4534
4535 kvm_check_segment_descriptor(vcpu, seg, selector);
37817f29
IE		 4536 kvm_seg.type |= type_bits;
4537
4538 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4539 seg != VCPU_SREG_LDTR)
4540 if (!kvm_seg.s)
4541 kvm_seg.unusable = 1;
4542
3e6e0aab 4543 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4544 return 0;
4545}
4546
4547static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4548 struct tss_segment_32 *tss)
4549{
4550 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4551 tss->eip = kvm_rip_read(vcpu);
91586a3b 4552 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4553 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4554 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4555 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4556 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4557 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4558 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4559 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4560 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4561 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4562 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4563 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4564 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4565 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4566 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4567 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4568}
4569
4570static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4571 struct tss_segment_32 *tss)
4572{
4573 kvm_set_cr3(vcpu, tss->cr3);
4574
5fdbf976 4575 kvm_rip_write(vcpu, tss->eip);
91586a3b 4576 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4577
5fdbf976
MT		 4578 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4579 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4580 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4581 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4582 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4583 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4584 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4585 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4586
3e6e0aab 4587 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4588 return 1;
4589
3e6e0aab 4590 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4591 return 1;
4592
3e6e0aab 4593 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4594 return 1;
4595
3e6e0aab 4596 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4597 return 1;
4598
3e6e0aab 4599 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4600 return 1;
4601
3e6e0aab 4602 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4603 return 1;
4604
3e6e0aab 4605 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4606 return 1;
4607 return 0;
4608}
4609
4610static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4611 struct tss_segment_16 *tss)
4612{
5fdbf976 4613 tss->ip = kvm_rip_read(vcpu);
91586a3b 4614 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4615 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4616 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4617 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4618 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4619 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4620 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4621 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4622 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4623
4624 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4625 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4626 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4627 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4628 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4629}
4630
4631static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4632 struct tss_segment_16 *tss)
4633{
5fdbf976 4634 kvm_rip_write(vcpu, tss->ip);
91586a3b 4635 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4636 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4637 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4638 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4639 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4640 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4641 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4642 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4643 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4644
3e6e0aab 4645 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4646 return 1;
4647
3e6e0aab 4648 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4649 return 1;
4650
3e6e0aab 4651 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4652 return 1;
4653
3e6e0aab 4654 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4655 return 1;
4656
3e6e0aab 4657 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4658 return 1;
4659 return 0;
4660}
4661
8b2cf73c 4662static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4663 u16 old_tss_sel, u32 old_tss_base,
4664 struct desc_struct *nseg_desc)
37817f29
IE		 4665{
4666 struct tss_segment_16 tss_segment_16;
4667 int ret = 0;
4668
34198bf8
MT		 4669 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4670 sizeof tss_segment_16))
37817f29
IE		 4671 goto out;
4672
4673 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4674
34198bf8
MT		 4675 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4676 sizeof tss_segment_16))
37817f29 4677 goto out;
34198bf8
MT		 4678
4679 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4680 &tss_segment_16, sizeof tss_segment_16))
4681 goto out;
4682
b237ac37
GN		 4683 if (old_tss_sel != 0xffff) {
4684 tss_segment_16.prev_task_link = old_tss_sel;
4685
4686 if (kvm_write_guest(vcpu->kvm,
4687 get_tss_base_addr(vcpu, nseg_desc),
4688 &tss_segment_16.prev_task_link,
4689 sizeof tss_segment_16.prev_task_link))
4690 goto out;
4691 }
4692
37817f29
IE		 4693 if (load_state_from_tss16(vcpu, &tss_segment_16))
4694 goto out;
4695
4696 ret = 1;
4697out:
4698 return ret;
4699}
4700
8b2cf73c 4701static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4702 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4703 struct desc_struct *nseg_desc)
4704{
4705 struct tss_segment_32 tss_segment_32;
4706 int ret = 0;
4707
34198bf8
MT		 4708 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4709 sizeof tss_segment_32))
37817f29
IE		 4710 goto out;
4711
4712 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4713
34198bf8
MT		 4714 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4715 sizeof tss_segment_32))
4716 goto out;
4717
4718 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4719 &tss_segment_32, sizeof tss_segment_32))
37817f29 4720 goto out;
34198bf8 4721
b237ac37
GN		 4722 if (old_tss_sel != 0xffff) {
4723 tss_segment_32.prev_task_link = old_tss_sel;
4724
4725 if (kvm_write_guest(vcpu->kvm,
4726 get_tss_base_addr(vcpu, nseg_desc),
4727 &tss_segment_32.prev_task_link,
4728 sizeof tss_segment_32.prev_task_link))
4729 goto out;
4730 }
4731
37817f29
IE		 4732 if (load_state_from_tss32(vcpu, &tss_segment_32))
4733 goto out;
4734
4735 ret = 1;
4736out:
4737 return ret;
4738}
4739
4740int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4741{
4742 struct kvm_segment tr_seg;
4743 struct desc_struct cseg_desc;
4744 struct desc_struct nseg_desc;
4745 int ret = 0;
34198bf8
MT		 4746 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4747 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4748
34198bf8 4749 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4750
34198bf8
MT		 4751 /* FIXME: Handle errors. Failure to read either TSS or their
4752 * descriptors should generate a pagefault.
4753 */
37817f29
IE		 4754 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4755 goto out;
4756
34198bf8 4757 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4758 goto out;
4759
37817f29
IE		 4760 if (reason != TASK_SWITCH_IRET) {
4761 int cpl;
4762
4763 cpl = kvm_x86_ops->get_cpl(vcpu);
4764 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4765 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4766 return 1;
4767 }
4768 }
4769
46a359e7 4770 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4771 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4772 return 1;
4773 }
4774
4775 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4776 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4777 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4778 }
4779
4780 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4781 u32 eflags = kvm_get_rflags(vcpu);
4782 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4783 }
4784
b237ac37
GN		 4785 /* set back link to prev task only if NT bit is set in eflags
4786 note that old_tss_sel is not used afetr this point */
4787 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4788 old_tss_sel = 0xffff;
4789
37817f29 4790 if (nseg_desc.type & 8)
b237ac37
GN		 4791 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4792 old_tss_base, &nseg_desc);
37817f29 4793 else
b237ac37
GN		 4794 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4795 old_tss_base, &nseg_desc);
37817f29
IE		 4796
4797 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4798 u32 eflags = kvm_get_rflags(vcpu);
4799 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4800 }
4801
4802 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4803 nseg_desc.type |= (1 << 1);
37817f29
IE		 4804 save_guest_segment_descriptor(vcpu, tss_selector,
4805 &nseg_desc);
4806 }
4807
4d4ec087 4808 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 4809 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4810 tr_seg.type = 11;
3e6e0aab 4811 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4812out:
37817f29
IE		 4813 return ret;
4814}
4815EXPORT_SYMBOL_GPL(kvm_task_switch);
4816
b6c7a5dc
HB		 4817int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4818 struct kvm_sregs *sregs)
4819{
4820 int mmu_reset_needed = 0;
923c61bb 4821 int pending_vec, max_bits;
b6c7a5dc
HB		 4822 struct descriptor_table dt;
4823
4824 vcpu_load(vcpu);
4825
4826 dt.limit = sregs->idt.limit;
4827 dt.base = sregs->idt.base;
4828 kvm_x86_ops->set_idt(vcpu, &dt);
4829 dt.limit = sregs->gdt.limit;
4830 dt.base = sregs->gdt.base;
4831 kvm_x86_ops->set_gdt(vcpu, &dt);
4832
ad312c7c
ZX		 4833 vcpu->arch.cr2 = sregs->cr2;
4834 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4835 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4836
2d3ad1f4 4837 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4838
ad312c7c 4839 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4840 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4841 kvm_set_apic_base(vcpu, sregs->apic_base);
4842
4d4ec087 4843 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4844 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4845 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4846
fc78f519 4847 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4848 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4849 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4850 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4851 mmu_reset_needed = 1;
4852 }
b6c7a5dc
HB		 4853
4854 if (mmu_reset_needed)
4855 kvm_mmu_reset_context(vcpu);
4856
923c61bb
GN		 4857 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4858 pending_vec = find_first_bit(
4859 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4860 if (pending_vec < max_bits) {
66fd3f7f 4861 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4862 pr_debug("Set back pending irq %d\n", pending_vec);
4863 if (irqchip_in_kernel(vcpu->kvm))
4864 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4865 }
4866
3e6e0aab
GT		 4867 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4868 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4869 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4870 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4871 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4872 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4873
3e6e0aab
GT		 4874 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4875 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4876
5f0269f5
ME		 4877 update_cr8_intercept(vcpu);
4878
9c3e4aab 4879 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4880 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4881 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4d4ec087 4882 !(kvm_read_cr0_bits(vcpu, X86_CR0_PE)))
9c3e4aab
MT		 4883 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4884
b6c7a5dc
HB		 4885 vcpu_put(vcpu);
4886
4887 return 0;
4888}
4889
d0bfb940
JK		 4890int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4891 struct kvm_guest_debug *dbg)
b6c7a5dc 4892{
355be0b9 4893 unsigned long rflags;
ae675ef0 4894 int i, r;
b6c7a5dc
HB		 4895
4896 vcpu_load(vcpu);
4897
4f926bf2
JK		 4898 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4899 r = -EBUSY;
4900 if (vcpu->arch.exception.pending)
4901 goto unlock_out;
4902 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4903 kvm_queue_exception(vcpu, DB_VECTOR);
4904 else
4905 kvm_queue_exception(vcpu, BP_VECTOR);
4906 }
4907
91586a3b
JK		 4908 /*
4909 * Read rflags as long as potentially injected trace flags are still
4910 * filtered out.
4911 */
4912 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4913
4914 vcpu->guest_debug = dbg->control;
4915 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4916 vcpu->guest_debug = 0;
4917
4918 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4919 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4920 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4921 vcpu->arch.switch_db_regs =
4922 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4923 } else {
4924 for (i = 0; i < KVM_NR_DB_REGS; i++)
4925 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4926 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4927 }
4928
94fe45da
JK		 4929 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4930 vcpu->arch.singlestep_cs =
4931 get_segment_selector(vcpu, VCPU_SREG_CS);
4932 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4933 }
4934
91586a3b
JK		 4935 /*
4936 * Trigger an rflags update that will inject or remove the trace
4937 * flags.
4938 */
4939 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4940
355be0b9 4941 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4942
4f926bf2 4943 r = 0;
d0bfb940 4944
4f926bf2 4945unlock_out:
b6c7a5dc
HB		 4946 vcpu_put(vcpu);
4947
4948 return r;
4949}
4950
d0752060
HB		 4951/*
4952 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4953 * we have asm/x86/processor.h
4954 */
4955struct fxsave {
4956 u16 cwd;
4957 u16 swd;
4958 u16 twd;
4959 u16 fop;
4960 u64 rip;
4961 u64 rdp;
4962 u32 mxcsr;
4963 u32 mxcsr_mask;
4964 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4965#ifdef CONFIG_X86_64
4966 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4967#else
4968 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4969#endif
4970};
4971
8b006791
ZX		 4972/*
4973 * Translate a guest virtual address to a guest physical address.
4974 */
4975int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4976 struct kvm_translation *tr)
4977{
4978 unsigned long vaddr = tr->linear_address;
4979 gpa_t gpa;
f656ce01 4980 int idx;
8b006791
ZX		 4981
4982 vcpu_load(vcpu);
f656ce01 4983 idx = srcu_read_lock(&vcpu->kvm->srcu);
ad312c7c 4984 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
f656ce01 4985 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 4986 tr->physical_address = gpa;
4987 tr->valid = gpa != UNMAPPED_GVA;
4988 tr->writeable = 1;
4989 tr->usermode = 0;
8b006791
ZX		 4990 vcpu_put(vcpu);
4991
4992 return 0;
4993}
4994
d0752060
HB		 4995int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4996{
ad312c7c 4997 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4998
4999 vcpu_load(vcpu);
5000
5001 memcpy(fpu->fpr, fxsave->st_space, 128);
5002 fpu->fcw = fxsave->cwd;
5003 fpu->fsw = fxsave->swd;
5004 fpu->ftwx = fxsave->twd;
5005 fpu->last_opcode = fxsave->fop;
5006 fpu->last_ip = fxsave->rip;
5007 fpu->last_dp = fxsave->rdp;
5008 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5009
5010 vcpu_put(vcpu);
5011
5012 return 0;
5013}
5014
5015int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5016{
ad312c7c 5017 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5018
5019 vcpu_load(vcpu);
5020
5021 memcpy(fxsave->st_space, fpu->fpr, 128);
5022 fxsave->cwd = fpu->fcw;
5023 fxsave->swd = fpu->fsw;
5024 fxsave->twd = fpu->ftwx;
5025 fxsave->fop = fpu->last_opcode;
5026 fxsave->rip = fpu->last_ip;
5027 fxsave->rdp = fpu->last_dp;
5028 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5029
5030 vcpu_put(vcpu);
5031
5032 return 0;
5033}
5034
5035void fx_init(struct kvm_vcpu *vcpu)
5036{
5037 unsigned after_mxcsr_mask;
5038
bc1a34f1
AA		 5039 /*
5040 * Touch the fpu the first time in non atomic context as if
5041 * this is the first fpu instruction the exception handler
5042 * will fire before the instruction returns and it'll have to
5043 * allocate ram with GFP_KERNEL.
5044 */
5045 if (!used_math())
d6e88aec 5046 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5047
d0752060
HB		 5048 /* Initialize guest FPU by resetting ours and saving into guest's */
5049 preempt_disable();
d6e88aec
AK		 5050 kvm_fx_save(&vcpu->arch.host_fx_image);
5051 kvm_fx_finit();
5052 kvm_fx_save(&vcpu->arch.guest_fx_image);
5053 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5054 preempt_enable();
5055
ad312c7c 5056 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5057 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5058 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5059 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5060 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5061}
5062EXPORT_SYMBOL_GPL(fx_init);
5063
5064void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5065{
5066 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
5067 return;
5068
5069 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5070 kvm_fx_save(&vcpu->arch.host_fx_image);
5071 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 5072}
5073EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
5074
5075void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5076{
5077 if (!vcpu->guest_fpu_loaded)
5078 return;
5079
5080 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5081 kvm_fx_save(&vcpu->arch.guest_fx_image);
5082 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5083 ++vcpu->stat.fpu_reload;
02daab21 5084 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
d0752060
HB		 5085}
5086EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 5087
5088void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5089{
7f1ea208
JR		 5090 if (vcpu->arch.time_page) {
5091 kvm_release_page_dirty(vcpu->arch.time_page);
5092 vcpu->arch.time_page = NULL;
5093 }
5094
e9b11c17
ZX		 5095 kvm_x86_ops->vcpu_free(vcpu);
5096}
5097
5098struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5099 unsigned int id)
5100{
26e5215f
AK		 5101 return kvm_x86_ops->vcpu_create(kvm, id);
5102}
e9b11c17 5103
26e5215f
AK		 5104int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5105{
5106 int r;
e9b11c17
ZX		 5107
5108 /* We do fxsave: this must be aligned. */
ad312c7c 5109 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5110
0bed3b56 5111 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5112 vcpu_load(vcpu);
5113 r = kvm_arch_vcpu_reset(vcpu);
5114 if (r == 0)
5115 r = kvm_mmu_setup(vcpu);
5116 vcpu_put(vcpu);
5117 if (r < 0)
5118 goto free_vcpu;
5119
26e5215f 5120 return 0;
e9b11c17
ZX		 5121free_vcpu:
5122 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5123 return r;
e9b11c17
ZX		 5124}
5125
d40ccc62 5126void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5127{
5128 vcpu_load(vcpu);
5129 kvm_mmu_unload(vcpu);
5130 vcpu_put(vcpu);
5131
5132 kvm_x86_ops->vcpu_free(vcpu);
5133}
5134
5135int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5136{
448fa4a9
JK		 5137 vcpu->arch.nmi_pending = false;
5138 vcpu->arch.nmi_injected = false;
5139
42dbaa5a
JK		 5140 vcpu->arch.switch_db_regs = 0;
5141 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5142 vcpu->arch.dr6 = DR6_FIXED_1;
5143 vcpu->arch.dr7 = DR7_FIXED_1;
5144
e9b11c17
ZX		 5145 return kvm_x86_ops->vcpu_reset(vcpu);
5146}
5147
10474ae8 5148int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5149{
0cca7907
ZA		 5150 /*
5151 * Since this may be called from a hotplug notifcation,
5152 * we can't get the CPU frequency directly.
5153 */
5154 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5155 int cpu = raw_smp_processor_id();
5156 per_cpu(cpu_tsc_khz, cpu) = 0;
5157 }
18863bdd
AK		 5158
5159 kvm_shared_msr_cpu_online();
5160
10474ae8 5161 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5162}
5163
5164void kvm_arch_hardware_disable(void *garbage)
5165{
5166 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5167 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5168}
5169
5170int kvm_arch_hardware_setup(void)
5171{
5172 return kvm_x86_ops->hardware_setup();
5173}
5174
5175void kvm_arch_hardware_unsetup(void)
5176{
5177 kvm_x86_ops->hardware_unsetup();
5178}
5179
5180void kvm_arch_check_processor_compat(void *rtn)
5181{
5182 kvm_x86_ops->check_processor_compatibility(rtn);
5183}
5184
5185int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5186{
5187 struct page *page;
5188 struct kvm *kvm;
5189 int r;
5190
5191 BUG_ON(vcpu->kvm == NULL);
5192 kvm = vcpu->kvm;
5193
ad312c7c 5194 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5195 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5196 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5197 else
a4535290 5198 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5199
5200 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5201 if (!page) {
5202 r = -ENOMEM;
5203 goto fail;
5204 }
ad312c7c 5205 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5206
5207 r = kvm_mmu_create(vcpu);
5208 if (r < 0)
5209 goto fail_free_pio_data;
5210
5211 if (irqchip_in_kernel(kvm)) {
5212 r = kvm_create_lapic(vcpu);
5213 if (r < 0)
5214 goto fail_mmu_destroy;
5215 }
5216
890ca9ae
HY		 5217 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5218 GFP_KERNEL);
5219 if (!vcpu->arch.mce_banks) {
5220 r = -ENOMEM;
443c39bc 5221 goto fail_free_lapic;
890ca9ae
HY		 5222 }
5223 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5224
e9b11c17 5225 return 0;
443c39bc
WY		 5226fail_free_lapic:
5227 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5228fail_mmu_destroy:
5229 kvm_mmu_destroy(vcpu);
5230fail_free_pio_data:
ad312c7c 5231 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5232fail:
5233 return r;
5234}
5235
5236void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5237{
f656ce01
MT		 5238 int idx;
5239
36cb93fd 5240 kfree(vcpu->arch.mce_banks);
e9b11c17 5241 kvm_free_lapic(vcpu);
f656ce01 5242 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5243 kvm_mmu_destroy(vcpu);
f656ce01 5244 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5245 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5246}
d19a9cd2
ZX		 5247
5248struct kvm *kvm_arch_create_vm(void)
5249{
5250 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5251
5252 if (!kvm)
5253 return ERR_PTR(-ENOMEM);
5254
fef9cce0
MT		 5255 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5256 if (!kvm->arch.aliases) {
5257 kfree(kvm);
5258 return ERR_PTR(-ENOMEM);
5259 }
5260
f05e70ac 5261 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5262 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5263
5550af4d
SY		 5264 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5265 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5266
53f658b3
MT		 5267 rdtscll(kvm->arch.vm_init_tsc);
5268
d19a9cd2
ZX		 5269 return kvm;
5270}
5271
5272static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5273{
5274 vcpu_load(vcpu);
5275 kvm_mmu_unload(vcpu);
5276 vcpu_put(vcpu);
5277}
5278
5279static void kvm_free_vcpus(struct kvm *kvm)
5280{
5281 unsigned int i;
988a2cae 5282 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5283
5284 /*
5285 * Unpin any mmu pages first.
5286 */
988a2cae
GN		 5287 kvm_for_each_vcpu(i, vcpu, kvm)
5288 kvm_unload_vcpu_mmu(vcpu);
5289 kvm_for_each_vcpu(i, vcpu, kvm)
5290 kvm_arch_vcpu_free(vcpu);
5291
5292 mutex_lock(&kvm->lock);
5293 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5294 kvm->vcpus[i] = NULL;
d19a9cd2 5295
988a2cae
GN		 5296 atomic_set(&kvm->online_vcpus, 0);
5297 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5298}
5299
ad8ba2cd
SY		 5300void kvm_arch_sync_events(struct kvm *kvm)
5301{
ba4cef31 5302 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5303}
5304
d19a9cd2
ZX		 5305void kvm_arch_destroy_vm(struct kvm *kvm)
5306{
6eb55818 5307 kvm_iommu_unmap_guest(kvm);
7837699f 5308 kvm_free_pit(kvm);
d7deeeb0
ZX		 5309 kfree(kvm->arch.vpic);
5310 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5311 kvm_free_vcpus(kvm);
5312 kvm_free_physmem(kvm);
3d45830c
AK		 5313 if (kvm->arch.apic_access_page)
5314 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5315 if (kvm->arch.ept_identity_pagetable)
5316 put_page(kvm->arch.ept_identity_pagetable);
fef9cce0 5317 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5318 kfree(kvm);
5319}
0de10343 5320
f7784b8e
MT		 5321int kvm_arch_prepare_memory_region(struct kvm *kvm,
5322 struct kvm_memory_slot *memslot,
0de10343 5323 struct kvm_memory_slot old,
f7784b8e 5324 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5325 int user_alloc)
5326{
f7784b8e 5327 int npages = memslot->npages;
0de10343
ZX		 5328
5329 /*To keep backward compatibility with older userspace,
5330 *x86 needs to hanlde !user_alloc case.
5331 */
5332 if (!user_alloc) {
5333 if (npages && !old.rmap) {
604b38ac
AA		 5334 unsigned long userspace_addr;
5335
72dc67a6 5336 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5337 userspace_addr = do_mmap(NULL, 0,
5338 npages * PAGE_SIZE,
5339 PROT_READ | PROT_WRITE,
acee3c04 5340 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5341 0);
72dc67a6 5342 up_write(&current->mm->mmap_sem);
0de10343 5343
604b38ac
AA		 5344 if (IS_ERR((void *)userspace_addr))
5345 return PTR_ERR((void *)userspace_addr);
5346
604b38ac 5347 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5348 }
5349 }
5350
f7784b8e
MT		 5351
5352 return 0;
5353}
5354
5355void kvm_arch_commit_memory_region(struct kvm *kvm,
5356 struct kvm_userspace_memory_region *mem,
5357 struct kvm_memory_slot old,
5358 int user_alloc)
5359{
5360
5361 int npages = mem->memory_size >> PAGE_SHIFT;
5362
5363 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5364 int ret;
5365
5366 down_write(&current->mm->mmap_sem);
5367 ret = do_munmap(current->mm, old.userspace_addr,
5368 old.npages * PAGE_SIZE);
5369 up_write(&current->mm->mmap_sem);
5370 if (ret < 0)
5371 printk(KERN_WARNING
5372 "kvm_vm_ioctl_set_memory_region: "
5373 "failed to munmap memory\n");
5374 }
5375
7c8a83b7 5376 spin_lock(&kvm->mmu_lock);
f05e70ac 5377 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5378 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5379 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5380 }
5381
5382 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5383 spin_unlock(&kvm->mmu_lock);
0de10343 5384}
1d737c8a 5385
34d4cb8f
MT		 5386void kvm_arch_flush_shadow(struct kvm *kvm)
5387{
5388 kvm_mmu_zap_all(kvm);
8986ecc0 5389 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5390}
5391
1d737c8a
ZX		 5392int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5393{
a4535290 5394 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5395 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5396 || vcpu->arch.nmi_pending ||
5397 (kvm_arch_interrupt_allowed(vcpu) &&
5398 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5399}
5736199a 5400
5736199a
ZX		 5401void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5402{
32f88400
MT		 5403 int me;
5404 int cpu = vcpu->cpu;
5736199a
ZX		 5405
5406 if (waitqueue_active(&vcpu->wq)) {
5407 wake_up_interruptible(&vcpu->wq);
5408 ++vcpu->stat.halt_wakeup;
5409 }
32f88400
MT		 5410
5411 me = get_cpu();
5412 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5413 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5414 smp_send_reschedule(cpu);
e9571ed5 5415 put_cpu();
5736199a 5416}
78646121
GN		 5417
5418int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5419{
5420 return kvm_x86_ops->interrupt_allowed(vcpu);
5421}
229456fc 5422
94fe45da
JK		 5423unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5424{
5425 unsigned long rflags;
5426
5427 rflags = kvm_x86_ops->get_rflags(vcpu);
5428 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5429 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5430 return rflags;
5431}
5432EXPORT_SYMBOL_GPL(kvm_get_rflags);
5433
5434void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5435{
5436 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5437 vcpu->arch.singlestep_cs ==
5438 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5439 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5440 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5441 kvm_x86_ops->set_rflags(vcpu, rflags);
5442}
5443EXPORT_SYMBOL_GPL(kvm_set_rflags);
5444
229456fc
MT		 5445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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