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KVM: remove the vmap usage
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
0bed3b56 43#include <asm/mtrr.h>
043405e1 44
313a3dc7 45#define MAX_IO_MSRS 256
a03490ed
CO		 46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50#define CR4_RESERVED_BITS \
51 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
52 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
53 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
54 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
55
56#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 57/* EFER defaults:
58 * - enable syscall per default because its emulated by KVM
59 * - enable LME and LMA per default on 64 bit KVM
60 */
61#ifdef CONFIG_X86_64
62static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
63#else
64static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
65#endif
313a3dc7 66
ba1389b7
AK		 67#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
68#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 69
674eea0f
AK		 70static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
71 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 72struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
73 u32 function, u32 index);
674eea0f 74
97896d04 75struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 76EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 77
417bc304 78struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 79 { "pf_fixed", VCPU_STAT(pf_fixed) },
80 { "pf_guest", VCPU_STAT(pf_guest) },
81 { "tlb_flush", VCPU_STAT(tlb_flush) },
82 { "invlpg", VCPU_STAT(invlpg) },
83 { "exits", VCPU_STAT(exits) },
84 { "io_exits", VCPU_STAT(io_exits) },
85 { "mmio_exits", VCPU_STAT(mmio_exits) },
86 { "signal_exits", VCPU_STAT(signal_exits) },
87 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 88 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 89 { "halt_exits", VCPU_STAT(halt_exits) },
90 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 91 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 92 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 93 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 94 { "irq_exits", VCPU_STAT(irq_exits) },
95 { "host_state_reload", VCPU_STAT(host_state_reload) },
96 { "efer_reload", VCPU_STAT(efer_reload) },
97 { "fpu_reload", VCPU_STAT(fpu_reload) },
98 { "insn_emulation", VCPU_STAT(insn_emulation) },
99 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 100 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 101 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 102 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
103 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
104 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
105 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
106 { "mmu_flooded", VM_STAT(mmu_flooded) },
107 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 108 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 109 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 110 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 111 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 112 { "largepages", VM_STAT(lpages) },
417bc304
HB		 113 { NULL }
114};
115
5fb76f9b
CO		 116unsigned long segment_base(u16 selector)
117{
118 struct descriptor_table gdt;
a5f61300 119 struct desc_struct *d;
5fb76f9b
CO		 120 unsigned long table_base;
121 unsigned long v;
122
123 if (selector == 0)
124 return 0;
125
126 asm("sgdt %0" : "=m"(gdt));
127 table_base = gdt.base;
128
129 if (selector & 4) { /* from ldt */
130 u16 ldt_selector;
131
132 asm("sldt %0" : "=g"(ldt_selector));
133 table_base = segment_base(ldt_selector);
134 }
a5f61300
AK		 135 d = (struct desc_struct *)(table_base + (selector & ~7));
136 v = d->base0 | ((unsigned long)d->base1 << 16) |
137 ((unsigned long)d->base2 << 24);
5fb76f9b 138#ifdef CONFIG_X86_64
a5f61300
AK		 139 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
140 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 141#endif
142 return v;
143}
144EXPORT_SYMBOL_GPL(segment_base);
145
6866b83e
CO		 146u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
147{
148 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 149 return vcpu->arch.apic_base;
6866b83e 150 else
ad312c7c 151 return vcpu->arch.apic_base;
6866b83e
CO		 152}
153EXPORT_SYMBOL_GPL(kvm_get_apic_base);
154
155void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
156{
157 /* TODO: reserve bits check */
158 if (irqchip_in_kernel(vcpu->kvm))
159 kvm_lapic_set_base(vcpu, data);
160 else
ad312c7c 161 vcpu->arch.apic_base = data;
6866b83e
CO		 162}
163EXPORT_SYMBOL_GPL(kvm_set_apic_base);
164
298101da
AK		 165void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
166{
ad312c7c
ZX		 167 WARN_ON(vcpu->arch.exception.pending);
168 vcpu->arch.exception.pending = true;
169 vcpu->arch.exception.has_error_code = false;
170 vcpu->arch.exception.nr = nr;
298101da
AK		 171}
172EXPORT_SYMBOL_GPL(kvm_queue_exception);
173
c3c91fee
AK		 174void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
175 u32 error_code)
176{
177 ++vcpu->stat.pf_guest;
d8017474 178
71c4dfaf
JR		 179 if (vcpu->arch.exception.pending) {
180 if (vcpu->arch.exception.nr == PF_VECTOR) {
181 printk(KERN_DEBUG "kvm: inject_page_fault:"
182 " double fault 0x%lx\n", addr);
183 vcpu->arch.exception.nr = DF_VECTOR;
184 vcpu->arch.exception.error_code = 0;
185 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
186 /* triple fault -> shutdown */
187 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
188 }
c3c91fee
AK		 189 return;
190 }
ad312c7c 191 vcpu->arch.cr2 = addr;
c3c91fee
AK		 192 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
193}
194
3419ffc8
SY		 195void kvm_inject_nmi(struct kvm_vcpu *vcpu)
196{
197 vcpu->arch.nmi_pending = 1;
198}
199EXPORT_SYMBOL_GPL(kvm_inject_nmi);
200
298101da
AK		 201void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
202{
ad312c7c
ZX		 203 WARN_ON(vcpu->arch.exception.pending);
204 vcpu->arch.exception.pending = true;
205 vcpu->arch.exception.has_error_code = true;
206 vcpu->arch.exception.nr = nr;
207 vcpu->arch.exception.error_code = error_code;
298101da
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
210
211static void __queue_exception(struct kvm_vcpu *vcpu)
212{
ad312c7c
ZX		 213 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
214 vcpu->arch.exception.has_error_code,
215 vcpu->arch.exception.error_code);
298101da
AK		 216}
217
a03490ed
CO		 218/*
219 * Load the pae pdptrs. Return true is they are all valid.
220 */
221int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
222{
223 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
224 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
225 int i;
226 int ret;
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 228
a03490ed
CO		 229 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
230 offset * sizeof(u64), sizeof(pdpte));
231 if (ret < 0) {
232 ret = 0;
233 goto out;
234 }
235 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
236 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
237 ret = 0;
238 goto out;
239 }
240 }
241 ret = 1;
242
ad312c7c 243 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 244out:
a03490ed
CO		 245
246 return ret;
247}
cc4b6871 248EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 249
d835dfec
AK		 250static bool pdptrs_changed(struct kvm_vcpu *vcpu)
251{
ad312c7c 252 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 253 bool changed = true;
254 int r;
255
256 if (is_long_mode(vcpu) || !is_pae(vcpu))
257 return false;
258
ad312c7c 259 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 260 if (r < 0)
261 goto out;
ad312c7c 262 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 263out:
d835dfec
AK		 264
265 return changed;
266}
267
2d3ad1f4 268void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 269{
270 if (cr0 & CR0_RESERVED_BITS) {
271 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 272 cr0, vcpu->arch.cr0);
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276
277 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
278 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 279 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 280 return;
281 }
282
283 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
284 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
285 "and a clear PE flag\n");
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
291#ifdef CONFIG_X86_64
ad312c7c 292 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 293 int cs_db, cs_l;
294
295 if (!is_pae(vcpu)) {
296 printk(KERN_DEBUG "set_cr0: #GP, start paging "
297 "in long mode while PAE is disabled\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
302 if (cs_l) {
303 printk(KERN_DEBUG "set_cr0: #GP, start paging "
304 "in long mode while CS.L == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307
308 }
309 } else
310#endif
ad312c7c 311 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 312 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
313 "reserved bits\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317
318 }
319
320 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 321 vcpu->arch.cr0 = cr0;
a03490ed 322
6cffe8ca 323 kvm_mmu_sync_global(vcpu);
a03490ed 324 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 325 return;
326}
2d3ad1f4 327EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 328
2d3ad1f4 329void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 330{
2d3ad1f4 331 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 332 KVMTRACE_1D(LMSW, vcpu,
333 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
334 handler);
a03490ed 335}
2d3ad1f4 336EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 337
2d3ad1f4 338void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 339{
340 if (cr4 & CR4_RESERVED_BITS) {
341 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 342 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 343 return;
344 }
345
346 if (is_long_mode(vcpu)) {
347 if (!(cr4 & X86_CR4_PAE)) {
348 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
349 "in long mode\n");
c1a5d4f9 350 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 351 return;
352 }
353 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 354 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 355 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (cr4 & X86_CR4_VMXE) {
361 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 366 vcpu->arch.cr4 = cr4;
2f0b3d60 367 vcpu->arch.mmu.base_role.cr4_pge = !!(cr4 & X86_CR4_PGE);
6cffe8ca 368 kvm_mmu_sync_global(vcpu);
a03490ed 369 kvm_mmu_reset_context(vcpu);
a03490ed 370}
2d3ad1f4 371EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 372
2d3ad1f4 373void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 374{
ad312c7c 375 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 376 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 377 kvm_mmu_flush_tlb(vcpu);
378 return;
379 }
380
a03490ed
CO		 381 if (is_long_mode(vcpu)) {
382 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
383 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 384 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 385 return;
386 }
387 } else {
388 if (is_pae(vcpu)) {
389 if (cr3 & CR3_PAE_RESERVED_BITS) {
390 printk(KERN_DEBUG
391 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 392 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 393 return;
394 }
395 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
396 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
397 "reserved bits\n");
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 }
402 /*
403 * We don't check reserved bits in nonpae mode, because
404 * this isn't enforced, and VMware depends on this.
405 */
406 }
407
a03490ed
CO		 408 /*
409 * Does the new cr3 value map to physical memory? (Note, we
410 * catch an invalid cr3 even in real-mode, because it would
411 * cause trouble later on when we turn on paging anyway.)
412 *
413 * A real CPU would silently accept an invalid cr3 and would
414 * attempt to use it - with largely undefined (and often hard
415 * to debug) behavior on the guest side.
416 */
417 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 418 kvm_inject_gp(vcpu, 0);
a03490ed 419 else {
ad312c7c
ZX		 420 vcpu->arch.cr3 = cr3;
421 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 422 }
a03490ed 423}
2d3ad1f4 424EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 425
2d3ad1f4 426void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 427{
428 if (cr8 & CR8_RESERVED_BITS) {
429 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 430 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 431 return;
432 }
433 if (irqchip_in_kernel(vcpu->kvm))
434 kvm_lapic_set_tpr(vcpu, cr8);
435 else
ad312c7c 436 vcpu->arch.cr8 = cr8;
a03490ed 437}
2d3ad1f4 438EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 439
2d3ad1f4 440unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 441{
442 if (irqchip_in_kernel(vcpu->kvm))
443 return kvm_lapic_get_cr8(vcpu);
444 else
ad312c7c 445 return vcpu->arch.cr8;
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 448
d8017474
AG		 449static inline u32 bit(int bitno)
450{
451 return 1 << (bitno & 31);
452}
453
043405e1
CO		 454/*
455 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
456 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
457 *
458 * This list is modified at module load time to reflect the
459 * capabilities of the host cpu.
460 */
461static u32 msrs_to_save[] = {
462 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
463 MSR_K6_STAR,
464#ifdef CONFIG_X86_64
465 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
466#endif
18068523 467 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 468 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 469};
470
471static unsigned num_msrs_to_save;
472
473static u32 emulated_msrs[] = {
474 MSR_IA32_MISC_ENABLE,
475};
476
15c4a640
CO		 477static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
478{
f2b4b7dd 479 if (efer & efer_reserved_bits) {
15c4a640
CO		 480 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
481 efer);
c1a5d4f9 482 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 483 return;
484 }
485
486 if (is_paging(vcpu)
ad312c7c 487 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 488 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 490 return;
491 }
492
d8017474
AG		 493 if (efer & EFER_SVME) {
494 struct kvm_cpuid_entry2 *feat;
495
496 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
497 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
498 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
499 kvm_inject_gp(vcpu, 0);
500 return;
501 }
502 }
503
15c4a640
CO		 504 kvm_x86_ops->set_efer(vcpu, efer);
505
506 efer &= ~EFER_LMA;
ad312c7c 507 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 508
ad312c7c 509 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 510}
511
f2b4b7dd
JR		 512void kvm_enable_efer_bits(u64 mask)
513{
514 efer_reserved_bits &= ~mask;
515}
516EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
517
518
15c4a640
CO		 519/*
520 * Writes msr value into into the appropriate "register".
521 * Returns 0 on success, non-0 otherwise.
522 * Assumes vcpu_load() was already called.
523 */
524int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
525{
526 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
527}
528
313a3dc7
CO		 529/*
530 * Adapt set_msr() to msr_io()'s calling convention
531 */
532static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
533{
534 return kvm_set_msr(vcpu, index, *data);
535}
536
18068523
GOC		 537static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
538{
539 static int version;
50d0a0f9
GH		 540 struct pvclock_wall_clock wc;
541 struct timespec now, sys, boot;
18068523
GOC		 542
543 if (!wall_clock)
544 return;
545
546 version++;
547
18068523
GOC		 548 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
549
50d0a0f9
GH		 550 /*
551 * The guest calculates current wall clock time by adding
552 * system time (updated by kvm_write_guest_time below) to the
553 * wall clock specified here. guest system time equals host
554 * system time for us, thus we must fill in host boot time here.
555 */
556 now = current_kernel_time();
557 ktime_get_ts(&sys);
558 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
559
560 wc.sec = boot.tv_sec;
561 wc.nsec = boot.tv_nsec;
562 wc.version = version;
18068523
GOC		 563
564 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
565
566 version++;
567 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 568}
569
50d0a0f9
GH		 570static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
571{
572 uint32_t quotient, remainder;
573
574 /* Don't try to replace with do_div(), this one calculates
575 * "(dividend << 32) / divisor" */
576 __asm__ ( "divl %4"
577 : "=a" (quotient), "=d" (remainder)
578 : "0" (0), "1" (dividend), "r" (divisor) );
579 return quotient;
580}
581
582static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
583{
584 uint64_t nsecs = 1000000000LL;
585 int32_t shift = 0;
586 uint64_t tps64;
587 uint32_t tps32;
588
589 tps64 = tsc_khz * 1000LL;
590 while (tps64 > nsecs*2) {
591 tps64 >>= 1;
592 shift--;
593 }
594
595 tps32 = (uint32_t)tps64;
596 while (tps32 <= (uint32_t)nsecs) {
597 tps32 <<= 1;
598 shift++;
599 }
600
601 hv_clock->tsc_shift = shift;
602 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
603
604 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 605 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 606 hv_clock->tsc_to_system_mul);
607}
608
18068523
GOC		 609static void kvm_write_guest_time(struct kvm_vcpu *v)
610{
611 struct timespec ts;
612 unsigned long flags;
613 struct kvm_vcpu_arch *vcpu = &v->arch;
614 void *shared_kaddr;
615
616 if ((!vcpu->time_page))
617 return;
618
50d0a0f9
GH		 619 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
620 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
621 vcpu->hv_clock_tsc_khz = tsc_khz;
622 }
623
18068523
GOC		 624 /* Keep irq disabled to prevent changes to the clock */
625 local_irq_save(flags);
626 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
627 &vcpu->hv_clock.tsc_timestamp);
628 ktime_get_ts(&ts);
629 local_irq_restore(flags);
630
631 /* With all the info we got, fill in the values */
632
633 vcpu->hv_clock.system_time = ts.tv_nsec +
634 (NSEC_PER_SEC * (u64)ts.tv_sec);
635 /*
636 * The interface expects us to write an even number signaling that the
637 * update is finished. Since the guest won't see the intermediate
50d0a0f9 638 * state, we just increase by 2 at the end.
18068523 639 */
50d0a0f9 640 vcpu->hv_clock.version += 2;
18068523
GOC		 641
642 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
643
644 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 645 sizeof(vcpu->hv_clock));
18068523
GOC		 646
647 kunmap_atomic(shared_kaddr, KM_USER0);
648
649 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
650}
651
9ba075a6
AK		 652static bool msr_mtrr_valid(unsigned msr)
653{
654 switch (msr) {
655 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
656 case MSR_MTRRfix64K_00000:
657 case MSR_MTRRfix16K_80000:
658 case MSR_MTRRfix16K_A0000:
659 case MSR_MTRRfix4K_C0000:
660 case MSR_MTRRfix4K_C8000:
661 case MSR_MTRRfix4K_D0000:
662 case MSR_MTRRfix4K_D8000:
663 case MSR_MTRRfix4K_E0000:
664 case MSR_MTRRfix4K_E8000:
665 case MSR_MTRRfix4K_F0000:
666 case MSR_MTRRfix4K_F8000:
667 case MSR_MTRRdefType:
668 case MSR_IA32_CR_PAT:
669 return true;
670 case 0x2f8:
671 return true;
672 }
673 return false;
674}
675
676static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
677{
0bed3b56
SY		 678 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
679
9ba075a6
AK		 680 if (!msr_mtrr_valid(msr))
681 return 1;
682
0bed3b56
SY		 683 if (msr == MSR_MTRRdefType) {
684 vcpu->arch.mtrr_state.def_type = data;
685 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
686 } else if (msr == MSR_MTRRfix64K_00000)
687 p[0] = data;
688 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
689 p[1 + msr - MSR_MTRRfix16K_80000] = data;
690 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
691 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
692 else if (msr == MSR_IA32_CR_PAT)
693 vcpu->arch.pat = data;
694 else { /* Variable MTRRs */
695 int idx, is_mtrr_mask;
696 u64 *pt;
697
698 idx = (msr - 0x200) / 2;
699 is_mtrr_mask = msr - 0x200 - 2 * idx;
700 if (!is_mtrr_mask)
701 pt =
702 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
703 else
704 pt =
705 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
706 *pt = data;
707 }
708
709 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 710 return 0;
711}
15c4a640
CO		 712
713int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
714{
715 switch (msr) {
15c4a640
CO		 716 case MSR_EFER:
717 set_efer(vcpu, data);
718 break;
15c4a640
CO		 719 case MSR_IA32_MC0_STATUS:
720 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 721 __func__, data);
15c4a640
CO		 722 break;
723 case MSR_IA32_MCG_STATUS:
724 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 725 __func__, data);
15c4a640 726 break;
c7ac679c
JR		 727 case MSR_IA32_MCG_CTL:
728 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 729 __func__, data);
c7ac679c 730 break;
b5e2fec0
AG		 731 case MSR_IA32_DEBUGCTLMSR:
732 if (!data) {
733 /* We support the non-activated case already */
734 break;
735 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
736 /* Values other than LBR and BTF are vendor-specific,
737 thus reserved and should throw a #GP */
738 return 1;
739 }
740 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
741 __func__, data);
742 break;
15c4a640
CO		 743 case MSR_IA32_UCODE_REV:
744 case MSR_IA32_UCODE_WRITE:
15c4a640 745 break;
9ba075a6
AK		 746 case 0x200 ... 0x2ff:
747 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 748 case MSR_IA32_APICBASE:
749 kvm_set_apic_base(vcpu, data);
750 break;
751 case MSR_IA32_MISC_ENABLE:
ad312c7c 752 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 753 break;
18068523
GOC		 754 case MSR_KVM_WALL_CLOCK:
755 vcpu->kvm->arch.wall_clock = data;
756 kvm_write_wall_clock(vcpu->kvm, data);
757 break;
758 case MSR_KVM_SYSTEM_TIME: {
759 if (vcpu->arch.time_page) {
760 kvm_release_page_dirty(vcpu->arch.time_page);
761 vcpu->arch.time_page = NULL;
762 }
763
764 vcpu->arch.time = data;
765
766 /* we verify if the enable bit is set... */
767 if (!(data & 1))
768 break;
769
770 /* ...but clean it before doing the actual write */
771 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
772
18068523
GOC		 773 vcpu->arch.time_page =
774 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 775
776 if (is_error_page(vcpu->arch.time_page)) {
777 kvm_release_page_clean(vcpu->arch.time_page);
778 vcpu->arch.time_page = NULL;
779 }
780
781 kvm_write_guest_time(vcpu);
782 break;
783 }
15c4a640 784 default:
565f1fbd 785 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 786 return 1;
787 }
788 return 0;
789}
790EXPORT_SYMBOL_GPL(kvm_set_msr_common);
791
792
793/*
794 * Reads an msr value (of 'msr_index') into 'pdata'.
795 * Returns 0 on success, non-0 otherwise.
796 * Assumes vcpu_load() was already called.
797 */
798int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
799{
800 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
801}
802
9ba075a6
AK		 803static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
804{
0bed3b56
SY		 805 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
806
9ba075a6
AK		 807 if (!msr_mtrr_valid(msr))
808 return 1;
809
0bed3b56
SY		 810 if (msr == MSR_MTRRdefType)
811 *pdata = vcpu->arch.mtrr_state.def_type +
812 (vcpu->arch.mtrr_state.enabled << 10);
813 else if (msr == MSR_MTRRfix64K_00000)
814 *pdata = p[0];
815 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
816 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
817 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
818 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
819 else if (msr == MSR_IA32_CR_PAT)
820 *pdata = vcpu->arch.pat;
821 else { /* Variable MTRRs */
822 int idx, is_mtrr_mask;
823 u64 *pt;
824
825 idx = (msr - 0x200) / 2;
826 is_mtrr_mask = msr - 0x200 - 2 * idx;
827 if (!is_mtrr_mask)
828 pt =
829 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
830 else
831 pt =
832 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
833 *pdata = *pt;
834 }
835
9ba075a6
AK		 836 return 0;
837}
838
15c4a640
CO		 839int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
840{
841 u64 data;
842
843 switch (msr) {
844 case 0xc0010010: /* SYSCFG */
845 case 0xc0010015: /* HWCR */
846 case MSR_IA32_PLATFORM_ID:
847 case MSR_IA32_P5_MC_ADDR:
848 case MSR_IA32_P5_MC_TYPE:
849 case MSR_IA32_MC0_CTL:
850 case MSR_IA32_MCG_STATUS:
851 case MSR_IA32_MCG_CAP:
c7ac679c 852 case MSR_IA32_MCG_CTL:
15c4a640
CO		 853 case MSR_IA32_MC0_MISC:
854 case MSR_IA32_MC0_MISC+4:
855 case MSR_IA32_MC0_MISC+8:
856 case MSR_IA32_MC0_MISC+12:
857 case MSR_IA32_MC0_MISC+16:
a89c1ad2 858 case MSR_IA32_MC0_MISC+20:
15c4a640 859 case MSR_IA32_UCODE_REV:
15c4a640 860 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 861 case MSR_IA32_DEBUGCTLMSR:
862 case MSR_IA32_LASTBRANCHFROMIP:
863 case MSR_IA32_LASTBRANCHTOIP:
864 case MSR_IA32_LASTINTFROMIP:
865 case MSR_IA32_LASTINTTOIP:
15c4a640
CO		 866 data = 0;
867 break;
9ba075a6
AK		 868 case MSR_MTRRcap:
869 data = 0x500 | KVM_NR_VAR_MTRR;
870 break;
871 case 0x200 ... 0x2ff:
872 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 873 case 0xcd: /* fsb frequency */
874 data = 3;
875 break;
876 case MSR_IA32_APICBASE:
877 data = kvm_get_apic_base(vcpu);
878 break;
879 case MSR_IA32_MISC_ENABLE:
ad312c7c 880 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 881 break;
847f0ad8
AG		 882 case MSR_IA32_PERF_STATUS:
883 /* TSC increment by tick */
884 data = 1000ULL;
885 /* CPU multiplier */
886 data |= (((uint64_t)4ULL) << 40);
887 break;
15c4a640 888 case MSR_EFER:
ad312c7c 889 data = vcpu->arch.shadow_efer;
15c4a640 890 break;
18068523
GOC		 891 case MSR_KVM_WALL_CLOCK:
892 data = vcpu->kvm->arch.wall_clock;
893 break;
894 case MSR_KVM_SYSTEM_TIME:
895 data = vcpu->arch.time;
896 break;
15c4a640
CO		 897 default:
898 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
899 return 1;
900 }
901 *pdata = data;
902 return 0;
903}
904EXPORT_SYMBOL_GPL(kvm_get_msr_common);
905
313a3dc7
CO		 906/*
907 * Read or write a bunch of msrs. All parameters are kernel addresses.
908 *
909 * @return number of msrs set successfully.
910 */
911static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
912 struct kvm_msr_entry *entries,
913 int (*do_msr)(struct kvm_vcpu *vcpu,
914 unsigned index, u64 *data))
915{
916 int i;
917
918 vcpu_load(vcpu);
919
3200f405 920 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 921 for (i = 0; i < msrs->nmsrs; ++i)
922 if (do_msr(vcpu, entries[i].index, &entries[i].data))
923 break;
3200f405 924 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 925
926 vcpu_put(vcpu);
927
928 return i;
929}
930
931/*
932 * Read or write a bunch of msrs. Parameters are user addresses.
933 *
934 * @return number of msrs set successfully.
935 */
936static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
937 int (*do_msr)(struct kvm_vcpu *vcpu,
938 unsigned index, u64 *data),
939 int writeback)
940{
941 struct kvm_msrs msrs;
942 struct kvm_msr_entry *entries;
943 int r, n;
944 unsigned size;
945
946 r = -EFAULT;
947 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
948 goto out;
949
950 r = -E2BIG;
951 if (msrs.nmsrs >= MAX_IO_MSRS)
952 goto out;
953
954 r = -ENOMEM;
955 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
956 entries = vmalloc(size);
957 if (!entries)
958 goto out;
959
960 r = -EFAULT;
961 if (copy_from_user(entries, user_msrs->entries, size))
962 goto out_free;
963
964 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
965 if (r < 0)
966 goto out_free;
967
968 r = -EFAULT;
969 if (writeback && copy_to_user(user_msrs->entries, entries, size))
970 goto out_free;
971
972 r = n;
973
974out_free:
975 vfree(entries);
976out:
977 return r;
978}
979
018d00d2
ZX		 980int kvm_dev_ioctl_check_extension(long ext)
981{
982 int r;
983
984 switch (ext) {
985 case KVM_CAP_IRQCHIP:
986 case KVM_CAP_HLT:
987 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 988 case KVM_CAP_SET_TSS_ADDR:
07716717 989 case KVM_CAP_EXT_CPUID:
7837699f 990 case KVM_CAP_PIT:
a28e4f5a 991 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 992 case KVM_CAP_MP_STATE:
ed848624 993 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 994 r = 1;
995 break;
542472b5
LV		 996 case KVM_CAP_COALESCED_MMIO:
997 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
998 break;
774ead3a
AK		 999 case KVM_CAP_VAPIC:
1000 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1001 break;
f725230a
AK		 1002 case KVM_CAP_NR_VCPUS:
1003 r = KVM_MAX_VCPUS;
1004 break;
a988b910
AK		 1005 case KVM_CAP_NR_MEMSLOTS:
1006 r = KVM_MEMORY_SLOTS;
1007 break;
2f333bcb
MT		 1008 case KVM_CAP_PV_MMU:
1009 r = !tdp_enabled;
1010 break;
62c476c7 1011 case KVM_CAP_IOMMU:
19de40a8 1012 r = iommu_found();
62c476c7 1013 break;
abe6655d
MT		 1014 case KVM_CAP_CLOCKSOURCE:
1015 r = boot_cpu_has(X86_FEATURE_CONSTANT_TSC);
1016 break;
018d00d2
ZX		 1017 default:
1018 r = 0;
1019 break;
1020 }
1021 return r;
1022
1023}
1024
043405e1
CO		 1025long kvm_arch_dev_ioctl(struct file *filp,
1026 unsigned int ioctl, unsigned long arg)
1027{
1028 void __user *argp = (void __user *)arg;
1029 long r;
1030
1031 switch (ioctl) {
1032 case KVM_GET_MSR_INDEX_LIST: {
1033 struct kvm_msr_list __user *user_msr_list = argp;
1034 struct kvm_msr_list msr_list;
1035 unsigned n;
1036
1037 r = -EFAULT;
1038 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1039 goto out;
1040 n = msr_list.nmsrs;
1041 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1042 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1043 goto out;
1044 r = -E2BIG;
1045 if (n < num_msrs_to_save)
1046 goto out;
1047 r = -EFAULT;
1048 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1049 num_msrs_to_save * sizeof(u32)))
1050 goto out;
1051 if (copy_to_user(user_msr_list->indices
1052 + num_msrs_to_save * sizeof(u32),
1053 &emulated_msrs,
1054 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1055 goto out;
1056 r = 0;
1057 break;
1058 }
674eea0f
AK		 1059 case KVM_GET_SUPPORTED_CPUID: {
1060 struct kvm_cpuid2 __user *cpuid_arg = argp;
1061 struct kvm_cpuid2 cpuid;
1062
1063 r = -EFAULT;
1064 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1065 goto out;
1066 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1067 cpuid_arg->entries);
1068 if (r)
1069 goto out;
1070
1071 r = -EFAULT;
1072 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1073 goto out;
1074 r = 0;
1075 break;
1076 }
043405e1
CO		 1077 default:
1078 r = -EINVAL;
1079 }
1080out:
1081 return r;
1082}
1083
313a3dc7
CO		 1084void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1085{
1086 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1087 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1088}
1089
1090void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1091{
1092 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1093 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1094}
1095
07716717 1096static int is_efer_nx(void)
313a3dc7
CO		 1097{
1098 u64 efer;
313a3dc7
CO		 1099
1100 rdmsrl(MSR_EFER, efer);
07716717
DK		 1101 return efer & EFER_NX;
1102}
1103
1104static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1105{
1106 int i;
1107 struct kvm_cpuid_entry2 *e, *entry;
1108
313a3dc7 1109 entry = NULL;
ad312c7c
ZX		 1110 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1111 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1112 if (e->function == 0x80000001) {
1113 entry = e;
1114 break;
1115 }
1116 }
07716717 1117 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1118 entry->edx &= ~(1 << 20);
1119 printk(KERN_INFO "kvm: guest NX capability removed\n");
1120 }
1121}
1122
07716717 1123/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1124static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1125 struct kvm_cpuid *cpuid,
1126 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1127{
1128 int r, i;
1129 struct kvm_cpuid_entry *cpuid_entries;
1130
1131 r = -E2BIG;
1132 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1133 goto out;
1134 r = -ENOMEM;
1135 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1136 if (!cpuid_entries)
1137 goto out;
1138 r = -EFAULT;
1139 if (copy_from_user(cpuid_entries, entries,
1140 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1141 goto out_free;
1142 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1143 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1144 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1145 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1146 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1147 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1148 vcpu->arch.cpuid_entries[i].index = 0;
1149 vcpu->arch.cpuid_entries[i].flags = 0;
1150 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1151 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1152 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1153 }
1154 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1155 cpuid_fix_nx_cap(vcpu);
1156 r = 0;
1157
1158out_free:
1159 vfree(cpuid_entries);
1160out:
1161 return r;
1162}
1163
1164static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1165 struct kvm_cpuid2 *cpuid,
1166 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1167{
1168 int r;
1169
1170 r = -E2BIG;
1171 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1172 goto out;
1173 r = -EFAULT;
ad312c7c 1174 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1175 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1176 goto out;
ad312c7c 1177 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1178 return 0;
1179
1180out:
1181 return r;
1182}
1183
07716717
DK		 1184static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1185 struct kvm_cpuid2 *cpuid,
1186 struct kvm_cpuid_entry2 __user *entries)
1187{
1188 int r;
1189
1190 r = -E2BIG;
ad312c7c 1191 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1192 goto out;
1193 r = -EFAULT;
ad312c7c
ZX		 1194 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1195 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1196 goto out;
1197 return 0;
1198
1199out:
ad312c7c 1200 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1201 return r;
1202}
1203
07716717
DK		 1204static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1205 u32 index)
1206{
1207 entry->function = function;
1208 entry->index = index;
1209 cpuid_count(entry->function, entry->index,
1210 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1211 entry->flags = 0;
1212}
1213
1214static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1215 u32 index, int *nent, int maxnent)
1216{
1217 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1218 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1219 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1220 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1221 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1222 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1223 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1224 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1225 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1226 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1227 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1228 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1229 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1230 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1231 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1232 bit(X86_FEATURE_PGE) |
1233 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1234 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1235 bit(X86_FEATURE_SYSCALL) |
1236 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1237#ifdef CONFIG_X86_64
1238 bit(X86_FEATURE_LM) |
1239#endif
1240 bit(X86_FEATURE_MMXEXT) |
1241 bit(X86_FEATURE_3DNOWEXT) |
1242 bit(X86_FEATURE_3DNOW);
1243 const u32 kvm_supported_word3_x86_features =
1244 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1245 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1246 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1247 bit(X86_FEATURE_SVM);
07716717
DK		 1248
1249 /* all func 2 cpuid_count() should be called on the same cpu */
1250 get_cpu();
1251 do_cpuid_1_ent(entry, function, index);
1252 ++*nent;
1253
1254 switch (function) {
1255 case 0:
1256 entry->eax = min(entry->eax, (u32)0xb);
1257 break;
1258 case 1:
1259 entry->edx &= kvm_supported_word0_x86_features;
1260 entry->ecx &= kvm_supported_word3_x86_features;
1261 break;
1262 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1263 * may return different values. This forces us to get_cpu() before
1264 * issuing the first command, and also to emulate this annoying behavior
1265 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1266 case 2: {
1267 int t, times = entry->eax & 0xff;
1268
1269 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1270 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1271 for (t = 1; t < times && *nent < maxnent; ++t) {
1272 do_cpuid_1_ent(&entry[t], function, 0);
1273 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1274 ++*nent;
1275 }
1276 break;
1277 }
1278 /* function 4 and 0xb have additional index. */
1279 case 4: {
14af3f3c 1280 int i, cache_type;
07716717
DK		 1281
1282 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1283 /* read more entries until cache_type is zero */
14af3f3c
HH		 1284 for (i = 1; *nent < maxnent; ++i) {
1285 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1286 if (!cache_type)
1287 break;
14af3f3c
HH		 1288 do_cpuid_1_ent(&entry[i], function, i);
1289 entry[i].flags |=
07716717
DK		 1290 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1291 ++*nent;
1292 }
1293 break;
1294 }
1295 case 0xb: {
14af3f3c 1296 int i, level_type;
07716717
DK		 1297
1298 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1299 /* read more entries until level_type is zero */
14af3f3c 1300 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1301 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1302 if (!level_type)
1303 break;
14af3f3c
HH		 1304 do_cpuid_1_ent(&entry[i], function, i);
1305 entry[i].flags |=
07716717
DK		 1306 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1307 ++*nent;
1308 }
1309 break;
1310 }
1311 case 0x80000000:
1312 entry->eax = min(entry->eax, 0x8000001a);
1313 break;
1314 case 0x80000001:
1315 entry->edx &= kvm_supported_word1_x86_features;
1316 entry->ecx &= kvm_supported_word6_x86_features;
1317 break;
1318 }
1319 put_cpu();
1320}
1321
674eea0f 1322static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1323 struct kvm_cpuid_entry2 __user *entries)
1324{
1325 struct kvm_cpuid_entry2 *cpuid_entries;
1326 int limit, nent = 0, r = -E2BIG;
1327 u32 func;
1328
1329 if (cpuid->nent < 1)
1330 goto out;
1331 r = -ENOMEM;
1332 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1333 if (!cpuid_entries)
1334 goto out;
1335
1336 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1337 limit = cpuid_entries[0].eax;
1338 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1339 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1340 &nent, cpuid->nent);
1341 r = -E2BIG;
1342 if (nent >= cpuid->nent)
1343 goto out_free;
1344
1345 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1346 limit = cpuid_entries[nent - 1].eax;
1347 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1348 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1349 &nent, cpuid->nent);
1350 r = -EFAULT;
1351 if (copy_to_user(entries, cpuid_entries,
1352 nent * sizeof(struct kvm_cpuid_entry2)))
1353 goto out_free;
1354 cpuid->nent = nent;
1355 r = 0;
1356
1357out_free:
1358 vfree(cpuid_entries);
1359out:
1360 return r;
1361}
1362
313a3dc7
CO		 1363static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1364 struct kvm_lapic_state *s)
1365{
1366 vcpu_load(vcpu);
ad312c7c 1367 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1368 vcpu_put(vcpu);
1369
1370 return 0;
1371}
1372
1373static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1374 struct kvm_lapic_state *s)
1375{
1376 vcpu_load(vcpu);
ad312c7c 1377 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1378 kvm_apic_post_state_restore(vcpu);
1379 vcpu_put(vcpu);
1380
1381 return 0;
1382}
1383
f77bc6a4
ZX		 1384static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1385 struct kvm_interrupt *irq)
1386{
1387 if (irq->irq < 0 || irq->irq >= 256)
1388 return -EINVAL;
1389 if (irqchip_in_kernel(vcpu->kvm))
1390 return -ENXIO;
1391 vcpu_load(vcpu);
1392
ad312c7c
ZX		 1393 set_bit(irq->irq, vcpu->arch.irq_pending);
1394 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1395
1396 vcpu_put(vcpu);
1397
1398 return 0;
1399}
1400
c4abb7c9
JK		 1401static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1402{
1403 vcpu_load(vcpu);
1404 kvm_inject_nmi(vcpu);
1405 vcpu_put(vcpu);
1406
1407 return 0;
1408}
1409
b209749f
AK		 1410static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1411 struct kvm_tpr_access_ctl *tac)
1412{
1413 if (tac->flags)
1414 return -EINVAL;
1415 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1416 return 0;
1417}
1418
313a3dc7
CO		 1419long kvm_arch_vcpu_ioctl(struct file *filp,
1420 unsigned int ioctl, unsigned long arg)
1421{
1422 struct kvm_vcpu *vcpu = filp->private_data;
1423 void __user *argp = (void __user *)arg;
1424 int r;
b772ff36 1425 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1426
1427 switch (ioctl) {
1428 case KVM_GET_LAPIC: {
b772ff36 1429 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1430
b772ff36
DH		 1431 r = -ENOMEM;
1432 if (!lapic)
1433 goto out;
1434 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1435 if (r)
1436 goto out;
1437 r = -EFAULT;
b772ff36 1438 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1439 goto out;
1440 r = 0;
1441 break;
1442 }
1443 case KVM_SET_LAPIC: {
b772ff36
DH		 1444 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1445 r = -ENOMEM;
1446 if (!lapic)
1447 goto out;
313a3dc7 1448 r = -EFAULT;
b772ff36 1449 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1450 goto out;
b772ff36 1451 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1452 if (r)
1453 goto out;
1454 r = 0;
1455 break;
1456 }
f77bc6a4
ZX		 1457 case KVM_INTERRUPT: {
1458 struct kvm_interrupt irq;
1459
1460 r = -EFAULT;
1461 if (copy_from_user(&irq, argp, sizeof irq))
1462 goto out;
1463 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1464 if (r)
1465 goto out;
1466 r = 0;
1467 break;
1468 }
c4abb7c9
JK		 1469 case KVM_NMI: {
1470 r = kvm_vcpu_ioctl_nmi(vcpu);
1471 if (r)
1472 goto out;
1473 r = 0;
1474 break;
1475 }
313a3dc7
CO		 1476 case KVM_SET_CPUID: {
1477 struct kvm_cpuid __user *cpuid_arg = argp;
1478 struct kvm_cpuid cpuid;
1479
1480 r = -EFAULT;
1481 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1482 goto out;
1483 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1484 if (r)
1485 goto out;
1486 break;
1487 }
07716717
DK		 1488 case KVM_SET_CPUID2: {
1489 struct kvm_cpuid2 __user *cpuid_arg = argp;
1490 struct kvm_cpuid2 cpuid;
1491
1492 r = -EFAULT;
1493 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1494 goto out;
1495 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1496 cpuid_arg->entries);
1497 if (r)
1498 goto out;
1499 break;
1500 }
1501 case KVM_GET_CPUID2: {
1502 struct kvm_cpuid2 __user *cpuid_arg = argp;
1503 struct kvm_cpuid2 cpuid;
1504
1505 r = -EFAULT;
1506 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1507 goto out;
1508 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1509 cpuid_arg->entries);
1510 if (r)
1511 goto out;
1512 r = -EFAULT;
1513 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1514 goto out;
1515 r = 0;
1516 break;
1517 }
313a3dc7
CO		 1518 case KVM_GET_MSRS:
1519 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1520 break;
1521 case KVM_SET_MSRS:
1522 r = msr_io(vcpu, argp, do_set_msr, 0);
1523 break;
b209749f
AK		 1524 case KVM_TPR_ACCESS_REPORTING: {
1525 struct kvm_tpr_access_ctl tac;
1526
1527 r = -EFAULT;
1528 if (copy_from_user(&tac, argp, sizeof tac))
1529 goto out;
1530 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1531 if (r)
1532 goto out;
1533 r = -EFAULT;
1534 if (copy_to_user(argp, &tac, sizeof tac))
1535 goto out;
1536 r = 0;
1537 break;
1538 };
b93463aa
AK		 1539 case KVM_SET_VAPIC_ADDR: {
1540 struct kvm_vapic_addr va;
1541
1542 r = -EINVAL;
1543 if (!irqchip_in_kernel(vcpu->kvm))
1544 goto out;
1545 r = -EFAULT;
1546 if (copy_from_user(&va, argp, sizeof va))
1547 goto out;
1548 r = 0;
1549 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1550 break;
1551 }
313a3dc7
CO		 1552 default:
1553 r = -EINVAL;
1554 }
1555out:
b772ff36
DH		 1556 if (lapic)
1557 kfree(lapic);
313a3dc7
CO		 1558 return r;
1559}
1560
1fe779f8
CO		 1561static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1562{
1563 int ret;
1564
1565 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1566 return -1;
1567 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1568 return ret;
1569}
1570
1571static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1572 u32 kvm_nr_mmu_pages)
1573{
1574 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1575 return -EINVAL;
1576
72dc67a6 1577 down_write(&kvm->slots_lock);
1fe779f8
CO		 1578
1579 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1580 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1581
72dc67a6 1582 up_write(&kvm->slots_lock);
1fe779f8
CO		 1583 return 0;
1584}
1585
1586static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1587{
f05e70ac 1588 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1589}
1590
e9f85cde
ZX		 1591gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1592{
1593 int i;
1594 struct kvm_mem_alias *alias;
1595
d69fb81f
ZX		 1596 for (i = 0; i < kvm->arch.naliases; ++i) {
1597 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1598 if (gfn >= alias->base_gfn
1599 && gfn < alias->base_gfn + alias->npages)
1600 return alias->target_gfn + gfn - alias->base_gfn;
1601 }
1602 return gfn;
1603}
1604
1fe779f8
CO		 1605/*
1606 * Set a new alias region. Aliases map a portion of physical memory into
1607 * another portion. This is useful for memory windows, for example the PC
1608 * VGA region.
1609 */
1610static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1611 struct kvm_memory_alias *alias)
1612{
1613 int r, n;
1614 struct kvm_mem_alias *p;
1615
1616 r = -EINVAL;
1617 /* General sanity checks */
1618 if (alias->memory_size & (PAGE_SIZE - 1))
1619 goto out;
1620 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1621 goto out;
1622 if (alias->slot >= KVM_ALIAS_SLOTS)
1623 goto out;
1624 if (alias->guest_phys_addr + alias->memory_size
1625 < alias->guest_phys_addr)
1626 goto out;
1627 if (alias->target_phys_addr + alias->memory_size
1628 < alias->target_phys_addr)
1629 goto out;
1630
72dc67a6 1631 down_write(&kvm->slots_lock);
a1708ce8 1632 spin_lock(&kvm->mmu_lock);
1fe779f8 1633
d69fb81f 1634 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1635 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1636 p->npages = alias->memory_size >> PAGE_SHIFT;
1637 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1638
1639 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1640 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1641 break;
d69fb81f 1642 kvm->arch.naliases = n;
1fe779f8 1643
a1708ce8 1644 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1645 kvm_mmu_zap_all(kvm);
1646
72dc67a6 1647 up_write(&kvm->slots_lock);
1fe779f8
CO		 1648
1649 return 0;
1650
1651out:
1652 return r;
1653}
1654
1655static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1656{
1657 int r;
1658
1659 r = 0;
1660 switch (chip->chip_id) {
1661 case KVM_IRQCHIP_PIC_MASTER:
1662 memcpy(&chip->chip.pic,
1663 &pic_irqchip(kvm)->pics[0],
1664 sizeof(struct kvm_pic_state));
1665 break;
1666 case KVM_IRQCHIP_PIC_SLAVE:
1667 memcpy(&chip->chip.pic,
1668 &pic_irqchip(kvm)->pics[1],
1669 sizeof(struct kvm_pic_state));
1670 break;
1671 case KVM_IRQCHIP_IOAPIC:
1672 memcpy(&chip->chip.ioapic,
1673 ioapic_irqchip(kvm),
1674 sizeof(struct kvm_ioapic_state));
1675 break;
1676 default:
1677 r = -EINVAL;
1678 break;
1679 }
1680 return r;
1681}
1682
1683static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1684{
1685 int r;
1686
1687 r = 0;
1688 switch (chip->chip_id) {
1689 case KVM_IRQCHIP_PIC_MASTER:
1690 memcpy(&pic_irqchip(kvm)->pics[0],
1691 &chip->chip.pic,
1692 sizeof(struct kvm_pic_state));
1693 break;
1694 case KVM_IRQCHIP_PIC_SLAVE:
1695 memcpy(&pic_irqchip(kvm)->pics[1],
1696 &chip->chip.pic,
1697 sizeof(struct kvm_pic_state));
1698 break;
1699 case KVM_IRQCHIP_IOAPIC:
1700 memcpy(ioapic_irqchip(kvm),
1701 &chip->chip.ioapic,
1702 sizeof(struct kvm_ioapic_state));
1703 break;
1704 default:
1705 r = -EINVAL;
1706 break;
1707 }
1708 kvm_pic_update_irq(pic_irqchip(kvm));
1709 return r;
1710}
1711
e0f63cb9
SY		 1712static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1713{
1714 int r = 0;
1715
1716 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1717 return r;
1718}
1719
1720static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1721{
1722 int r = 0;
1723
1724 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1725 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1726 return r;
1727}
1728
5bb064dc
ZX		 1729/*
1730 * Get (and clear) the dirty memory log for a memory slot.
1731 */
1732int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1733 struct kvm_dirty_log *log)
1734{
1735 int r;
1736 int n;
1737 struct kvm_memory_slot *memslot;
1738 int is_dirty = 0;
1739
72dc67a6 1740 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1741
1742 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1743 if (r)
1744 goto out;
1745
1746 /* If nothing is dirty, don't bother messing with page tables. */
1747 if (is_dirty) {
1748 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1749 kvm_flush_remote_tlbs(kvm);
1750 memslot = &kvm->memslots[log->slot];
1751 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1752 memset(memslot->dirty_bitmap, 0, n);
1753 }
1754 r = 0;
1755out:
72dc67a6 1756 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1757 return r;
1758}
1759
1fe779f8
CO		 1760long kvm_arch_vm_ioctl(struct file *filp,
1761 unsigned int ioctl, unsigned long arg)
1762{
1763 struct kvm *kvm = filp->private_data;
1764 void __user *argp = (void __user *)arg;
1765 int r = -EINVAL;
f0d66275
DH		 1766 /*
1767 * This union makes it completely explicit to gcc-3.x
1768 * that these two variables' stack usage should be
1769 * combined, not added together.
1770 */
1771 union {
1772 struct kvm_pit_state ps;
1773 struct kvm_memory_alias alias;
1774 } u;
1fe779f8
CO		 1775
1776 switch (ioctl) {
1777 case KVM_SET_TSS_ADDR:
1778 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1779 if (r < 0)
1780 goto out;
1781 break;
1782 case KVM_SET_MEMORY_REGION: {
1783 struct kvm_memory_region kvm_mem;
1784 struct kvm_userspace_memory_region kvm_userspace_mem;
1785
1786 r = -EFAULT;
1787 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1788 goto out;
1789 kvm_userspace_mem.slot = kvm_mem.slot;
1790 kvm_userspace_mem.flags = kvm_mem.flags;
1791 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1792 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1793 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1794 if (r)
1795 goto out;
1796 break;
1797 }
1798 case KVM_SET_NR_MMU_PAGES:
1799 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1800 if (r)
1801 goto out;
1802 break;
1803 case KVM_GET_NR_MMU_PAGES:
1804 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1805 break;
f0d66275 1806 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1807 r = -EFAULT;
f0d66275 1808 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1809 goto out;
f0d66275 1810 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1811 if (r)
1812 goto out;
1813 break;
1fe779f8
CO		 1814 case KVM_CREATE_IRQCHIP:
1815 r = -ENOMEM;
d7deeeb0
ZX		 1816 kvm->arch.vpic = kvm_create_pic(kvm);
1817 if (kvm->arch.vpic) {
1fe779f8
CO		 1818 r = kvm_ioapic_init(kvm);
1819 if (r) {
d7deeeb0
ZX		 1820 kfree(kvm->arch.vpic);
1821 kvm->arch.vpic = NULL;
1fe779f8
CO		 1822 goto out;
1823 }
1824 } else
1825 goto out;
1826 break;
7837699f
SY		 1827 case KVM_CREATE_PIT:
1828 r = -ENOMEM;
1829 kvm->arch.vpit = kvm_create_pit(kvm);
1830 if (kvm->arch.vpit)
1831 r = 0;
1832 break;
1fe779f8
CO		 1833 case KVM_IRQ_LINE: {
1834 struct kvm_irq_level irq_event;
1835
1836 r = -EFAULT;
1837 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1838 goto out;
1839 if (irqchip_in_kernel(kvm)) {
1840 mutex_lock(&kvm->lock);
5550af4d
SY		 1841 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1842 irq_event.irq, irq_event.level);
1fe779f8
CO		 1843 mutex_unlock(&kvm->lock);
1844 r = 0;
1845 }
1846 break;
1847 }
1848 case KVM_GET_IRQCHIP: {
1849 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1850 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1851
f0d66275
DH		 1852 r = -ENOMEM;
1853 if (!chip)
1fe779f8 1854 goto out;
f0d66275
DH		 1855 r = -EFAULT;
1856 if (copy_from_user(chip, argp, sizeof *chip))
1857 goto get_irqchip_out;
1fe779f8
CO		 1858 r = -ENXIO;
1859 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1860 goto get_irqchip_out;
1861 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1862 if (r)
f0d66275 1863 goto get_irqchip_out;
1fe779f8 1864 r = -EFAULT;
f0d66275
DH		 1865 if (copy_to_user(argp, chip, sizeof *chip))
1866 goto get_irqchip_out;
1fe779f8 1867 r = 0;
f0d66275
DH		 1868 get_irqchip_out:
1869 kfree(chip);
1870 if (r)
1871 goto out;
1fe779f8
CO		 1872 break;
1873 }
1874 case KVM_SET_IRQCHIP: {
1875 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1876 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1877
f0d66275
DH		 1878 r = -ENOMEM;
1879 if (!chip)
1fe779f8 1880 goto out;
f0d66275
DH		 1881 r = -EFAULT;
1882 if (copy_from_user(chip, argp, sizeof *chip))
1883 goto set_irqchip_out;
1fe779f8
CO		 1884 r = -ENXIO;
1885 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1886 goto set_irqchip_out;
1887 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1888 if (r)
f0d66275 1889 goto set_irqchip_out;
1fe779f8 1890 r = 0;
f0d66275
DH		 1891 set_irqchip_out:
1892 kfree(chip);
1893 if (r)
1894 goto out;
1fe779f8
CO		 1895 break;
1896 }
e0f63cb9 1897 case KVM_GET_PIT: {
e0f63cb9 1898 r = -EFAULT;
f0d66275 1899 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1900 goto out;
1901 r = -ENXIO;
1902 if (!kvm->arch.vpit)
1903 goto out;
f0d66275 1904 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1905 if (r)
1906 goto out;
1907 r = -EFAULT;
f0d66275 1908 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1909 goto out;
1910 r = 0;
1911 break;
1912 }
1913 case KVM_SET_PIT: {
e0f63cb9 1914 r = -EFAULT;
f0d66275 1915 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1916 goto out;
1917 r = -ENXIO;
1918 if (!kvm->arch.vpit)
1919 goto out;
f0d66275 1920 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1921 if (r)
1922 goto out;
1923 r = 0;
1924 break;
1925 }
1fe779f8
CO		 1926 default:
1927 ;
1928 }
1929out:
1930 return r;
1931}
1932
a16b043c 1933static void kvm_init_msr_list(void)
043405e1
CO		 1934{
1935 u32 dummy[2];
1936 unsigned i, j;
1937
1938 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1939 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1940 continue;
1941 if (j < i)
1942 msrs_to_save[j] = msrs_to_save[i];
1943 j++;
1944 }
1945 num_msrs_to_save = j;
1946}
1947
bbd9b64e
CO		 1948/*
1949 * Only apic need an MMIO device hook, so shortcut now..
1950 */
1951static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1952 gpa_t addr, int len,
1953 int is_write)
bbd9b64e
CO		 1954{
1955 struct kvm_io_device *dev;
1956
ad312c7c
ZX		 1957 if (vcpu->arch.apic) {
1958 dev = &vcpu->arch.apic->dev;
92760499 1959 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1960 return dev;
1961 }
1962 return NULL;
1963}
1964
1965
1966static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1967 gpa_t addr, int len,
1968 int is_write)
bbd9b64e
CO		 1969{
1970 struct kvm_io_device *dev;
1971
92760499 1972 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1973 if (dev == NULL)
92760499
LV		 1974 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1975 is_write);
bbd9b64e
CO		 1976 return dev;
1977}
1978
77c2002e
IE		 1979int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
1980 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 1981{
1982 void *data = val;
10589a46 1983 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1984
1985 while (bytes) {
ad312c7c 1986 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 1987 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 1988 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 1989 int ret;
1990
10589a46
MT		 1991 if (gpa == UNMAPPED_GVA) {
1992 r = X86EMUL_PROPAGATE_FAULT;
1993 goto out;
1994 }
77c2002e 1995 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 1996 if (ret < 0) {
1997 r = X86EMUL_UNHANDLEABLE;
1998 goto out;
1999 }
bbd9b64e 2000
77c2002e
IE		 2001 bytes -= toread;
2002 data += toread;
2003 addr += toread;
bbd9b64e 2004 }
10589a46 2005out:
10589a46 2006 return r;
bbd9b64e 2007}
77c2002e
IE		 2008
2009int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2010 struct kvm_vcpu *vcpu)
2011{
2012 void *data = val;
2013 int r = X86EMUL_CONTINUE;
2014
2015 while (bytes) {
2016 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2017 unsigned offset = addr & (PAGE_SIZE-1);
2018 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2019 int ret;
2020
2021 if (gpa == UNMAPPED_GVA) {
2022 r = X86EMUL_PROPAGATE_FAULT;
2023 goto out;
2024 }
2025 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2026 if (ret < 0) {
2027 r = X86EMUL_UNHANDLEABLE;
2028 goto out;
2029 }
2030
2031 bytes -= towrite;
2032 data += towrite;
2033 addr += towrite;
2034 }
2035out:
2036 return r;
2037}
2038
bbd9b64e 2039
bbd9b64e
CO		 2040static int emulator_read_emulated(unsigned long addr,
2041 void *val,
2042 unsigned int bytes,
2043 struct kvm_vcpu *vcpu)
2044{
2045 struct kvm_io_device *mmio_dev;
2046 gpa_t gpa;
2047
2048 if (vcpu->mmio_read_completed) {
2049 memcpy(val, vcpu->mmio_data, bytes);
2050 vcpu->mmio_read_completed = 0;
2051 return X86EMUL_CONTINUE;
2052 }
2053
ad312c7c 2054 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2055
2056 /* For APIC access vmexit */
2057 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2058 goto mmio;
2059
77c2002e
IE		 2060 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2061 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2062 return X86EMUL_CONTINUE;
2063 if (gpa == UNMAPPED_GVA)
2064 return X86EMUL_PROPAGATE_FAULT;
2065
2066mmio:
2067 /*
2068 * Is this MMIO handled locally?
2069 */
10589a46 2070 mutex_lock(&vcpu->kvm->lock);
92760499 2071 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2072 if (mmio_dev) {
2073 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2074 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2075 return X86EMUL_CONTINUE;
2076 }
10589a46 2077 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2078
2079 vcpu->mmio_needed = 1;
2080 vcpu->mmio_phys_addr = gpa;
2081 vcpu->mmio_size = bytes;
2082 vcpu->mmio_is_write = 0;
2083
2084 return X86EMUL_UNHANDLEABLE;
2085}
2086
3200f405 2087int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2088 const void *val, int bytes)
bbd9b64e
CO		 2089{
2090 int ret;
2091
2092 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2093 if (ret < 0)
bbd9b64e 2094 return 0;
ad218f85 2095 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2096 return 1;
2097}
2098
2099static int emulator_write_emulated_onepage(unsigned long addr,
2100 const void *val,
2101 unsigned int bytes,
2102 struct kvm_vcpu *vcpu)
2103{
2104 struct kvm_io_device *mmio_dev;
10589a46
MT		 2105 gpa_t gpa;
2106
10589a46 2107 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2108
2109 if (gpa == UNMAPPED_GVA) {
c3c91fee 2110 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2111 return X86EMUL_PROPAGATE_FAULT;
2112 }
2113
2114 /* For APIC access vmexit */
2115 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2116 goto mmio;
2117
2118 if (emulator_write_phys(vcpu, gpa, val, bytes))
2119 return X86EMUL_CONTINUE;
2120
2121mmio:
2122 /*
2123 * Is this MMIO handled locally?
2124 */
10589a46 2125 mutex_lock(&vcpu->kvm->lock);
92760499 2126 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2127 if (mmio_dev) {
2128 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2129 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2130 return X86EMUL_CONTINUE;
2131 }
10589a46 2132 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2133
2134 vcpu->mmio_needed = 1;
2135 vcpu->mmio_phys_addr = gpa;
2136 vcpu->mmio_size = bytes;
2137 vcpu->mmio_is_write = 1;
2138 memcpy(vcpu->mmio_data, val, bytes);
2139
2140 return X86EMUL_CONTINUE;
2141}
2142
2143int emulator_write_emulated(unsigned long addr,
2144 const void *val,
2145 unsigned int bytes,
2146 struct kvm_vcpu *vcpu)
2147{
2148 /* Crossing a page boundary? */
2149 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2150 int rc, now;
2151
2152 now = -addr & ~PAGE_MASK;
2153 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2154 if (rc != X86EMUL_CONTINUE)
2155 return rc;
2156 addr += now;
2157 val += now;
2158 bytes -= now;
2159 }
2160 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2161}
2162EXPORT_SYMBOL_GPL(emulator_write_emulated);
2163
2164static int emulator_cmpxchg_emulated(unsigned long addr,
2165 const void *old,
2166 const void *new,
2167 unsigned int bytes,
2168 struct kvm_vcpu *vcpu)
2169{
2170 static int reported;
2171
2172 if (!reported) {
2173 reported = 1;
2174 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2175 }
2bacc55c
MT		 2176#ifndef CONFIG_X86_64
2177 /* guests cmpxchg8b have to be emulated atomically */
2178 if (bytes == 8) {
10589a46 2179 gpa_t gpa;
2bacc55c 2180 struct page *page;
c0b49b0d 2181 char *kaddr;
2bacc55c
MT		 2182 u64 val;
2183
10589a46
MT		 2184 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2185
2bacc55c
MT		 2186 if (gpa == UNMAPPED_GVA ||
2187 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2188 goto emul_write;
2189
2190 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2191 goto emul_write;
2192
2193 val = *(u64 *)new;
72dc67a6 2194
2bacc55c 2195 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2196
c0b49b0d
AM		 2197 kaddr = kmap_atomic(page, KM_USER0);
2198 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2199 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2200 kvm_release_page_dirty(page);
2201 }
3200f405 2202emul_write:
2bacc55c
MT		 2203#endif
2204
bbd9b64e
CO		 2205 return emulator_write_emulated(addr, new, bytes, vcpu);
2206}
2207
2208static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2209{
2210 return kvm_x86_ops->get_segment_base(vcpu, seg);
2211}
2212
2213int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2214{
a7052897 2215 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2216 return X86EMUL_CONTINUE;
2217}
2218
2219int emulate_clts(struct kvm_vcpu *vcpu)
2220{
54e445ca 2221 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2222 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2223 return X86EMUL_CONTINUE;
2224}
2225
2226int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2227{
2228 struct kvm_vcpu *vcpu = ctxt->vcpu;
2229
2230 switch (dr) {
2231 case 0 ... 3:
2232 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2233 return X86EMUL_CONTINUE;
2234 default:
b8688d51 2235 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2236 return X86EMUL_UNHANDLEABLE;
2237 }
2238}
2239
2240int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2241{
2242 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2243 int exception;
2244
2245 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2246 if (exception) {
2247 /* FIXME: better handling */
2248 return X86EMUL_UNHANDLEABLE;
2249 }
2250 return X86EMUL_CONTINUE;
2251}
2252
2253void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2254{
bbd9b64e 2255 u8 opcodes[4];
5fdbf976 2256 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2257 unsigned long rip_linear;
2258
f76c710d 2259 if (!printk_ratelimit())
bbd9b64e
CO		 2260 return;
2261
25be4608
GC		 2262 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2263
77c2002e 2264 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2265
2266 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2267 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2268}
2269EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2270
14af3f3c 2271static struct x86_emulate_ops emulate_ops = {
77c2002e 2272 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2273 .read_emulated = emulator_read_emulated,
2274 .write_emulated = emulator_write_emulated,
2275 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2276};
2277
5fdbf976
MT		 2278static void cache_all_regs(struct kvm_vcpu *vcpu)
2279{
2280 kvm_register_read(vcpu, VCPU_REGS_RAX);
2281 kvm_register_read(vcpu, VCPU_REGS_RSP);
2282 kvm_register_read(vcpu, VCPU_REGS_RIP);
2283 vcpu->arch.regs_dirty = ~0;
2284}
2285
bbd9b64e
CO		 2286int emulate_instruction(struct kvm_vcpu *vcpu,
2287 struct kvm_run *run,
2288 unsigned long cr2,
2289 u16 error_code,
571008da 2290 int emulation_type)
bbd9b64e
CO		 2291{
2292 int r;
571008da 2293 struct decode_cache *c;
bbd9b64e 2294
26eef70c 2295 kvm_clear_exception_queue(vcpu);
ad312c7c 2296 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2297 /*
2298 * TODO: fix x86_emulate.c to use guest_read/write_register
2299 * instead of direct ->regs accesses, can save hundred cycles
2300 * on Intel for instructions that don't read/change RSP, for
2301 * for example.
2302 */
2303 cache_all_regs(vcpu);
bbd9b64e
CO		 2304
2305 vcpu->mmio_is_write = 0;
ad312c7c 2306 vcpu->arch.pio.string = 0;
bbd9b64e 2307
571008da 2308 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2309 int cs_db, cs_l;
2310 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2311
ad312c7c
ZX		 2312 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2313 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2314 vcpu->arch.emulate_ctxt.mode =
2315 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2316 ? X86EMUL_MODE_REAL : cs_l
2317 ? X86EMUL_MODE_PROT64 : cs_db
2318 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2319
ad312c7c 2320 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2321
2322 /* Reject the instructions other than VMCALL/VMMCALL when
2323 * try to emulate invalid opcode */
2324 c = &vcpu->arch.emulate_ctxt.decode;
2325 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2326 (!(c->twobyte && c->b == 0x01 &&
2327 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2328 c->modrm_mod == 3 && c->modrm_rm == 1)))
2329 return EMULATE_FAIL;
2330
f2b5756b 2331 ++vcpu->stat.insn_emulation;
bbd9b64e 2332 if (r) {
f2b5756b 2333 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2334 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2335 return EMULATE_DONE;
2336 return EMULATE_FAIL;
2337 }
2338 }
2339
ad312c7c 2340 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2341
ad312c7c 2342 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2343 return EMULATE_DO_MMIO;
2344
2345 if ((r || vcpu->mmio_is_write) && run) {
2346 run->exit_reason = KVM_EXIT_MMIO;
2347 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2348 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2349 run->mmio.len = vcpu->mmio_size;
2350 run->mmio.is_write = vcpu->mmio_is_write;
2351 }
2352
2353 if (r) {
2354 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2355 return EMULATE_DONE;
2356 if (!vcpu->mmio_needed) {
2357 kvm_report_emulation_failure(vcpu, "mmio");
2358 return EMULATE_FAIL;
2359 }
2360 return EMULATE_DO_MMIO;
2361 }
2362
ad312c7c 2363 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2364
2365 if (vcpu->mmio_is_write) {
2366 vcpu->mmio_needed = 0;
2367 return EMULATE_DO_MMIO;
2368 }
2369
2370 return EMULATE_DONE;
2371}
2372EXPORT_SYMBOL_GPL(emulate_instruction);
2373
de7d789a
CO		 2374static int pio_copy_data(struct kvm_vcpu *vcpu)
2375{
ad312c7c 2376 void *p = vcpu->arch.pio_data;
0f346074 2377 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2378 unsigned bytes;
0f346074 2379 int ret;
de7d789a 2380
ad312c7c
ZX		 2381 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2382 if (vcpu->arch.pio.in)
0f346074 2383 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2384 else
0f346074
IE		 2385 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2386 return ret;
de7d789a
CO		 2387}
2388
2389int complete_pio(struct kvm_vcpu *vcpu)
2390{
ad312c7c 2391 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2392 long delta;
2393 int r;
5fdbf976 2394 unsigned long val;
de7d789a
CO		 2395
2396 if (!io->string) {
5fdbf976
MT		 2397 if (io->in) {
2398 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2399 memcpy(&val, vcpu->arch.pio_data, io->size);
2400 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2401 }
de7d789a
CO		 2402 } else {
2403 if (io->in) {
2404 r = pio_copy_data(vcpu);
5fdbf976 2405 if (r)
de7d789a 2406 return r;
de7d789a
CO		 2407 }
2408
2409 delta = 1;
2410 if (io->rep) {
2411 delta *= io->cur_count;
2412 /*
2413 * The size of the register should really depend on
2414 * current address size.
2415 */
5fdbf976
MT		 2416 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2417 val -= delta;
2418 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2419 }
2420 if (io->down)
2421 delta = -delta;
2422 delta *= io->size;
5fdbf976
MT		 2423 if (io->in) {
2424 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2425 val += delta;
2426 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2427 } else {
2428 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2429 val += delta;
2430 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2431 }
de7d789a
CO		 2432 }
2433
de7d789a
CO		 2434 io->count -= io->cur_count;
2435 io->cur_count = 0;
2436
2437 return 0;
2438}
2439
2440static void kernel_pio(struct kvm_io_device *pio_dev,
2441 struct kvm_vcpu *vcpu,
2442 void *pd)
2443{
2444 /* TODO: String I/O for in kernel device */
2445
2446 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2447 if (vcpu->arch.pio.in)
2448 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2449 vcpu->arch.pio.size,
de7d789a
CO		 2450 pd);
2451 else
ad312c7c
ZX		 2452 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2453 vcpu->arch.pio.size,
de7d789a
CO		 2454 pd);
2455 mutex_unlock(&vcpu->kvm->lock);
2456}
2457
2458static void pio_string_write(struct kvm_io_device *pio_dev,
2459 struct kvm_vcpu *vcpu)
2460{
ad312c7c
ZX		 2461 struct kvm_pio_request *io = &vcpu->arch.pio;
2462 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2463 int i;
2464
2465 mutex_lock(&vcpu->kvm->lock);
2466 for (i = 0; i < io->cur_count; i++) {
2467 kvm_iodevice_write(pio_dev, io->port,
2468 io->size,
2469 pd);
2470 pd += io->size;
2471 }
2472 mutex_unlock(&vcpu->kvm->lock);
2473}
2474
2475static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2476 gpa_t addr, int len,
2477 int is_write)
de7d789a 2478{
92760499 2479 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2480}
2481
2482int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2483 int size, unsigned port)
2484{
2485 struct kvm_io_device *pio_dev;
5fdbf976 2486 unsigned long val;
de7d789a
CO		 2487
2488 vcpu->run->exit_reason = KVM_EXIT_IO;
2489 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2490 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2491 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2492 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2493 vcpu->run->io.port = vcpu->arch.pio.port = port;
2494 vcpu->arch.pio.in = in;
2495 vcpu->arch.pio.string = 0;
2496 vcpu->arch.pio.down = 0;
ad312c7c 2497 vcpu->arch.pio.rep = 0;
de7d789a 2498
2714d1d3
FEL		 2499 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2500 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2501 handler);
2502 else
2503 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2504 handler);
2505
5fdbf976
MT		 2506 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2507 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2508
92760499 2509 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2510 if (pio_dev) {
ad312c7c 2511 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2512 complete_pio(vcpu);
2513 return 1;
2514 }
2515 return 0;
2516}
2517EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2518
2519int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2520 int size, unsigned long count, int down,
2521 gva_t address, int rep, unsigned port)
2522{
2523 unsigned now, in_page;
0f346074 2524 int ret = 0;
de7d789a
CO		 2525 struct kvm_io_device *pio_dev;
2526
2527 vcpu->run->exit_reason = KVM_EXIT_IO;
2528 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2529 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2530 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2531 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2532 vcpu->run->io.port = vcpu->arch.pio.port = port;
2533 vcpu->arch.pio.in = in;
2534 vcpu->arch.pio.string = 1;
2535 vcpu->arch.pio.down = down;
ad312c7c 2536 vcpu->arch.pio.rep = rep;
de7d789a 2537
2714d1d3
FEL		 2538 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2539 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2540 handler);
2541 else
2542 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2543 handler);
2544
de7d789a
CO		 2545 if (!count) {
2546 kvm_x86_ops->skip_emulated_instruction(vcpu);
2547 return 1;
2548 }
2549
2550 if (!down)
2551 in_page = PAGE_SIZE - offset_in_page(address);
2552 else
2553 in_page = offset_in_page(address) + size;
2554 now = min(count, (unsigned long)in_page / size);
0f346074 2555 if (!now)
de7d789a 2556 now = 1;
de7d789a
CO		 2557 if (down) {
2558 /*
2559 * String I/O in reverse. Yuck. Kill the guest, fix later.
2560 */
2561 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2562 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2563 return 1;
2564 }
2565 vcpu->run->io.count = now;
ad312c7c 2566 vcpu->arch.pio.cur_count = now;
de7d789a 2567
ad312c7c 2568 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2569 kvm_x86_ops->skip_emulated_instruction(vcpu);
2570
0f346074 2571 vcpu->arch.pio.guest_gva = address;
de7d789a 2572
92760499
LV		 2573 pio_dev = vcpu_find_pio_dev(vcpu, port,
2574 vcpu->arch.pio.cur_count,
2575 !vcpu->arch.pio.in);
ad312c7c 2576 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2577 /* string PIO write */
2578 ret = pio_copy_data(vcpu);
0f346074
IE		 2579 if (ret == X86EMUL_PROPAGATE_FAULT) {
2580 kvm_inject_gp(vcpu, 0);
2581 return 1;
2582 }
2583 if (ret == 0 && pio_dev) {
de7d789a
CO		 2584 pio_string_write(pio_dev, vcpu);
2585 complete_pio(vcpu);
ad312c7c 2586 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2587 ret = 1;
2588 }
2589 } else if (pio_dev)
2590 pr_unimpl(vcpu, "no string pio read support yet, "
2591 "port %x size %d count %ld\n",
2592 port, size, count);
2593
2594 return ret;
2595}
2596EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2597
f8c16bba 2598int kvm_arch_init(void *opaque)
043405e1 2599{
56c6d28a 2600 int r;
f8c16bba
ZX		 2601 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2602
f8c16bba
ZX		 2603 if (kvm_x86_ops) {
2604 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2605 r = -EEXIST;
2606 goto out;
f8c16bba
ZX		 2607 }
2608
2609 if (!ops->cpu_has_kvm_support()) {
2610 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2611 r = -EOPNOTSUPP;
2612 goto out;
f8c16bba
ZX		 2613 }
2614 if (ops->disabled_by_bios()) {
2615 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2616 r = -EOPNOTSUPP;
2617 goto out;
f8c16bba
ZX		 2618 }
2619
97db56ce
AK		 2620 r = kvm_mmu_module_init();
2621 if (r)
2622 goto out;
2623
2624 kvm_init_msr_list();
2625
f8c16bba 2626 kvm_x86_ops = ops;
56c6d28a 2627 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2628 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2629 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2630 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2631 return 0;
56c6d28a
ZX		 2632
2633out:
56c6d28a 2634 return r;
043405e1 2635}
8776e519 2636
f8c16bba
ZX		 2637void kvm_arch_exit(void)
2638{
2639 kvm_x86_ops = NULL;
56c6d28a
ZX		 2640 kvm_mmu_module_exit();
2641}
f8c16bba 2642
8776e519
HB		 2643int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2644{
2645 ++vcpu->stat.halt_exits;
2714d1d3 2646 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2647 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2648 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2649 return 1;
2650 } else {
2651 vcpu->run->exit_reason = KVM_EXIT_HLT;
2652 return 0;
2653 }
2654}
2655EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2656
2f333bcb
MT		 2657static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2658 unsigned long a1)
2659{
2660 if (is_long_mode(vcpu))
2661 return a0;
2662 else
2663 return a0 | ((gpa_t)a1 << 32);
2664}
2665
8776e519
HB		 2666int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2667{
2668 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2669 int r = 1;
8776e519 2670
5fdbf976
MT		 2671 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2672 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2673 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2674 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2675 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2676
2714d1d3
FEL		 2677 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2678
8776e519
HB		 2679 if (!is_long_mode(vcpu)) {
2680 nr &= 0xFFFFFFFF;
2681 a0 &= 0xFFFFFFFF;
2682 a1 &= 0xFFFFFFFF;
2683 a2 &= 0xFFFFFFFF;
2684 a3 &= 0xFFFFFFFF;
2685 }
2686
2687 switch (nr) {
b93463aa
AK		 2688 case KVM_HC_VAPIC_POLL_IRQ:
2689 ret = 0;
2690 break;
2f333bcb
MT		 2691 case KVM_HC_MMU_OP:
2692 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2693 break;
8776e519
HB		 2694 default:
2695 ret = -KVM_ENOSYS;
2696 break;
2697 }
5fdbf976 2698 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2699 ++vcpu->stat.hypercalls;
2f333bcb 2700 return r;
8776e519
HB		 2701}
2702EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2703
2704int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2705{
2706 char instruction[3];
2707 int ret = 0;
5fdbf976 2708 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2709
8776e519
HB		 2710
2711 /*
2712 * Blow out the MMU to ensure that no other VCPU has an active mapping
2713 * to ensure that the updated hypercall appears atomically across all
2714 * VCPUs.
2715 */
2716 kvm_mmu_zap_all(vcpu->kvm);
2717
8776e519 2718 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2719 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2720 != X86EMUL_CONTINUE)
2721 ret = -EFAULT;
2722
8776e519
HB		 2723 return ret;
2724}
2725
2726static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2727{
2728 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2729}
2730
2731void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2732{
2733 struct descriptor_table dt = { limit, base };
2734
2735 kvm_x86_ops->set_gdt(vcpu, &dt);
2736}
2737
2738void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2739{
2740 struct descriptor_table dt = { limit, base };
2741
2742 kvm_x86_ops->set_idt(vcpu, &dt);
2743}
2744
2745void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2746 unsigned long *rflags)
2747{
2d3ad1f4 2748 kvm_lmsw(vcpu, msw);
8776e519
HB		 2749 *rflags = kvm_x86_ops->get_rflags(vcpu);
2750}
2751
2752unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2753{
54e445ca
JR		 2754 unsigned long value;
2755
8776e519
HB		 2756 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2757 switch (cr) {
2758 case 0:
54e445ca
JR		 2759 value = vcpu->arch.cr0;
2760 break;
8776e519 2761 case 2:
54e445ca
JR		 2762 value = vcpu->arch.cr2;
2763 break;
8776e519 2764 case 3:
54e445ca
JR		 2765 value = vcpu->arch.cr3;
2766 break;
8776e519 2767 case 4:
54e445ca
JR		 2768 value = vcpu->arch.cr4;
2769 break;
152ff9be 2770 case 8:
54e445ca
JR		 2771 value = kvm_get_cr8(vcpu);
2772 break;
8776e519 2773 default:
b8688d51 2774 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2775 return 0;
2776 }
54e445ca
JR		 2777 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2778 (u32)((u64)value >> 32), handler);
2779
2780 return value;
8776e519
HB		 2781}
2782
2783void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2784 unsigned long *rflags)
2785{
54e445ca
JR		 2786 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2787 (u32)((u64)val >> 32), handler);
2788
8776e519
HB		 2789 switch (cr) {
2790 case 0:
2d3ad1f4 2791 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2792 *rflags = kvm_x86_ops->get_rflags(vcpu);
2793 break;
2794 case 2:
ad312c7c 2795 vcpu->arch.cr2 = val;
8776e519
HB		 2796 break;
2797 case 3:
2d3ad1f4 2798 kvm_set_cr3(vcpu, val);
8776e519
HB		 2799 break;
2800 case 4:
2d3ad1f4 2801 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2802 break;
152ff9be 2803 case 8:
2d3ad1f4 2804 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2805 break;
8776e519 2806 default:
b8688d51 2807 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2808 }
2809}
2810
07716717
DK		 2811static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2812{
ad312c7c
ZX		 2813 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2814 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2815
2816 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2817 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2818 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2819 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2820 if (ej->function == e->function) {
2821 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2822 return j;
2823 }
2824 }
2825 return 0; /* silence gcc, even though control never reaches here */
2826}
2827
2828/* find an entry with matching function, matching index (if needed), and that
2829 * should be read next (if it's stateful) */
2830static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2831 u32 function, u32 index)
2832{
2833 if (e->function != function)
2834 return 0;
2835 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2836 return 0;
2837 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2838 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2839 return 0;
2840 return 1;
2841}
2842
d8017474
AG		 2843struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2844 u32 function, u32 index)
8776e519
HB		 2845{
2846 int i;
d8017474 2847 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2848
ad312c7c 2849 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2850 struct kvm_cpuid_entry2 *e;
2851
ad312c7c 2852 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2853 if (is_matching_cpuid_entry(e, function, index)) {
2854 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2855 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2856 best = e;
2857 break;
2858 }
2859 /*
2860 * Both basic or both extended?
2861 */
2862 if (((e->function ^ function) & 0x80000000) == 0)
2863 if (!best || e->function > best->function)
2864 best = e;
2865 }
d8017474
AG		 2866
2867 return best;
2868}
2869
2870void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2871{
2872 u32 function, index;
2873 struct kvm_cpuid_entry2 *best;
2874
2875 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2876 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2877 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2878 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2879 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2880 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
2881 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 2882 if (best) {
5fdbf976
MT		 2883 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2884 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2885 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2886 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2887 }
8776e519 2888 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2889 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2890 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2891 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2892 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2893 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2894}
2895EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2896
b6c7a5dc
HB		 2897/*
2898 * Check if userspace requested an interrupt window, and that the
2899 * interrupt window is open.
2900 *
2901 * No need to exit to userspace if we already have an interrupt queued.
2902 */
2903static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2904 struct kvm_run *kvm_run)
2905{
ad312c7c 2906 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2907 kvm_run->request_interrupt_window &&
ad312c7c 2908 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2909 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2910}
2911
2912static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2913 struct kvm_run *kvm_run)
2914{
2915 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2916 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2917 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 2918 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2919 kvm_run->ready_for_interrupt_injection = 1;
4531220b 2920 else
b6c7a5dc 2921 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2922 (vcpu->arch.interrupt_window_open &&
2923 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2924}
2925
b93463aa
AK		 2926static void vapic_enter(struct kvm_vcpu *vcpu)
2927{
2928 struct kvm_lapic *apic = vcpu->arch.apic;
2929 struct page *page;
2930
2931 if (!apic || !apic->vapic_addr)
2932 return;
2933
2934 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2935
2936 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2937}
2938
2939static void vapic_exit(struct kvm_vcpu *vcpu)
2940{
2941 struct kvm_lapic *apic = vcpu->arch.apic;
2942
2943 if (!apic || !apic->vapic_addr)
2944 return;
2945
f8b78fa3 2946 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2947 kvm_release_page_dirty(apic->vapic_page);
2948 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2949 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2950}
2951
d7690175 2952static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2953{
2954 int r;
2955
2e53d63a
MT		 2956 if (vcpu->requests)
2957 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2958 kvm_mmu_unload(vcpu);
2959
b6c7a5dc
HB		 2960 r = kvm_mmu_reload(vcpu);
2961 if (unlikely(r))
2962 goto out;
2963
2f52d58c
AK		 2964 if (vcpu->requests) {
2965 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2966 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 2967 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
2968 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 2969 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2970 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2971 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2972 &vcpu->requests)) {
2973 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2974 r = 0;
2975 goto out;
2976 }
71c4dfaf
JR		 2977 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2978 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2979 r = 0;
2980 goto out;
2981 }
2f52d58c 2982 }
b93463aa 2983
06e05645 2984 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2985 kvm_inject_pending_timer_irqs(vcpu);
2986
2987 preempt_disable();
2988
2989 kvm_x86_ops->prepare_guest_switch(vcpu);
2990 kvm_load_guest_fpu(vcpu);
2991
2992 local_irq_disable();
2993
d7690175 2994 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 2995 local_irq_enable();
2996 preempt_enable();
2997 r = 1;
2998 goto out;
2999 }
3000
e9571ed5
MT		 3001 vcpu->guest_mode = 1;
3002 /*
3003 * Make sure that guest_mode assignment won't happen after
3004 * testing the pending IRQ vector bitmap.
3005 */
3006 smp_wmb();
3007
ad312c7c 3008 if (vcpu->arch.exception.pending)
298101da
AK		 3009 __queue_exception(vcpu);
3010 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3011 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3012 else
b6c7a5dc
HB		 3013 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3014
b93463aa
AK		 3015 kvm_lapic_sync_to_vapic(vcpu);
3016
3200f405
MT		 3017 up_read(&vcpu->kvm->slots_lock);
3018
b6c7a5dc
HB		 3019 kvm_guest_enter();
3020
42dbaa5a
JK		 3021 get_debugreg(vcpu->arch.host_dr6, 6);
3022 get_debugreg(vcpu->arch.host_dr7, 7);
3023 if (unlikely(vcpu->arch.switch_db_regs)) {
3024 get_debugreg(vcpu->arch.host_db[0], 0);
3025 get_debugreg(vcpu->arch.host_db[1], 1);
3026 get_debugreg(vcpu->arch.host_db[2], 2);
3027 get_debugreg(vcpu->arch.host_db[3], 3);
3028
3029 set_debugreg(0, 7);
3030 set_debugreg(vcpu->arch.eff_db[0], 0);
3031 set_debugreg(vcpu->arch.eff_db[1], 1);
3032 set_debugreg(vcpu->arch.eff_db[2], 2);
3033 set_debugreg(vcpu->arch.eff_db[3], 3);
3034 }
b6c7a5dc 3035
2714d1d3 3036 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3037 kvm_x86_ops->run(vcpu, kvm_run);
3038
42dbaa5a
JK		 3039 if (unlikely(vcpu->arch.switch_db_regs)) {
3040 set_debugreg(0, 7);
3041 set_debugreg(vcpu->arch.host_db[0], 0);
3042 set_debugreg(vcpu->arch.host_db[1], 1);
3043 set_debugreg(vcpu->arch.host_db[2], 2);
3044 set_debugreg(vcpu->arch.host_db[3], 3);
3045 }
3046 set_debugreg(vcpu->arch.host_dr6, 6);
3047 set_debugreg(vcpu->arch.host_dr7, 7);
3048
b6c7a5dc
HB		 3049 vcpu->guest_mode = 0;
3050 local_irq_enable();
3051
3052 ++vcpu->stat.exits;
3053
3054 /*
3055 * We must have an instruction between local_irq_enable() and
3056 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3057 * the interrupt shadow. The stat.exits increment will do nicely.
3058 * But we need to prevent reordering, hence this barrier():
3059 */
3060 barrier();
3061
3062 kvm_guest_exit();
3063
3064 preempt_enable();
3065
3200f405
MT		 3066 down_read(&vcpu->kvm->slots_lock);
3067
b6c7a5dc
HB		 3068 /*
3069 * Profile KVM exit RIPs:
3070 */
3071 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3072 unsigned long rip = kvm_rip_read(vcpu);
3073 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3074 }
3075
ad312c7c
ZX		 3076 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3077 vcpu->arch.exception.pending = false;
298101da 3078
b93463aa
AK		 3079 kvm_lapic_sync_from_vapic(vcpu);
3080
b6c7a5dc 3081 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3082out:
3083 return r;
3084}
b6c7a5dc 3085
d7690175
MT		 3086static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3087{
3088 int r;
3089
3090 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3091 pr_debug("vcpu %d received sipi with vector # %x\n",
3092 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3093 kvm_lapic_reset(vcpu);
5f179287 3094 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3095 if (r)
3096 return r;
3097 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3098 }
3099
d7690175
MT		 3100 down_read(&vcpu->kvm->slots_lock);
3101 vapic_enter(vcpu);
3102
3103 r = 1;
3104 while (r > 0) {
af2152f5 3105 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3106 r = vcpu_enter_guest(vcpu, kvm_run);
3107 else {
3108 up_read(&vcpu->kvm->slots_lock);
3109 kvm_vcpu_block(vcpu);
3110 down_read(&vcpu->kvm->slots_lock);
3111 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3112 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3113 vcpu->arch.mp_state =
3114 KVM_MP_STATE_RUNNABLE;
3115 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3116 r = -EINTR;
3117 }
3118
3119 if (r > 0) {
3120 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3121 r = -EINTR;
3122 kvm_run->exit_reason = KVM_EXIT_INTR;
3123 ++vcpu->stat.request_irq_exits;
3124 }
3125 if (signal_pending(current)) {
3126 r = -EINTR;
3127 kvm_run->exit_reason = KVM_EXIT_INTR;
3128 ++vcpu->stat.signal_exits;
3129 }
3130 if (need_resched()) {
3131 up_read(&vcpu->kvm->slots_lock);
3132 kvm_resched(vcpu);
3133 down_read(&vcpu->kvm->slots_lock);
3134 }
3135 }
b6c7a5dc
HB		 3136 }
3137
d7690175 3138 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3139 post_kvm_run_save(vcpu, kvm_run);
3140
b93463aa
AK		 3141 vapic_exit(vcpu);
3142
b6c7a5dc
HB		 3143 return r;
3144}
3145
3146int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3147{
3148 int r;
3149 sigset_t sigsaved;
3150
3151 vcpu_load(vcpu);
3152
ac9f6dc0
AK		 3153 if (vcpu->sigset_active)
3154 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3155
a4535290 3156 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3157 kvm_vcpu_block(vcpu);
d7690175 3158 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3159 r = -EAGAIN;
3160 goto out;
b6c7a5dc
HB		 3161 }
3162
b6c7a5dc
HB		 3163 /* re-sync apic's tpr */
3164 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3165 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3166
ad312c7c 3167 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3168 r = complete_pio(vcpu);
3169 if (r)
3170 goto out;
3171 }
3172#if CONFIG_HAS_IOMEM
3173 if (vcpu->mmio_needed) {
3174 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3175 vcpu->mmio_read_completed = 1;
3176 vcpu->mmio_needed = 0;
3200f405
MT		 3177
3178 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3179 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3180 vcpu->arch.mmio_fault_cr2, 0,
3181 EMULTYPE_NO_DECODE);
3200f405 3182 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3183 if (r == EMULATE_DO_MMIO) {
3184 /*
3185 * Read-modify-write. Back to userspace.
3186 */
3187 r = 0;
3188 goto out;
3189 }
3190 }
3191#endif
5fdbf976
MT		 3192 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3193 kvm_register_write(vcpu, VCPU_REGS_RAX,
3194 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3195
3196 r = __vcpu_run(vcpu, kvm_run);
3197
3198out:
3199 if (vcpu->sigset_active)
3200 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3201
3202 vcpu_put(vcpu);
3203 return r;
3204}
3205
3206int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3207{
3208 vcpu_load(vcpu);
3209
5fdbf976
MT		 3210 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3211 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3212 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3213 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3214 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3215 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3216 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3217 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3218#ifdef CONFIG_X86_64
5fdbf976
MT		 3219 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3220 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3221 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3222 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3223 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3224 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3225 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3226 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3227#endif
3228
5fdbf976 3229 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3230 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3231
3232 /*
3233 * Don't leak debug flags in case they were set for guest debugging
3234 */
d0bfb940 3235 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3236 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3237
3238 vcpu_put(vcpu);
3239
3240 return 0;
3241}
3242
3243int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3244{
3245 vcpu_load(vcpu);
3246
5fdbf976
MT		 3247 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3248 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3249 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3250 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3251 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3252 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3253 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3254 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3255#ifdef CONFIG_X86_64
5fdbf976
MT		 3256 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3257 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3258 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3259 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3260 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3261 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3262 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3263 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3264
b6c7a5dc
HB		 3265#endif
3266
5fdbf976 3267 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3268 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3269
b6c7a5dc 3270
b4f14abd
JK		 3271 vcpu->arch.exception.pending = false;
3272
b6c7a5dc
HB		 3273 vcpu_put(vcpu);
3274
3275 return 0;
3276}
3277
3e6e0aab
GT		 3278void kvm_get_segment(struct kvm_vcpu *vcpu,
3279 struct kvm_segment *var, int seg)
b6c7a5dc 3280{
14af3f3c 3281 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3282}
3283
3284void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3285{
3286 struct kvm_segment cs;
3287
3e6e0aab 3288 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3289 *db = cs.db;
3290 *l = cs.l;
3291}
3292EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3293
3294int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3295 struct kvm_sregs *sregs)
3296{
3297 struct descriptor_table dt;
3298 int pending_vec;
3299
3300 vcpu_load(vcpu);
3301
3e6e0aab
GT		 3302 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3303 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3304 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3305 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3306 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3307 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3308
3e6e0aab
GT		 3309 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3310 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3311
3312 kvm_x86_ops->get_idt(vcpu, &dt);
3313 sregs->idt.limit = dt.limit;
3314 sregs->idt.base = dt.base;
3315 kvm_x86_ops->get_gdt(vcpu, &dt);
3316 sregs->gdt.limit = dt.limit;
3317 sregs->gdt.base = dt.base;
3318
3319 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3320 sregs->cr0 = vcpu->arch.cr0;
3321 sregs->cr2 = vcpu->arch.cr2;
3322 sregs->cr3 = vcpu->arch.cr3;
3323 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3324 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3325 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3326 sregs->apic_base = kvm_get_apic_base(vcpu);
3327
3328 if (irqchip_in_kernel(vcpu->kvm)) {
3329 memset(sregs->interrupt_bitmap, 0,
3330 sizeof sregs->interrupt_bitmap);
3331 pending_vec = kvm_x86_ops->get_irq(vcpu);
3332 if (pending_vec >= 0)
3333 set_bit(pending_vec,
3334 (unsigned long *)sregs->interrupt_bitmap);
3335 } else
ad312c7c 3336 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3337 sizeof sregs->interrupt_bitmap);
3338
3339 vcpu_put(vcpu);
3340
3341 return 0;
3342}
3343
62d9f0db
MT		 3344int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3345 struct kvm_mp_state *mp_state)
3346{
3347 vcpu_load(vcpu);
3348 mp_state->mp_state = vcpu->arch.mp_state;
3349 vcpu_put(vcpu);
3350 return 0;
3351}
3352
3353int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3354 struct kvm_mp_state *mp_state)
3355{
3356 vcpu_load(vcpu);
3357 vcpu->arch.mp_state = mp_state->mp_state;
3358 vcpu_put(vcpu);
3359 return 0;
3360}
3361
3e6e0aab 3362static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3363 struct kvm_segment *var, int seg)
3364{
14af3f3c 3365 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3366}
3367
37817f29
IE		 3368static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3369 struct kvm_segment *kvm_desct)
3370{
3371 kvm_desct->base = seg_desc->base0;
3372 kvm_desct->base |= seg_desc->base1 << 16;
3373 kvm_desct->base |= seg_desc->base2 << 24;
3374 kvm_desct->limit = seg_desc->limit0;
3375 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3376 if (seg_desc->g) {
3377 kvm_desct->limit <<= 12;
3378 kvm_desct->limit |= 0xfff;
3379 }
37817f29
IE		 3380 kvm_desct->selector = selector;
3381 kvm_desct->type = seg_desc->type;
3382 kvm_desct->present = seg_desc->p;
3383 kvm_desct->dpl = seg_desc->dpl;
3384 kvm_desct->db = seg_desc->d;
3385 kvm_desct->s = seg_desc->s;
3386 kvm_desct->l = seg_desc->l;
3387 kvm_desct->g = seg_desc->g;
3388 kvm_desct->avl = seg_desc->avl;
3389 if (!selector)
3390 kvm_desct->unusable = 1;
3391 else
3392 kvm_desct->unusable = 0;
3393 kvm_desct->padding = 0;
3394}
3395
b8222ad2
AS		 3396static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3397 u16 selector,
3398 struct descriptor_table *dtable)
37817f29
IE		 3399{
3400 if (selector & 1 << 2) {
3401 struct kvm_segment kvm_seg;
3402
3e6e0aab 3403 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3404
3405 if (kvm_seg.unusable)
3406 dtable->limit = 0;
3407 else
3408 dtable->limit = kvm_seg.limit;
3409 dtable->base = kvm_seg.base;
3410 }
3411 else
3412 kvm_x86_ops->get_gdt(vcpu, dtable);
3413}
3414
3415/* allowed just for 8 bytes segments */
3416static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3417 struct desc_struct *seg_desc)
3418{
98899aa0 3419 gpa_t gpa;
37817f29
IE		 3420 struct descriptor_table dtable;
3421 u16 index = selector >> 3;
3422
b8222ad2 3423 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3424
3425 if (dtable.limit < index * 8 + 7) {
3426 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3427 return 1;
3428 }
98899aa0
MT		 3429 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3430 gpa += index * 8;
3431 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3432}
3433
3434/* allowed just for 8 bytes segments */
3435static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3436 struct desc_struct *seg_desc)
3437{
98899aa0 3438 gpa_t gpa;
37817f29
IE		 3439 struct descriptor_table dtable;
3440 u16 index = selector >> 3;
3441
b8222ad2 3442 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3443
3444 if (dtable.limit < index * 8 + 7)
3445 return 1;
98899aa0
MT		 3446 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3447 gpa += index * 8;
3448 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3449}
3450
3451static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3452 struct desc_struct *seg_desc)
3453{
3454 u32 base_addr;
3455
3456 base_addr = seg_desc->base0;
3457 base_addr |= (seg_desc->base1 << 16);
3458 base_addr |= (seg_desc->base2 << 24);
3459
98899aa0 3460 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3461}
3462
37817f29
IE		 3463static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3464{
3465 struct kvm_segment kvm_seg;
3466
3e6e0aab 3467 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3468 return kvm_seg.selector;
3469}
3470
3471static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3472 u16 selector,
3473 struct kvm_segment *kvm_seg)
3474{
3475 struct desc_struct seg_desc;
3476
3477 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3478 return 1;
3479 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3480 return 0;
3481}
3482
2259e3a7 3483static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3484{
3485 struct kvm_segment segvar = {
3486 .base = selector << 4,
3487 .limit = 0xffff,
3488 .selector = selector,
3489 .type = 3,
3490 .present = 1,
3491 .dpl = 3,
3492 .db = 0,
3493 .s = 1,
3494 .l = 0,
3495 .g = 0,
3496 .avl = 0,
3497 .unusable = 0,
3498 };
3499 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3500 return 0;
3501}
3502
3e6e0aab
GT		 3503int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3504 int type_bits, int seg)
37817f29
IE		 3505{
3506 struct kvm_segment kvm_seg;
3507
f4bbd9aa
AK		 3508 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3509 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3510 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3511 return 1;
3512 kvm_seg.type |= type_bits;
3513
3514 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3515 seg != VCPU_SREG_LDTR)
3516 if (!kvm_seg.s)
3517 kvm_seg.unusable = 1;
3518
3e6e0aab 3519 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3520 return 0;
3521}
3522
3523static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3524 struct tss_segment_32 *tss)
3525{
3526 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3527 tss->eip = kvm_rip_read(vcpu);
37817f29 3528 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3529 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3530 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3531 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3532 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3533 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3534 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3535 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3536 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3537 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3538 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3539 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3540 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3541 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3542 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3543 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3544 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3545}
3546
3547static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3548 struct tss_segment_32 *tss)
3549{
3550 kvm_set_cr3(vcpu, tss->cr3);
3551
5fdbf976 3552 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3553 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3554
5fdbf976
MT		 3555 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3556 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3557 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3558 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3559 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3560 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3561 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3562 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3563
3e6e0aab 3564 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3565 return 1;
3566
3e6e0aab 3567 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3568 return 1;
3569
3e6e0aab 3570 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3571 return 1;
3572
3e6e0aab 3573 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3574 return 1;
3575
3e6e0aab 3576 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3577 return 1;
3578
3e6e0aab 3579 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3580 return 1;
3581
3e6e0aab 3582 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3583 return 1;
3584 return 0;
3585}
3586
3587static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3588 struct tss_segment_16 *tss)
3589{
5fdbf976 3590 tss->ip = kvm_rip_read(vcpu);
37817f29 3591 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3592 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3593 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3594 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3595 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3596 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3597 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3598 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3599 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3600
3601 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3602 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3603 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3604 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3605 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3606 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3607}
3608
3609static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3610 struct tss_segment_16 *tss)
3611{
5fdbf976 3612 kvm_rip_write(vcpu, tss->ip);
37817f29 3613 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3614 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3615 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3616 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3617 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3618 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3619 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3620 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3621 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3622
3e6e0aab 3623 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3624 return 1;
3625
3e6e0aab 3626 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3627 return 1;
3628
3e6e0aab 3629 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3630 return 1;
3631
3e6e0aab 3632 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3633 return 1;
3634
3e6e0aab 3635 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3636 return 1;
3637 return 0;
3638}
3639
8b2cf73c 3640static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3641 u32 old_tss_base,
37817f29
IE		 3642 struct desc_struct *nseg_desc)
3643{
3644 struct tss_segment_16 tss_segment_16;
3645 int ret = 0;
3646
34198bf8
MT		 3647 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3648 sizeof tss_segment_16))
37817f29
IE		 3649 goto out;
3650
3651 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3652
34198bf8
MT		 3653 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3654 sizeof tss_segment_16))
37817f29 3655 goto out;
34198bf8
MT		 3656
3657 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3658 &tss_segment_16, sizeof tss_segment_16))
3659 goto out;
3660
37817f29
IE		 3661 if (load_state_from_tss16(vcpu, &tss_segment_16))
3662 goto out;
3663
3664 ret = 1;
3665out:
3666 return ret;
3667}
3668
8b2cf73c 3669static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3670 u32 old_tss_base,
37817f29
IE		 3671 struct desc_struct *nseg_desc)
3672{
3673 struct tss_segment_32 tss_segment_32;
3674 int ret = 0;
3675
34198bf8
MT		 3676 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3677 sizeof tss_segment_32))
37817f29
IE		 3678 goto out;
3679
3680 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3681
34198bf8
MT		 3682 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3683 sizeof tss_segment_32))
3684 goto out;
3685
3686 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3687 &tss_segment_32, sizeof tss_segment_32))
37817f29 3688 goto out;
34198bf8 3689
37817f29
IE		 3690 if (load_state_from_tss32(vcpu, &tss_segment_32))
3691 goto out;
3692
3693 ret = 1;
3694out:
3695 return ret;
3696}
3697
3698int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3699{
3700 struct kvm_segment tr_seg;
3701 struct desc_struct cseg_desc;
3702 struct desc_struct nseg_desc;
3703 int ret = 0;
34198bf8
MT		 3704 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3705 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3706
34198bf8 3707 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3708
34198bf8
MT		 3709 /* FIXME: Handle errors. Failure to read either TSS or their
3710 * descriptors should generate a pagefault.
3711 */
37817f29
IE		 3712 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3713 goto out;
3714
34198bf8 3715 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3716 goto out;
3717
37817f29
IE		 3718 if (reason != TASK_SWITCH_IRET) {
3719 int cpl;
3720
3721 cpl = kvm_x86_ops->get_cpl(vcpu);
3722 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3723 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3724 return 1;
3725 }
3726 }
3727
3728 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3729 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3730 return 1;
3731 }
3732
3733 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3734 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3735 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3736 }
3737
3738 if (reason == TASK_SWITCH_IRET) {
3739 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3740 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3741 }
3742
3743 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3744
3745 if (nseg_desc.type & 8)
34198bf8 3746 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3747 &nseg_desc);
3748 else
34198bf8 3749 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3750 &nseg_desc);
3751
3752 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3753 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3754 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3755 }
3756
3757 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3758 nseg_desc.type |= (1 << 1);
37817f29
IE		 3759 save_guest_segment_descriptor(vcpu, tss_selector,
3760 &nseg_desc);
3761 }
3762
3763 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3764 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3765 tr_seg.type = 11;
3e6e0aab 3766 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3767out:
37817f29
IE		 3768 return ret;
3769}
3770EXPORT_SYMBOL_GPL(kvm_task_switch);
3771
b6c7a5dc
HB		 3772int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3773 struct kvm_sregs *sregs)
3774{
3775 int mmu_reset_needed = 0;
3776 int i, pending_vec, max_bits;
3777 struct descriptor_table dt;
3778
3779 vcpu_load(vcpu);
3780
3781 dt.limit = sregs->idt.limit;
3782 dt.base = sregs->idt.base;
3783 kvm_x86_ops->set_idt(vcpu, &dt);
3784 dt.limit = sregs->gdt.limit;
3785 dt.base = sregs->gdt.base;
3786 kvm_x86_ops->set_gdt(vcpu, &dt);
3787
ad312c7c
ZX		 3788 vcpu->arch.cr2 = sregs->cr2;
3789 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3790 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3791
2d3ad1f4 3792 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3793
ad312c7c 3794 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3795 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3796 kvm_set_apic_base(vcpu, sregs->apic_base);
3797
3798 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3799
ad312c7c 3800 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3801 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3802 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3803
ad312c7c 3804 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3805 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3806 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3807 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3808
3809 if (mmu_reset_needed)
3810 kvm_mmu_reset_context(vcpu);
3811
3812 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3813 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3814 sizeof vcpu->arch.irq_pending);
3815 vcpu->arch.irq_summary = 0;
3816 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3817 if (vcpu->arch.irq_pending[i])
3818 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3819 } else {
3820 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3821 pending_vec = find_first_bit(
3822 (const unsigned long *)sregs->interrupt_bitmap,
3823 max_bits);
3824 /* Only pending external irq is handled here */
3825 if (pending_vec < max_bits) {
3826 kvm_x86_ops->set_irq(vcpu, pending_vec);
3827 pr_debug("Set back pending irq %d\n",
3828 pending_vec);
3829 }
e4825800 3830 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3831 }
3832
3e6e0aab
GT		 3833 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3834 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3835 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3836 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3837 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3838 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3839
3e6e0aab
GT		 3840 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3841 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3842
9c3e4aab
MT		 3843 /* Older userspace won't unhalt the vcpu on reset. */
3844 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3845 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3846 !(vcpu->arch.cr0 & X86_CR0_PE))
3847 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3848
b6c7a5dc
HB		 3849 vcpu_put(vcpu);
3850
3851 return 0;
3852}
3853
d0bfb940
JK		 3854int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
3855 struct kvm_guest_debug *dbg)
b6c7a5dc 3856{
ae675ef0 3857 int i, r;
b6c7a5dc
HB		 3858
3859 vcpu_load(vcpu);
3860
ae675ef0
JK		 3861 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
3862 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
3863 for (i = 0; i < KVM_NR_DB_REGS; ++i)
3864 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
3865 vcpu->arch.switch_db_regs =
3866 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
3867 } else {
3868 for (i = 0; i < KVM_NR_DB_REGS; i++)
3869 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
3870 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
3871 }
3872
b6c7a5dc
HB		 3873 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3874
d0bfb940
JK		 3875 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
3876 kvm_queue_exception(vcpu, DB_VECTOR);
3877 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
3878 kvm_queue_exception(vcpu, BP_VECTOR);
3879
b6c7a5dc
HB		 3880 vcpu_put(vcpu);
3881
3882 return r;
3883}
3884
d0752060
HB		 3885/*
3886 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3887 * we have asm/x86/processor.h
3888 */
3889struct fxsave {
3890 u16 cwd;
3891 u16 swd;
3892 u16 twd;
3893 u16 fop;
3894 u64 rip;
3895 u64 rdp;
3896 u32 mxcsr;
3897 u32 mxcsr_mask;
3898 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3899#ifdef CONFIG_X86_64
3900 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3901#else
3902 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3903#endif
3904};
3905
8b006791
ZX		 3906/*
3907 * Translate a guest virtual address to a guest physical address.
3908 */
3909int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3910 struct kvm_translation *tr)
3911{
3912 unsigned long vaddr = tr->linear_address;
3913 gpa_t gpa;
3914
3915 vcpu_load(vcpu);
72dc67a6 3916 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3917 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3918 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3919 tr->physical_address = gpa;
3920 tr->valid = gpa != UNMAPPED_GVA;
3921 tr->writeable = 1;
3922 tr->usermode = 0;
8b006791
ZX		 3923 vcpu_put(vcpu);
3924
3925 return 0;
3926}
3927
d0752060
HB		 3928int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3929{
ad312c7c 3930 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3931
3932 vcpu_load(vcpu);
3933
3934 memcpy(fpu->fpr, fxsave->st_space, 128);
3935 fpu->fcw = fxsave->cwd;
3936 fpu->fsw = fxsave->swd;
3937 fpu->ftwx = fxsave->twd;
3938 fpu->last_opcode = fxsave->fop;
3939 fpu->last_ip = fxsave->rip;
3940 fpu->last_dp = fxsave->rdp;
3941 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3942
3943 vcpu_put(vcpu);
3944
3945 return 0;
3946}
3947
3948int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3949{
ad312c7c 3950 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3951
3952 vcpu_load(vcpu);
3953
3954 memcpy(fxsave->st_space, fpu->fpr, 128);
3955 fxsave->cwd = fpu->fcw;
3956 fxsave->swd = fpu->fsw;
3957 fxsave->twd = fpu->ftwx;
3958 fxsave->fop = fpu->last_opcode;
3959 fxsave->rip = fpu->last_ip;
3960 fxsave->rdp = fpu->last_dp;
3961 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3962
3963 vcpu_put(vcpu);
3964
3965 return 0;
3966}
3967
3968void fx_init(struct kvm_vcpu *vcpu)
3969{
3970 unsigned after_mxcsr_mask;
3971
bc1a34f1
AA		 3972 /*
3973 * Touch the fpu the first time in non atomic context as if
3974 * this is the first fpu instruction the exception handler
3975 * will fire before the instruction returns and it'll have to
3976 * allocate ram with GFP_KERNEL.
3977 */
3978 if (!used_math())
d6e88aec 3979 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3980
d0752060
HB		 3981 /* Initialize guest FPU by resetting ours and saving into guest's */
3982 preempt_disable();
d6e88aec
AK		 3983 kvm_fx_save(&vcpu->arch.host_fx_image);
3984 kvm_fx_finit();
3985 kvm_fx_save(&vcpu->arch.guest_fx_image);
3986 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3987 preempt_enable();
3988
ad312c7c 3989 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3990 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3991 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3992 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3993 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3994}
3995EXPORT_SYMBOL_GPL(fx_init);
3996
3997void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3998{
3999 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4000 return;
4001
4002 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4003 kvm_fx_save(&vcpu->arch.host_fx_image);
4004 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4005}
4006EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4007
4008void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4009{
4010 if (!vcpu->guest_fpu_loaded)
4011 return;
4012
4013 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4014 kvm_fx_save(&vcpu->arch.guest_fx_image);
4015 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4016 ++vcpu->stat.fpu_reload;
d0752060
HB		 4017}
4018EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4019
4020void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4021{
4022 kvm_x86_ops->vcpu_free(vcpu);
4023}
4024
4025struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4026 unsigned int id)
4027{
26e5215f
AK		 4028 return kvm_x86_ops->vcpu_create(kvm, id);
4029}
e9b11c17 4030
26e5215f
AK		 4031int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4032{
4033 int r;
e9b11c17
ZX		 4034
4035 /* We do fxsave: this must be aligned. */
ad312c7c 4036 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4037
0bed3b56 4038 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4039 vcpu_load(vcpu);
4040 r = kvm_arch_vcpu_reset(vcpu);
4041 if (r == 0)
4042 r = kvm_mmu_setup(vcpu);
4043 vcpu_put(vcpu);
4044 if (r < 0)
4045 goto free_vcpu;
4046
26e5215f 4047 return 0;
e9b11c17
ZX		 4048free_vcpu:
4049 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4050 return r;
e9b11c17
ZX		 4051}
4052
d40ccc62 4053void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4054{
4055 vcpu_load(vcpu);
4056 kvm_mmu_unload(vcpu);
4057 vcpu_put(vcpu);
4058
4059 kvm_x86_ops->vcpu_free(vcpu);
4060}
4061
4062int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4063{
448fa4a9
JK		 4064 vcpu->arch.nmi_pending = false;
4065 vcpu->arch.nmi_injected = false;
4066
42dbaa5a
JK		 4067 vcpu->arch.switch_db_regs = 0;
4068 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4069 vcpu->arch.dr6 = DR6_FIXED_1;
4070 vcpu->arch.dr7 = DR7_FIXED_1;
4071
e9b11c17
ZX		 4072 return kvm_x86_ops->vcpu_reset(vcpu);
4073}
4074
4075void kvm_arch_hardware_enable(void *garbage)
4076{
4077 kvm_x86_ops->hardware_enable(garbage);
4078}
4079
4080void kvm_arch_hardware_disable(void *garbage)
4081{
4082 kvm_x86_ops->hardware_disable(garbage);
4083}
4084
4085int kvm_arch_hardware_setup(void)
4086{
4087 return kvm_x86_ops->hardware_setup();
4088}
4089
4090void kvm_arch_hardware_unsetup(void)
4091{
4092 kvm_x86_ops->hardware_unsetup();
4093}
4094
4095void kvm_arch_check_processor_compat(void *rtn)
4096{
4097 kvm_x86_ops->check_processor_compatibility(rtn);
4098}
4099
4100int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4101{
4102 struct page *page;
4103 struct kvm *kvm;
4104 int r;
4105
4106 BUG_ON(vcpu->kvm == NULL);
4107 kvm = vcpu->kvm;
4108
ad312c7c 4109 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4110 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4111 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4112 else
a4535290 4113 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4114
4115 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4116 if (!page) {
4117 r = -ENOMEM;
4118 goto fail;
4119 }
ad312c7c 4120 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4121
4122 r = kvm_mmu_create(vcpu);
4123 if (r < 0)
4124 goto fail_free_pio_data;
4125
4126 if (irqchip_in_kernel(kvm)) {
4127 r = kvm_create_lapic(vcpu);
4128 if (r < 0)
4129 goto fail_mmu_destroy;
4130 }
4131
4132 return 0;
4133
4134fail_mmu_destroy:
4135 kvm_mmu_destroy(vcpu);
4136fail_free_pio_data:
ad312c7c 4137 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4138fail:
4139 return r;
4140}
4141
4142void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4143{
4144 kvm_free_lapic(vcpu);
3200f405 4145 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4146 kvm_mmu_destroy(vcpu);
3200f405 4147 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4148 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4149}
d19a9cd2
ZX		 4150
4151struct kvm *kvm_arch_create_vm(void)
4152{
4153 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4154
4155 if (!kvm)
4156 return ERR_PTR(-ENOMEM);
4157
f05e70ac 4158 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4159 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4160 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4161
5550af4d
SY		 4162 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4163 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4164
53f658b3
MT		 4165 rdtscll(kvm->arch.vm_init_tsc);
4166
d19a9cd2
ZX		 4167 return kvm;
4168}
4169
4170static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4171{
4172 vcpu_load(vcpu);
4173 kvm_mmu_unload(vcpu);
4174 vcpu_put(vcpu);
4175}
4176
4177static void kvm_free_vcpus(struct kvm *kvm)
4178{
4179 unsigned int i;
4180
4181 /*
4182 * Unpin any mmu pages first.
4183 */
4184 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4185 if (kvm->vcpus[i])
4186 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4187 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4188 if (kvm->vcpus[i]) {
4189 kvm_arch_vcpu_free(kvm->vcpus[i]);
4190 kvm->vcpus[i] = NULL;
4191 }
4192 }
4193
4194}
4195
ad8ba2cd
SY		 4196void kvm_arch_sync_events(struct kvm *kvm)
4197{
ba4cef31 4198 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4199}
4200
d19a9cd2
ZX		 4201void kvm_arch_destroy_vm(struct kvm *kvm)
4202{
6eb55818 4203 kvm_iommu_unmap_guest(kvm);
7837699f 4204 kvm_free_pit(kvm);
d7deeeb0
ZX		 4205 kfree(kvm->arch.vpic);
4206 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4207 kvm_free_vcpus(kvm);
4208 kvm_free_physmem(kvm);
3d45830c
AK		 4209 if (kvm->arch.apic_access_page)
4210 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4211 if (kvm->arch.ept_identity_pagetable)
4212 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4213 kfree(kvm);
4214}
0de10343
ZX		 4215
4216int kvm_arch_set_memory_region(struct kvm *kvm,
4217 struct kvm_userspace_memory_region *mem,
4218 struct kvm_memory_slot old,
4219 int user_alloc)
4220{
4221 int npages = mem->memory_size >> PAGE_SHIFT;
4222 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4223
4224 /*To keep backward compatibility with older userspace,
4225 *x86 needs to hanlde !user_alloc case.
4226 */
4227 if (!user_alloc) {
4228 if (npages && !old.rmap) {
604b38ac
AA		 4229 unsigned long userspace_addr;
4230
72dc67a6 4231 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4232 userspace_addr = do_mmap(NULL, 0,
4233 npages * PAGE_SIZE,
4234 PROT_READ | PROT_WRITE,
acee3c04 4235 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4236 0);
72dc67a6 4237 up_write(&current->mm->mmap_sem);
0de10343 4238
604b38ac
AA		 4239 if (IS_ERR((void *)userspace_addr))
4240 return PTR_ERR((void *)userspace_addr);
4241
4242 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4243 spin_lock(&kvm->mmu_lock);
4244 memslot->userspace_addr = userspace_addr;
4245 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4246 } else {
4247 if (!old.user_alloc && old.rmap) {
4248 int ret;
4249
72dc67a6 4250 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4251 ret = do_munmap(current->mm, old.userspace_addr,
4252 old.npages * PAGE_SIZE);
72dc67a6 4253 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4254 if (ret < 0)
4255 printk(KERN_WARNING
4256 "kvm_vm_ioctl_set_memory_region: "
4257 "failed to munmap memory\n");
4258 }
4259 }
4260 }
4261
f05e70ac 4262 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4263 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4264 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4265 }
4266
4267 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4268 kvm_flush_remote_tlbs(kvm);
4269
4270 return 0;
4271}
1d737c8a 4272
34d4cb8f
MT		 4273void kvm_arch_flush_shadow(struct kvm *kvm)
4274{
4275 kvm_mmu_zap_all(kvm);
4276}
4277
1d737c8a
ZX		 4278int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4279{
a4535290 4280 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4281 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4282 || vcpu->arch.nmi_pending;
1d737c8a 4283}
5736199a
ZX		 4284
4285static void vcpu_kick_intr(void *info)
4286{
4287#ifdef DEBUG
4288 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4289 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4290#endif
4291}
4292
4293void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4294{
4295 int ipi_pcpu = vcpu->cpu;
e9571ed5 4296 int cpu = get_cpu();
5736199a
ZX		 4297
4298 if (waitqueue_active(&vcpu->wq)) {
4299 wake_up_interruptible(&vcpu->wq);
4300 ++vcpu->stat.halt_wakeup;
4301 }
e9571ed5
MT		 4302 /*
4303 * We may be called synchronously with irqs disabled in guest mode,
4304 * So need not to call smp_call_function_single() in that case.
4305 */
4306 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4307 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4308 put_cpu();
5736199a 4309}
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