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KVM: x86 emulator: make set_cr() callback return error if it fails
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
0f12244f 417static int __kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
f9a48e6a
AK		 419 cr0 |= X86_CR0_ET;
420
ab344828 421#ifdef CONFIG_X86_64
0f12244f
GN		 422 if (cr0 & 0xffffffff00000000UL)
423 return 1;
ab344828
GN		 424#endif
425
426 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 427
0f12244f
GN		 428 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
429 return 1;
a03490ed 430
0f12244f
GN		 431 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
432 return 1;
a03490ed
CO		 433
434 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
435#ifdef CONFIG_X86_64
f6801dff 436 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 437 int cs_db, cs_l;
438
0f12244f
GN		 439 if (!is_pae(vcpu))
440 return 1;
a03490ed 441 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 442 if (cs_l)
443 return 1;
a03490ed
CO		 444 } else
445#endif
0f12244f
GN		 446 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
447 return 1;
a03490ed
CO		 448 }
449
450 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 451
a03490ed 452 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 453 return 0;
454}
455
456void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
457{
458 if (__kvm_set_cr0(vcpu, cr0))
459 kvm_inject_gp(vcpu, 0);
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 462
2d3ad1f4 463void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 464{
f78e9176 465 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 466}
2d3ad1f4 467EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 468
0f12244f 469int __kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 470{
fc78f519 471 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 472 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
473
0f12244f
GN		 474 if (cr4 & CR4_RESERVED_BITS)
475 return 1;
a03490ed
CO		 476
477 if (is_long_mode(vcpu)) {
0f12244f
GN		 478 if (!(cr4 & X86_CR4_PAE))
479 return 1;
a2edf57f
AK		 480 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
481 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 482 && !load_pdptrs(vcpu, vcpu->arch.cr3))
483 return 1;
484
485 if (cr4 & X86_CR4_VMXE)
486 return 1;
a03490ed 487
a03490ed 488 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 489 vcpu->arch.cr4 = cr4;
a03490ed 490 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 491
492 return 0;
493}
494
495void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
496{
497 if (__kvm_set_cr4(vcpu, cr4))
498 kvm_inject_gp(vcpu, 0);
a03490ed 499}
2d3ad1f4 500EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 501
0f12244f 502static int __kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 503{
ad312c7c 504 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 505 kvm_mmu_sync_roots(vcpu);
d835dfec 506 kvm_mmu_flush_tlb(vcpu);
0f12244f 507 return 0;
d835dfec
AK		 508 }
509
a03490ed 510 if (is_long_mode(vcpu)) {
0f12244f
GN		 511 if (cr3 & CR3_L_MODE_RESERVED_BITS)
512 return 1;
a03490ed
CO		 513 } else {
514 if (is_pae(vcpu)) {
0f12244f
GN		 515 if (cr3 & CR3_PAE_RESERVED_BITS)
516 return 1;
517 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
518 return 1;
a03490ed
CO		 519 }
520 /*
521 * We don't check reserved bits in nonpae mode, because
522 * this isn't enforced, and VMware depends on this.
523 */
524 }
525
a03490ed
CO		 526 /*
527 * Does the new cr3 value map to physical memory? (Note, we
528 * catch an invalid cr3 even in real-mode, because it would
529 * cause trouble later on when we turn on paging anyway.)
530 *
531 * A real CPU would silently accept an invalid cr3 and would
532 * attempt to use it - with largely undefined (and often hard
533 * to debug) behavior on the guest side.
534 */
535 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 536 return 1;
537 vcpu->arch.cr3 = cr3;
538 vcpu->arch.mmu.new_cr3(vcpu);
539 return 0;
540}
541
542void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
543{
544 if (__kvm_set_cr3(vcpu, cr3))
c1a5d4f9 545 kvm_inject_gp(vcpu, 0);
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 548
0f12244f 549int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 550{
0f12244f
GN		 551 if (cr8 & CR8_RESERVED_BITS)
552 return 1;
a03490ed
CO		 553 if (irqchip_in_kernel(vcpu->kvm))
554 kvm_lapic_set_tpr(vcpu, cr8);
555 else
ad312c7c 556 vcpu->arch.cr8 = cr8;
0f12244f
GN		 557 return 0;
558}
559
560void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
561{
562 if (__kvm_set_cr8(vcpu, cr8))
563 kvm_inject_gp(vcpu, 0);
a03490ed 564}
2d3ad1f4 565EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 566
2d3ad1f4 567unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 568{
569 if (irqchip_in_kernel(vcpu->kvm))
570 return kvm_lapic_get_cr8(vcpu);
571 else
ad312c7c 572 return vcpu->arch.cr8;
a03490ed 573}
2d3ad1f4 574EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 575
020df079
GN		 576int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
577{
578 switch (dr) {
579 case 0 ... 3:
580 vcpu->arch.db[dr] = val;
581 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
582 vcpu->arch.eff_db[dr] = val;
583 break;
584 case 4:
585 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
586 kvm_queue_exception(vcpu, UD_VECTOR);
587 return 1;
588 }
589 /* fall through */
590 case 6:
591 if (val & 0xffffffff00000000ULL) {
592 kvm_inject_gp(vcpu, 0);
593 return 1;
594 }
595 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
596 break;
597 case 5:
598 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
599 kvm_queue_exception(vcpu, UD_VECTOR);
600 return 1;
601 }
602 /* fall through */
603 default: /* 7 */
604 if (val & 0xffffffff00000000ULL) {
605 kvm_inject_gp(vcpu, 0);
606 return 1;
607 }
608 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
609 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
610 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
611 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
612 }
613 break;
614 }
615
616 return 0;
617}
618EXPORT_SYMBOL_GPL(kvm_set_dr);
619
620int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
621{
622 switch (dr) {
623 case 0 ... 3:
624 *val = vcpu->arch.db[dr];
625 break;
626 case 4:
627 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
628 kvm_queue_exception(vcpu, UD_VECTOR);
629 return 1;
630 }
631 /* fall through */
632 case 6:
633 *val = vcpu->arch.dr6;
634 break;
635 case 5:
636 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
637 kvm_queue_exception(vcpu, UD_VECTOR);
638 return 1;
639 }
640 /* fall through */
641 default: /* 7 */
642 *val = vcpu->arch.dr7;
643 break;
644 }
645
646 return 0;
647}
648EXPORT_SYMBOL_GPL(kvm_get_dr);
649
d8017474
AG		 650static inline u32 bit(int bitno)
651{
652 return 1 << (bitno & 31);
653}
654
043405e1
CO		 655/*
656 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
657 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
658 *
659 * This list is modified at module load time to reflect the
e3267cbb
GC		 660 * capabilities of the host cpu. This capabilities test skips MSRs that are
661 * kvm-specific. Those are put in the beginning of the list.
043405e1 662 */
e3267cbb 663
11c6bffa 664#define KVM_SAVE_MSRS_BEGIN 7
043405e1 665static u32 msrs_to_save[] = {
e3267cbb 666 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 667 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 668 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 669 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 670 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
671 MSR_K6_STAR,
672#ifdef CONFIG_X86_64
673 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
674#endif
e3267cbb 675 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 676};
677
678static unsigned num_msrs_to_save;
679
680static u32 emulated_msrs[] = {
681 MSR_IA32_MISC_ENABLE,
682};
683
b69e8cae 684static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 685{
b69e8cae
RJ		 686 if (efer & efer_reserved_bits)
687 return 1;
15c4a640
CO		 688
689 if (is_paging(vcpu)
b69e8cae
RJ		 690 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
691 return 1;
15c4a640 692
1b2fd70c
AG		 693 if (efer & EFER_FFXSR) {
694 struct kvm_cpuid_entry2 *feat;
695
696 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 697 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
698 return 1;
1b2fd70c
AG		 699 }
700
d8017474
AG		 701 if (efer & EFER_SVME) {
702 struct kvm_cpuid_entry2 *feat;
703
704 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 705 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
706 return 1;
d8017474
AG		 707 }
708
15c4a640 709 efer &= ~EFER_LMA;
f6801dff 710 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 711
a3d204e2
SY		 712 kvm_x86_ops->set_efer(vcpu, efer);
713
f6801dff 714 vcpu->arch.efer = efer;
9645bb56
AK		 715
716 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
717 kvm_mmu_reset_context(vcpu);
b69e8cae
RJ		 718
719 return 0;
15c4a640
CO		 720}
721
f2b4b7dd
JR		 722void kvm_enable_efer_bits(u64 mask)
723{
724 efer_reserved_bits &= ~mask;
725}
726EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
727
728
15c4a640
CO		 729/*
730 * Writes msr value into into the appropriate "register".
731 * Returns 0 on success, non-0 otherwise.
732 * Assumes vcpu_load() was already called.
733 */
734int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
735{
736 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
737}
738
313a3dc7
CO		 739/*
740 * Adapt set_msr() to msr_io()'s calling convention
741 */
742static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
743{
744 return kvm_set_msr(vcpu, index, *data);
745}
746
18068523
GOC		 747static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
748{
9ed3c444
AK		 749 int version;
750 int r;
50d0a0f9 751 struct pvclock_wall_clock wc;
923de3cf 752 struct timespec boot;
18068523
GOC		 753
754 if (!wall_clock)
755 return;
756
9ed3c444
AK		 757 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
758 if (r)
759 return;
760
761 if (version & 1)
762 ++version; /* first time write, random junk */
763
764 ++version;
18068523 765
18068523
GOC		 766 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
767
50d0a0f9
GH		 768 /*
769 * The guest calculates current wall clock time by adding
770 * system time (updated by kvm_write_guest_time below) to the
771 * wall clock specified here. guest system time equals host
772 * system time for us, thus we must fill in host boot time here.
773 */
923de3cf 774 getboottime(&boot);
50d0a0f9
GH		 775
776 wc.sec = boot.tv_sec;
777 wc.nsec = boot.tv_nsec;
778 wc.version = version;
18068523
GOC		 779
780 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
781
782 version++;
783 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 784}
785
50d0a0f9
GH		 786static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
787{
788 uint32_t quotient, remainder;
789
790 /* Don't try to replace with do_div(), this one calculates
791 * "(dividend << 32) / divisor" */
792 __asm__ ( "divl %4"
793 : "=a" (quotient), "=d" (remainder)
794 : "0" (0), "1" (dividend), "r" (divisor) );
795 return quotient;
796}
797
798static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
799{
800 uint64_t nsecs = 1000000000LL;
801 int32_t shift = 0;
802 uint64_t tps64;
803 uint32_t tps32;
804
805 tps64 = tsc_khz * 1000LL;
806 while (tps64 > nsecs*2) {
807 tps64 >>= 1;
808 shift--;
809 }
810
811 tps32 = (uint32_t)tps64;
812 while (tps32 <= (uint32_t)nsecs) {
813 tps32 <<= 1;
814 shift++;
815 }
816
817 hv_clock->tsc_shift = shift;
818 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
819
820 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 821 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 822 hv_clock->tsc_to_system_mul);
823}
824
c8076604
GH		 825static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
826
18068523
GOC		 827static void kvm_write_guest_time(struct kvm_vcpu *v)
828{
829 struct timespec ts;
830 unsigned long flags;
831 struct kvm_vcpu_arch *vcpu = &v->arch;
832 void *shared_kaddr;
463656c0 833 unsigned long this_tsc_khz;
18068523
GOC		 834
835 if ((!vcpu->time_page))
836 return;
837
463656c0
AK		 838 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
839 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
840 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
841 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 842 }
463656c0 843 put_cpu_var(cpu_tsc_khz);
50d0a0f9 844
18068523
GOC		 845 /* Keep irq disabled to prevent changes to the clock */
846 local_irq_save(flags);
af24a4e4 847 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 848 ktime_get_ts(&ts);
923de3cf 849 monotonic_to_bootbased(&ts);
18068523
GOC		 850 local_irq_restore(flags);
851
852 /* With all the info we got, fill in the values */
853
854 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 855 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
856
371bcf64
GC		 857 vcpu->hv_clock.flags = 0;
858
18068523
GOC		 859 /*
860 * The interface expects us to write an even number signaling that the
861 * update is finished. Since the guest won't see the intermediate
50d0a0f9 862 * state, we just increase by 2 at the end.
18068523 863 */
50d0a0f9 864 vcpu->hv_clock.version += 2;
18068523
GOC		 865
866 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
867
868 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 869 sizeof(vcpu->hv_clock));
18068523
GOC		 870
871 kunmap_atomic(shared_kaddr, KM_USER0);
872
873 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
874}
875
c8076604
GH		 876static int kvm_request_guest_time_update(struct kvm_vcpu *v)
877{
878 struct kvm_vcpu_arch *vcpu = &v->arch;
879
880 if (!vcpu->time_page)
881 return 0;
882 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
883 return 1;
884}
885
9ba075a6
AK		 886static bool msr_mtrr_valid(unsigned msr)
887{
888 switch (msr) {
889 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
890 case MSR_MTRRfix64K_00000:
891 case MSR_MTRRfix16K_80000:
892 case MSR_MTRRfix16K_A0000:
893 case MSR_MTRRfix4K_C0000:
894 case MSR_MTRRfix4K_C8000:
895 case MSR_MTRRfix4K_D0000:
896 case MSR_MTRRfix4K_D8000:
897 case MSR_MTRRfix4K_E0000:
898 case MSR_MTRRfix4K_E8000:
899 case MSR_MTRRfix4K_F0000:
900 case MSR_MTRRfix4K_F8000:
901 case MSR_MTRRdefType:
902 case MSR_IA32_CR_PAT:
903 return true;
904 case 0x2f8:
905 return true;
906 }
907 return false;
908}
909
d6289b93
MT		 910static bool valid_pat_type(unsigned t)
911{
912 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
913}
914
915static bool valid_mtrr_type(unsigned t)
916{
917 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
918}
919
920static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
921{
922 int i;
923
924 if (!msr_mtrr_valid(msr))
925 return false;
926
927 if (msr == MSR_IA32_CR_PAT) {
928 for (i = 0; i < 8; i++)
929 if (!valid_pat_type((data >> (i * 8)) & 0xff))
930 return false;
931 return true;
932 } else if (msr == MSR_MTRRdefType) {
933 if (data & ~0xcff)
934 return false;
935 return valid_mtrr_type(data & 0xff);
936 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
937 for (i = 0; i < 8 ; i++)
938 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
939 return false;
940 return true;
941 }
942
943 /* variable MTRRs */
944 return valid_mtrr_type(data & 0xff);
945}
946
9ba075a6
AK		 947static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
948{
0bed3b56
SY		 949 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
950
d6289b93 951 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 952 return 1;
953
0bed3b56
SY		 954 if (msr == MSR_MTRRdefType) {
955 vcpu->arch.mtrr_state.def_type = data;
956 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
957 } else if (msr == MSR_MTRRfix64K_00000)
958 p[0] = data;
959 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
960 p[1 + msr - MSR_MTRRfix16K_80000] = data;
961 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
962 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
963 else if (msr == MSR_IA32_CR_PAT)
964 vcpu->arch.pat = data;
965 else { /* Variable MTRRs */
966 int idx, is_mtrr_mask;
967 u64 *pt;
968
969 idx = (msr - 0x200) / 2;
970 is_mtrr_mask = msr - 0x200 - 2 * idx;
971 if (!is_mtrr_mask)
972 pt =
973 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
974 else
975 pt =
976 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
977 *pt = data;
978 }
979
980 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 981 return 0;
982}
15c4a640 983
890ca9ae 984static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 985{
890ca9ae
HY		 986 u64 mcg_cap = vcpu->arch.mcg_cap;
987 unsigned bank_num = mcg_cap & 0xff;
988
15c4a640 989 switch (msr) {
15c4a640 990 case MSR_IA32_MCG_STATUS:
890ca9ae 991 vcpu->arch.mcg_status = data;
15c4a640 992 break;
c7ac679c 993 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 994 if (!(mcg_cap & MCG_CTL_P))
995 return 1;
996 if (data != 0 && data != ~(u64)0)
997 return -1;
998 vcpu->arch.mcg_ctl = data;
999 break;
1000 default:
1001 if (msr >= MSR_IA32_MC0_CTL &&
1002 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1003 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1004 /* only 0 or all 1s can be written to IA32_MCi_CTL
1005 * some Linux kernels though clear bit 10 in bank 4 to
1006 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1007 * this to avoid an uncatched #GP in the guest
1008 */
890ca9ae 1009 if ((offset & 0x3) == 0 &&
114be429 1010 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1011 return -1;
1012 vcpu->arch.mce_banks[offset] = data;
1013 break;
1014 }
1015 return 1;
1016 }
1017 return 0;
1018}
1019
ffde22ac
ES		 1020static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1021{
1022 struct kvm *kvm = vcpu->kvm;
1023 int lm = is_long_mode(vcpu);
1024 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1025 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1026 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1027 : kvm->arch.xen_hvm_config.blob_size_32;
1028 u32 page_num = data & ~PAGE_MASK;
1029 u64 page_addr = data & PAGE_MASK;
1030 u8 *page;
1031 int r;
1032
1033 r = -E2BIG;
1034 if (page_num >= blob_size)
1035 goto out;
1036 r = -ENOMEM;
1037 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1038 if (!page)
1039 goto out;
1040 r = -EFAULT;
1041 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1042 goto out_free;
1043 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1044 goto out_free;
1045 r = 0;
1046out_free:
1047 kfree(page);
1048out:
1049 return r;
1050}
1051
55cd8e5a
GN		 1052static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1053{
1054 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1055}
1056
1057static bool kvm_hv_msr_partition_wide(u32 msr)
1058{
1059 bool r = false;
1060 switch (msr) {
1061 case HV_X64_MSR_GUEST_OS_ID:
1062 case HV_X64_MSR_HYPERCALL:
1063 r = true;
1064 break;
1065 }
1066
1067 return r;
1068}
1069
1070static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1071{
1072 struct kvm *kvm = vcpu->kvm;
1073
1074 switch (msr) {
1075 case HV_X64_MSR_GUEST_OS_ID:
1076 kvm->arch.hv_guest_os_id = data;
1077 /* setting guest os id to zero disables hypercall page */
1078 if (!kvm->arch.hv_guest_os_id)
1079 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1080 break;
1081 case HV_X64_MSR_HYPERCALL: {
1082 u64 gfn;
1083 unsigned long addr;
1084 u8 instructions[4];
1085
1086 /* if guest os id is not set hypercall should remain disabled */
1087 if (!kvm->arch.hv_guest_os_id)
1088 break;
1089 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1090 kvm->arch.hv_hypercall = data;
1091 break;
1092 }
1093 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1094 addr = gfn_to_hva(kvm, gfn);
1095 if (kvm_is_error_hva(addr))
1096 return 1;
1097 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1098 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1099 if (copy_to_user((void __user *)addr, instructions, 4))
1100 return 1;
1101 kvm->arch.hv_hypercall = data;
1102 break;
1103 }
1104 default:
1105 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1106 "data 0x%llx\n", msr, data);
1107 return 1;
1108 }
1109 return 0;
1110}
1111
1112static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1113{
10388a07
GN		 1114 switch (msr) {
1115 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1116 unsigned long addr;
55cd8e5a 1117
10388a07
GN		 1118 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1119 vcpu->arch.hv_vapic = data;
1120 break;
1121 }
1122 addr = gfn_to_hva(vcpu->kvm, data >>
1123 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1124 if (kvm_is_error_hva(addr))
1125 return 1;
1126 if (clear_user((void __user *)addr, PAGE_SIZE))
1127 return 1;
1128 vcpu->arch.hv_vapic = data;
1129 break;
1130 }
1131 case HV_X64_MSR_EOI:
1132 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1133 case HV_X64_MSR_ICR:
1134 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1135 case HV_X64_MSR_TPR:
1136 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1137 default:
1138 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1139 "data 0x%llx\n", msr, data);
1140 return 1;
1141 }
1142
1143 return 0;
55cd8e5a
GN		 1144}
1145
15c4a640
CO		 1146int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1147{
1148 switch (msr) {
15c4a640 1149 case MSR_EFER:
b69e8cae 1150 return set_efer(vcpu, data);
8f1589d9
AP		 1151 case MSR_K7_HWCR:
1152 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1153 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1154 if (data != 0) {
1155 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1156 data);
1157 return 1;
1158 }
15c4a640 1159 break;
f7c6d140
AP		 1160 case MSR_FAM10H_MMIO_CONF_BASE:
1161 if (data != 0) {
1162 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1163 "0x%llx\n", data);
1164 return 1;
1165 }
15c4a640 1166 break;
c323c0e5 1167 case MSR_AMD64_NB_CFG:
c7ac679c 1168 break;
b5e2fec0
AG		 1169 case MSR_IA32_DEBUGCTLMSR:
1170 if (!data) {
1171 /* We support the non-activated case already */
1172 break;
1173 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1174 /* Values other than LBR and BTF are vendor-specific,
1175 thus reserved and should throw a #GP */
1176 return 1;
1177 }
1178 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1179 __func__, data);
1180 break;
15c4a640
CO		 1181 case MSR_IA32_UCODE_REV:
1182 case MSR_IA32_UCODE_WRITE:
61a6bd67 1183 case MSR_VM_HSAVE_PA:
6098ca93 1184 case MSR_AMD64_PATCH_LOADER:
15c4a640 1185 break;
9ba075a6
AK		 1186 case 0x200 ... 0x2ff:
1187 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1188 case MSR_IA32_APICBASE:
1189 kvm_set_apic_base(vcpu, data);
1190 break;
0105d1a5
GN		 1191 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1192 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1193 case MSR_IA32_MISC_ENABLE:
ad312c7c 1194 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1195 break;
11c6bffa 1196 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1197 case MSR_KVM_WALL_CLOCK:
1198 vcpu->kvm->arch.wall_clock = data;
1199 kvm_write_wall_clock(vcpu->kvm, data);
1200 break;
11c6bffa 1201 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1202 case MSR_KVM_SYSTEM_TIME: {
1203 if (vcpu->arch.time_page) {
1204 kvm_release_page_dirty(vcpu->arch.time_page);
1205 vcpu->arch.time_page = NULL;
1206 }
1207
1208 vcpu->arch.time = data;
1209
1210 /* we verify if the enable bit is set... */
1211 if (!(data & 1))
1212 break;
1213
1214 /* ...but clean it before doing the actual write */
1215 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1216
18068523
GOC		 1217 vcpu->arch.time_page =
1218 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1219
1220 if (is_error_page(vcpu->arch.time_page)) {
1221 kvm_release_page_clean(vcpu->arch.time_page);
1222 vcpu->arch.time_page = NULL;
1223 }
1224
c8076604 1225 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1226 break;
1227 }
890ca9ae
HY		 1228 case MSR_IA32_MCG_CTL:
1229 case MSR_IA32_MCG_STATUS:
1230 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1231 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1232
1233 /* Performance counters are not protected by a CPUID bit,
1234 * so we should check all of them in the generic path for the sake of
1235 * cross vendor migration.
1236 * Writing a zero into the event select MSRs disables them,
1237 * which we perfectly emulate ;-). Any other value should be at least
1238 * reported, some guests depend on them.
1239 */
1240 case MSR_P6_EVNTSEL0:
1241 case MSR_P6_EVNTSEL1:
1242 case MSR_K7_EVNTSEL0:
1243 case MSR_K7_EVNTSEL1:
1244 case MSR_K7_EVNTSEL2:
1245 case MSR_K7_EVNTSEL3:
1246 if (data != 0)
1247 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1248 "0x%x data 0x%llx\n", msr, data);
1249 break;
1250 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1251 * so we ignore writes to make it happy.
1252 */
1253 case MSR_P6_PERFCTR0:
1254 case MSR_P6_PERFCTR1:
1255 case MSR_K7_PERFCTR0:
1256 case MSR_K7_PERFCTR1:
1257 case MSR_K7_PERFCTR2:
1258 case MSR_K7_PERFCTR3:
1259 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1260 "0x%x data 0x%llx\n", msr, data);
1261 break;
55cd8e5a
GN		 1262 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1263 if (kvm_hv_msr_partition_wide(msr)) {
1264 int r;
1265 mutex_lock(&vcpu->kvm->lock);
1266 r = set_msr_hyperv_pw(vcpu, msr, data);
1267 mutex_unlock(&vcpu->kvm->lock);
1268 return r;
1269 } else
1270 return set_msr_hyperv(vcpu, msr, data);
1271 break;
15c4a640 1272 default:
ffde22ac
ES		 1273 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1274 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1275 if (!ignore_msrs) {
1276 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1277 msr, data);
1278 return 1;
1279 } else {
1280 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1281 msr, data);
1282 break;
1283 }
15c4a640
CO		 1284 }
1285 return 0;
1286}
1287EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1288
1289
1290/*
1291 * Reads an msr value (of 'msr_index') into 'pdata'.
1292 * Returns 0 on success, non-0 otherwise.
1293 * Assumes vcpu_load() was already called.
1294 */
1295int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1296{
1297 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1298}
1299
9ba075a6
AK		 1300static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1301{
0bed3b56
SY		 1302 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1303
9ba075a6
AK		 1304 if (!msr_mtrr_valid(msr))
1305 return 1;
1306
0bed3b56
SY		 1307 if (msr == MSR_MTRRdefType)
1308 *pdata = vcpu->arch.mtrr_state.def_type +
1309 (vcpu->arch.mtrr_state.enabled << 10);
1310 else if (msr == MSR_MTRRfix64K_00000)
1311 *pdata = p[0];
1312 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1313 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1314 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1315 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1316 else if (msr == MSR_IA32_CR_PAT)
1317 *pdata = vcpu->arch.pat;
1318 else { /* Variable MTRRs */
1319 int idx, is_mtrr_mask;
1320 u64 *pt;
1321
1322 idx = (msr - 0x200) / 2;
1323 is_mtrr_mask = msr - 0x200 - 2 * idx;
1324 if (!is_mtrr_mask)
1325 pt =
1326 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1327 else
1328 pt =
1329 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1330 *pdata = *pt;
1331 }
1332
9ba075a6
AK		 1333 return 0;
1334}
1335
890ca9ae 1336static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1337{
1338 u64 data;
890ca9ae
HY		 1339 u64 mcg_cap = vcpu->arch.mcg_cap;
1340 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1341
1342 switch (msr) {
15c4a640
CO		 1343 case MSR_IA32_P5_MC_ADDR:
1344 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1345 data = 0;
1346 break;
15c4a640 1347 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1348 data = vcpu->arch.mcg_cap;
1349 break;
c7ac679c 1350 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1351 if (!(mcg_cap & MCG_CTL_P))
1352 return 1;
1353 data = vcpu->arch.mcg_ctl;
1354 break;
1355 case MSR_IA32_MCG_STATUS:
1356 data = vcpu->arch.mcg_status;
1357 break;
1358 default:
1359 if (msr >= MSR_IA32_MC0_CTL &&
1360 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1361 u32 offset = msr - MSR_IA32_MC0_CTL;
1362 data = vcpu->arch.mce_banks[offset];
1363 break;
1364 }
1365 return 1;
1366 }
1367 *pdata = data;
1368 return 0;
1369}
1370
55cd8e5a
GN		 1371static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1372{
1373 u64 data = 0;
1374 struct kvm *kvm = vcpu->kvm;
1375
1376 switch (msr) {
1377 case HV_X64_MSR_GUEST_OS_ID:
1378 data = kvm->arch.hv_guest_os_id;
1379 break;
1380 case HV_X64_MSR_HYPERCALL:
1381 data = kvm->arch.hv_hypercall;
1382 break;
1383 default:
1384 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1385 return 1;
1386 }
1387
1388 *pdata = data;
1389 return 0;
1390}
1391
1392static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1393{
1394 u64 data = 0;
1395
1396 switch (msr) {
1397 case HV_X64_MSR_VP_INDEX: {
1398 int r;
1399 struct kvm_vcpu *v;
1400 kvm_for_each_vcpu(r, v, vcpu->kvm)
1401 if (v == vcpu)
1402 data = r;
1403 break;
1404 }
10388a07
GN		 1405 case HV_X64_MSR_EOI:
1406 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1407 case HV_X64_MSR_ICR:
1408 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1409 case HV_X64_MSR_TPR:
1410 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1411 default:
1412 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1413 return 1;
1414 }
1415 *pdata = data;
1416 return 0;
1417}
1418
890ca9ae
HY		 1419int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1420{
1421 u64 data;
1422
1423 switch (msr) {
890ca9ae 1424 case MSR_IA32_PLATFORM_ID:
15c4a640 1425 case MSR_IA32_UCODE_REV:
15c4a640 1426 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1427 case MSR_IA32_DEBUGCTLMSR:
1428 case MSR_IA32_LASTBRANCHFROMIP:
1429 case MSR_IA32_LASTBRANCHTOIP:
1430 case MSR_IA32_LASTINTFROMIP:
1431 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1432 case MSR_K8_SYSCFG:
1433 case MSR_K7_HWCR:
61a6bd67 1434 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1435 case MSR_P6_PERFCTR0:
1436 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1437 case MSR_P6_EVNTSEL0:
1438 case MSR_P6_EVNTSEL1:
9e699624 1439 case MSR_K7_EVNTSEL0:
1f3ee616 1440 case MSR_K7_PERFCTR0:
1fdbd48c 1441 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1442 case MSR_AMD64_NB_CFG:
f7c6d140 1443 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1444 data = 0;
1445 break;
9ba075a6
AK		 1446 case MSR_MTRRcap:
1447 data = 0x500 | KVM_NR_VAR_MTRR;
1448 break;
1449 case 0x200 ... 0x2ff:
1450 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1451 case 0xcd: /* fsb frequency */
1452 data = 3;
1453 break;
1454 case MSR_IA32_APICBASE:
1455 data = kvm_get_apic_base(vcpu);
1456 break;
0105d1a5
GN		 1457 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1458 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1459 break;
15c4a640 1460 case MSR_IA32_MISC_ENABLE:
ad312c7c 1461 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1462 break;
847f0ad8
AG		 1463 case MSR_IA32_PERF_STATUS:
1464 /* TSC increment by tick */
1465 data = 1000ULL;
1466 /* CPU multiplier */
1467 data |= (((uint64_t)4ULL) << 40);
1468 break;
15c4a640 1469 case MSR_EFER:
f6801dff 1470 data = vcpu->arch.efer;
15c4a640 1471 break;
18068523 1472 case MSR_KVM_WALL_CLOCK:
11c6bffa 1473 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1474 data = vcpu->kvm->arch.wall_clock;
1475 break;
1476 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1477 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1478 data = vcpu->arch.time;
1479 break;
890ca9ae
HY		 1480 case MSR_IA32_P5_MC_ADDR:
1481 case MSR_IA32_P5_MC_TYPE:
1482 case MSR_IA32_MCG_CAP:
1483 case MSR_IA32_MCG_CTL:
1484 case MSR_IA32_MCG_STATUS:
1485 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1486 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1487 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1488 if (kvm_hv_msr_partition_wide(msr)) {
1489 int r;
1490 mutex_lock(&vcpu->kvm->lock);
1491 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1492 mutex_unlock(&vcpu->kvm->lock);
1493 return r;
1494 } else
1495 return get_msr_hyperv(vcpu, msr, pdata);
1496 break;
15c4a640 1497 default:
ed85c068
AP		 1498 if (!ignore_msrs) {
1499 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1500 return 1;
1501 } else {
1502 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1503 data = 0;
1504 }
1505 break;
15c4a640
CO		 1506 }
1507 *pdata = data;
1508 return 0;
1509}
1510EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1511
313a3dc7
CO		 1512/*
1513 * Read or write a bunch of msrs. All parameters are kernel addresses.
1514 *
1515 * @return number of msrs set successfully.
1516 */
1517static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1518 struct kvm_msr_entry *entries,
1519 int (*do_msr)(struct kvm_vcpu *vcpu,
1520 unsigned index, u64 *data))
1521{
f656ce01 1522 int i, idx;
313a3dc7
CO		 1523
1524 vcpu_load(vcpu);
1525
f656ce01 1526 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1527 for (i = 0; i < msrs->nmsrs; ++i)
1528 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1529 break;
f656ce01 1530 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1531
1532 vcpu_put(vcpu);
1533
1534 return i;
1535}
1536
1537/*
1538 * Read or write a bunch of msrs. Parameters are user addresses.
1539 *
1540 * @return number of msrs set successfully.
1541 */
1542static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1543 int (*do_msr)(struct kvm_vcpu *vcpu,
1544 unsigned index, u64 *data),
1545 int writeback)
1546{
1547 struct kvm_msrs msrs;
1548 struct kvm_msr_entry *entries;
1549 int r, n;
1550 unsigned size;
1551
1552 r = -EFAULT;
1553 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1554 goto out;
1555
1556 r = -E2BIG;
1557 if (msrs.nmsrs >= MAX_IO_MSRS)
1558 goto out;
1559
1560 r = -ENOMEM;
1561 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1562 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1563 if (!entries)
1564 goto out;
1565
1566 r = -EFAULT;
1567 if (copy_from_user(entries, user_msrs->entries, size))
1568 goto out_free;
1569
1570 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1571 if (r < 0)
1572 goto out_free;
1573
1574 r = -EFAULT;
1575 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1576 goto out_free;
1577
1578 r = n;
1579
1580out_free:
7a73c028 1581 kfree(entries);
313a3dc7
CO		 1582out:
1583 return r;
1584}
1585
018d00d2
ZX		 1586int kvm_dev_ioctl_check_extension(long ext)
1587{
1588 int r;
1589
1590 switch (ext) {
1591 case KVM_CAP_IRQCHIP:
1592 case KVM_CAP_HLT:
1593 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1594 case KVM_CAP_SET_TSS_ADDR:
07716717 1595 case KVM_CAP_EXT_CPUID:
c8076604 1596 case KVM_CAP_CLOCKSOURCE:
7837699f 1597 case KVM_CAP_PIT:
a28e4f5a 1598 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1599 case KVM_CAP_MP_STATE:
ed848624 1600 case KVM_CAP_SYNC_MMU:
52d939a0 1601 case KVM_CAP_REINJECT_CONTROL:
4925663a 1602 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1603 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1604 case KVM_CAP_IRQFD:
d34e6b17 1605 case KVM_CAP_IOEVENTFD:
c5ff41ce 1606 case KVM_CAP_PIT2:
e9f42757 1607 case KVM_CAP_PIT_STATE2:
b927a3ce 1608 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1609 case KVM_CAP_XEN_HVM:
afbcf7ab 1610 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1611 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1612 case KVM_CAP_HYPERV:
10388a07 1613 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1614 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1615 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1616 case KVM_CAP_DEBUGREGS:
d2be1651 1617 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1618 r = 1;
1619 break;
542472b5
LV		 1620 case KVM_CAP_COALESCED_MMIO:
1621 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1622 break;
774ead3a
AK		 1623 case KVM_CAP_VAPIC:
1624 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1625 break;
f725230a
AK		 1626 case KVM_CAP_NR_VCPUS:
1627 r = KVM_MAX_VCPUS;
1628 break;
a988b910
AK		 1629 case KVM_CAP_NR_MEMSLOTS:
1630 r = KVM_MEMORY_SLOTS;
1631 break;
a68a6a72
MT		 1632 case KVM_CAP_PV_MMU: /* obsolete */
1633 r = 0;
2f333bcb 1634 break;
62c476c7 1635 case KVM_CAP_IOMMU:
19de40a8 1636 r = iommu_found();
62c476c7 1637 break;
890ca9ae
HY		 1638 case KVM_CAP_MCE:
1639 r = KVM_MAX_MCE_BANKS;
1640 break;
018d00d2
ZX		 1641 default:
1642 r = 0;
1643 break;
1644 }
1645 return r;
1646
1647}
1648
043405e1
CO		 1649long kvm_arch_dev_ioctl(struct file *filp,
1650 unsigned int ioctl, unsigned long arg)
1651{
1652 void __user *argp = (void __user *)arg;
1653 long r;
1654
1655 switch (ioctl) {
1656 case KVM_GET_MSR_INDEX_LIST: {
1657 struct kvm_msr_list __user *user_msr_list = argp;
1658 struct kvm_msr_list msr_list;
1659 unsigned n;
1660
1661 r = -EFAULT;
1662 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1663 goto out;
1664 n = msr_list.nmsrs;
1665 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1666 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1667 goto out;
1668 r = -E2BIG;
e125e7b6 1669 if (n < msr_list.nmsrs)
043405e1
CO		 1670 goto out;
1671 r = -EFAULT;
1672 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1673 num_msrs_to_save * sizeof(u32)))
1674 goto out;
e125e7b6 1675 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1676 &emulated_msrs,
1677 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1678 goto out;
1679 r = 0;
1680 break;
1681 }
674eea0f
AK		 1682 case KVM_GET_SUPPORTED_CPUID: {
1683 struct kvm_cpuid2 __user *cpuid_arg = argp;
1684 struct kvm_cpuid2 cpuid;
1685
1686 r = -EFAULT;
1687 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1688 goto out;
1689 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1690 cpuid_arg->entries);
674eea0f
AK		 1691 if (r)
1692 goto out;
1693
1694 r = -EFAULT;
1695 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1696 goto out;
1697 r = 0;
1698 break;
1699 }
890ca9ae
HY		 1700 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1701 u64 mce_cap;
1702
1703 mce_cap = KVM_MCE_CAP_SUPPORTED;
1704 r = -EFAULT;
1705 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1706 goto out;
1707 r = 0;
1708 break;
1709 }
043405e1
CO		 1710 default:
1711 r = -EINVAL;
1712 }
1713out:
1714 return r;
1715}
1716
313a3dc7
CO		 1717void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1718{
1719 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1720 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1721 unsigned long khz = cpufreq_quick_get(cpu);
1722 if (!khz)
1723 khz = tsc_khz;
1724 per_cpu(cpu_tsc_khz, cpu) = khz;
1725 }
c8076604 1726 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1727}
1728
1729void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1730{
02daab21 1731 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1732 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1733}
1734
07716717 1735static int is_efer_nx(void)
313a3dc7 1736{
e286e86e 1737 unsigned long long efer = 0;
313a3dc7 1738
e286e86e 1739 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1740 return efer & EFER_NX;
1741}
1742
1743static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1744{
1745 int i;
1746 struct kvm_cpuid_entry2 *e, *entry;
1747
313a3dc7 1748 entry = NULL;
ad312c7c
ZX		 1749 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1750 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1751 if (e->function == 0x80000001) {
1752 entry = e;
1753 break;
1754 }
1755 }
07716717 1756 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1757 entry->edx &= ~(1 << 20);
1758 printk(KERN_INFO "kvm: guest NX capability removed\n");
1759 }
1760}
1761
07716717 1762/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1763static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1764 struct kvm_cpuid *cpuid,
1765 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1766{
1767 int r, i;
1768 struct kvm_cpuid_entry *cpuid_entries;
1769
1770 r = -E2BIG;
1771 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1772 goto out;
1773 r = -ENOMEM;
1774 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1775 if (!cpuid_entries)
1776 goto out;
1777 r = -EFAULT;
1778 if (copy_from_user(cpuid_entries, entries,
1779 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1780 goto out_free;
fe19c5a4 1781 vcpu_load(vcpu);
07716717 1782 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1783 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1784 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1785 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1786 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1787 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1788 vcpu->arch.cpuid_entries[i].index = 0;
1789 vcpu->arch.cpuid_entries[i].flags = 0;
1790 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1791 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1792 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1793 }
1794 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1795 cpuid_fix_nx_cap(vcpu);
1796 r = 0;
fc61b800 1797 kvm_apic_set_version(vcpu);
0e851880 1798 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1799 vcpu_put(vcpu);
07716717
DK		 1800
1801out_free:
1802 vfree(cpuid_entries);
1803out:
1804 return r;
1805}
1806
1807static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1808 struct kvm_cpuid2 *cpuid,
1809 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1810{
1811 int r;
1812
1813 r = -E2BIG;
1814 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1815 goto out;
1816 r = -EFAULT;
ad312c7c 1817 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1818 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1819 goto out;
fe19c5a4 1820 vcpu_load(vcpu);
ad312c7c 1821 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1822 kvm_apic_set_version(vcpu);
0e851880 1823 kvm_x86_ops->cpuid_update(vcpu);
fe19c5a4 1824 vcpu_put(vcpu);
313a3dc7
CO		 1825 return 0;
1826
1827out:
1828 return r;
1829}
1830
07716717 1831static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1832 struct kvm_cpuid2 *cpuid,
1833 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1834{
1835 int r;
1836
8fbf065d 1837 vcpu_load(vcpu);
07716717 1838 r = -E2BIG;
ad312c7c 1839 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1840 goto out;
1841 r = -EFAULT;
ad312c7c 1842 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1843 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1844 goto out;
1845 return 0;
1846
1847out:
ad312c7c 1848 cpuid->nent = vcpu->arch.cpuid_nent;
8fbf065d 1849 vcpu_put(vcpu);
07716717
DK		 1850 return r;
1851}
1852
07716717 1853static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1854 u32 index)
07716717
DK		 1855{
1856 entry->function = function;
1857 entry->index = index;
1858 cpuid_count(entry->function, entry->index,
19355475 1859 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1860 entry->flags = 0;
1861}
1862
7faa4ee1
AK		 1863#define F(x) bit(X86_FEATURE_##x)
1864
07716717
DK		 1865static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1866 u32 index, int *nent, int maxnent)
1867{
7faa4ee1 1868 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1869#ifdef CONFIG_X86_64
17cc3935
SY		 1870 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1871 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1872 unsigned f_lm = F(LM);
1873#else
17cc3935 1874 unsigned f_gbpages = 0;
7faa4ee1 1875 unsigned f_lm = 0;
07716717 1876#endif
4e47c7a6 1877 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1878
1879 /* cpuid 1.edx */
1880 const u32 kvm_supported_word0_x86_features =
1881 F(FPU) | F(VME) | F(DE) | F(PSE) |
1882 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1883 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1884 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1885 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1886 0 /* Reserved, DS, ACPI */ | F(MMX) |
1887 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1888 0 /* HTT, TM, Reserved, PBE */;
1889 /* cpuid 0x80000001.edx */
1890 const u32 kvm_supported_word1_x86_features =
1891 F(FPU) | F(VME) | F(DE) | F(PSE) |
1892 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1893 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1894 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1895 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1896 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1897 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1898 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1899 /* cpuid 1.ecx */
1900 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1901 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1902 0 /* DS-CPL, VMX, SMX, EST */ |
1903 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1904 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1905 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1906 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1907 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1908 /* cpuid 0x80000001.ecx */
07716717 1909 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1910 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1911 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1912 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1913 0 /* SKINIT */ | 0 /* WDT */;
07716717 1914
19355475 1915 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1916 get_cpu();
1917 do_cpuid_1_ent(entry, function, index);
1918 ++*nent;
1919
1920 switch (function) {
1921 case 0:
1922 entry->eax = min(entry->eax, (u32)0xb);
1923 break;
1924 case 1:
1925 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1926 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1927 /* we support x2apic emulation even if host does not support
1928 * it since we emulate x2apic in software */
1929 entry->ecx |= F(X2APIC);
07716717
DK		 1930 break;
1931 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1932 * may return different values. This forces us to get_cpu() before
1933 * issuing the first command, and also to emulate this annoying behavior
1934 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1935 case 2: {
1936 int t, times = entry->eax & 0xff;
1937
1938 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1939 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1940 for (t = 1; t < times && *nent < maxnent; ++t) {
1941 do_cpuid_1_ent(&entry[t], function, 0);
1942 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1943 ++*nent;
1944 }
1945 break;
1946 }
1947 /* function 4 and 0xb have additional index. */
1948 case 4: {
14af3f3c 1949 int i, cache_type;
07716717
DK		 1950
1951 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1952 /* read more entries until cache_type is zero */
14af3f3c
HH		 1953 for (i = 1; *nent < maxnent; ++i) {
1954 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1955 if (!cache_type)
1956 break;
14af3f3c
HH		 1957 do_cpuid_1_ent(&entry[i], function, i);
1958 entry[i].flags |=
07716717
DK		 1959 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1960 ++*nent;
1961 }
1962 break;
1963 }
1964 case 0xb: {
14af3f3c 1965 int i, level_type;
07716717
DK		 1966
1967 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1968 /* read more entries until level_type is zero */
14af3f3c 1969 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1970 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1971 if (!level_type)
1972 break;
14af3f3c
HH		 1973 do_cpuid_1_ent(&entry[i], function, i);
1974 entry[i].flags |=
07716717
DK		 1975 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1976 ++*nent;
1977 }
1978 break;
1979 }
84478c82
GC		 1980 case KVM_CPUID_SIGNATURE: {
1981 char signature[12] = "KVMKVMKVM\0\0";
1982 u32 *sigptr = (u32 *)signature;
1983 entry->eax = 0;
1984 entry->ebx = sigptr[0];
1985 entry->ecx = sigptr[1];
1986 entry->edx = sigptr[2];
1987 break;
1988 }
1989 case KVM_CPUID_FEATURES:
1990 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1991 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 1992 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1993 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 1994 entry->ebx = 0;
1995 entry->ecx = 0;
1996 entry->edx = 0;
1997 break;
07716717
DK		 1998 case 0x80000000:
1999 entry->eax = min(entry->eax, 0x8000001a);
2000 break;
2001 case 0x80000001:
2002 entry->edx &= kvm_supported_word1_x86_features;
2003 entry->ecx &= kvm_supported_word6_x86_features;
2004 break;
2005 }
d4330ef2
JR		 2006
2007 kvm_x86_ops->set_supported_cpuid(function, entry);
2008
07716717
DK		 2009 put_cpu();
2010}
2011
7faa4ee1
AK		 2012#undef F
2013
674eea0f 2014static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2015 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2016{
2017 struct kvm_cpuid_entry2 *cpuid_entries;
2018 int limit, nent = 0, r = -E2BIG;
2019 u32 func;
2020
2021 if (cpuid->nent < 1)
2022 goto out;
6a544355
AK		 2023 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2024 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2025 r = -ENOMEM;
2026 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2027 if (!cpuid_entries)
2028 goto out;
2029
2030 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2031 limit = cpuid_entries[0].eax;
2032 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2033 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2034 &nent, cpuid->nent);
07716717
DK		 2035 r = -E2BIG;
2036 if (nent >= cpuid->nent)
2037 goto out_free;
2038
2039 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2040 limit = cpuid_entries[nent - 1].eax;
2041 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2042 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2043 &nent, cpuid->nent);
84478c82
GC		 2044
2045
2046
2047 r = -E2BIG;
2048 if (nent >= cpuid->nent)
2049 goto out_free;
2050
2051 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2052 cpuid->nent);
2053
2054 r = -E2BIG;
2055 if (nent >= cpuid->nent)
2056 goto out_free;
2057
2058 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2059 cpuid->nent);
2060
cb007648
MM		 2061 r = -E2BIG;
2062 if (nent >= cpuid->nent)
2063 goto out_free;
2064
07716717
DK		 2065 r = -EFAULT;
2066 if (copy_to_user(entries, cpuid_entries,
19355475 2067 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2068 goto out_free;
2069 cpuid->nent = nent;
2070 r = 0;
2071
2072out_free:
2073 vfree(cpuid_entries);
2074out:
2075 return r;
2076}
2077
313a3dc7
CO		 2078static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2079 struct kvm_lapic_state *s)
2080{
2081 vcpu_load(vcpu);
ad312c7c 2082 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2083 vcpu_put(vcpu);
2084
2085 return 0;
2086}
2087
2088static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2089 struct kvm_lapic_state *s)
2090{
2091 vcpu_load(vcpu);
ad312c7c 2092 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2093 kvm_apic_post_state_restore(vcpu);
cb142eb7 2094 update_cr8_intercept(vcpu);
313a3dc7
CO		 2095 vcpu_put(vcpu);
2096
2097 return 0;
2098}
2099
f77bc6a4
ZX		 2100static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2101 struct kvm_interrupt *irq)
2102{
2103 if (irq->irq < 0 || irq->irq >= 256)
2104 return -EINVAL;
2105 if (irqchip_in_kernel(vcpu->kvm))
2106 return -ENXIO;
2107 vcpu_load(vcpu);
2108
66fd3f7f 2109 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2110
2111 vcpu_put(vcpu);
2112
2113 return 0;
2114}
2115
c4abb7c9
JK		 2116static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2117{
2118 vcpu_load(vcpu);
2119 kvm_inject_nmi(vcpu);
2120 vcpu_put(vcpu);
2121
2122 return 0;
2123}
2124
b209749f
AK		 2125static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2126 struct kvm_tpr_access_ctl *tac)
2127{
2128 if (tac->flags)
2129 return -EINVAL;
2130 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2131 return 0;
2132}
2133
890ca9ae
HY		 2134static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2135 u64 mcg_cap)
2136{
2137 int r;
2138 unsigned bank_num = mcg_cap & 0xff, bank;
2139
8fbf065d 2140 vcpu_load(vcpu);
890ca9ae 2141 r = -EINVAL;
a9e38c3e 2142 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2143 goto out;
2144 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2145 goto out;
2146 r = 0;
2147 vcpu->arch.mcg_cap = mcg_cap;
2148 /* Init IA32_MCG_CTL to all 1s */
2149 if (mcg_cap & MCG_CTL_P)
2150 vcpu->arch.mcg_ctl = ~(u64)0;
2151 /* Init IA32_MCi_CTL to all 1s */
2152 for (bank = 0; bank < bank_num; bank++)
2153 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2154out:
8fbf065d 2155 vcpu_put(vcpu);
890ca9ae
HY		 2156 return r;
2157}
2158
2159static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2160 struct kvm_x86_mce *mce)
2161{
2162 u64 mcg_cap = vcpu->arch.mcg_cap;
2163 unsigned bank_num = mcg_cap & 0xff;
2164 u64 *banks = vcpu->arch.mce_banks;
2165
2166 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2167 return -EINVAL;
2168 /*
2169 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2170 * reporting is disabled
2171 */
2172 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2173 vcpu->arch.mcg_ctl != ~(u64)0)
2174 return 0;
2175 banks += 4 * mce->bank;
2176 /*
2177 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2178 * reporting is disabled for the bank
2179 */
2180 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2181 return 0;
2182 if (mce->status & MCI_STATUS_UC) {
2183 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2184 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2185 printk(KERN_DEBUG "kvm: set_mce: "
2186 "injects mce exception while "
2187 "previous one is in progress!\n");
2188 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2189 return 0;
2190 }
2191 if (banks[1] & MCI_STATUS_VAL)
2192 mce->status |= MCI_STATUS_OVER;
2193 banks[2] = mce->addr;
2194 banks[3] = mce->misc;
2195 vcpu->arch.mcg_status = mce->mcg_status;
2196 banks[1] = mce->status;
2197 kvm_queue_exception(vcpu, MC_VECTOR);
2198 } else if (!(banks[1] & MCI_STATUS_VAL)
2199 || !(banks[1] & MCI_STATUS_UC)) {
2200 if (banks[1] & MCI_STATUS_VAL)
2201 mce->status |= MCI_STATUS_OVER;
2202 banks[2] = mce->addr;
2203 banks[3] = mce->misc;
2204 banks[1] = mce->status;
2205 } else
2206 banks[1] |= MCI_STATUS_OVER;
2207 return 0;
2208}
2209
3cfc3092
JK		 2210static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2211 struct kvm_vcpu_events *events)
2212{
2213 vcpu_load(vcpu);
2214
03b82a30
JK		 2215 events->exception.injected =
2216 vcpu->arch.exception.pending &&
2217 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2218 events->exception.nr = vcpu->arch.exception.nr;
2219 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2220 events->exception.error_code = vcpu->arch.exception.error_code;
2221
03b82a30
JK		 2222 events->interrupt.injected =
2223 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2224 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2225 events->interrupt.soft = 0;
48005f64
JK		 2226 events->interrupt.shadow =
2227 kvm_x86_ops->get_interrupt_shadow(vcpu,
2228 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2229
2230 events->nmi.injected = vcpu->arch.nmi_injected;
2231 events->nmi.pending = vcpu->arch.nmi_pending;
2232 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2233
2234 events->sipi_vector = vcpu->arch.sipi_vector;
2235
dab4b911 2236 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2237 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2238 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2239
2240 vcpu_put(vcpu);
2241}
2242
2243static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2244 struct kvm_vcpu_events *events)
2245{
dab4b911 2246 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2247 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2248 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2249 return -EINVAL;
2250
2251 vcpu_load(vcpu);
2252
2253 vcpu->arch.exception.pending = events->exception.injected;
2254 vcpu->arch.exception.nr = events->exception.nr;
2255 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2256 vcpu->arch.exception.error_code = events->exception.error_code;
2257
2258 vcpu->arch.interrupt.pending = events->interrupt.injected;
2259 vcpu->arch.interrupt.nr = events->interrupt.nr;
2260 vcpu->arch.interrupt.soft = events->interrupt.soft;
2261 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2262 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2263 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2264 kvm_x86_ops->set_interrupt_shadow(vcpu,
2265 events->interrupt.shadow);
3cfc3092
JK		 2266
2267 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2268 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2269 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2270 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2271
dab4b911
JK		 2272 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2273 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2274
2275 vcpu_put(vcpu);
2276
2277 return 0;
2278}
2279
a1efbe77
JK		 2280static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2281 struct kvm_debugregs *dbgregs)
2282{
2283 vcpu_load(vcpu);
2284
2285 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2286 dbgregs->dr6 = vcpu->arch.dr6;
2287 dbgregs->dr7 = vcpu->arch.dr7;
2288 dbgregs->flags = 0;
2289
2290 vcpu_put(vcpu);
2291}
2292
2293static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2294 struct kvm_debugregs *dbgregs)
2295{
2296 if (dbgregs->flags)
2297 return -EINVAL;
2298
2299 vcpu_load(vcpu);
2300
2301 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2302 vcpu->arch.dr6 = dbgregs->dr6;
2303 vcpu->arch.dr7 = dbgregs->dr7;
2304
2305 vcpu_put(vcpu);
2306
2307 return 0;
2308}
2309
313a3dc7
CO		 2310long kvm_arch_vcpu_ioctl(struct file *filp,
2311 unsigned int ioctl, unsigned long arg)
2312{
2313 struct kvm_vcpu *vcpu = filp->private_data;
2314 void __user *argp = (void __user *)arg;
2315 int r;
b772ff36 2316 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2317
2318 switch (ioctl) {
2319 case KVM_GET_LAPIC: {
2204ae3c
MT		 2320 r = -EINVAL;
2321 if (!vcpu->arch.apic)
2322 goto out;
b772ff36 2323 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2324
b772ff36
DH		 2325 r = -ENOMEM;
2326 if (!lapic)
2327 goto out;
2328 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2329 if (r)
2330 goto out;
2331 r = -EFAULT;
b772ff36 2332 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2333 goto out;
2334 r = 0;
2335 break;
2336 }
2337 case KVM_SET_LAPIC: {
2204ae3c
MT		 2338 r = -EINVAL;
2339 if (!vcpu->arch.apic)
2340 goto out;
b772ff36
DH		 2341 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2342 r = -ENOMEM;
2343 if (!lapic)
2344 goto out;
313a3dc7 2345 r = -EFAULT;
b772ff36 2346 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2347 goto out;
b772ff36 2348 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2349 if (r)
2350 goto out;
2351 r = 0;
2352 break;
2353 }
f77bc6a4
ZX		 2354 case KVM_INTERRUPT: {
2355 struct kvm_interrupt irq;
2356
2357 r = -EFAULT;
2358 if (copy_from_user(&irq, argp, sizeof irq))
2359 goto out;
2360 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2361 if (r)
2362 goto out;
2363 r = 0;
2364 break;
2365 }
c4abb7c9
JK		 2366 case KVM_NMI: {
2367 r = kvm_vcpu_ioctl_nmi(vcpu);
2368 if (r)
2369 goto out;
2370 r = 0;
2371 break;
2372 }
313a3dc7
CO		 2373 case KVM_SET_CPUID: {
2374 struct kvm_cpuid __user *cpuid_arg = argp;
2375 struct kvm_cpuid cpuid;
2376
2377 r = -EFAULT;
2378 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2379 goto out;
2380 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2381 if (r)
2382 goto out;
2383 break;
2384 }
07716717
DK		 2385 case KVM_SET_CPUID2: {
2386 struct kvm_cpuid2 __user *cpuid_arg = argp;
2387 struct kvm_cpuid2 cpuid;
2388
2389 r = -EFAULT;
2390 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2391 goto out;
2392 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2393 cpuid_arg->entries);
07716717
DK		 2394 if (r)
2395 goto out;
2396 break;
2397 }
2398 case KVM_GET_CPUID2: {
2399 struct kvm_cpuid2 __user *cpuid_arg = argp;
2400 struct kvm_cpuid2 cpuid;
2401
2402 r = -EFAULT;
2403 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2404 goto out;
2405 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2406 cpuid_arg->entries);
07716717
DK		 2407 if (r)
2408 goto out;
2409 r = -EFAULT;
2410 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2411 goto out;
2412 r = 0;
2413 break;
2414 }
313a3dc7
CO		 2415 case KVM_GET_MSRS:
2416 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2417 break;
2418 case KVM_SET_MSRS:
2419 r = msr_io(vcpu, argp, do_set_msr, 0);
2420 break;
b209749f
AK		 2421 case KVM_TPR_ACCESS_REPORTING: {
2422 struct kvm_tpr_access_ctl tac;
2423
2424 r = -EFAULT;
2425 if (copy_from_user(&tac, argp, sizeof tac))
2426 goto out;
2427 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2428 if (r)
2429 goto out;
2430 r = -EFAULT;
2431 if (copy_to_user(argp, &tac, sizeof tac))
2432 goto out;
2433 r = 0;
2434 break;
2435 };
b93463aa
AK		 2436 case KVM_SET_VAPIC_ADDR: {
2437 struct kvm_vapic_addr va;
2438
2439 r = -EINVAL;
2440 if (!irqchip_in_kernel(vcpu->kvm))
2441 goto out;
2442 r = -EFAULT;
2443 if (copy_from_user(&va, argp, sizeof va))
2444 goto out;
2445 r = 0;
2446 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2447 break;
2448 }
890ca9ae
HY		 2449 case KVM_X86_SETUP_MCE: {
2450 u64 mcg_cap;
2451
2452 r = -EFAULT;
2453 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2454 goto out;
2455 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2456 break;
2457 }
2458 case KVM_X86_SET_MCE: {
2459 struct kvm_x86_mce mce;
2460
2461 r = -EFAULT;
2462 if (copy_from_user(&mce, argp, sizeof mce))
2463 goto out;
8fbf065d 2464 vcpu_load(vcpu);
890ca9ae 2465 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
8fbf065d 2466 vcpu_put(vcpu);
890ca9ae
HY		 2467 break;
2468 }
3cfc3092
JK		 2469 case KVM_GET_VCPU_EVENTS: {
2470 struct kvm_vcpu_events events;
2471
2472 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2473
2474 r = -EFAULT;
2475 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2476 break;
2477 r = 0;
2478 break;
2479 }
2480 case KVM_SET_VCPU_EVENTS: {
2481 struct kvm_vcpu_events events;
2482
2483 r = -EFAULT;
2484 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2485 break;
2486
2487 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2488 break;
2489 }
a1efbe77
JK		 2490 case KVM_GET_DEBUGREGS: {
2491 struct kvm_debugregs dbgregs;
2492
2493 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2494
2495 r = -EFAULT;
2496 if (copy_to_user(argp, &dbgregs,
2497 sizeof(struct kvm_debugregs)))
2498 break;
2499 r = 0;
2500 break;
2501 }
2502 case KVM_SET_DEBUGREGS: {
2503 struct kvm_debugregs dbgregs;
2504
2505 r = -EFAULT;
2506 if (copy_from_user(&dbgregs, argp,
2507 sizeof(struct kvm_debugregs)))
2508 break;
2509
2510 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2511 break;
2512 }
313a3dc7
CO		 2513 default:
2514 r = -EINVAL;
2515 }
2516out:
7a6ce84c 2517 kfree(lapic);
313a3dc7
CO		 2518 return r;
2519}
2520
1fe779f8
CO		 2521static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2522{
2523 int ret;
2524
2525 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2526 return -1;
2527 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2528 return ret;
2529}
2530
b927a3ce
SY		 2531static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2532 u64 ident_addr)
2533{
2534 kvm->arch.ept_identity_map_addr = ident_addr;
2535 return 0;
2536}
2537
1fe779f8
CO		 2538static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2539 u32 kvm_nr_mmu_pages)
2540{
2541 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2542 return -EINVAL;
2543
79fac95e 2544 mutex_lock(&kvm->slots_lock);
7c8a83b7 2545 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2546
2547 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2548 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2549
7c8a83b7 2550 spin_unlock(&kvm->mmu_lock);
79fac95e 2551 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2552 return 0;
2553}
2554
2555static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2556{
f05e70ac 2557 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2558}
2559
a983fb23
MT		 2560gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2561{
2562 int i;
2563 struct kvm_mem_alias *alias;
2564 struct kvm_mem_aliases *aliases;
2565
90d83dc3 2566 aliases = kvm_aliases(kvm);
a983fb23
MT		 2567
2568 for (i = 0; i < aliases->naliases; ++i) {
2569 alias = &aliases->aliases[i];
2570 if (alias->flags & KVM_ALIAS_INVALID)
2571 continue;
2572 if (gfn >= alias->base_gfn
2573 && gfn < alias->base_gfn + alias->npages)
2574 return alias->target_gfn + gfn - alias->base_gfn;
2575 }
2576 return gfn;
2577}
2578
e9f85cde
ZX		 2579gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2580{
2581 int i;
2582 struct kvm_mem_alias *alias;
a983fb23
MT		 2583 struct kvm_mem_aliases *aliases;
2584
90d83dc3 2585 aliases = kvm_aliases(kvm);
e9f85cde 2586
fef9cce0
MT		 2587 for (i = 0; i < aliases->naliases; ++i) {
2588 alias = &aliases->aliases[i];
e9f85cde
ZX		 2589 if (gfn >= alias->base_gfn
2590 && gfn < alias->base_gfn + alias->npages)
2591 return alias->target_gfn + gfn - alias->base_gfn;
2592 }
2593 return gfn;
2594}
2595
1fe779f8
CO		 2596/*
2597 * Set a new alias region. Aliases map a portion of physical memory into
2598 * another portion. This is useful for memory windows, for example the PC
2599 * VGA region.
2600 */
2601static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2602 struct kvm_memory_alias *alias)
2603{
2604 int r, n;
2605 struct kvm_mem_alias *p;
a983fb23 2606 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2607
2608 r = -EINVAL;
2609 /* General sanity checks */
2610 if (alias->memory_size & (PAGE_SIZE - 1))
2611 goto out;
2612 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2613 goto out;
2614 if (alias->slot >= KVM_ALIAS_SLOTS)
2615 goto out;
2616 if (alias->guest_phys_addr + alias->memory_size
2617 < alias->guest_phys_addr)
2618 goto out;
2619 if (alias->target_phys_addr + alias->memory_size
2620 < alias->target_phys_addr)
2621 goto out;
2622
a983fb23
MT		 2623 r = -ENOMEM;
2624 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2625 if (!aliases)
2626 goto out;
2627
79fac95e 2628 mutex_lock(&kvm->slots_lock);
1fe779f8 2629
a983fb23
MT		 2630 /* invalidate any gfn reference in case of deletion/shrinking */
2631 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2632 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2633 old_aliases = kvm->arch.aliases;
2634 rcu_assign_pointer(kvm->arch.aliases, aliases);
2635 synchronize_srcu_expedited(&kvm->srcu);
2636 kvm_mmu_zap_all(kvm);
2637 kfree(old_aliases);
2638
2639 r = -ENOMEM;
2640 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2641 if (!aliases)
2642 goto out_unlock;
2643
2644 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2645
2646 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2647 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2648 p->npages = alias->memory_size >> PAGE_SHIFT;
2649 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2650 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2651
2652 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2653 if (aliases->aliases[n - 1].npages)
1fe779f8 2654 break;
fef9cce0 2655 aliases->naliases = n;
1fe779f8 2656
a983fb23
MT		 2657 old_aliases = kvm->arch.aliases;
2658 rcu_assign_pointer(kvm->arch.aliases, aliases);
2659 synchronize_srcu_expedited(&kvm->srcu);
2660 kfree(old_aliases);
2661 r = 0;
1fe779f8 2662
a983fb23 2663out_unlock:
79fac95e 2664 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2665out:
2666 return r;
2667}
2668
2669static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2670{
2671 int r;
2672
2673 r = 0;
2674 switch (chip->chip_id) {
2675 case KVM_IRQCHIP_PIC_MASTER:
2676 memcpy(&chip->chip.pic,
2677 &pic_irqchip(kvm)->pics[0],
2678 sizeof(struct kvm_pic_state));
2679 break;
2680 case KVM_IRQCHIP_PIC_SLAVE:
2681 memcpy(&chip->chip.pic,
2682 &pic_irqchip(kvm)->pics[1],
2683 sizeof(struct kvm_pic_state));
2684 break;
2685 case KVM_IRQCHIP_IOAPIC:
eba0226b 2686 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2687 break;
2688 default:
2689 r = -EINVAL;
2690 break;
2691 }
2692 return r;
2693}
2694
2695static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2696{
2697 int r;
2698
2699 r = 0;
2700 switch (chip->chip_id) {
2701 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2702 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2703 memcpy(&pic_irqchip(kvm)->pics[0],
2704 &chip->chip.pic,
2705 sizeof(struct kvm_pic_state));
fa8273e9 2706 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2707 break;
2708 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2709 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2710 memcpy(&pic_irqchip(kvm)->pics[1],
2711 &chip->chip.pic,
2712 sizeof(struct kvm_pic_state));
fa8273e9 2713 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2714 break;
2715 case KVM_IRQCHIP_IOAPIC:
eba0226b 2716 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2717 break;
2718 default:
2719 r = -EINVAL;
2720 break;
2721 }
2722 kvm_pic_update_irq(pic_irqchip(kvm));
2723 return r;
2724}
2725
e0f63cb9
SY		 2726static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2727{
2728 int r = 0;
2729
894a9c55 2730 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2731 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2732 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2733 return r;
2734}
2735
2736static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2737{
2738 int r = 0;
2739
894a9c55 2740 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2741 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2742 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2743 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2744 return r;
2745}
2746
2747static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2748{
2749 int r = 0;
2750
2751 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2752 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2753 sizeof(ps->channels));
2754 ps->flags = kvm->arch.vpit->pit_state.flags;
2755 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2756 return r;
2757}
2758
2759static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2760{
2761 int r = 0, start = 0;
2762 u32 prev_legacy, cur_legacy;
2763 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2764 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2765 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2766 if (!prev_legacy && cur_legacy)
2767 start = 1;
2768 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2769 sizeof(kvm->arch.vpit->pit_state.channels));
2770 kvm->arch.vpit->pit_state.flags = ps->flags;
2771 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2772 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2773 return r;
2774}
2775
52d939a0
MT		 2776static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2777 struct kvm_reinject_control *control)
2778{
2779 if (!kvm->arch.vpit)
2780 return -ENXIO;
894a9c55 2781 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2782 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2783 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2784 return 0;
2785}
2786
5bb064dc
ZX		 2787/*
2788 * Get (and clear) the dirty memory log for a memory slot.
2789 */
2790int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2791 struct kvm_dirty_log *log)
2792{
87bf6e7d 2793 int r, i;
5bb064dc 2794 struct kvm_memory_slot *memslot;
87bf6e7d 2795 unsigned long n;
b050b015 2796 unsigned long is_dirty = 0;
5bb064dc 2797
79fac95e 2798 mutex_lock(&kvm->slots_lock);
5bb064dc 2799
b050b015
MT		 2800 r = -EINVAL;
2801 if (log->slot >= KVM_MEMORY_SLOTS)
2802 goto out;
2803
2804 memslot = &kvm->memslots->memslots[log->slot];
2805 r = -ENOENT;
2806 if (!memslot->dirty_bitmap)
2807 goto out;
2808
87bf6e7d 2809 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2810
b050b015
MT		 2811 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2812 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2813
2814 /* If nothing is dirty, don't bother messing with page tables. */
2815 if (is_dirty) {
b050b015 2816 struct kvm_memslots *slots, *old_slots;
914ebccd 2817 unsigned long *dirty_bitmap;
b050b015 2818
7c8a83b7 2819 spin_lock(&kvm->mmu_lock);
5bb064dc 2820 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2821 spin_unlock(&kvm->mmu_lock);
b050b015 2822
914ebccd
TY		 2823 r = -ENOMEM;
2824 dirty_bitmap = vmalloc(n);
2825 if (!dirty_bitmap)
2826 goto out;
2827 memset(dirty_bitmap, 0, n);
b050b015 2828
914ebccd
TY		 2829 r = -ENOMEM;
2830 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2831 if (!slots) {
2832 vfree(dirty_bitmap);
2833 goto out;
2834 }
b050b015
MT		 2835 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2836 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2837
2838 old_slots = kvm->memslots;
2839 rcu_assign_pointer(kvm->memslots, slots);
2840 synchronize_srcu_expedited(&kvm->srcu);
2841 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2842 kfree(old_slots);
914ebccd
TY		 2843
2844 r = -EFAULT;
2845 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2846 vfree(dirty_bitmap);
2847 goto out;
2848 }
2849 vfree(dirty_bitmap);
2850 } else {
2851 r = -EFAULT;
2852 if (clear_user(log->dirty_bitmap, n))
2853 goto out;
5bb064dc 2854 }
b050b015 2855
5bb064dc
ZX		 2856 r = 0;
2857out:
79fac95e 2858 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2859 return r;
2860}
2861
1fe779f8
CO		 2862long kvm_arch_vm_ioctl(struct file *filp,
2863 unsigned int ioctl, unsigned long arg)
2864{
2865 struct kvm *kvm = filp->private_data;
2866 void __user *argp = (void __user *)arg;
367e1319 2867 int r = -ENOTTY;
f0d66275
DH		 2868 /*
2869 * This union makes it completely explicit to gcc-3.x
2870 * that these two variables' stack usage should be
2871 * combined, not added together.
2872 */
2873 union {
2874 struct kvm_pit_state ps;
e9f42757 2875 struct kvm_pit_state2 ps2;
f0d66275 2876 struct kvm_memory_alias alias;
c5ff41ce 2877 struct kvm_pit_config pit_config;
f0d66275 2878 } u;
1fe779f8
CO		 2879
2880 switch (ioctl) {
2881 case KVM_SET_TSS_ADDR:
2882 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2883 if (r < 0)
2884 goto out;
2885 break;
b927a3ce
SY		 2886 case KVM_SET_IDENTITY_MAP_ADDR: {
2887 u64 ident_addr;
2888
2889 r = -EFAULT;
2890 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2891 goto out;
2892 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2893 if (r < 0)
2894 goto out;
2895 break;
2896 }
1fe779f8
CO		 2897 case KVM_SET_MEMORY_REGION: {
2898 struct kvm_memory_region kvm_mem;
2899 struct kvm_userspace_memory_region kvm_userspace_mem;
2900
2901 r = -EFAULT;
2902 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2903 goto out;
2904 kvm_userspace_mem.slot = kvm_mem.slot;
2905 kvm_userspace_mem.flags = kvm_mem.flags;
2906 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2907 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2908 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2909 if (r)
2910 goto out;
2911 break;
2912 }
2913 case KVM_SET_NR_MMU_PAGES:
2914 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2915 if (r)
2916 goto out;
2917 break;
2918 case KVM_GET_NR_MMU_PAGES:
2919 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2920 break;
f0d66275 2921 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2922 r = -EFAULT;
f0d66275 2923 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2924 goto out;
f0d66275 2925 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2926 if (r)
2927 goto out;
2928 break;
3ddea128
MT		 2929 case KVM_CREATE_IRQCHIP: {
2930 struct kvm_pic *vpic;
2931
2932 mutex_lock(&kvm->lock);
2933 r = -EEXIST;
2934 if (kvm->arch.vpic)
2935 goto create_irqchip_unlock;
1fe779f8 2936 r = -ENOMEM;
3ddea128
MT		 2937 vpic = kvm_create_pic(kvm);
2938 if (vpic) {
1fe779f8
CO		 2939 r = kvm_ioapic_init(kvm);
2940 if (r) {
72bb2fcd
WY		 2941 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2942 &vpic->dev);
3ddea128
MT		 2943 kfree(vpic);
2944 goto create_irqchip_unlock;
1fe779f8
CO		 2945 }
2946 } else
3ddea128
MT		 2947 goto create_irqchip_unlock;
2948 smp_wmb();
2949 kvm->arch.vpic = vpic;
2950 smp_wmb();
399ec807
AK		 2951 r = kvm_setup_default_irq_routing(kvm);
2952 if (r) {
3ddea128 2953 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2954 kvm_ioapic_destroy(kvm);
2955 kvm_destroy_pic(kvm);
3ddea128 2956 mutex_unlock(&kvm->irq_lock);
399ec807 2957 }
3ddea128
MT		 2958 create_irqchip_unlock:
2959 mutex_unlock(&kvm->lock);
1fe779f8 2960 break;
3ddea128 2961 }
7837699f 2962 case KVM_CREATE_PIT:
c5ff41ce
JK		 2963 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2964 goto create_pit;
2965 case KVM_CREATE_PIT2:
2966 r = -EFAULT;
2967 if (copy_from_user(&u.pit_config, argp,
2968 sizeof(struct kvm_pit_config)))
2969 goto out;
2970 create_pit:
79fac95e 2971 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2972 r = -EEXIST;
2973 if (kvm->arch.vpit)
2974 goto create_pit_unlock;
7837699f 2975 r = -ENOMEM;
c5ff41ce 2976 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2977 if (kvm->arch.vpit)
2978 r = 0;
269e05e4 2979 create_pit_unlock:
79fac95e 2980 mutex_unlock(&kvm->slots_lock);
7837699f 2981 break;
4925663a 2982 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2983 case KVM_IRQ_LINE: {
2984 struct kvm_irq_level irq_event;
2985
2986 r = -EFAULT;
2987 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2988 goto out;
160d2f6c 2989 r = -ENXIO;
1fe779f8 2990 if (irqchip_in_kernel(kvm)) {
4925663a 2991 __s32 status;
4925663a
GN		 2992 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2993 irq_event.irq, irq_event.level);
4925663a 2994 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2995 r = -EFAULT;
4925663a
GN		 2996 irq_event.status = status;
2997 if (copy_to_user(argp, &irq_event,
2998 sizeof irq_event))
2999 goto out;
3000 }
1fe779f8
CO		 3001 r = 0;
3002 }
3003 break;
3004 }
3005 case KVM_GET_IRQCHIP: {
3006 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3007 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3008
f0d66275
DH		 3009 r = -ENOMEM;
3010 if (!chip)
1fe779f8 3011 goto out;
f0d66275
DH		 3012 r = -EFAULT;
3013 if (copy_from_user(chip, argp, sizeof *chip))
3014 goto get_irqchip_out;
1fe779f8
CO		 3015 r = -ENXIO;
3016 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3017 goto get_irqchip_out;
3018 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3019 if (r)
f0d66275 3020 goto get_irqchip_out;
1fe779f8 3021 r = -EFAULT;
f0d66275
DH		 3022 if (copy_to_user(argp, chip, sizeof *chip))
3023 goto get_irqchip_out;
1fe779f8 3024 r = 0;
f0d66275
DH		 3025 get_irqchip_out:
3026 kfree(chip);
3027 if (r)
3028 goto out;
1fe779f8
CO		 3029 break;
3030 }
3031 case KVM_SET_IRQCHIP: {
3032 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3033 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3034
f0d66275
DH		 3035 r = -ENOMEM;
3036 if (!chip)
1fe779f8 3037 goto out;
f0d66275
DH		 3038 r = -EFAULT;
3039 if (copy_from_user(chip, argp, sizeof *chip))
3040 goto set_irqchip_out;
1fe779f8
CO		 3041 r = -ENXIO;
3042 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3043 goto set_irqchip_out;
3044 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3045 if (r)
f0d66275 3046 goto set_irqchip_out;
1fe779f8 3047 r = 0;
f0d66275
DH		 3048 set_irqchip_out:
3049 kfree(chip);
3050 if (r)
3051 goto out;
1fe779f8
CO		 3052 break;
3053 }
e0f63cb9 3054 case KVM_GET_PIT: {
e0f63cb9 3055 r = -EFAULT;
f0d66275 3056 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3057 goto out;
3058 r = -ENXIO;
3059 if (!kvm->arch.vpit)
3060 goto out;
f0d66275 3061 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3062 if (r)
3063 goto out;
3064 r = -EFAULT;
f0d66275 3065 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3066 goto out;
3067 r = 0;
3068 break;
3069 }
3070 case KVM_SET_PIT: {
e0f63cb9 3071 r = -EFAULT;
f0d66275 3072 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3073 goto out;
3074 r = -ENXIO;
3075 if (!kvm->arch.vpit)
3076 goto out;
f0d66275 3077 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3078 if (r)
3079 goto out;
3080 r = 0;
3081 break;
3082 }
e9f42757
BK		 3083 case KVM_GET_PIT2: {
3084 r = -ENXIO;
3085 if (!kvm->arch.vpit)
3086 goto out;
3087 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3088 if (r)
3089 goto out;
3090 r = -EFAULT;
3091 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3092 goto out;
3093 r = 0;
3094 break;
3095 }
3096 case KVM_SET_PIT2: {
3097 r = -EFAULT;
3098 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3099 goto out;
3100 r = -ENXIO;
3101 if (!kvm->arch.vpit)
3102 goto out;
3103 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3104 if (r)
3105 goto out;
3106 r = 0;
3107 break;
3108 }
52d939a0
MT		 3109 case KVM_REINJECT_CONTROL: {
3110 struct kvm_reinject_control control;
3111 r = -EFAULT;
3112 if (copy_from_user(&control, argp, sizeof(control)))
3113 goto out;
3114 r = kvm_vm_ioctl_reinject(kvm, &control);
3115 if (r)
3116 goto out;
3117 r = 0;
3118 break;
3119 }
ffde22ac
ES		 3120 case KVM_XEN_HVM_CONFIG: {
3121 r = -EFAULT;
3122 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3123 sizeof(struct kvm_xen_hvm_config)))
3124 goto out;
3125 r = -EINVAL;
3126 if (kvm->arch.xen_hvm_config.flags)
3127 goto out;
3128 r = 0;
3129 break;
3130 }
afbcf7ab
GC		 3131 case KVM_SET_CLOCK: {
3132 struct timespec now;
3133 struct kvm_clock_data user_ns;
3134 u64 now_ns;
3135 s64 delta;
3136
3137 r = -EFAULT;
3138 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3139 goto out;
3140
3141 r = -EINVAL;
3142 if (user_ns.flags)
3143 goto out;
3144
3145 r = 0;
3146 ktime_get_ts(&now);
3147 now_ns = timespec_to_ns(&now);
3148 delta = user_ns.clock - now_ns;
3149 kvm->arch.kvmclock_offset = delta;
3150 break;
3151 }
3152 case KVM_GET_CLOCK: {
3153 struct timespec now;
3154 struct kvm_clock_data user_ns;
3155 u64 now_ns;
3156
3157 ktime_get_ts(&now);
3158 now_ns = timespec_to_ns(&now);
3159 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3160 user_ns.flags = 0;
3161
3162 r = -EFAULT;
3163 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3164 goto out;
3165 r = 0;
3166 break;
3167 }
3168
1fe779f8
CO		 3169 default:
3170 ;
3171 }
3172out:
3173 return r;
3174}
3175
a16b043c 3176static void kvm_init_msr_list(void)
043405e1
CO		 3177{
3178 u32 dummy[2];
3179 unsigned i, j;
3180
e3267cbb
GC		 3181 /* skip the first msrs in the list. KVM-specific */
3182 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3183 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3184 continue;
3185 if (j < i)
3186 msrs_to_save[j] = msrs_to_save[i];
3187 j++;
3188 }
3189 num_msrs_to_save = j;
3190}
3191
bda9020e
MT		 3192static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3193 const void *v)
bbd9b64e 3194{
bda9020e
MT		 3195 if (vcpu->arch.apic &&
3196 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3197 return 0;
bbd9b64e 3198
e93f8a0f 3199 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3200}
3201
bda9020e 3202static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3203{
bda9020e
MT		 3204 if (vcpu->arch.apic &&
3205 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3206 return 0;
bbd9b64e 3207
e93f8a0f 3208 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3209}
3210
2dafc6c2
GN		 3211static void kvm_set_segment(struct kvm_vcpu *vcpu,
3212 struct kvm_segment *var, int seg)
3213{
3214 kvm_x86_ops->set_segment(vcpu, var, seg);
3215}
3216
3217void kvm_get_segment(struct kvm_vcpu *vcpu,
3218 struct kvm_segment *var, int seg)
3219{
3220 kvm_x86_ops->get_segment(vcpu, var, seg);
3221}
3222
1871c602
GN		 3223gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3224{
3225 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3226 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3227}
3228
3229 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3230{
3231 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3232 access |= PFERR_FETCH_MASK;
3233 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3234}
3235
3236gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3237{
3238 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3239 access |= PFERR_WRITE_MASK;
3240 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3241}
3242
3243/* uses this to access any guest's mapped memory without checking CPL */
3244gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3245{
3246 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3247}
3248
3249static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3250 struct kvm_vcpu *vcpu, u32 access,
3251 u32 *error)
bbd9b64e
CO		 3252{
3253 void *data = val;
10589a46 3254 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3255
3256 while (bytes) {
1871c602 3257 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3258 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3259 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3260 int ret;
3261
10589a46
MT		 3262 if (gpa == UNMAPPED_GVA) {
3263 r = X86EMUL_PROPAGATE_FAULT;
3264 goto out;
3265 }
77c2002e 3266 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3267 if (ret < 0) {
3268 r = X86EMUL_UNHANDLEABLE;
3269 goto out;
3270 }
bbd9b64e 3271
77c2002e
IE		 3272 bytes -= toread;
3273 data += toread;
3274 addr += toread;
bbd9b64e 3275 }
10589a46 3276out:
10589a46 3277 return r;
bbd9b64e 3278}
77c2002e 3279
1871c602
GN		 3280/* used for instruction fetching */
3281static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3282 struct kvm_vcpu *vcpu, u32 *error)
3283{
3284 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3285 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3286 access | PFERR_FETCH_MASK, error);
3287}
3288
3289static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3290 struct kvm_vcpu *vcpu, u32 *error)
3291{
3292 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3293 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3294 error);
3295}
3296
3297static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3298 struct kvm_vcpu *vcpu, u32 *error)
3299{
3300 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3301}
3302
7972995b 3303static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3304 unsigned int bytes,
7972995b 3305 struct kvm_vcpu *vcpu,
2dafc6c2 3306 u32 *error)
77c2002e
IE		 3307{
3308 void *data = val;
3309 int r = X86EMUL_CONTINUE;
3310
3311 while (bytes) {
7972995b
GN		 3312 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3313 PFERR_WRITE_MASK, error);
77c2002e
IE		 3314 unsigned offset = addr & (PAGE_SIZE-1);
3315 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3316 int ret;
3317
3318 if (gpa == UNMAPPED_GVA) {
3319 r = X86EMUL_PROPAGATE_FAULT;
3320 goto out;
3321 }
3322 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3323 if (ret < 0) {
3324 r = X86EMUL_UNHANDLEABLE;
3325 goto out;
3326 }
3327
3328 bytes -= towrite;
3329 data += towrite;
3330 addr += towrite;
3331 }
3332out:
3333 return r;
3334}
3335
bbd9b64e
CO		 3336static int emulator_read_emulated(unsigned long addr,
3337 void *val,
3338 unsigned int bytes,
3339 struct kvm_vcpu *vcpu)
3340{
bbd9b64e 3341 gpa_t gpa;
1871c602 3342 u32 error_code;
bbd9b64e
CO		 3343
3344 if (vcpu->mmio_read_completed) {
3345 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3346 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3347 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3348 vcpu->mmio_read_completed = 0;
3349 return X86EMUL_CONTINUE;
3350 }
3351
1871c602
GN		 3352 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3353
3354 if (gpa == UNMAPPED_GVA) {
3355 kvm_inject_page_fault(vcpu, addr, error_code);
3356 return X86EMUL_PROPAGATE_FAULT;
3357 }
bbd9b64e
CO		 3358
3359 /* For APIC access vmexit */
3360 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3361 goto mmio;
3362
1871c602 3363 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3364 == X86EMUL_CONTINUE)
bbd9b64e 3365 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3366
3367mmio:
3368 /*
3369 * Is this MMIO handled locally?
3370 */
aec51dc4
AK		 3371 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3372 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3373 return X86EMUL_CONTINUE;
3374 }
aec51dc4
AK		 3375
3376 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3377
3378 vcpu->mmio_needed = 1;
3379 vcpu->mmio_phys_addr = gpa;
3380 vcpu->mmio_size = bytes;
3381 vcpu->mmio_is_write = 0;
3382
3383 return X86EMUL_UNHANDLEABLE;
3384}
3385
3200f405 3386int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3387 const void *val, int bytes)
bbd9b64e
CO		 3388{
3389 int ret;
3390
3391 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3392 if (ret < 0)
bbd9b64e 3393 return 0;
ad218f85 3394 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3395 return 1;
3396}
3397
3398static int emulator_write_emulated_onepage(unsigned long addr,
3399 const void *val,
3400 unsigned int bytes,
3401 struct kvm_vcpu *vcpu)
3402{
10589a46 3403 gpa_t gpa;
1871c602 3404 u32 error_code;
10589a46 3405
1871c602 3406 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3407
3408 if (gpa == UNMAPPED_GVA) {
1871c602 3409 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3410 return X86EMUL_PROPAGATE_FAULT;
3411 }
3412
3413 /* For APIC access vmexit */
3414 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3415 goto mmio;
3416
3417 if (emulator_write_phys(vcpu, gpa, val, bytes))
3418 return X86EMUL_CONTINUE;
3419
3420mmio:
aec51dc4 3421 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3422 /*
3423 * Is this MMIO handled locally?
3424 */
bda9020e 3425 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3426 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3427
3428 vcpu->mmio_needed = 1;
3429 vcpu->mmio_phys_addr = gpa;
3430 vcpu->mmio_size = bytes;
3431 vcpu->mmio_is_write = 1;
3432 memcpy(vcpu->mmio_data, val, bytes);
3433
3434 return X86EMUL_CONTINUE;
3435}
3436
3437int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3438 const void *val,
3439 unsigned int bytes,
3440 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3441{
3442 /* Crossing a page boundary? */
3443 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3444 int rc, now;
3445
3446 now = -addr & ~PAGE_MASK;
3447 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3448 if (rc != X86EMUL_CONTINUE)
3449 return rc;
3450 addr += now;
3451 val += now;
3452 bytes -= now;
3453 }
3454 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3455}
3456EXPORT_SYMBOL_GPL(emulator_write_emulated);
3457
daea3e73
AK		 3458#define CMPXCHG_TYPE(t, ptr, old, new) \
3459 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3460
3461#ifdef CONFIG_X86_64
3462# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3463#else
3464# define CMPXCHG64(ptr, old, new) \
9749a6c0 3465 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3466#endif
3467
bbd9b64e
CO		 3468static int emulator_cmpxchg_emulated(unsigned long addr,
3469 const void *old,
3470 const void *new,
3471 unsigned int bytes,
3472 struct kvm_vcpu *vcpu)
3473{
daea3e73
AK		 3474 gpa_t gpa;
3475 struct page *page;
3476 char *kaddr;
3477 bool exchanged;
2bacc55c 3478
daea3e73
AK		 3479 /* guests cmpxchg8b have to be emulated atomically */
3480 if (bytes > 8 || (bytes & (bytes - 1)))
3481 goto emul_write;
10589a46 3482
daea3e73 3483 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3484
daea3e73
AK		 3485 if (gpa == UNMAPPED_GVA ||
3486 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3487 goto emul_write;
2bacc55c 3488
daea3e73
AK		 3489 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3490 goto emul_write;
72dc67a6 3491
daea3e73 3492 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3493
daea3e73
AK		 3494 kaddr = kmap_atomic(page, KM_USER0);
3495 kaddr += offset_in_page(gpa);
3496 switch (bytes) {
3497 case 1:
3498 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3499 break;
3500 case 2:
3501 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3502 break;
3503 case 4:
3504 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3505 break;
3506 case 8:
3507 exchanged = CMPXCHG64(kaddr, old, new);
3508 break;
3509 default:
3510 BUG();
2bacc55c 3511 }
daea3e73
AK		 3512 kunmap_atomic(kaddr, KM_USER0);
3513 kvm_release_page_dirty(page);
3514
3515 if (!exchanged)
3516 return X86EMUL_CMPXCHG_FAILED;
3517
8f6abd06
GN		 3518 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3519
3520 return X86EMUL_CONTINUE;
4a5f48f6 3521
3200f405 3522emul_write:
daea3e73 3523 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3524
bbd9b64e
CO		 3525 return emulator_write_emulated(addr, new, bytes, vcpu);
3526}
3527
cf8f70bf
GN		 3528static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3529{
3530 /* TODO: String I/O for in kernel device */
3531 int r;
3532
3533 if (vcpu->arch.pio.in)
3534 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3535 vcpu->arch.pio.size, pd);
3536 else
3537 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3538 vcpu->arch.pio.port, vcpu->arch.pio.size,
3539 pd);
3540 return r;
3541}
3542
3543
3544static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3545 unsigned int count, struct kvm_vcpu *vcpu)
3546{
7972995b 3547 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3548 goto data_avail;
3549
3550 trace_kvm_pio(1, port, size, 1);
3551
3552 vcpu->arch.pio.port = port;
3553 vcpu->arch.pio.in = 1;
7972995b 3554 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3555 vcpu->arch.pio.size = size;
3556
3557 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3558 data_avail:
3559 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3560 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3561 return 1;
3562 }
3563
3564 vcpu->run->exit_reason = KVM_EXIT_IO;
3565 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3566 vcpu->run->io.size = size;
3567 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3568 vcpu->run->io.count = count;
3569 vcpu->run->io.port = port;
3570
3571 return 0;
3572}
3573
3574static int emulator_pio_out_emulated(int size, unsigned short port,
3575 const void *val, unsigned int count,
3576 struct kvm_vcpu *vcpu)
3577{
3578 trace_kvm_pio(0, port, size, 1);
3579
3580 vcpu->arch.pio.port = port;
3581 vcpu->arch.pio.in = 0;
7972995b 3582 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3583 vcpu->arch.pio.size = size;
3584
3585 memcpy(vcpu->arch.pio_data, val, size * count);
3586
3587 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3588 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3589 return 1;
3590 }
3591
3592 vcpu->run->exit_reason = KVM_EXIT_IO;
3593 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3594 vcpu->run->io.size = size;
3595 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3596 vcpu->run->io.count = count;
3597 vcpu->run->io.port = port;
3598
3599 return 0;
3600}
3601
bbd9b64e
CO		 3602static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3603{
3604 return kvm_x86_ops->get_segment_base(vcpu, seg);
3605}
3606
3607int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3608{
a7052897 3609 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3610 return X86EMUL_CONTINUE;
3611}
3612
3613int emulate_clts(struct kvm_vcpu *vcpu)
3614{
4d4ec087 3615 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3616 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3617 return X86EMUL_CONTINUE;
3618}
3619
35aa5375 3620int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3621{
35aa5375 3622 return kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3623}
3624
35aa5375 3625int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3626{
35aa5375 3627 return kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3628}
3629
3630void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3631{
bbd9b64e 3632 u8 opcodes[4];
5fdbf976 3633 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3634 unsigned long rip_linear;
3635
f76c710d 3636 if (!printk_ratelimit())
bbd9b64e
CO		 3637 return;
3638
25be4608
GC		 3639 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3640
1871c602 3641 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3642
3643 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3644 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3645}
3646EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3647
52a46617 3648static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3649{
52a46617 3650 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3651}
3652
52a46617 3653static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3654{
52a46617
GN		 3655 unsigned long value;
3656
3657 switch (cr) {
3658 case 0:
3659 value = kvm_read_cr0(vcpu);
3660 break;
3661 case 2:
3662 value = vcpu->arch.cr2;
3663 break;
3664 case 3:
3665 value = vcpu->arch.cr3;
3666 break;
3667 case 4:
3668 value = kvm_read_cr4(vcpu);
3669 break;
3670 case 8:
3671 value = kvm_get_cr8(vcpu);
3672 break;
3673 default:
3674 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3675 return 0;
3676 }
3677
3678 return value;
3679}
3680
0f12244f 3681static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3682{
0f12244f
GN		 3683 int res = 0;
3684
52a46617
GN		 3685 switch (cr) {
3686 case 0:
0f12244f 3687 res = __kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3688 break;
3689 case 2:
3690 vcpu->arch.cr2 = val;
3691 break;
3692 case 3:
0f12244f 3693 res = __kvm_set_cr3(vcpu, val);
52a46617
GN		 3694 break;
3695 case 4:
0f12244f 3696 res = __kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3697 break;
3698 case 8:
0f12244f 3699 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3700 break;
3701 default:
3702 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3703 res = -1;
52a46617 3704 }
0f12244f
GN		 3705
3706 return res;
52a46617
GN		 3707}
3708
9c537244
GN		 3709static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3710{
3711 return kvm_x86_ops->get_cpl(vcpu);
3712}
3713
2dafc6c2
GN		 3714static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3715{
3716 kvm_x86_ops->get_gdt(vcpu, dt);
3717}
3718
5951c442
GN		 3719static unsigned long emulator_get_cached_segment_base(int seg,
3720 struct kvm_vcpu *vcpu)
3721{
3722 return get_segment_base(vcpu, seg);
3723}
3724
2dafc6c2
GN		 3725static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3726 struct kvm_vcpu *vcpu)
3727{
3728 struct kvm_segment var;
3729
3730 kvm_get_segment(vcpu, &var, seg);
3731
3732 if (var.unusable)
3733 return false;
3734
3735 if (var.g)
3736 var.limit >>= 12;
3737 set_desc_limit(desc, var.limit);
3738 set_desc_base(desc, (unsigned long)var.base);
3739 desc->type = var.type;
3740 desc->s = var.s;
3741 desc->dpl = var.dpl;
3742 desc->p = var.present;
3743 desc->avl = var.avl;
3744 desc->l = var.l;
3745 desc->d = var.db;
3746 desc->g = var.g;
3747
3748 return true;
3749}
3750
3751static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3752 struct kvm_vcpu *vcpu)
3753{
3754 struct kvm_segment var;
3755
3756 /* needed to preserve selector */
3757 kvm_get_segment(vcpu, &var, seg);
3758
3759 var.base = get_desc_base(desc);
3760 var.limit = get_desc_limit(desc);
3761 if (desc->g)
3762 var.limit = (var.limit << 12) | 0xfff;
3763 var.type = desc->type;
3764 var.present = desc->p;
3765 var.dpl = desc->dpl;
3766 var.db = desc->d;
3767 var.s = desc->s;
3768 var.l = desc->l;
3769 var.g = desc->g;
3770 var.avl = desc->avl;
3771 var.present = desc->p;
3772 var.unusable = !var.present;
3773 var.padding = 0;
3774
3775 kvm_set_segment(vcpu, &var, seg);
3776 return;
3777}
3778
3779static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3780{
3781 struct kvm_segment kvm_seg;
3782
3783 kvm_get_segment(vcpu, &kvm_seg, seg);
3784 return kvm_seg.selector;
3785}
3786
3787static void emulator_set_segment_selector(u16 sel, int seg,
3788 struct kvm_vcpu *vcpu)
3789{
3790 struct kvm_segment kvm_seg;
3791
3792 kvm_get_segment(vcpu, &kvm_seg, seg);
3793 kvm_seg.selector = sel;
3794 kvm_set_segment(vcpu, &kvm_seg, seg);
3795}
3796
482ac18a
GN		 3797static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3798{
3799 kvm_x86_ops->set_rflags(vcpu, rflags);
3800}
3801
14af3f3c 3802static struct x86_emulate_ops emulate_ops = {
1871c602 3803 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3804 .write_std = kvm_write_guest_virt_system,
1871c602 3805 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3806 .read_emulated = emulator_read_emulated,
3807 .write_emulated = emulator_write_emulated,
3808 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3809 .pio_in_emulated = emulator_pio_in_emulated,
3810 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3811 .get_cached_descriptor = emulator_get_cached_descriptor,
3812 .set_cached_descriptor = emulator_set_cached_descriptor,
3813 .get_segment_selector = emulator_get_segment_selector,
3814 .set_segment_selector = emulator_set_segment_selector,
5951c442 3815 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3816 .get_gdt = emulator_get_gdt,
52a46617
GN		 3817 .get_cr = emulator_get_cr,
3818 .set_cr = emulator_set_cr,
9c537244 3819 .cpl = emulator_get_cpl,
482ac18a 3820 .set_rflags = emulator_set_rflags,
35aa5375
GN		 3821 .get_dr = emulator_get_dr,
3822 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3823 .set_msr = kvm_set_msr,
3824 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3825};
3826
5fdbf976
MT		 3827static void cache_all_regs(struct kvm_vcpu *vcpu)
3828{
3829 kvm_register_read(vcpu, VCPU_REGS_RAX);
3830 kvm_register_read(vcpu, VCPU_REGS_RSP);
3831 kvm_register_read(vcpu, VCPU_REGS_RIP);
3832 vcpu->arch.regs_dirty = ~0;
3833}
3834
bbd9b64e 3835int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3836 unsigned long cr2,
3837 u16 error_code,
571008da 3838 int emulation_type)
bbd9b64e 3839{
310b5d30 3840 int r, shadow_mask;
571008da 3841 struct decode_cache *c;
851ba692 3842 struct kvm_run *run = vcpu->run;
bbd9b64e 3843
26eef70c 3844 kvm_clear_exception_queue(vcpu);
ad312c7c 3845 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3846 /*
56e82318 3847 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3848 * instead of direct ->regs accesses, can save hundred cycles
3849 * on Intel for instructions that don't read/change RSP, for
3850 * for example.
3851 */
3852 cache_all_regs(vcpu);
bbd9b64e
CO		 3853
3854 vcpu->mmio_is_write = 0;
bbd9b64e 3855
571008da 3856 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3857 int cs_db, cs_l;
3858 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3859
ad312c7c 3860 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3861 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3862 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3863 vcpu->arch.emulate_ctxt.mode =
a0044755 3864 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3865 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3866 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3867 ? X86EMUL_MODE_PROT64 : cs_db
3868 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3869
ad312c7c 3870 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3871 trace_kvm_emulate_insn_start(vcpu);
571008da 3872
0cb5762e
AP		 3873 /* Only allow emulation of specific instructions on #UD
3874 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3875 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3876 if (emulation_type & EMULTYPE_TRAP_UD) {
3877 if (!c->twobyte)
3878 return EMULATE_FAIL;
3879 switch (c->b) {
3880 case 0x01: /* VMMCALL */
3881 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3882 return EMULATE_FAIL;
3883 break;
3884 case 0x34: /* sysenter */
3885 case 0x35: /* sysexit */
3886 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3887 return EMULATE_FAIL;
3888 break;
3889 case 0x05: /* syscall */
3890 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3891 return EMULATE_FAIL;
3892 break;
3893 default:
3894 return EMULATE_FAIL;
3895 }
3896
3897 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3898 return EMULATE_FAIL;
3899 }
571008da 3900
f2b5756b 3901 ++vcpu->stat.insn_emulation;
bbd9b64e 3902 if (r) {
f2b5756b 3903 ++vcpu->stat.insn_emulation_fail;
e46479f8 3904 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3905 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3906 return EMULATE_DONE;
3907 return EMULATE_FAIL;
3908 }
3909 }
3910
ba8afb6b
GN		 3911 if (emulation_type & EMULTYPE_SKIP) {
3912 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3913 return EMULATE_DONE;
3914 }
3915
5cd21917 3916restart:
ad312c7c 3917 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3918 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3919
3920 if (r == 0)
3921 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3922
7972995b 3923 if (vcpu->arch.pio.count) {
cf8f70bf 3924 if (!vcpu->arch.pio.in)
7972995b 3925 vcpu->arch.pio.count = 0;
bbd9b64e 3926 return EMULATE_DO_MMIO;
cf8f70bf 3927 }
bbd9b64e 3928
112592da 3929 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3930 run->exit_reason = KVM_EXIT_MMIO;
3931 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3932 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3933 run->mmio.len = vcpu->mmio_size;
3934 run->mmio.is_write = vcpu->mmio_is_write;
3935 }
3936
3937 if (r) {
3938 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3939 goto done;
bbd9b64e 3940 if (!vcpu->mmio_needed) {
e46479f8
AK		 3941 ++vcpu->stat.insn_emulation_fail;
3942 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3943 kvm_report_emulation_failure(vcpu, "mmio");
3944 return EMULATE_FAIL;
3945 }
3946 return EMULATE_DO_MMIO;
3947 }
3948
bbd9b64e
CO		 3949 if (vcpu->mmio_is_write) {
3950 vcpu->mmio_needed = 0;
3951 return EMULATE_DO_MMIO;
3952 }
3953
5cd21917
GN		 3954done:
3955 if (vcpu->arch.exception.pending)
3956 vcpu->arch.emulate_ctxt.restart = false;
de7d789a 3957
5cd21917
GN		 3958 if (vcpu->arch.emulate_ctxt.restart)
3959 goto restart;
f850e2e6 3960
bbd9b64e 3961 return EMULATE_DONE;
de7d789a 3962}
bbd9b64e 3963EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 3964
cf8f70bf 3965int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 3966{
cf8f70bf
GN		 3967 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3968 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3969 /* do not return to emulator after return from userspace */
7972995b 3970 vcpu->arch.pio.count = 0;
de7d789a
CO		 3971 return ret;
3972}
cf8f70bf 3973EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 3974
c8076604
GH		 3975static void bounce_off(void *info)
3976{
3977 /* nothing */
3978}
3979
c8076604
GH		 3980static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3981 void *data)
3982{
3983 struct cpufreq_freqs *freq = data;
3984 struct kvm *kvm;
3985 struct kvm_vcpu *vcpu;
3986 int i, send_ipi = 0;
3987
c8076604
GH		 3988 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3989 return 0;
3990 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3991 return 0;
0cca7907 3992 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3993
3994 spin_lock(&kvm_lock);
3995 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3996 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3997 if (vcpu->cpu != freq->cpu)
3998 continue;
3999 if (!kvm_request_guest_time_update(vcpu))
4000 continue;
4001 if (vcpu->cpu != smp_processor_id())
4002 send_ipi++;
4003 }
4004 }
4005 spin_unlock(&kvm_lock);
4006
4007 if (freq->old < freq->new && send_ipi) {
4008 /*
4009 * We upscale the frequency. Must make the guest
4010 * doesn't see old kvmclock values while running with
4011 * the new frequency, otherwise we risk the guest sees
4012 * time go backwards.
4013 *
4014 * In case we update the frequency for another cpu
4015 * (which might be in guest context) send an interrupt
4016 * to kick the cpu out of guest context. Next time
4017 * guest context is entered kvmclock will be updated,
4018 * so the guest will not see stale values.
4019 */
4020 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4021 }
4022 return 0;
4023}
4024
4025static struct notifier_block kvmclock_cpufreq_notifier_block = {
4026 .notifier_call = kvmclock_cpufreq_notifier
4027};
4028
b820cc0c
ZA		 4029static void kvm_timer_init(void)
4030{
4031 int cpu;
4032
b820cc0c 4033 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4034 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4035 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4036 for_each_online_cpu(cpu) {
4037 unsigned long khz = cpufreq_get(cpu);
4038 if (!khz)
4039 khz = tsc_khz;
4040 per_cpu(cpu_tsc_khz, cpu) = khz;
4041 }
0cca7907
ZA		 4042 } else {
4043 for_each_possible_cpu(cpu)
4044 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4045 }
4046}
4047
ff9d07a0
ZY		 4048static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4049
4050static int kvm_is_in_guest(void)
4051{
4052 return percpu_read(current_vcpu) != NULL;
4053}
4054
4055static int kvm_is_user_mode(void)
4056{
4057 int user_mode = 3;
dcf46b94 4058
ff9d07a0
ZY		 4059 if (percpu_read(current_vcpu))
4060 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4061
ff9d07a0
ZY		 4062 return user_mode != 0;
4063}
4064
4065static unsigned long kvm_get_guest_ip(void)
4066{
4067 unsigned long ip = 0;
dcf46b94 4068
ff9d07a0
ZY		 4069 if (percpu_read(current_vcpu))
4070 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4071
ff9d07a0
ZY		 4072 return ip;
4073}
4074
4075static struct perf_guest_info_callbacks kvm_guest_cbs = {
4076 .is_in_guest = kvm_is_in_guest,
4077 .is_user_mode = kvm_is_user_mode,
4078 .get_guest_ip = kvm_get_guest_ip,
4079};
4080
4081void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4082{
4083 percpu_write(current_vcpu, vcpu);
4084}
4085EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4086
4087void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4088{
4089 percpu_write(current_vcpu, NULL);
4090}
4091EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4092
f8c16bba 4093int kvm_arch_init(void *opaque)
043405e1 4094{
b820cc0c 4095 int r;
f8c16bba
ZX		 4096 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4097
f8c16bba
ZX		 4098 if (kvm_x86_ops) {
4099 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4100 r = -EEXIST;
4101 goto out;
f8c16bba
ZX		 4102 }
4103
4104 if (!ops->cpu_has_kvm_support()) {
4105 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4106 r = -EOPNOTSUPP;
4107 goto out;
f8c16bba
ZX		 4108 }
4109 if (ops->disabled_by_bios()) {
4110 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4111 r = -EOPNOTSUPP;
4112 goto out;
f8c16bba
ZX		 4113 }
4114
97db56ce
AK		 4115 r = kvm_mmu_module_init();
4116 if (r)
4117 goto out;
4118
4119 kvm_init_msr_list();
4120
f8c16bba 4121 kvm_x86_ops = ops;
56c6d28a 4122 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4123 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4124 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4125 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4126
b820cc0c 4127 kvm_timer_init();
c8076604 4128
ff9d07a0
ZY		 4129 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4130
f8c16bba 4131 return 0;
56c6d28a
ZX		 4132
4133out:
56c6d28a 4134 return r;
043405e1 4135}
8776e519 4136
f8c16bba
ZX		 4137void kvm_arch_exit(void)
4138{
ff9d07a0
ZY		 4139 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4140
888d256e
JK		 4141 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4142 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4143 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4144 kvm_x86_ops = NULL;
56c6d28a
ZX		 4145 kvm_mmu_module_exit();
4146}
f8c16bba 4147
8776e519
HB		 4148int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4149{
4150 ++vcpu->stat.halt_exits;
4151 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4152 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4153 return 1;
4154 } else {
4155 vcpu->run->exit_reason = KVM_EXIT_HLT;
4156 return 0;
4157 }
4158}
4159EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4160
2f333bcb
MT		 4161static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4162 unsigned long a1)
4163{
4164 if (is_long_mode(vcpu))
4165 return a0;
4166 else
4167 return a0 | ((gpa_t)a1 << 32);
4168}
4169
55cd8e5a
GN		 4170int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4171{
4172 u64 param, ingpa, outgpa, ret;
4173 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4174 bool fast, longmode;
4175 int cs_db, cs_l;
4176
4177 /*
4178 * hypercall generates UD from non zero cpl and real mode
4179 * per HYPER-V spec
4180 */
3eeb3288 4181 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4182 kvm_queue_exception(vcpu, UD_VECTOR);
4183 return 0;
4184 }
4185
4186 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4187 longmode = is_long_mode(vcpu) && cs_l == 1;
4188
4189 if (!longmode) {
ccd46936
GN		 4190 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4191 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4192 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4193 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4194 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4195 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4196 }
4197#ifdef CONFIG_X86_64
4198 else {
4199 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4200 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4201 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4202 }
4203#endif
4204
4205 code = param & 0xffff;
4206 fast = (param >> 16) & 0x1;
4207 rep_cnt = (param >> 32) & 0xfff;
4208 rep_idx = (param >> 48) & 0xfff;
4209
4210 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4211
c25bc163
GN		 4212 switch (code) {
4213 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4214 kvm_vcpu_on_spin(vcpu);
4215 break;
4216 default:
4217 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4218 break;
4219 }
55cd8e5a
GN		 4220
4221 ret = res | (((u64)rep_done & 0xfff) << 32);
4222 if (longmode) {
4223 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4224 } else {
4225 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4226 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4227 }
4228
4229 return 1;
4230}
4231
8776e519
HB		 4232int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4233{
4234 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4235 int r = 1;
8776e519 4236
55cd8e5a
GN		 4237 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4238 return kvm_hv_hypercall(vcpu);
4239
5fdbf976
MT		 4240 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4241 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4242 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4243 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4244 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4245
229456fc 4246 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4247
8776e519
HB		 4248 if (!is_long_mode(vcpu)) {
4249 nr &= 0xFFFFFFFF;
4250 a0 &= 0xFFFFFFFF;
4251 a1 &= 0xFFFFFFFF;
4252 a2 &= 0xFFFFFFFF;
4253 a3 &= 0xFFFFFFFF;
4254 }
4255
07708c4a
JK		 4256 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4257 ret = -KVM_EPERM;
4258 goto out;
4259 }
4260
8776e519 4261 switch (nr) {
b93463aa
AK		 4262 case KVM_HC_VAPIC_POLL_IRQ:
4263 ret = 0;
4264 break;
2f333bcb
MT		 4265 case KVM_HC_MMU_OP:
4266 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4267 break;
8776e519
HB		 4268 default:
4269 ret = -KVM_ENOSYS;
4270 break;
4271 }
07708c4a 4272out:
5fdbf976 4273 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4274 ++vcpu->stat.hypercalls;
2f333bcb 4275 return r;
8776e519
HB		 4276}
4277EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4278
4279int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4280{
4281 char instruction[3];
5fdbf976 4282 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4283
8776e519
HB		 4284 /*
4285 * Blow out the MMU to ensure that no other VCPU has an active mapping
4286 * to ensure that the updated hypercall appears atomically across all
4287 * VCPUs.
4288 */
4289 kvm_mmu_zap_all(vcpu->kvm);
4290
8776e519 4291 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4292
7edcface 4293 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4294}
4295
8776e519
HB		 4296void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4297{
89a27f4d 4298 struct desc_ptr dt = { limit, base };
8776e519
HB		 4299
4300 kvm_x86_ops->set_gdt(vcpu, &dt);
4301}
4302
4303void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4304{
89a27f4d 4305 struct desc_ptr dt = { limit, base };
8776e519
HB		 4306
4307 kvm_x86_ops->set_idt(vcpu, &dt);
4308}
4309
07716717
DK		 4310static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4311{
ad312c7c
ZX		 4312 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4313 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4314
4315 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4316 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4317 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4318 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4319 if (ej->function == e->function) {
4320 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4321 return j;
4322 }
4323 }
4324 return 0; /* silence gcc, even though control never reaches here */
4325}
4326
4327/* find an entry with matching function, matching index (if needed), and that
4328 * should be read next (if it's stateful) */
4329static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4330 u32 function, u32 index)
4331{
4332 if (e->function != function)
4333 return 0;
4334 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4335 return 0;
4336 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4337 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4338 return 0;
4339 return 1;
4340}
4341
d8017474
AG		 4342struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4343 u32 function, u32 index)
8776e519
HB		 4344{
4345 int i;
d8017474 4346 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4347
ad312c7c 4348 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4349 struct kvm_cpuid_entry2 *e;
4350
ad312c7c 4351 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4352 if (is_matching_cpuid_entry(e, function, index)) {
4353 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4354 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4355 best = e;
4356 break;
4357 }
4358 /*
4359 * Both basic or both extended?
4360 */
4361 if (((e->function ^ function) & 0x80000000) == 0)
4362 if (!best || e->function > best->function)
4363 best = e;
4364 }
d8017474
AG		 4365 return best;
4366}
0e851880 4367EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4368
82725b20
DE		 4369int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4370{
4371 struct kvm_cpuid_entry2 *best;
4372
f7a71197
AK		 4373 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4374 if (!best || best->eax < 0x80000008)
4375 goto not_found;
82725b20
DE		 4376 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4377 if (best)
4378 return best->eax & 0xff;
f7a71197 4379not_found:
82725b20
DE		 4380 return 36;
4381}
4382
d8017474
AG		 4383void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4384{
4385 u32 function, index;
4386 struct kvm_cpuid_entry2 *best;
4387
4388 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4389 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4390 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4391 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4392 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4393 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4394 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4395 if (best) {
5fdbf976
MT		 4396 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4397 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4398 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4399 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4400 }
8776e519 4401 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4402 trace_kvm_cpuid(function,
4403 kvm_register_read(vcpu, VCPU_REGS_RAX),
4404 kvm_register_read(vcpu, VCPU_REGS_RBX),
4405 kvm_register_read(vcpu, VCPU_REGS_RCX),
4406 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4407}
4408EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4409
b6c7a5dc
HB		 4410/*
4411 * Check if userspace requested an interrupt window, and that the
4412 * interrupt window is open.
4413 *
4414 * No need to exit to userspace if we already have an interrupt queued.
4415 */
851ba692 4416static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4417{
8061823a 4418 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4419 vcpu->run->request_interrupt_window &&
5df56646 4420 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4421}
4422
851ba692 4423static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4424{
851ba692
AK		 4425 struct kvm_run *kvm_run = vcpu->run;
4426
91586a3b 4427 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4428 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4429 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4430 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4431 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4432 else
b6c7a5dc 4433 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4434 kvm_arch_interrupt_allowed(vcpu) &&
4435 !kvm_cpu_has_interrupt(vcpu) &&
4436 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4437}
4438
b93463aa
AK		 4439static void vapic_enter(struct kvm_vcpu *vcpu)
4440{
4441 struct kvm_lapic *apic = vcpu->arch.apic;
4442 struct page *page;
4443
4444 if (!apic || !apic->vapic_addr)
4445 return;
4446
4447 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4448
4449 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4450}
4451
4452static void vapic_exit(struct kvm_vcpu *vcpu)
4453{
4454 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4455 int idx;
b93463aa
AK		 4456
4457 if (!apic || !apic->vapic_addr)
4458 return;
4459
f656ce01 4460 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4461 kvm_release_page_dirty(apic->vapic_page);
4462 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4463 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4464}
4465
95ba8273
GN		 4466static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4467{
4468 int max_irr, tpr;
4469
4470 if (!kvm_x86_ops->update_cr8_intercept)
4471 return;
4472
88c808fd
AK		 4473 if (!vcpu->arch.apic)
4474 return;
4475
8db3baa2
GN		 4476 if (!vcpu->arch.apic->vapic_addr)
4477 max_irr = kvm_lapic_find_highest_irr(vcpu);
4478 else
4479 max_irr = -1;
95ba8273
GN		 4480
4481 if (max_irr != -1)
4482 max_irr >>= 4;
4483
4484 tpr = kvm_lapic_get_cr8(vcpu);
4485
4486 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4487}
4488
851ba692 4489static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4490{
4491 /* try to reinject previous events if any */
b59bb7bd 4492 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4493 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4494 vcpu->arch.exception.has_error_code,
4495 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4496 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4497 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4498 vcpu->arch.exception.error_code,
4499 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4500 return;
4501 }
4502
95ba8273
GN		 4503 if (vcpu->arch.nmi_injected) {
4504 kvm_x86_ops->set_nmi(vcpu);
4505 return;
4506 }
4507
4508 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4509 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4510 return;
4511 }
4512
4513 /* try to inject new event if pending */
4514 if (vcpu->arch.nmi_pending) {
4515 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4516 vcpu->arch.nmi_pending = false;
4517 vcpu->arch.nmi_injected = true;
4518 kvm_x86_ops->set_nmi(vcpu);
4519 }
4520 } else if (kvm_cpu_has_interrupt(vcpu)) {
4521 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4522 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4523 false);
4524 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4525 }
4526 }
4527}
4528
851ba692 4529static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4530{
4531 int r;
6a8b1d13 4532 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4533 vcpu->run->request_interrupt_window;
b6c7a5dc 4534
2e53d63a
MT		 4535 if (vcpu->requests)
4536 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4537 kvm_mmu_unload(vcpu);
4538
b6c7a5dc
HB		 4539 r = kvm_mmu_reload(vcpu);
4540 if (unlikely(r))
4541 goto out;
4542
2f52d58c
AK		 4543 if (vcpu->requests) {
4544 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4545 __kvm_migrate_timers(vcpu);
c8076604
GH		 4546 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4547 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4548 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4549 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4550 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4551 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4552 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4553 &vcpu->requests)) {
851ba692 4554 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4555 r = 0;
4556 goto out;
4557 }
71c4dfaf 4558 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4559 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4560 r = 0;
4561 goto out;
4562 }
02daab21
AK		 4563 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4564 vcpu->fpu_active = 0;
4565 kvm_x86_ops->fpu_deactivate(vcpu);
4566 }
2f52d58c 4567 }
b93463aa 4568
b6c7a5dc
HB		 4569 preempt_disable();
4570
4571 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4572 if (vcpu->fpu_active)
4573 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4574
4575 local_irq_disable();
4576
32f88400
MT		 4577 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4578 smp_mb__after_clear_bit();
4579
d7690175 4580 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4581 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4582 local_irq_enable();
4583 preempt_enable();
4584 r = 1;
4585 goto out;
4586 }
4587
851ba692 4588 inject_pending_event(vcpu);
b6c7a5dc 4589
6a8b1d13
GN		 4590 /* enable NMI/IRQ window open exits if needed */
4591 if (vcpu->arch.nmi_pending)
4592 kvm_x86_ops->enable_nmi_window(vcpu);
4593 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4594 kvm_x86_ops->enable_irq_window(vcpu);
4595
95ba8273 4596 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4597 update_cr8_intercept(vcpu);
4598 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4599 }
b93463aa 4600
f656ce01 4601 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4602
b6c7a5dc
HB		 4603 kvm_guest_enter();
4604
42dbaa5a 4605 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4606 set_debugreg(0, 7);
4607 set_debugreg(vcpu->arch.eff_db[0], 0);
4608 set_debugreg(vcpu->arch.eff_db[1], 1);
4609 set_debugreg(vcpu->arch.eff_db[2], 2);
4610 set_debugreg(vcpu->arch.eff_db[3], 3);
4611 }
b6c7a5dc 4612
229456fc 4613 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4614 kvm_x86_ops->run(vcpu);
b6c7a5dc 4615
24f1e32c
FW		 4616 /*
4617 * If the guest has used debug registers, at least dr7
4618 * will be disabled while returning to the host.
4619 * If we don't have active breakpoints in the host, we don't
4620 * care about the messed up debug address registers. But if
4621 * we have some of them active, restore the old state.
4622 */
59d8eb53 4623 if (hw_breakpoint_active())
24f1e32c 4624 hw_breakpoint_restore();
42dbaa5a 4625
32f88400 4626 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4627 local_irq_enable();
4628
4629 ++vcpu->stat.exits;
4630
4631 /*
4632 * We must have an instruction between local_irq_enable() and
4633 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4634 * the interrupt shadow. The stat.exits increment will do nicely.
4635 * But we need to prevent reordering, hence this barrier():
4636 */
4637 barrier();
4638
4639 kvm_guest_exit();
4640
4641 preempt_enable();
4642
f656ce01 4643 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4644
b6c7a5dc
HB		 4645 /*
4646 * Profile KVM exit RIPs:
4647 */
4648 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4649 unsigned long rip = kvm_rip_read(vcpu);
4650 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4651 }
4652
298101da 4653
b93463aa
AK		 4654 kvm_lapic_sync_from_vapic(vcpu);
4655
851ba692 4656 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4657out:
4658 return r;
4659}
b6c7a5dc 4660
09cec754 4661
851ba692 4662static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4663{
4664 int r;
f656ce01 4665 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4666
4667 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4668 pr_debug("vcpu %d received sipi with vector # %x\n",
4669 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4670 kvm_lapic_reset(vcpu);
5f179287 4671 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4672 if (r)
4673 return r;
4674 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4675 }
4676
f656ce01 4677 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4678 vapic_enter(vcpu);
4679
4680 r = 1;
4681 while (r > 0) {
af2152f5 4682 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4683 r = vcpu_enter_guest(vcpu);
d7690175 4684 else {
f656ce01 4685 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4686 kvm_vcpu_block(vcpu);
f656ce01 4687 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4688 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4689 {
4690 switch(vcpu->arch.mp_state) {
4691 case KVM_MP_STATE_HALTED:
d7690175 4692 vcpu->arch.mp_state =
09cec754
GN		 4693 KVM_MP_STATE_RUNNABLE;
4694 case KVM_MP_STATE_RUNNABLE:
4695 break;
4696 case KVM_MP_STATE_SIPI_RECEIVED:
4697 default:
4698 r = -EINTR;
4699 break;
4700 }
4701 }
d7690175
MT		 4702 }
4703
09cec754
GN		 4704 if (r <= 0)
4705 break;
4706
4707 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4708 if (kvm_cpu_has_pending_timer(vcpu))
4709 kvm_inject_pending_timer_irqs(vcpu);
4710
851ba692 4711 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4712 r = -EINTR;
851ba692 4713 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4714 ++vcpu->stat.request_irq_exits;
4715 }
4716 if (signal_pending(current)) {
4717 r = -EINTR;
851ba692 4718 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4719 ++vcpu->stat.signal_exits;
4720 }
4721 if (need_resched()) {
f656ce01 4722 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4723 kvm_resched(vcpu);
f656ce01 4724 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4725 }
b6c7a5dc
HB		 4726 }
4727
f656ce01 4728 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4729
b93463aa
AK		 4730 vapic_exit(vcpu);
4731
b6c7a5dc
HB		 4732 return r;
4733}
4734
4735int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4736{
4737 int r;
4738 sigset_t sigsaved;
4739
4740 vcpu_load(vcpu);
4741
ac9f6dc0
AK		 4742 if (vcpu->sigset_active)
4743 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4744
a4535290 4745 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4746 kvm_vcpu_block(vcpu);
d7690175 4747 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4748 r = -EAGAIN;
4749 goto out;
b6c7a5dc
HB		 4750 }
4751
b6c7a5dc
HB		 4752 /* re-sync apic's tpr */
4753 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4754 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4755
92bf9748
GN		 4756 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4757 vcpu->arch.emulate_ctxt.restart) {
4758 if (vcpu->mmio_needed) {
4759 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4760 vcpu->mmio_read_completed = 1;
4761 vcpu->mmio_needed = 0;
b6c7a5dc 4762 }
f656ce01 4763 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4764 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4765 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4766 if (r == EMULATE_DO_MMIO) {
b6c7a5dc
HB		 4767 r = 0;
4768 goto out;
4769 }
4770 }
5fdbf976
MT		 4771 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4772 kvm_register_write(vcpu, VCPU_REGS_RAX,
4773 kvm_run->hypercall.ret);
b6c7a5dc 4774
851ba692 4775 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4776
4777out:
f1d86e46 4778 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4779 if (vcpu->sigset_active)
4780 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4781
4782 vcpu_put(vcpu);
4783 return r;
4784}
4785
4786int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4787{
4788 vcpu_load(vcpu);
4789
5fdbf976
MT		 4790 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4791 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4792 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4793 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4794 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4795 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4796 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4797 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4798#ifdef CONFIG_X86_64
5fdbf976
MT		 4799 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4800 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4801 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4802 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4803 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4804 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4805 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4806 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4807#endif
4808
5fdbf976 4809 regs->rip = kvm_rip_read(vcpu);
91586a3b 4810 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4811
4812 vcpu_put(vcpu);
4813
4814 return 0;
4815}
4816
4817int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4818{
4819 vcpu_load(vcpu);
4820
5fdbf976
MT		 4821 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4822 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4823 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4824 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4825 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4826 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4827 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4828 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4829#ifdef CONFIG_X86_64
5fdbf976
MT		 4830 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4831 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4832 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4833 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4834 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4835 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4836 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4837 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4838#endif
4839
5fdbf976 4840 kvm_rip_write(vcpu, regs->rip);
91586a3b 4841 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4842
b4f14abd
JK		 4843 vcpu->arch.exception.pending = false;
4844
b6c7a5dc
HB		 4845 vcpu_put(vcpu);
4846
4847 return 0;
4848}
4849
b6c7a5dc
HB		 4850void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4851{
4852 struct kvm_segment cs;
4853
3e6e0aab 4854 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4855 *db = cs.db;
4856 *l = cs.l;
4857}
4858EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4859
4860int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4861 struct kvm_sregs *sregs)
4862{
89a27f4d 4863 struct desc_ptr dt;
b6c7a5dc
HB		 4864
4865 vcpu_load(vcpu);
4866
3e6e0aab
GT		 4867 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4868 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4869 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4870 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4871 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4872 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4873
3e6e0aab
GT		 4874 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4875 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4876
4877 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4878 sregs->idt.limit = dt.size;
4879 sregs->idt.base = dt.address;
b6c7a5dc 4880 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4881 sregs->gdt.limit = dt.size;
4882 sregs->gdt.base = dt.address;
b6c7a5dc 4883
4d4ec087 4884 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4885 sregs->cr2 = vcpu->arch.cr2;
4886 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4887 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4888 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4889 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4890 sregs->apic_base = kvm_get_apic_base(vcpu);
4891
923c61bb 4892 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4893
36752c9b 4894 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4895 set_bit(vcpu->arch.interrupt.nr,
4896 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4897
b6c7a5dc
HB		 4898 vcpu_put(vcpu);
4899
4900 return 0;
4901}
4902
62d9f0db
MT		 4903int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4904 struct kvm_mp_state *mp_state)
4905{
4906 vcpu_load(vcpu);
4907 mp_state->mp_state = vcpu->arch.mp_state;
4908 vcpu_put(vcpu);
4909 return 0;
4910}
4911
4912int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4913 struct kvm_mp_state *mp_state)
4914{
4915 vcpu_load(vcpu);
4916 vcpu->arch.mp_state = mp_state->mp_state;
4917 vcpu_put(vcpu);
4918 return 0;
4919}
4920
e269fb21
JK		 4921int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4922 bool has_error_code, u32 error_code)
b6c7a5dc 4923{
ceffb459
GN		 4924 int cs_db, cs_l, ret;
4925 cache_all_regs(vcpu);
37817f29 4926
ceffb459 4927 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4928
ceffb459
GN		 4929 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4930 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4931 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4932 vcpu->arch.emulate_ctxt.mode =
4933 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4934 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4935 ? X86EMUL_MODE_VM86 : cs_l
4936 ? X86EMUL_MODE_PROT64 : cs_db
4937 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c697518a 4938
ceffb459 4939 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4940 tss_selector, reason, has_error_code,
4941 error_code);
c697518a 4942
c697518a 4943 if (ret)
19d04437 4944 return EMULATE_FAIL;
37817f29 4945
19d04437
GN		 4946 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4947 return EMULATE_DONE;
37817f29
IE		 4948}
4949EXPORT_SYMBOL_GPL(kvm_task_switch);
4950
b6c7a5dc
HB		 4951int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4952 struct kvm_sregs *sregs)
4953{
4954 int mmu_reset_needed = 0;
923c61bb 4955 int pending_vec, max_bits;
89a27f4d 4956 struct desc_ptr dt;
b6c7a5dc
HB		 4957
4958 vcpu_load(vcpu);
4959
89a27f4d
GN		 4960 dt.size = sregs->idt.limit;
4961 dt.address = sregs->idt.base;
b6c7a5dc 4962 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4963 dt.size = sregs->gdt.limit;
4964 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4965 kvm_x86_ops->set_gdt(vcpu, &dt);
4966
ad312c7c
ZX		 4967 vcpu->arch.cr2 = sregs->cr2;
4968 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4969 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4970
2d3ad1f4 4971 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4972
f6801dff 4973 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4974 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4975 kvm_set_apic_base(vcpu, sregs->apic_base);
4976
4d4ec087 4977 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4978 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4979 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4980
fc78f519 4981 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4982 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4983 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4984 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4985 mmu_reset_needed = 1;
4986 }
b6c7a5dc
HB		 4987
4988 if (mmu_reset_needed)
4989 kvm_mmu_reset_context(vcpu);
4990
923c61bb
GN		 4991 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4992 pending_vec = find_first_bit(
4993 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4994 if (pending_vec < max_bits) {
66fd3f7f 4995 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4996 pr_debug("Set back pending irq %d\n", pending_vec);
4997 if (irqchip_in_kernel(vcpu->kvm))
4998 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4999 }
5000
3e6e0aab
GT		 5001 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5002 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5003 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5004 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5005 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5006 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5007
3e6e0aab
GT		 5008 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5009 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5010
5f0269f5
ME		 5011 update_cr8_intercept(vcpu);
5012
9c3e4aab 5013 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5014 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5015 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5016 !is_protmode(vcpu))
9c3e4aab
MT		 5017 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5018
b6c7a5dc
HB		 5019 vcpu_put(vcpu);
5020
5021 return 0;
5022}
5023
d0bfb940
JK		 5024int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5025 struct kvm_guest_debug *dbg)
b6c7a5dc 5026{
355be0b9 5027 unsigned long rflags;
ae675ef0 5028 int i, r;
b6c7a5dc
HB		 5029
5030 vcpu_load(vcpu);
5031
4f926bf2
JK		 5032 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5033 r = -EBUSY;
5034 if (vcpu->arch.exception.pending)
5035 goto unlock_out;
5036 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5037 kvm_queue_exception(vcpu, DB_VECTOR);
5038 else
5039 kvm_queue_exception(vcpu, BP_VECTOR);
5040 }
5041
91586a3b
JK		 5042 /*
5043 * Read rflags as long as potentially injected trace flags are still
5044 * filtered out.
5045 */
5046 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5047
5048 vcpu->guest_debug = dbg->control;
5049 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5050 vcpu->guest_debug = 0;
5051
5052 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5053 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5054 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5055 vcpu->arch.switch_db_regs =
5056 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5057 } else {
5058 for (i = 0; i < KVM_NR_DB_REGS; i++)
5059 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5060 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5061 }
5062
f92653ee
JK		 5063 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5064 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5065 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5066
91586a3b
JK		 5067 /*
5068 * Trigger an rflags update that will inject or remove the trace
5069 * flags.
5070 */
5071 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5072
355be0b9 5073 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5074
4f926bf2 5075 r = 0;
d0bfb940 5076
4f926bf2 5077unlock_out:
b6c7a5dc
HB		 5078 vcpu_put(vcpu);
5079
5080 return r;
5081}
5082
d0752060
HB		 5083/*
5084 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5085 * we have asm/x86/processor.h
5086 */
5087struct fxsave {
5088 u16 cwd;
5089 u16 swd;
5090 u16 twd;
5091 u16 fop;
5092 u64 rip;
5093 u64 rdp;
5094 u32 mxcsr;
5095 u32 mxcsr_mask;
5096 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5097#ifdef CONFIG_X86_64
5098 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5099#else
5100 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5101#endif
5102};
5103
8b006791
ZX		 5104/*
5105 * Translate a guest virtual address to a guest physical address.
5106 */
5107int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5108 struct kvm_translation *tr)
5109{
5110 unsigned long vaddr = tr->linear_address;
5111 gpa_t gpa;
f656ce01 5112 int idx;
8b006791
ZX		 5113
5114 vcpu_load(vcpu);
f656ce01 5115 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5116 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5117 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5118 tr->physical_address = gpa;
5119 tr->valid = gpa != UNMAPPED_GVA;
5120 tr->writeable = 1;
5121 tr->usermode = 0;
8b006791
ZX		 5122 vcpu_put(vcpu);
5123
5124 return 0;
5125}
5126
d0752060
HB		 5127int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5128{
ad312c7c 5129 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5130
5131 vcpu_load(vcpu);
5132
5133 memcpy(fpu->fpr, fxsave->st_space, 128);
5134 fpu->fcw = fxsave->cwd;
5135 fpu->fsw = fxsave->swd;
5136 fpu->ftwx = fxsave->twd;
5137 fpu->last_opcode = fxsave->fop;
5138 fpu->last_ip = fxsave->rip;
5139 fpu->last_dp = fxsave->rdp;
5140 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5141
5142 vcpu_put(vcpu);
5143
5144 return 0;
5145}
5146
5147int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5148{
ad312c7c 5149 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5150
5151 vcpu_load(vcpu);
5152
5153 memcpy(fxsave->st_space, fpu->fpr, 128);
5154 fxsave->cwd = fpu->fcw;
5155 fxsave->swd = fpu->fsw;
5156 fxsave->twd = fpu->ftwx;
5157 fxsave->fop = fpu->last_opcode;
5158 fxsave->rip = fpu->last_ip;
5159 fxsave->rdp = fpu->last_dp;
5160 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5161
5162 vcpu_put(vcpu);
5163
5164 return 0;
5165}
5166
5167void fx_init(struct kvm_vcpu *vcpu)
5168{
5169 unsigned after_mxcsr_mask;
5170
bc1a34f1
AA		 5171 /*
5172 * Touch the fpu the first time in non atomic context as if
5173 * this is the first fpu instruction the exception handler
5174 * will fire before the instruction returns and it'll have to
5175 * allocate ram with GFP_KERNEL.
5176 */
5177 if (!used_math())
d6e88aec 5178 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5179
d0752060
HB		 5180 /* Initialize guest FPU by resetting ours and saving into guest's */
5181 preempt_disable();
d6e88aec
AK		 5182 kvm_fx_save(&vcpu->arch.host_fx_image);
5183 kvm_fx_finit();
5184 kvm_fx_save(&vcpu->arch.guest_fx_image);
5185 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5186 preempt_enable();
5187
ad312c7c 5188 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5189 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5190 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5191 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5192 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5193}
5194EXPORT_SYMBOL_GPL(fx_init);
5195
5196void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5197{
2608d7a1 5198 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5199 return;
5200
5201 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5202 kvm_fx_save(&vcpu->arch.host_fx_image);
5203 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5204 trace_kvm_fpu(1);
d0752060 5205}
d0752060
HB		 5206
5207void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5208{
5209 if (!vcpu->guest_fpu_loaded)
5210 return;
5211
5212 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5213 kvm_fx_save(&vcpu->arch.guest_fx_image);
5214 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5215 ++vcpu->stat.fpu_reload;
02daab21 5216 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5217 trace_kvm_fpu(0);
d0752060 5218}
e9b11c17
ZX		 5219
5220void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5221{
7f1ea208
JR		 5222 if (vcpu->arch.time_page) {
5223 kvm_release_page_dirty(vcpu->arch.time_page);
5224 vcpu->arch.time_page = NULL;
5225 }
5226
e9b11c17
ZX		 5227 kvm_x86_ops->vcpu_free(vcpu);
5228}
5229
5230struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5231 unsigned int id)
5232{
26e5215f
AK		 5233 return kvm_x86_ops->vcpu_create(kvm, id);
5234}
e9b11c17 5235
26e5215f
AK		 5236int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5237{
5238 int r;
e9b11c17
ZX		 5239
5240 /* We do fxsave: this must be aligned. */
ad312c7c 5241 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5242
0bed3b56 5243 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5244 vcpu_load(vcpu);
5245 r = kvm_arch_vcpu_reset(vcpu);
5246 if (r == 0)
5247 r = kvm_mmu_setup(vcpu);
5248 vcpu_put(vcpu);
5249 if (r < 0)
5250 goto free_vcpu;
5251
26e5215f 5252 return 0;
e9b11c17
ZX		 5253free_vcpu:
5254 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5255 return r;
e9b11c17
ZX		 5256}
5257
d40ccc62 5258void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5259{
5260 vcpu_load(vcpu);
5261 kvm_mmu_unload(vcpu);
5262 vcpu_put(vcpu);
5263
5264 kvm_x86_ops->vcpu_free(vcpu);
5265}
5266
5267int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5268{
448fa4a9
JK		 5269 vcpu->arch.nmi_pending = false;
5270 vcpu->arch.nmi_injected = false;
5271
42dbaa5a
JK		 5272 vcpu->arch.switch_db_regs = 0;
5273 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5274 vcpu->arch.dr6 = DR6_FIXED_1;
5275 vcpu->arch.dr7 = DR7_FIXED_1;
5276
e9b11c17
ZX		 5277 return kvm_x86_ops->vcpu_reset(vcpu);
5278}
5279
10474ae8 5280int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5281{
0cca7907
ZA		 5282 /*
5283 * Since this may be called from a hotplug notifcation,
5284 * we can't get the CPU frequency directly.
5285 */
5286 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5287 int cpu = raw_smp_processor_id();
5288 per_cpu(cpu_tsc_khz, cpu) = 0;
5289 }
18863bdd
AK		 5290
5291 kvm_shared_msr_cpu_online();
5292
10474ae8 5293 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5294}
5295
5296void kvm_arch_hardware_disable(void *garbage)
5297{
5298 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5299 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5300}
5301
5302int kvm_arch_hardware_setup(void)
5303{
5304 return kvm_x86_ops->hardware_setup();
5305}
5306
5307void kvm_arch_hardware_unsetup(void)
5308{
5309 kvm_x86_ops->hardware_unsetup();
5310}
5311
5312void kvm_arch_check_processor_compat(void *rtn)
5313{
5314 kvm_x86_ops->check_processor_compatibility(rtn);
5315}
5316
5317int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5318{
5319 struct page *page;
5320 struct kvm *kvm;
5321 int r;
5322
5323 BUG_ON(vcpu->kvm == NULL);
5324 kvm = vcpu->kvm;
5325
ad312c7c 5326 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5327 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5328 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5329 else
a4535290 5330 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5331
5332 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5333 if (!page) {
5334 r = -ENOMEM;
5335 goto fail;
5336 }
ad312c7c 5337 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5338
5339 r = kvm_mmu_create(vcpu);
5340 if (r < 0)
5341 goto fail_free_pio_data;
5342
5343 if (irqchip_in_kernel(kvm)) {
5344 r = kvm_create_lapic(vcpu);
5345 if (r < 0)
5346 goto fail_mmu_destroy;
5347 }
5348
890ca9ae
HY		 5349 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5350 GFP_KERNEL);
5351 if (!vcpu->arch.mce_banks) {
5352 r = -ENOMEM;
443c39bc 5353 goto fail_free_lapic;
890ca9ae
HY		 5354 }
5355 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5356
e9b11c17 5357 return 0;
443c39bc
WY		 5358fail_free_lapic:
5359 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5360fail_mmu_destroy:
5361 kvm_mmu_destroy(vcpu);
5362fail_free_pio_data:
ad312c7c 5363 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5364fail:
5365 return r;
5366}
5367
5368void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5369{
f656ce01
MT		 5370 int idx;
5371
36cb93fd 5372 kfree(vcpu->arch.mce_banks);
e9b11c17 5373 kvm_free_lapic(vcpu);
f656ce01 5374 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5375 kvm_mmu_destroy(vcpu);
f656ce01 5376 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5377 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5378}
d19a9cd2
ZX		 5379
5380struct kvm *kvm_arch_create_vm(void)
5381{
5382 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5383
5384 if (!kvm)
5385 return ERR_PTR(-ENOMEM);
5386
fef9cce0
MT		 5387 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5388 if (!kvm->arch.aliases) {
5389 kfree(kvm);
5390 return ERR_PTR(-ENOMEM);
5391 }
5392
f05e70ac 5393 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5394 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5395
5550af4d
SY		 5396 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5397 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5398
53f658b3
MT		 5399 rdtscll(kvm->arch.vm_init_tsc);
5400
d19a9cd2
ZX		 5401 return kvm;
5402}
5403
5404static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5405{
5406 vcpu_load(vcpu);
5407 kvm_mmu_unload(vcpu);
5408 vcpu_put(vcpu);
5409}
5410
5411static void kvm_free_vcpus(struct kvm *kvm)
5412{
5413 unsigned int i;
988a2cae 5414 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5415
5416 /*
5417 * Unpin any mmu pages first.
5418 */
988a2cae
GN		 5419 kvm_for_each_vcpu(i, vcpu, kvm)
5420 kvm_unload_vcpu_mmu(vcpu);
5421 kvm_for_each_vcpu(i, vcpu, kvm)
5422 kvm_arch_vcpu_free(vcpu);
5423
5424 mutex_lock(&kvm->lock);
5425 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5426 kvm->vcpus[i] = NULL;
d19a9cd2 5427
988a2cae
GN		 5428 atomic_set(&kvm->online_vcpus, 0);
5429 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5430}
5431
ad8ba2cd
SY		 5432void kvm_arch_sync_events(struct kvm *kvm)
5433{
ba4cef31 5434 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5435}
5436
d19a9cd2
ZX		 5437void kvm_arch_destroy_vm(struct kvm *kvm)
5438{
6eb55818 5439 kvm_iommu_unmap_guest(kvm);
7837699f 5440 kvm_free_pit(kvm);
d7deeeb0
ZX		 5441 kfree(kvm->arch.vpic);
5442 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5443 kvm_free_vcpus(kvm);
5444 kvm_free_physmem(kvm);
3d45830c
AK		 5445 if (kvm->arch.apic_access_page)
5446 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5447 if (kvm->arch.ept_identity_pagetable)
5448 put_page(kvm->arch.ept_identity_pagetable);
64749204 5449 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5450 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5451 kfree(kvm);
5452}
0de10343 5453
f7784b8e
MT		 5454int kvm_arch_prepare_memory_region(struct kvm *kvm,
5455 struct kvm_memory_slot *memslot,
0de10343 5456 struct kvm_memory_slot old,
f7784b8e 5457 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5458 int user_alloc)
5459{
f7784b8e 5460 int npages = memslot->npages;
0de10343
ZX		 5461
5462 /*To keep backward compatibility with older userspace,
5463 *x86 needs to hanlde !user_alloc case.
5464 */
5465 if (!user_alloc) {
5466 if (npages && !old.rmap) {
604b38ac
AA		 5467 unsigned long userspace_addr;
5468
72dc67a6 5469 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5470 userspace_addr = do_mmap(NULL, 0,
5471 npages * PAGE_SIZE,
5472 PROT_READ | PROT_WRITE,
acee3c04 5473 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5474 0);
72dc67a6 5475 up_write(&current->mm->mmap_sem);
0de10343 5476
604b38ac
AA		 5477 if (IS_ERR((void *)userspace_addr))
5478 return PTR_ERR((void *)userspace_addr);
5479
604b38ac 5480 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5481 }
5482 }
5483
f7784b8e
MT		 5484
5485 return 0;
5486}
5487
5488void kvm_arch_commit_memory_region(struct kvm *kvm,
5489 struct kvm_userspace_memory_region *mem,
5490 struct kvm_memory_slot old,
5491 int user_alloc)
5492{
5493
5494 int npages = mem->memory_size >> PAGE_SHIFT;
5495
5496 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5497 int ret;
5498
5499 down_write(&current->mm->mmap_sem);
5500 ret = do_munmap(current->mm, old.userspace_addr,
5501 old.npages * PAGE_SIZE);
5502 up_write(&current->mm->mmap_sem);
5503 if (ret < 0)
5504 printk(KERN_WARNING
5505 "kvm_vm_ioctl_set_memory_region: "
5506 "failed to munmap memory\n");
5507 }
5508
7c8a83b7 5509 spin_lock(&kvm->mmu_lock);
f05e70ac 5510 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5511 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5512 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5513 }
5514
5515 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5516 spin_unlock(&kvm->mmu_lock);
0de10343 5517}
1d737c8a 5518
34d4cb8f
MT		 5519void kvm_arch_flush_shadow(struct kvm *kvm)
5520{
5521 kvm_mmu_zap_all(kvm);
8986ecc0 5522 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5523}
5524
1d737c8a
ZX		 5525int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5526{
a4535290 5527 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5528 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5529 || vcpu->arch.nmi_pending ||
5530 (kvm_arch_interrupt_allowed(vcpu) &&
5531 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5532}
5736199a 5533
5736199a
ZX		 5534void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5535{
32f88400
MT		 5536 int me;
5537 int cpu = vcpu->cpu;
5736199a
ZX		 5538
5539 if (waitqueue_active(&vcpu->wq)) {
5540 wake_up_interruptible(&vcpu->wq);
5541 ++vcpu->stat.halt_wakeup;
5542 }
32f88400
MT		 5543
5544 me = get_cpu();
5545 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5546 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5547 smp_send_reschedule(cpu);
e9571ed5 5548 put_cpu();
5736199a 5549}
78646121
GN		 5550
5551int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5552{
5553 return kvm_x86_ops->interrupt_allowed(vcpu);
5554}
229456fc 5555
f92653ee
JK		 5556bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5557{
5558 unsigned long current_rip = kvm_rip_read(vcpu) +
5559 get_segment_base(vcpu, VCPU_SREG_CS);
5560
5561 return current_rip == linear_rip;
5562}
5563EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5564
94fe45da
JK		 5565unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5566{
5567 unsigned long rflags;
5568
5569 rflags = kvm_x86_ops->get_rflags(vcpu);
5570 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5571 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5572 return rflags;
5573}
5574EXPORT_SYMBOL_GPL(kvm_get_rflags);
5575
5576void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5577{
5578 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5579 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5580 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5581 kvm_x86_ops->set_rflags(vcpu, rflags);
5582}
5583EXPORT_SYMBOL_GPL(kvm_set_rflags);
5584
229456fc
MT		 5585EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5586EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5587EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5588EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5589EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5590EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5591EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5592EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5593EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5594EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5595EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5596EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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