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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 8 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
cafd6659 | 31 | #include <linux/tboot.h> |
5fdbf976 | 32 | #include "kvm_cache_regs.h" |
35920a35 | 33 | #include "x86.h" |
e495606d | 34 | |
6aa8b732 | 35 | #include <asm/io.h> |
3b3be0d1 | 36 | #include <asm/desc.h> |
13673a90 | 37 | #include <asm/vmx.h> |
6210e37b | 38 | #include <asm/virtext.h> |
a0861c02 | 39 | #include <asm/mce.h> |
2acf923e DC |
40 | #include <asm/i387.h> |
41 | #include <asm/xcr.h> | |
6aa8b732 | 42 | |
229456fc MT |
43 | #include "trace.h" |
44 | ||
4ecac3fd AK |
45 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
46 | ||
6aa8b732 AK |
47 | MODULE_AUTHOR("Qumranet"); |
48 | MODULE_LICENSE("GPL"); | |
49 | ||
4462d21a | 50 | static int __read_mostly bypass_guest_pf = 1; |
c1f8bc04 | 51 | module_param(bypass_guest_pf, bool, S_IRUGO); |
c7addb90 | 52 | |
4462d21a | 53 | static int __read_mostly enable_vpid = 1; |
736caefe | 54 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 55 | |
4462d21a | 56 | static int __read_mostly flexpriority_enabled = 1; |
736caefe | 57 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 58 | |
4462d21a | 59 | static int __read_mostly enable_ept = 1; |
736caefe | 60 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 61 | |
3a624e29 NK |
62 | static int __read_mostly enable_unrestricted_guest = 1; |
63 | module_param_named(unrestricted_guest, | |
64 | enable_unrestricted_guest, bool, S_IRUGO); | |
65 | ||
4462d21a | 66 | static int __read_mostly emulate_invalid_guest_state = 0; |
c1f8bc04 | 67 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 68 | |
b923e62e DX |
69 | static int __read_mostly vmm_exclusive = 1; |
70 | module_param(vmm_exclusive, bool, S_IRUGO); | |
71 | ||
cdc0e244 AK |
72 | #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \ |
73 | (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD) | |
74 | #define KVM_GUEST_CR0_MASK \ | |
75 | (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
76 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \ | |
81231c69 | 77 | (X86_CR0_WP | X86_CR0_NE) |
cdc0e244 AK |
78 | #define KVM_VM_CR0_ALWAYS_ON \ |
79 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
80 | #define KVM_CR4_GUEST_OWNED_BITS \ |
81 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
82 | | X86_CR4_OSXMMEXCPT) | |
83 | ||
cdc0e244 AK |
84 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
85 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
86 | ||
78ac8b47 AK |
87 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
88 | ||
4b8d54f9 ZE |
89 | /* |
90 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
91 | * ple_gap: upper bound on the amount of time between two successive | |
92 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
93 | * According to test, this time is usually small than 41 cycles. | |
94 | * ple_window: upper bound on the amount of time a guest is allowed to execute | |
95 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
96 | * less than 2^12 cycles | |
97 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
98 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
99 | */ | |
100 | #define KVM_VMX_DEFAULT_PLE_GAP 41 | |
101 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
102 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; | |
103 | module_param(ple_gap, int, S_IRUGO); | |
104 | ||
105 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
106 | module_param(ple_window, int, S_IRUGO); | |
107 | ||
61d2ef2c AK |
108 | #define NR_AUTOLOAD_MSRS 1 |
109 | ||
a2fa3e9f GH |
110 | struct vmcs { |
111 | u32 revision_id; | |
112 | u32 abort; | |
113 | char data[0]; | |
114 | }; | |
115 | ||
26bb0981 AK |
116 | struct shared_msr_entry { |
117 | unsigned index; | |
118 | u64 data; | |
d5696725 | 119 | u64 mask; |
26bb0981 AK |
120 | }; |
121 | ||
a2fa3e9f | 122 | struct vcpu_vmx { |
fb3f0f51 | 123 | struct kvm_vcpu vcpu; |
543e4243 | 124 | struct list_head local_vcpus_link; |
313dbd49 | 125 | unsigned long host_rsp; |
a2fa3e9f | 126 | int launched; |
29bd8a78 | 127 | u8 fail; |
1155f76a | 128 | u32 idt_vectoring_info; |
26bb0981 | 129 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
130 | int nmsrs; |
131 | int save_nmsrs; | |
a2fa3e9f | 132 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
133 | u64 msr_host_kernel_gs_base; |
134 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f GH |
135 | #endif |
136 | struct vmcs *vmcs; | |
61d2ef2c AK |
137 | struct msr_autoload { |
138 | unsigned nr; | |
139 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
140 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
141 | } msr_autoload; | |
a2fa3e9f GH |
142 | struct { |
143 | int loaded; | |
144 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
145 | int gs_ldt_reload_needed; |
146 | int fs_reload_needed; | |
d77c26fc | 147 | } host_state; |
9c8cba37 | 148 | struct { |
7ffd92c5 | 149 | int vm86_active; |
78ac8b47 | 150 | ulong save_rflags; |
7ffd92c5 AK |
151 | struct kvm_save_segment { |
152 | u16 selector; | |
153 | unsigned long base; | |
154 | u32 limit; | |
155 | u32 ar; | |
156 | } tr, es, ds, fs, gs; | |
9c8cba37 AK |
157 | struct { |
158 | bool pending; | |
159 | u8 vector; | |
160 | unsigned rip; | |
161 | } irq; | |
162 | } rmode; | |
2384d2b3 | 163 | int vpid; |
04fa4d32 | 164 | bool emulation_required; |
3b86cd99 JK |
165 | |
166 | /* Support for vnmi-less CPUs */ | |
167 | int soft_vnmi_blocked; | |
168 | ktime_t entry_time; | |
169 | s64 vnmi_blocked_time; | |
a0861c02 | 170 | u32 exit_reason; |
4e47c7a6 SY |
171 | |
172 | bool rdtscp_enabled; | |
a2fa3e9f GH |
173 | }; |
174 | ||
175 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
176 | { | |
fb3f0f51 | 177 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
178 | } |
179 | ||
b7ebfb05 | 180 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 181 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
182 | static void kvm_cpu_vmxon(u64 addr); |
183 | static void kvm_cpu_vmxoff(void); | |
75880a01 | 184 | |
6aa8b732 AK |
185 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
186 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 187 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
3444d7da | 188 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 189 | |
3e7c73e9 AK |
190 | static unsigned long *vmx_io_bitmap_a; |
191 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
192 | static unsigned long *vmx_msr_bitmap_legacy; |
193 | static unsigned long *vmx_msr_bitmap_longmode; | |
fdef3ad1 | 194 | |
2384d2b3 SY |
195 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
196 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
197 | ||
1c3d14fe | 198 | static struct vmcs_config { |
6aa8b732 AK |
199 | int size; |
200 | int order; | |
201 | u32 revision_id; | |
1c3d14fe YS |
202 | u32 pin_based_exec_ctrl; |
203 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 204 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
205 | u32 vmexit_ctrl; |
206 | u32 vmentry_ctrl; | |
207 | } vmcs_config; | |
6aa8b732 | 208 | |
efff9e53 | 209 | static struct vmx_capability { |
d56f546d SY |
210 | u32 ept; |
211 | u32 vpid; | |
212 | } vmx_capability; | |
213 | ||
6aa8b732 AK |
214 | #define VMX_SEGMENT_FIELD(seg) \ |
215 | [VCPU_SREG_##seg] = { \ | |
216 | .selector = GUEST_##seg##_SELECTOR, \ | |
217 | .base = GUEST_##seg##_BASE, \ | |
218 | .limit = GUEST_##seg##_LIMIT, \ | |
219 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
220 | } | |
221 | ||
222 | static struct kvm_vmx_segment_field { | |
223 | unsigned selector; | |
224 | unsigned base; | |
225 | unsigned limit; | |
226 | unsigned ar_bytes; | |
227 | } kvm_vmx_segment_fields[] = { | |
228 | VMX_SEGMENT_FIELD(CS), | |
229 | VMX_SEGMENT_FIELD(DS), | |
230 | VMX_SEGMENT_FIELD(ES), | |
231 | VMX_SEGMENT_FIELD(FS), | |
232 | VMX_SEGMENT_FIELD(GS), | |
233 | VMX_SEGMENT_FIELD(SS), | |
234 | VMX_SEGMENT_FIELD(TR), | |
235 | VMX_SEGMENT_FIELD(LDTR), | |
236 | }; | |
237 | ||
26bb0981 AK |
238 | static u64 host_efer; |
239 | ||
6de4f3ad AK |
240 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
241 | ||
4d56c8a7 | 242 | /* |
8c06585d | 243 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
244 | * away by decrementing the array size. |
245 | */ | |
6aa8b732 | 246 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 247 | #ifdef CONFIG_X86_64 |
44ea2b17 | 248 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 249 | #endif |
8c06585d | 250 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 251 | }; |
9d8f549d | 252 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 253 | |
31299944 | 254 | static inline bool is_page_fault(u32 intr_info) |
6aa8b732 AK |
255 | { |
256 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
257 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 258 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
259 | } |
260 | ||
31299944 | 261 | static inline bool is_no_device(u32 intr_info) |
2ab455cc AL |
262 | { |
263 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
264 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 265 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
266 | } |
267 | ||
31299944 | 268 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 AL |
269 | { |
270 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
271 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 272 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
273 | } |
274 | ||
31299944 | 275 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
276 | { |
277 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
278 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
279 | } | |
280 | ||
31299944 | 281 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
282 | { |
283 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
284 | INTR_INFO_VALID_MASK)) == | |
285 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
286 | } | |
287 | ||
31299944 | 288 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 289 | { |
04547156 | 290 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
291 | } |
292 | ||
31299944 | 293 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 294 | { |
04547156 | 295 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
296 | } |
297 | ||
31299944 | 298 | static inline bool vm_need_tpr_shadow(struct kvm *kvm) |
6e5d865c | 299 | { |
04547156 | 300 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
6e5d865c YS |
301 | } |
302 | ||
31299944 | 303 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 304 | { |
04547156 SY |
305 | return vmcs_config.cpu_based_exec_ctrl & |
306 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
307 | } |
308 | ||
774ead3a | 309 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 310 | { |
04547156 SY |
311 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
312 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
313 | } | |
314 | ||
315 | static inline bool cpu_has_vmx_flexpriority(void) | |
316 | { | |
317 | return cpu_has_vmx_tpr_shadow() && | |
318 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
319 | } |
320 | ||
e799794e MT |
321 | static inline bool cpu_has_vmx_ept_execute_only(void) |
322 | { | |
31299944 | 323 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
324 | } |
325 | ||
326 | static inline bool cpu_has_vmx_eptp_uncacheable(void) | |
327 | { | |
31299944 | 328 | return vmx_capability.ept & VMX_EPTP_UC_BIT; |
e799794e MT |
329 | } |
330 | ||
331 | static inline bool cpu_has_vmx_eptp_writeback(void) | |
332 | { | |
31299944 | 333 | return vmx_capability.ept & VMX_EPTP_WB_BIT; |
e799794e MT |
334 | } |
335 | ||
336 | static inline bool cpu_has_vmx_ept_2m_page(void) | |
337 | { | |
31299944 | 338 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
339 | } |
340 | ||
878403b7 SY |
341 | static inline bool cpu_has_vmx_ept_1g_page(void) |
342 | { | |
31299944 | 343 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
344 | } |
345 | ||
4bc9b982 SY |
346 | static inline bool cpu_has_vmx_ept_4levels(void) |
347 | { | |
348 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
349 | } | |
350 | ||
31299944 | 351 | static inline bool cpu_has_vmx_invept_individual_addr(void) |
d56f546d | 352 | { |
31299944 | 353 | return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT; |
d56f546d SY |
354 | } |
355 | ||
31299944 | 356 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 357 | { |
31299944 | 358 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
359 | } |
360 | ||
31299944 | 361 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 362 | { |
31299944 | 363 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
364 | } |
365 | ||
518c8aee GJ |
366 | static inline bool cpu_has_vmx_invvpid_single(void) |
367 | { | |
368 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
369 | } | |
370 | ||
b9d762fa GJ |
371 | static inline bool cpu_has_vmx_invvpid_global(void) |
372 | { | |
373 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
374 | } | |
375 | ||
31299944 | 376 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 377 | { |
04547156 SY |
378 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
379 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
380 | } |
381 | ||
31299944 | 382 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
383 | { |
384 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
385 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
386 | } | |
387 | ||
31299944 | 388 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
389 | { |
390 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
391 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
392 | } | |
393 | ||
31299944 | 394 | static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) |
f78e0e2e | 395 | { |
6d3e435e | 396 | return flexpriority_enabled && irqchip_in_kernel(kvm); |
f78e0e2e SY |
397 | } |
398 | ||
31299944 | 399 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 400 | { |
04547156 SY |
401 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
402 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
403 | } |
404 | ||
31299944 | 405 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
406 | { |
407 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
408 | SECONDARY_EXEC_RDTSCP; | |
409 | } | |
410 | ||
31299944 | 411 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
412 | { |
413 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
414 | } | |
415 | ||
f5f48ee1 SY |
416 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
417 | { | |
418 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
419 | SECONDARY_EXEC_WBINVD_EXITING; | |
420 | } | |
421 | ||
04547156 SY |
422 | static inline bool report_flexpriority(void) |
423 | { | |
424 | return flexpriority_enabled; | |
425 | } | |
426 | ||
8b9cf98c | 427 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
428 | { |
429 | int i; | |
430 | ||
a2fa3e9f | 431 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 432 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
433 | return i; |
434 | return -1; | |
435 | } | |
436 | ||
2384d2b3 SY |
437 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
438 | { | |
439 | struct { | |
440 | u64 vpid : 16; | |
441 | u64 rsvd : 48; | |
442 | u64 gva; | |
443 | } operand = { vpid, 0, gva }; | |
444 | ||
4ecac3fd | 445 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
446 | /* CF==1 or ZF==1 --> rc = -1 */ |
447 | "; ja 1f ; ud2 ; 1:" | |
448 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
449 | } | |
450 | ||
1439442c SY |
451 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
452 | { | |
453 | struct { | |
454 | u64 eptp, gpa; | |
455 | } operand = {eptp, gpa}; | |
456 | ||
4ecac3fd | 457 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
458 | /* CF==1 or ZF==1 --> rc = -1 */ |
459 | "; ja 1f ; ud2 ; 1:\n" | |
460 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
461 | } | |
462 | ||
26bb0981 | 463 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
464 | { |
465 | int i; | |
466 | ||
8b9cf98c | 467 | i = __find_msr_index(vmx, msr); |
a75beee6 | 468 | if (i >= 0) |
a2fa3e9f | 469 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 470 | return NULL; |
7725f0ba AK |
471 | } |
472 | ||
6aa8b732 AK |
473 | static void vmcs_clear(struct vmcs *vmcs) |
474 | { | |
475 | u64 phys_addr = __pa(vmcs); | |
476 | u8 error; | |
477 | ||
4ecac3fd | 478 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
479 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
480 | : "cc", "memory"); | |
481 | if (error) | |
482 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
483 | vmcs, phys_addr); | |
484 | } | |
485 | ||
7725b894 DX |
486 | static void vmcs_load(struct vmcs *vmcs) |
487 | { | |
488 | u64 phys_addr = __pa(vmcs); | |
489 | u8 error; | |
490 | ||
491 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
492 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
493 | : "cc", "memory"); | |
494 | if (error) | |
495 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
496 | vmcs, phys_addr); | |
497 | } | |
498 | ||
6aa8b732 AK |
499 | static void __vcpu_clear(void *arg) |
500 | { | |
8b9cf98c | 501 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 502 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 503 | |
8b9cf98c | 504 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
505 | vmcs_clear(vmx->vmcs); |
506 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 507 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 508 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
509 | list_del(&vmx->local_vcpus_link); |
510 | vmx->vcpu.cpu = -1; | |
511 | vmx->launched = 0; | |
6aa8b732 AK |
512 | } |
513 | ||
8b9cf98c | 514 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 515 | { |
eae5ecb5 AK |
516 | if (vmx->vcpu.cpu == -1) |
517 | return; | |
8691e5a8 | 518 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
519 | } |
520 | ||
1760dd49 | 521 | static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx) |
2384d2b3 SY |
522 | { |
523 | if (vmx->vpid == 0) | |
524 | return; | |
525 | ||
518c8aee GJ |
526 | if (cpu_has_vmx_invvpid_single()) |
527 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
2384d2b3 SY |
528 | } |
529 | ||
b9d762fa GJ |
530 | static inline void vpid_sync_vcpu_global(void) |
531 | { | |
532 | if (cpu_has_vmx_invvpid_global()) | |
533 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
534 | } | |
535 | ||
536 | static inline void vpid_sync_context(struct vcpu_vmx *vmx) | |
537 | { | |
538 | if (cpu_has_vmx_invvpid_single()) | |
1760dd49 | 539 | vpid_sync_vcpu_single(vmx); |
b9d762fa GJ |
540 | else |
541 | vpid_sync_vcpu_global(); | |
542 | } | |
543 | ||
1439442c SY |
544 | static inline void ept_sync_global(void) |
545 | { | |
546 | if (cpu_has_vmx_invept_global()) | |
547 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
548 | } | |
549 | ||
550 | static inline void ept_sync_context(u64 eptp) | |
551 | { | |
089d034e | 552 | if (enable_ept) { |
1439442c SY |
553 | if (cpu_has_vmx_invept_context()) |
554 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
555 | else | |
556 | ept_sync_global(); | |
557 | } | |
558 | } | |
559 | ||
560 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
561 | { | |
089d034e | 562 | if (enable_ept) { |
1439442c SY |
563 | if (cpu_has_vmx_invept_individual_addr()) |
564 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
565 | eptp, gpa); | |
566 | else | |
567 | ept_sync_context(eptp); | |
568 | } | |
569 | } | |
570 | ||
6aa8b732 AK |
571 | static unsigned long vmcs_readl(unsigned long field) |
572 | { | |
573 | unsigned long value; | |
574 | ||
4ecac3fd | 575 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
576 | : "=a"(value) : "d"(field) : "cc"); |
577 | return value; | |
578 | } | |
579 | ||
580 | static u16 vmcs_read16(unsigned long field) | |
581 | { | |
582 | return vmcs_readl(field); | |
583 | } | |
584 | ||
585 | static u32 vmcs_read32(unsigned long field) | |
586 | { | |
587 | return vmcs_readl(field); | |
588 | } | |
589 | ||
590 | static u64 vmcs_read64(unsigned long field) | |
591 | { | |
05b3e0c2 | 592 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
593 | return vmcs_readl(field); |
594 | #else | |
595 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
596 | #endif | |
597 | } | |
598 | ||
e52de1b8 AK |
599 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
600 | { | |
601 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
602 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
603 | dump_stack(); | |
604 | } | |
605 | ||
6aa8b732 AK |
606 | static void vmcs_writel(unsigned long field, unsigned long value) |
607 | { | |
608 | u8 error; | |
609 | ||
4ecac3fd | 610 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 611 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
612 | if (unlikely(error)) |
613 | vmwrite_error(field, value); | |
6aa8b732 AK |
614 | } |
615 | ||
616 | static void vmcs_write16(unsigned long field, u16 value) | |
617 | { | |
618 | vmcs_writel(field, value); | |
619 | } | |
620 | ||
621 | static void vmcs_write32(unsigned long field, u32 value) | |
622 | { | |
623 | vmcs_writel(field, value); | |
624 | } | |
625 | ||
626 | static void vmcs_write64(unsigned long field, u64 value) | |
627 | { | |
6aa8b732 | 628 | vmcs_writel(field, value); |
7682f2d0 | 629 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
630 | asm volatile (""); |
631 | vmcs_writel(field+1, value >> 32); | |
632 | #endif | |
633 | } | |
634 | ||
2ab455cc AL |
635 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
636 | { | |
637 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
638 | } | |
639 | ||
640 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
641 | { | |
642 | vmcs_writel(field, vmcs_readl(field) | mask); | |
643 | } | |
644 | ||
abd3f2d6 AK |
645 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
646 | { | |
647 | u32 eb; | |
648 | ||
fd7373cc JK |
649 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
650 | (1u << NM_VECTOR) | (1u << DB_VECTOR); | |
651 | if ((vcpu->guest_debug & | |
652 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
653 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
654 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 655 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 656 | eb = ~0; |
089d034e | 657 | if (enable_ept) |
1439442c | 658 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
659 | if (vcpu->fpu_active) |
660 | eb &= ~(1u << NM_VECTOR); | |
abd3f2d6 AK |
661 | vmcs_write32(EXCEPTION_BITMAP, eb); |
662 | } | |
663 | ||
61d2ef2c AK |
664 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
665 | { | |
666 | unsigned i; | |
667 | struct msr_autoload *m = &vmx->msr_autoload; | |
668 | ||
669 | for (i = 0; i < m->nr; ++i) | |
670 | if (m->guest[i].index == msr) | |
671 | break; | |
672 | ||
673 | if (i == m->nr) | |
674 | return; | |
675 | --m->nr; | |
676 | m->guest[i] = m->guest[m->nr]; | |
677 | m->host[i] = m->host[m->nr]; | |
678 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
679 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
680 | } | |
681 | ||
682 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, | |
683 | u64 guest_val, u64 host_val) | |
684 | { | |
685 | unsigned i; | |
686 | struct msr_autoload *m = &vmx->msr_autoload; | |
687 | ||
688 | for (i = 0; i < m->nr; ++i) | |
689 | if (m->guest[i].index == msr) | |
690 | break; | |
691 | ||
692 | if (i == m->nr) { | |
693 | ++m->nr; | |
694 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
695 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
696 | } | |
697 | ||
698 | m->guest[i].index = msr; | |
699 | m->guest[i].value = guest_val; | |
700 | m->host[i].index = msr; | |
701 | m->host[i].value = host_val; | |
702 | } | |
703 | ||
33ed6329 AK |
704 | static void reload_tss(void) |
705 | { | |
33ed6329 AK |
706 | /* |
707 | * VT restores TR but not its size. Useless. | |
708 | */ | |
89a27f4d | 709 | struct desc_ptr gdt; |
a5f61300 | 710 | struct desc_struct *descs; |
33ed6329 | 711 | |
d6ab1ed4 | 712 | native_store_gdt(&gdt); |
89a27f4d | 713 | descs = (void *)gdt.address; |
33ed6329 AK |
714 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
715 | load_TR_desc(); | |
33ed6329 AK |
716 | } |
717 | ||
92c0d900 | 718 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 719 | { |
3a34a881 | 720 | u64 guest_efer; |
51c6cf66 AK |
721 | u64 ignore_bits; |
722 | ||
f6801dff | 723 | guest_efer = vmx->vcpu.arch.efer; |
3a34a881 | 724 | |
51c6cf66 AK |
725 | /* |
726 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
727 | * outside long mode | |
728 | */ | |
729 | ignore_bits = EFER_NX | EFER_SCE; | |
730 | #ifdef CONFIG_X86_64 | |
731 | ignore_bits |= EFER_LMA | EFER_LME; | |
732 | /* SCE is meaningful only in long mode on Intel */ | |
733 | if (guest_efer & EFER_LMA) | |
734 | ignore_bits &= ~(u64)EFER_SCE; | |
735 | #endif | |
51c6cf66 AK |
736 | guest_efer &= ~ignore_bits; |
737 | guest_efer |= host_efer & ignore_bits; | |
26bb0981 | 738 | vmx->guest_msrs[efer_offset].data = guest_efer; |
d5696725 | 739 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
84ad33ef AK |
740 | |
741 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
742 | /* On ept, can't emulate nx, and must switch nx atomically */ | |
743 | if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) { | |
744 | guest_efer = vmx->vcpu.arch.efer; | |
745 | if (!(guest_efer & EFER_LMA)) | |
746 | guest_efer &= ~EFER_LME; | |
747 | add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer); | |
748 | return false; | |
749 | } | |
750 | ||
26bb0981 | 751 | return true; |
51c6cf66 AK |
752 | } |
753 | ||
2d49ec72 GN |
754 | static unsigned long segment_base(u16 selector) |
755 | { | |
756 | struct desc_ptr gdt; | |
757 | struct desc_struct *d; | |
758 | unsigned long table_base; | |
759 | unsigned long v; | |
760 | ||
761 | if (!(selector & ~3)) | |
762 | return 0; | |
763 | ||
764 | native_store_gdt(&gdt); | |
765 | table_base = gdt.address; | |
766 | ||
767 | if (selector & 4) { /* from ldt */ | |
768 | u16 ldt_selector = kvm_read_ldt(); | |
769 | ||
770 | if (!(ldt_selector & ~3)) | |
771 | return 0; | |
772 | ||
773 | table_base = segment_base(ldt_selector); | |
774 | } | |
775 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
776 | v = get_desc_base(d); | |
777 | #ifdef CONFIG_X86_64 | |
778 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
779 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
780 | #endif | |
781 | return v; | |
782 | } | |
783 | ||
784 | static inline unsigned long kvm_read_tr_base(void) | |
785 | { | |
786 | u16 tr; | |
787 | asm("str %0" : "=g"(tr)); | |
788 | return segment_base(tr); | |
789 | } | |
790 | ||
04d2cc77 | 791 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 792 | { |
04d2cc77 | 793 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 794 | int i; |
04d2cc77 | 795 | |
a2fa3e9f | 796 | if (vmx->host_state.loaded) |
33ed6329 AK |
797 | return; |
798 | ||
a2fa3e9f | 799 | vmx->host_state.loaded = 1; |
33ed6329 AK |
800 | /* |
801 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
802 | * allow segment selectors with cpl > 0 or ti == 1. | |
803 | */ | |
d6e88aec | 804 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 805 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 806 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 807 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 808 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
809 | vmx->host_state.fs_reload_needed = 0; |
810 | } else { | |
33ed6329 | 811 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 812 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 813 | } |
9581d442 | 814 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
815 | if (!(vmx->host_state.gs_sel & 7)) |
816 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
817 | else { |
818 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 819 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
820 | } |
821 | ||
822 | #ifdef CONFIG_X86_64 | |
823 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
824 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
825 | #else | |
a2fa3e9f GH |
826 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
827 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 828 | #endif |
707c0874 AK |
829 | |
830 | #ifdef CONFIG_X86_64 | |
44ea2b17 AK |
831 | if (is_long_mode(&vmx->vcpu)) { |
832 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); | |
833 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
834 | } | |
707c0874 | 835 | #endif |
26bb0981 AK |
836 | for (i = 0; i < vmx->save_nmsrs; ++i) |
837 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
838 | vmx->guest_msrs[i].data, |
839 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
840 | } |
841 | ||
a9b21b62 | 842 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 843 | { |
a2fa3e9f | 844 | if (!vmx->host_state.loaded) |
33ed6329 AK |
845 | return; |
846 | ||
e1beb1d3 | 847 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 848 | vmx->host_state.loaded = 0; |
152d3f2f | 849 | if (vmx->host_state.fs_reload_needed) |
9581d442 | 850 | loadsegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 851 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 852 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 853 | #ifdef CONFIG_X86_64 |
9581d442 AK |
854 | load_gs_index(vmx->host_state.gs_sel); |
855 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); | |
856 | #else | |
857 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 858 | #endif |
33ed6329 | 859 | } |
152d3f2f | 860 | reload_tss(); |
44ea2b17 AK |
861 | #ifdef CONFIG_X86_64 |
862 | if (is_long_mode(&vmx->vcpu)) { | |
863 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
864 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); | |
865 | } | |
866 | #endif | |
1c11e713 AK |
867 | if (current_thread_info()->status & TS_USEDFPU) |
868 | clts(); | |
3444d7da | 869 | load_gdt(&__get_cpu_var(host_gdt)); |
33ed6329 AK |
870 | } |
871 | ||
a9b21b62 AK |
872 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
873 | { | |
874 | preempt_disable(); | |
875 | __vmx_load_host_state(vmx); | |
876 | preempt_enable(); | |
877 | } | |
878 | ||
6aa8b732 AK |
879 | /* |
880 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
881 | * vcpu mutex is already taken. | |
882 | */ | |
15ad7146 | 883 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 884 | { |
a2fa3e9f | 885 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
019960ae | 886 | u64 tsc_this, delta, new_offset; |
4610c9cc | 887 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 888 | |
4610c9cc DX |
889 | if (!vmm_exclusive) |
890 | kvm_cpu_vmxon(phys_addr); | |
891 | else if (vcpu->cpu != cpu) | |
8b9cf98c | 892 | vcpu_clear(vmx); |
6aa8b732 | 893 | |
a2fa3e9f | 894 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
a2fa3e9f | 895 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
7725b894 | 896 | vmcs_load(vmx->vmcs); |
6aa8b732 AK |
897 | } |
898 | ||
899 | if (vcpu->cpu != cpu) { | |
89a27f4d | 900 | struct desc_ptr dt; |
6aa8b732 AK |
901 | unsigned long sysenter_esp; |
902 | ||
92fe13be | 903 | kvm_migrate_timers(vcpu); |
a8eeb04a | 904 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be DX |
905 | local_irq_disable(); |
906 | list_add(&vmx->local_vcpus_link, | |
907 | &per_cpu(vcpus_on_cpu, cpu)); | |
908 | local_irq_enable(); | |
909 | ||
6aa8b732 AK |
910 | vcpu->cpu = cpu; |
911 | /* | |
912 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
913 | * processors. | |
914 | */ | |
d6e88aec | 915 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d6ab1ed4 | 916 | native_store_gdt(&dt); |
89a27f4d | 917 | vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */ |
6aa8b732 AK |
918 | |
919 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
920 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
921 | |
922 | /* | |
923 | * Make sure the time stamp counter is monotonous. | |
924 | */ | |
925 | rdtscll(tsc_this); | |
019960ae AK |
926 | if (tsc_this < vcpu->arch.host_tsc) { |
927 | delta = vcpu->arch.host_tsc - tsc_this; | |
928 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
929 | vmcs_write64(TSC_OFFSET, new_offset); | |
930 | } | |
6aa8b732 | 931 | } |
6aa8b732 AK |
932 | } |
933 | ||
934 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
935 | { | |
a9b21b62 | 936 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 937 | if (!vmm_exclusive) { |
b923e62e | 938 | __vcpu_clear(to_vmx(vcpu)); |
4610c9cc DX |
939 | kvm_cpu_vmxoff(); |
940 | } | |
6aa8b732 AK |
941 | } |
942 | ||
5fd86fcf AK |
943 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
944 | { | |
81231c69 AK |
945 | ulong cr0; |
946 | ||
5fd86fcf AK |
947 | if (vcpu->fpu_active) |
948 | return; | |
949 | vcpu->fpu_active = 1; | |
81231c69 AK |
950 | cr0 = vmcs_readl(GUEST_CR0); |
951 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
952 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
953 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 954 | update_exception_bitmap(vcpu); |
edcafe3c AK |
955 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
956 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
5fd86fcf AK |
957 | } |
958 | ||
edcafe3c AK |
959 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
960 | ||
5fd86fcf AK |
961 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
962 | { | |
edcafe3c | 963 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 964 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 965 | update_exception_bitmap(vcpu); |
edcafe3c AK |
966 | vcpu->arch.cr0_guest_owned_bits = 0; |
967 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
968 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
969 | } |
970 | ||
6aa8b732 AK |
971 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
972 | { | |
78ac8b47 | 973 | unsigned long rflags, save_rflags; |
345dcaa8 AK |
974 | |
975 | rflags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
976 | if (to_vmx(vcpu)->rmode.vm86_active) { |
977 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
978 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
979 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
980 | } | |
345dcaa8 | 981 | return rflags; |
6aa8b732 AK |
982 | } |
983 | ||
984 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
985 | { | |
78ac8b47 AK |
986 | if (to_vmx(vcpu)->rmode.vm86_active) { |
987 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 988 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 989 | } |
6aa8b732 AK |
990 | vmcs_writel(GUEST_RFLAGS, rflags); |
991 | } | |
992 | ||
2809f5d2 GC |
993 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
994 | { | |
995 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
996 | int ret = 0; | |
997 | ||
998 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 999 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 1000 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 1001 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
1002 | |
1003 | return ret & mask; | |
1004 | } | |
1005 | ||
1006 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
1007 | { | |
1008 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1009 | u32 interruptibility = interruptibility_old; | |
1010 | ||
1011 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
1012 | ||
48005f64 | 1013 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 1014 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 1015 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
1016 | interruptibility |= GUEST_INTR_STATE_STI; |
1017 | ||
1018 | if ((interruptibility != interruptibility_old)) | |
1019 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
1020 | } | |
1021 | ||
6aa8b732 AK |
1022 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
1023 | { | |
1024 | unsigned long rip; | |
6aa8b732 | 1025 | |
5fdbf976 | 1026 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 1027 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 1028 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 1029 | |
2809f5d2 GC |
1030 | /* skipping an emulated instruction also counts */ |
1031 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
1032 | } |
1033 | ||
298101da | 1034 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
1035 | bool has_error_code, u32 error_code, |
1036 | bool reinject) | |
298101da | 1037 | { |
77ab6db0 | 1038 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 1039 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 1040 | |
8ab2d2e2 | 1041 | if (has_error_code) { |
77ab6db0 | 1042 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
1043 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
1044 | } | |
77ab6db0 | 1045 | |
7ffd92c5 | 1046 | if (vmx->rmode.vm86_active) { |
77ab6db0 JK |
1047 | vmx->rmode.irq.pending = true; |
1048 | vmx->rmode.irq.vector = nr; | |
1049 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
ae0bb3e0 GN |
1050 | if (kvm_exception_is_soft(nr)) |
1051 | vmx->rmode.irq.rip += | |
1052 | vmx->vcpu.arch.event_exit_inst_len; | |
8ab2d2e2 JK |
1053 | intr_info |= INTR_TYPE_SOFT_INTR; |
1054 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
77ab6db0 JK |
1055 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); |
1056 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
1057 | return; | |
1058 | } | |
1059 | ||
66fd3f7f GN |
1060 | if (kvm_exception_is_soft(nr)) { |
1061 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
1062 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
1063 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
1064 | } else | |
1065 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
1066 | ||
1067 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
1068 | } |
1069 | ||
4e47c7a6 SY |
1070 | static bool vmx_rdtscp_supported(void) |
1071 | { | |
1072 | return cpu_has_vmx_rdtscp(); | |
1073 | } | |
1074 | ||
a75beee6 ED |
1075 | /* |
1076 | * Swap MSR entry in host/guest MSR entry array. | |
1077 | */ | |
8b9cf98c | 1078 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 1079 | { |
26bb0981 | 1080 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
1081 | |
1082 | tmp = vmx->guest_msrs[to]; | |
1083 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
1084 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
1085 | } |
1086 | ||
e38aea3e AK |
1087 | /* |
1088 | * Set up the vmcs to automatically save and restore system | |
1089 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
1090 | * mode, as fiddling with msrs is very expensive. | |
1091 | */ | |
8b9cf98c | 1092 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 1093 | { |
26bb0981 | 1094 | int save_nmsrs, index; |
5897297b | 1095 | unsigned long *msr_bitmap; |
e38aea3e | 1096 | |
33f9c505 | 1097 | vmx_load_host_state(vmx); |
a75beee6 ED |
1098 | save_nmsrs = 0; |
1099 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 1100 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 1101 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 1102 | if (index >= 0) |
8b9cf98c RR |
1103 | move_msr_up(vmx, index, save_nmsrs++); |
1104 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 1105 | if (index >= 0) |
8b9cf98c RR |
1106 | move_msr_up(vmx, index, save_nmsrs++); |
1107 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 1108 | if (index >= 0) |
8b9cf98c | 1109 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 SY |
1110 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1111 | if (index >= 0 && vmx->rdtscp_enabled) | |
1112 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 | 1113 | /* |
8c06585d | 1114 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
1115 | * if efer.sce is enabled. |
1116 | */ | |
8c06585d | 1117 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 1118 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 1119 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
1120 | } |
1121 | #endif | |
92c0d900 AK |
1122 | index = __find_msr_index(vmx, MSR_EFER); |
1123 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 1124 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 1125 | |
26bb0981 | 1126 | vmx->save_nmsrs = save_nmsrs; |
5897297b AK |
1127 | |
1128 | if (cpu_has_vmx_msr_bitmap()) { | |
1129 | if (is_long_mode(&vmx->vcpu)) | |
1130 | msr_bitmap = vmx_msr_bitmap_longmode; | |
1131 | else | |
1132 | msr_bitmap = vmx_msr_bitmap_legacy; | |
1133 | ||
1134 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
1135 | } | |
e38aea3e AK |
1136 | } |
1137 | ||
6aa8b732 AK |
1138 | /* |
1139 | * reads and returns guest's timestamp counter "register" | |
1140 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
1141 | */ | |
1142 | static u64 guest_read_tsc(void) | |
1143 | { | |
1144 | u64 host_tsc, tsc_offset; | |
1145 | ||
1146 | rdtscll(host_tsc); | |
1147 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
1148 | return host_tsc + tsc_offset; | |
1149 | } | |
1150 | ||
1151 | /* | |
1152 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
1153 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
1154 | */ | |
53f658b3 | 1155 | static void guest_write_tsc(u64 guest_tsc, u64 host_tsc) |
6aa8b732 | 1156 | { |
6aa8b732 AK |
1157 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); |
1158 | } | |
1159 | ||
6aa8b732 AK |
1160 | /* |
1161 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1162 | * Returns 0 on success, non-0 otherwise. | |
1163 | * Assumes vcpu_load() was already called. | |
1164 | */ | |
1165 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1166 | { | |
1167 | u64 data; | |
26bb0981 | 1168 | struct shared_msr_entry *msr; |
6aa8b732 AK |
1169 | |
1170 | if (!pdata) { | |
1171 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
1175 | switch (msr_index) { | |
05b3e0c2 | 1176 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1177 | case MSR_FS_BASE: |
1178 | data = vmcs_readl(GUEST_FS_BASE); | |
1179 | break; | |
1180 | case MSR_GS_BASE: | |
1181 | data = vmcs_readl(GUEST_GS_BASE); | |
1182 | break; | |
44ea2b17 AK |
1183 | case MSR_KERNEL_GS_BASE: |
1184 | vmx_load_host_state(to_vmx(vcpu)); | |
1185 | data = to_vmx(vcpu)->msr_guest_kernel_gs_base; | |
1186 | break; | |
26bb0981 | 1187 | #endif |
6aa8b732 | 1188 | case MSR_EFER: |
3bab1f5d | 1189 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
af24a4e4 | 1190 | case MSR_IA32_TSC: |
6aa8b732 AK |
1191 | data = guest_read_tsc(); |
1192 | break; | |
1193 | case MSR_IA32_SYSENTER_CS: | |
1194 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
1195 | break; | |
1196 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1197 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
1198 | break; |
1199 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1200 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 1201 | break; |
4e47c7a6 SY |
1202 | case MSR_TSC_AUX: |
1203 | if (!to_vmx(vcpu)->rdtscp_enabled) | |
1204 | return 1; | |
1205 | /* Otherwise falls through */ | |
6aa8b732 | 1206 | default: |
26bb0981 | 1207 | vmx_load_host_state(to_vmx(vcpu)); |
8b9cf98c | 1208 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d | 1209 | if (msr) { |
542423b0 | 1210 | vmx_load_host_state(to_vmx(vcpu)); |
3bab1f5d AK |
1211 | data = msr->data; |
1212 | break; | |
6aa8b732 | 1213 | } |
3bab1f5d | 1214 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
1215 | } |
1216 | ||
1217 | *pdata = data; | |
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | /* | |
1222 | * Writes msr value into into the appropriate "register". | |
1223 | * Returns 0 on success, non-0 otherwise. | |
1224 | * Assumes vcpu_load() was already called. | |
1225 | */ | |
1226 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
1227 | { | |
a2fa3e9f | 1228 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 1229 | struct shared_msr_entry *msr; |
53f658b3 | 1230 | u64 host_tsc; |
2cc51560 ED |
1231 | int ret = 0; |
1232 | ||
6aa8b732 | 1233 | switch (msr_index) { |
3bab1f5d | 1234 | case MSR_EFER: |
a9b21b62 | 1235 | vmx_load_host_state(vmx); |
2cc51560 | 1236 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 1237 | break; |
16175a79 | 1238 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1239 | case MSR_FS_BASE: |
1240 | vmcs_writel(GUEST_FS_BASE, data); | |
1241 | break; | |
1242 | case MSR_GS_BASE: | |
1243 | vmcs_writel(GUEST_GS_BASE, data); | |
1244 | break; | |
44ea2b17 AK |
1245 | case MSR_KERNEL_GS_BASE: |
1246 | vmx_load_host_state(vmx); | |
1247 | vmx->msr_guest_kernel_gs_base = data; | |
1248 | break; | |
6aa8b732 AK |
1249 | #endif |
1250 | case MSR_IA32_SYSENTER_CS: | |
1251 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
1252 | break; | |
1253 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1254 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
1255 | break; |
1256 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1257 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 1258 | break; |
af24a4e4 | 1259 | case MSR_IA32_TSC: |
53f658b3 MT |
1260 | rdtscll(host_tsc); |
1261 | guest_write_tsc(data, host_tsc); | |
6aa8b732 | 1262 | break; |
468d472f SY |
1263 | case MSR_IA32_CR_PAT: |
1264 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
1265 | vmcs_write64(GUEST_IA32_PAT, data); | |
1266 | vcpu->arch.pat = data; | |
1267 | break; | |
1268 | } | |
4e47c7a6 SY |
1269 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
1270 | break; | |
1271 | case MSR_TSC_AUX: | |
1272 | if (!vmx->rdtscp_enabled) | |
1273 | return 1; | |
1274 | /* Check reserved bit, higher 32 bits should be zero */ | |
1275 | if ((data >> 32) != 0) | |
1276 | return 1; | |
1277 | /* Otherwise falls through */ | |
6aa8b732 | 1278 | default: |
8b9cf98c | 1279 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 1280 | if (msr) { |
542423b0 | 1281 | vmx_load_host_state(vmx); |
3bab1f5d AK |
1282 | msr->data = data; |
1283 | break; | |
6aa8b732 | 1284 | } |
2cc51560 | 1285 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
1286 | } |
1287 | ||
2cc51560 | 1288 | return ret; |
6aa8b732 AK |
1289 | } |
1290 | ||
5fdbf976 | 1291 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 1292 | { |
5fdbf976 MT |
1293 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
1294 | switch (reg) { | |
1295 | case VCPU_REGS_RSP: | |
1296 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
1297 | break; | |
1298 | case VCPU_REGS_RIP: | |
1299 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
1300 | break; | |
6de4f3ad AK |
1301 | case VCPU_EXREG_PDPTR: |
1302 | if (enable_ept) | |
1303 | ept_save_pdptrs(vcpu); | |
1304 | break; | |
5fdbf976 MT |
1305 | default: |
1306 | break; | |
1307 | } | |
6aa8b732 AK |
1308 | } |
1309 | ||
355be0b9 | 1310 | static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
6aa8b732 | 1311 | { |
ae675ef0 JK |
1312 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1313 | vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); | |
1314 | else | |
1315 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
1316 | ||
abd3f2d6 | 1317 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1318 | } |
1319 | ||
1320 | static __init int cpu_has_kvm_support(void) | |
1321 | { | |
6210e37b | 1322 | return cpu_has_vmx(); |
6aa8b732 AK |
1323 | } |
1324 | ||
1325 | static __init int vmx_disabled_by_bios(void) | |
1326 | { | |
1327 | u64 msr; | |
1328 | ||
1329 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 SW |
1330 | if (msr & FEATURE_CONTROL_LOCKED) { |
1331 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) | |
1332 | && tboot_enabled()) | |
1333 | return 1; | |
1334 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
1335 | && !tboot_enabled()) | |
1336 | return 1; | |
1337 | } | |
1338 | ||
1339 | return 0; | |
62b3ffb8 | 1340 | /* locked but not enabled */ |
6aa8b732 AK |
1341 | } |
1342 | ||
7725b894 DX |
1343 | static void kvm_cpu_vmxon(u64 addr) |
1344 | { | |
1345 | asm volatile (ASM_VMX_VMXON_RAX | |
1346 | : : "a"(&addr), "m"(addr) | |
1347 | : "memory", "cc"); | |
1348 | } | |
1349 | ||
10474ae8 | 1350 | static int hardware_enable(void *garbage) |
6aa8b732 AK |
1351 | { |
1352 | int cpu = raw_smp_processor_id(); | |
1353 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 1354 | u64 old, test_bits; |
6aa8b732 | 1355 | |
10474ae8 AG |
1356 | if (read_cr4() & X86_CR4_VMXE) |
1357 | return -EBUSY; | |
1358 | ||
543e4243 | 1359 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1360 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
1361 | |
1362 | test_bits = FEATURE_CONTROL_LOCKED; | |
1363 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1364 | if (tboot_enabled()) | |
1365 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
1366 | ||
1367 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 1368 | /* enable and lock */ |
cafd6659 SW |
1369 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
1370 | } | |
66aee91a | 1371 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
10474ae8 | 1372 | |
4610c9cc DX |
1373 | if (vmm_exclusive) { |
1374 | kvm_cpu_vmxon(phys_addr); | |
1375 | ept_sync_global(); | |
1376 | } | |
10474ae8 | 1377 | |
3444d7da AK |
1378 | store_gdt(&__get_cpu_var(host_gdt)); |
1379 | ||
10474ae8 | 1380 | return 0; |
6aa8b732 AK |
1381 | } |
1382 | ||
543e4243 AK |
1383 | static void vmclear_local_vcpus(void) |
1384 | { | |
1385 | int cpu = raw_smp_processor_id(); | |
1386 | struct vcpu_vmx *vmx, *n; | |
1387 | ||
1388 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1389 | local_vcpus_link) | |
1390 | __vcpu_clear(vmx); | |
1391 | } | |
1392 | ||
710ff4a8 EH |
1393 | |
1394 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
1395 | * tricks. | |
1396 | */ | |
1397 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 1398 | { |
4ecac3fd | 1399 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
6aa8b732 AK |
1400 | } |
1401 | ||
710ff4a8 EH |
1402 | static void hardware_disable(void *garbage) |
1403 | { | |
4610c9cc DX |
1404 | if (vmm_exclusive) { |
1405 | vmclear_local_vcpus(); | |
1406 | kvm_cpu_vmxoff(); | |
1407 | } | |
7725b894 | 1408 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
710ff4a8 EH |
1409 | } |
1410 | ||
1c3d14fe | 1411 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1412 | u32 msr, u32 *result) |
1c3d14fe YS |
1413 | { |
1414 | u32 vmx_msr_low, vmx_msr_high; | |
1415 | u32 ctl = ctl_min | ctl_opt; | |
1416 | ||
1417 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1418 | ||
1419 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1420 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1421 | ||
1422 | /* Ensure minimum (required) set of control bits are supported. */ | |
1423 | if (ctl_min & ~ctl) | |
002c7f7c | 1424 | return -EIO; |
1c3d14fe YS |
1425 | |
1426 | *result = ctl; | |
1427 | return 0; | |
1428 | } | |
1429 | ||
002c7f7c | 1430 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1431 | { |
1432 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1433 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1434 | u32 _pin_based_exec_control = 0; |
1435 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1436 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1437 | u32 _vmexit_control = 0; |
1438 | u32 _vmentry_control = 0; | |
1439 | ||
1440 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1441 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1442 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1443 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1444 | return -EIO; |
1c3d14fe YS |
1445 | |
1446 | min = CPU_BASED_HLT_EXITING | | |
1447 | #ifdef CONFIG_X86_64 | |
1448 | CPU_BASED_CR8_LOAD_EXITING | | |
1449 | CPU_BASED_CR8_STORE_EXITING | | |
1450 | #endif | |
d56f546d SY |
1451 | CPU_BASED_CR3_LOAD_EXITING | |
1452 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1453 | CPU_BASED_USE_IO_BITMAPS | |
1454 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 1455 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
1456 | CPU_BASED_MWAIT_EXITING | |
1457 | CPU_BASED_MONITOR_EXITING | | |
a7052897 | 1458 | CPU_BASED_INVLPG_EXITING; |
f78e0e2e | 1459 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1460 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1461 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1462 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1463 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1464 | return -EIO; |
6e5d865c YS |
1465 | #ifdef CONFIG_X86_64 |
1466 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1467 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1468 | ~CPU_BASED_CR8_STORE_EXITING; | |
1469 | #endif | |
f78e0e2e | 1470 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1471 | min2 = 0; |
1472 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1473 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 1474 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 1475 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 1476 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 SY |
1477 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
1478 | SECONDARY_EXEC_RDTSCP; | |
d56f546d SY |
1479 | if (adjust_vmx_controls(min2, opt2, |
1480 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1481 | &_cpu_based_2nd_exec_control) < 0) |
1482 | return -EIO; | |
1483 | } | |
1484 | #ifndef CONFIG_X86_64 | |
1485 | if (!(_cpu_based_2nd_exec_control & | |
1486 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1487 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1488 | #endif | |
d56f546d | 1489 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1490 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1491 | enabled */ | |
5fff7d27 GN |
1492 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
1493 | CPU_BASED_CR3_STORE_EXITING | | |
1494 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1495 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
1496 | vmx_capability.ept, vmx_capability.vpid); | |
1497 | } | |
1c3d14fe YS |
1498 | |
1499 | min = 0; | |
1500 | #ifdef CONFIG_X86_64 | |
1501 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1502 | #endif | |
468d472f | 1503 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
1504 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
1505 | &_vmexit_control) < 0) | |
002c7f7c | 1506 | return -EIO; |
1c3d14fe | 1507 | |
468d472f SY |
1508 | min = 0; |
1509 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
1510 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
1511 | &_vmentry_control) < 0) | |
002c7f7c | 1512 | return -EIO; |
6aa8b732 | 1513 | |
c68876fd | 1514 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1515 | |
1516 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1517 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1518 | return -EIO; |
1c3d14fe YS |
1519 | |
1520 | #ifdef CONFIG_X86_64 | |
1521 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1522 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1523 | return -EIO; |
1c3d14fe YS |
1524 | #endif |
1525 | ||
1526 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1527 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1528 | return -EIO; |
1c3d14fe | 1529 | |
002c7f7c YS |
1530 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1531 | vmcs_conf->order = get_order(vmcs_config.size); | |
1532 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1533 | |
002c7f7c YS |
1534 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1535 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1536 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1537 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1538 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1539 | |
1540 | return 0; | |
c68876fd | 1541 | } |
6aa8b732 AK |
1542 | |
1543 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1544 | { | |
1545 | int node = cpu_to_node(cpu); | |
1546 | struct page *pages; | |
1547 | struct vmcs *vmcs; | |
1548 | ||
6484eb3e | 1549 | pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1550 | if (!pages) |
1551 | return NULL; | |
1552 | vmcs = page_address(pages); | |
1c3d14fe YS |
1553 | memset(vmcs, 0, vmcs_config.size); |
1554 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1555 | return vmcs; |
1556 | } | |
1557 | ||
1558 | static struct vmcs *alloc_vmcs(void) | |
1559 | { | |
d3b2c338 | 1560 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1561 | } |
1562 | ||
1563 | static void free_vmcs(struct vmcs *vmcs) | |
1564 | { | |
1c3d14fe | 1565 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1566 | } |
1567 | ||
39959588 | 1568 | static void free_kvm_area(void) |
6aa8b732 AK |
1569 | { |
1570 | int cpu; | |
1571 | ||
3230bb47 | 1572 | for_each_possible_cpu(cpu) { |
6aa8b732 | 1573 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
1574 | per_cpu(vmxarea, cpu) = NULL; |
1575 | } | |
6aa8b732 AK |
1576 | } |
1577 | ||
6aa8b732 AK |
1578 | static __init int alloc_kvm_area(void) |
1579 | { | |
1580 | int cpu; | |
1581 | ||
3230bb47 | 1582 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1583 | struct vmcs *vmcs; |
1584 | ||
1585 | vmcs = alloc_vmcs_cpu(cpu); | |
1586 | if (!vmcs) { | |
1587 | free_kvm_area(); | |
1588 | return -ENOMEM; | |
1589 | } | |
1590 | ||
1591 | per_cpu(vmxarea, cpu) = vmcs; | |
1592 | } | |
1593 | return 0; | |
1594 | } | |
1595 | ||
1596 | static __init int hardware_setup(void) | |
1597 | { | |
002c7f7c YS |
1598 | if (setup_vmcs_config(&vmcs_config) < 0) |
1599 | return -EIO; | |
50a37eb4 JR |
1600 | |
1601 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1602 | kvm_enable_efer_bits(EFER_NX); | |
1603 | ||
93ba03c2 SY |
1604 | if (!cpu_has_vmx_vpid()) |
1605 | enable_vpid = 0; | |
1606 | ||
4bc9b982 SY |
1607 | if (!cpu_has_vmx_ept() || |
1608 | !cpu_has_vmx_ept_4levels()) { | |
93ba03c2 | 1609 | enable_ept = 0; |
3a624e29 NK |
1610 | enable_unrestricted_guest = 0; |
1611 | } | |
1612 | ||
1613 | if (!cpu_has_vmx_unrestricted_guest()) | |
1614 | enable_unrestricted_guest = 0; | |
93ba03c2 SY |
1615 | |
1616 | if (!cpu_has_vmx_flexpriority()) | |
1617 | flexpriority_enabled = 0; | |
1618 | ||
95ba8273 GN |
1619 | if (!cpu_has_vmx_tpr_shadow()) |
1620 | kvm_x86_ops->update_cr8_intercept = NULL; | |
1621 | ||
54dee993 MT |
1622 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) |
1623 | kvm_disable_largepages(); | |
1624 | ||
4b8d54f9 ZE |
1625 | if (!cpu_has_vmx_ple()) |
1626 | ple_gap = 0; | |
1627 | ||
6aa8b732 AK |
1628 | return alloc_kvm_area(); |
1629 | } | |
1630 | ||
1631 | static __exit void hardware_unsetup(void) | |
1632 | { | |
1633 | free_kvm_area(); | |
1634 | } | |
1635 | ||
6aa8b732 AK |
1636 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1637 | { | |
1638 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1639 | ||
6af11b9e | 1640 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1641 | vmcs_write16(sf->selector, save->selector); |
1642 | vmcs_writel(sf->base, save->base); | |
1643 | vmcs_write32(sf->limit, save->limit); | |
1644 | vmcs_write32(sf->ar_bytes, save->ar); | |
1645 | } else { | |
1646 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1647 | << AR_DPL_SHIFT; | |
1648 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1649 | } | |
1650 | } | |
1651 | ||
1652 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1653 | { | |
1654 | unsigned long flags; | |
a89a8fb9 | 1655 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1656 | |
a89a8fb9 | 1657 | vmx->emulation_required = 1; |
7ffd92c5 | 1658 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 1659 | |
7ffd92c5 AK |
1660 | vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base); |
1661 | vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit); | |
1662 | vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar); | |
6aa8b732 AK |
1663 | |
1664 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
1665 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
1666 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
1667 | vmcs_writel(GUEST_RFLAGS, flags); |
1668 | ||
66aee91a RR |
1669 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1670 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1671 | |
1672 | update_exception_bitmap(vcpu); | |
1673 | ||
a89a8fb9 MG |
1674 | if (emulate_invalid_guest_state) |
1675 | return; | |
1676 | ||
7ffd92c5 AK |
1677 | fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es); |
1678 | fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds); | |
1679 | fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs); | |
1680 | fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs); | |
6aa8b732 AK |
1681 | |
1682 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1683 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1684 | ||
1685 | vmcs_write16(GUEST_CS_SELECTOR, | |
1686 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1687 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1688 | } | |
1689 | ||
d77c26fc | 1690 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1691 | { |
bfc6d222 | 1692 | if (!kvm->arch.tss_addr) { |
bc6678a3 MT |
1693 | struct kvm_memslots *slots; |
1694 | gfn_t base_gfn; | |
1695 | ||
90d83dc3 | 1696 | slots = kvm_memslots(kvm); |
f495c6e5 | 1697 | base_gfn = slots->memslots[0].base_gfn + |
46a26bf5 | 1698 | kvm->memslots->memslots[0].npages - 3; |
cbc94022 IE |
1699 | return base_gfn << PAGE_SHIFT; |
1700 | } | |
bfc6d222 | 1701 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1702 | } |
1703 | ||
1704 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1705 | { | |
1706 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1707 | ||
1708 | save->selector = vmcs_read16(sf->selector); | |
1709 | save->base = vmcs_readl(sf->base); | |
1710 | save->limit = vmcs_read32(sf->limit); | |
1711 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1712 | vmcs_write16(sf->selector, save->base >> 4); |
1713 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1714 | vmcs_write32(sf->limit, 0xffff); |
1715 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1716 | } | |
1717 | ||
1718 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1719 | { | |
1720 | unsigned long flags; | |
a89a8fb9 | 1721 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1722 | |
3a624e29 NK |
1723 | if (enable_unrestricted_guest) |
1724 | return; | |
1725 | ||
a89a8fb9 | 1726 | vmx->emulation_required = 1; |
7ffd92c5 | 1727 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 1728 | |
7ffd92c5 | 1729 | vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1730 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1731 | ||
7ffd92c5 | 1732 | vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1733 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1734 | ||
7ffd92c5 | 1735 | vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1736 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1737 | ||
1738 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 1739 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 1740 | |
053de044 | 1741 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1742 | |
1743 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1744 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1745 | update_exception_bitmap(vcpu); |
1746 | ||
a89a8fb9 MG |
1747 | if (emulate_invalid_guest_state) |
1748 | goto continue_rmode; | |
1749 | ||
6aa8b732 AK |
1750 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
1751 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1752 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1753 | ||
1754 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1755 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1756 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1757 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1758 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1759 | ||
7ffd92c5 AK |
1760 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es); |
1761 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds); | |
1762 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs); | |
1763 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs); | |
75880a01 | 1764 | |
a89a8fb9 | 1765 | continue_rmode: |
8668a3c4 | 1766 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1767 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1768 | } |
1769 | ||
401d10de AS |
1770 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1771 | { | |
1772 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
1773 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
1774 | ||
1775 | if (!msr) | |
1776 | return; | |
401d10de | 1777 | |
44ea2b17 AK |
1778 | /* |
1779 | * Force kernel_gs_base reloading before EFER changes, as control | |
1780 | * of this msr depends on is_long_mode(). | |
1781 | */ | |
1782 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 1783 | vcpu->arch.efer = efer; |
401d10de AS |
1784 | if (efer & EFER_LMA) { |
1785 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1786 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1787 | VM_ENTRY_IA32E_MODE); | |
1788 | msr->data = efer; | |
1789 | } else { | |
1790 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1791 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1792 | ~VM_ENTRY_IA32E_MODE); | |
1793 | ||
1794 | msr->data = efer & ~EFER_LME; | |
1795 | } | |
1796 | setup_msrs(vmx); | |
1797 | } | |
1798 | ||
05b3e0c2 | 1799 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1800 | |
1801 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1802 | { | |
1803 | u32 guest_tr_ar; | |
1804 | ||
1805 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1806 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1807 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1808 | __func__); |
6aa8b732 AK |
1809 | vmcs_write32(GUEST_TR_AR_BYTES, |
1810 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1811 | | AR_TYPE_BUSY_64_TSS); | |
1812 | } | |
da38f438 | 1813 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
1814 | } |
1815 | ||
1816 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1817 | { | |
6aa8b732 AK |
1818 | vmcs_write32(VM_ENTRY_CONTROLS, |
1819 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1820 | & ~VM_ENTRY_IA32E_MODE); |
da38f438 | 1821 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
1822 | } |
1823 | ||
1824 | #endif | |
1825 | ||
2384d2b3 SY |
1826 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1827 | { | |
b9d762fa | 1828 | vpid_sync_context(to_vmx(vcpu)); |
dd180b3e XG |
1829 | if (enable_ept) { |
1830 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
1831 | return; | |
4e1096d2 | 1832 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 1833 | } |
2384d2b3 SY |
1834 | } |
1835 | ||
e8467fda AK |
1836 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1837 | { | |
1838 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
1839 | ||
1840 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
1841 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
1842 | } | |
1843 | ||
25c4c276 | 1844 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1845 | { |
fc78f519 AK |
1846 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
1847 | ||
1848 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
1849 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
1850 | } |
1851 | ||
1439442c SY |
1852 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1853 | { | |
6de4f3ad AK |
1854 | if (!test_bit(VCPU_EXREG_PDPTR, |
1855 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
1856 | return; | |
1857 | ||
1439442c | 1858 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
1439442c SY |
1859 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); |
1860 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1861 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1862 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1863 | } | |
1864 | } | |
1865 | ||
8f5d549f AK |
1866 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
1867 | { | |
1868 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1869 | vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0); | |
1870 | vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
1871 | vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
1872 | vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
1873 | } | |
6de4f3ad AK |
1874 | |
1875 | __set_bit(VCPU_EXREG_PDPTR, | |
1876 | (unsigned long *)&vcpu->arch.regs_avail); | |
1877 | __set_bit(VCPU_EXREG_PDPTR, | |
1878 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
1879 | } |
1880 | ||
1439442c SY |
1881 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1882 | ||
1883 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1884 | unsigned long cr0, | |
1885 | struct kvm_vcpu *vcpu) | |
1886 | { | |
1887 | if (!(cr0 & X86_CR0_PG)) { | |
1888 | /* From paging/starting to nonpaging */ | |
1889 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1890 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1891 | (CPU_BASED_CR3_LOAD_EXITING | |
1892 | CPU_BASED_CR3_STORE_EXITING)); | |
1893 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 1894 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
1895 | } else if (!is_paging(vcpu)) { |
1896 | /* From nonpaging to paging */ | |
1897 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1898 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1899 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1900 | CPU_BASED_CR3_STORE_EXITING)); | |
1901 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 1902 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 1903 | } |
95eb84a7 SY |
1904 | |
1905 | if (!(cr0 & X86_CR0_WP)) | |
1906 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
1907 | } |
1908 | ||
6aa8b732 AK |
1909 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1910 | { | |
7ffd92c5 | 1911 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
1912 | unsigned long hw_cr0; |
1913 | ||
1914 | if (enable_unrestricted_guest) | |
1915 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST) | |
1916 | | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; | |
1917 | else | |
1918 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON; | |
1439442c | 1919 | |
7ffd92c5 | 1920 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1921 | enter_pmode(vcpu); |
1922 | ||
7ffd92c5 | 1923 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1924 | enter_rmode(vcpu); |
1925 | ||
05b3e0c2 | 1926 | #ifdef CONFIG_X86_64 |
f6801dff | 1927 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1928 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1929 | enter_lmode(vcpu); |
707d92fa | 1930 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1931 | exit_lmode(vcpu); |
1932 | } | |
1933 | #endif | |
1934 | ||
089d034e | 1935 | if (enable_ept) |
1439442c SY |
1936 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
1937 | ||
02daab21 | 1938 | if (!vcpu->fpu_active) |
81231c69 | 1939 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 1940 | |
6aa8b732 | 1941 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1942 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1943 | vcpu->arch.cr0 = cr0; |
6aa8b732 AK |
1944 | } |
1945 | ||
1439442c SY |
1946 | static u64 construct_eptp(unsigned long root_hpa) |
1947 | { | |
1948 | u64 eptp; | |
1949 | ||
1950 | /* TODO write the value reading from MSR */ | |
1951 | eptp = VMX_EPT_DEFAULT_MT | | |
1952 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1953 | eptp |= (root_hpa & PAGE_MASK); | |
1954 | ||
1955 | return eptp; | |
1956 | } | |
1957 | ||
6aa8b732 AK |
1958 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1959 | { | |
1439442c SY |
1960 | unsigned long guest_cr3; |
1961 | u64 eptp; | |
1962 | ||
1963 | guest_cr3 = cr3; | |
089d034e | 1964 | if (enable_ept) { |
1439442c SY |
1965 | eptp = construct_eptp(cr3); |
1966 | vmcs_write64(EPT_POINTER, eptp); | |
1439442c | 1967 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : |
b927a3ce | 1968 | vcpu->kvm->arch.ept_identity_map_addr; |
7c93be44 | 1969 | ept_load_pdptrs(vcpu); |
1439442c SY |
1970 | } |
1971 | ||
2384d2b3 | 1972 | vmx_flush_tlb(vcpu); |
1439442c | 1973 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
1974 | } |
1975 | ||
1976 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1977 | { | |
7ffd92c5 | 1978 | unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
1439442c SY |
1979 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
1980 | ||
ad312c7c | 1981 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
1982 | if (enable_ept) { |
1983 | if (!is_paging(vcpu)) { | |
1984 | hw_cr4 &= ~X86_CR4_PAE; | |
1985 | hw_cr4 |= X86_CR4_PSE; | |
1986 | } else if (!(cr4 & X86_CR4_PAE)) { | |
1987 | hw_cr4 &= ~X86_CR4_PAE; | |
1988 | } | |
1989 | } | |
1439442c SY |
1990 | |
1991 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1992 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1993 | } |
1994 | ||
6aa8b732 AK |
1995 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1996 | { | |
1997 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1998 | ||
1999 | return vmcs_readl(sf->base); | |
2000 | } | |
2001 | ||
2002 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
2003 | struct kvm_segment *var, int seg) | |
2004 | { | |
2005 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2006 | u32 ar; | |
2007 | ||
2008 | var->base = vmcs_readl(sf->base); | |
2009 | var->limit = vmcs_read32(sf->limit); | |
2010 | var->selector = vmcs_read16(sf->selector); | |
2011 | ar = vmcs_read32(sf->ar_bytes); | |
9fd4a3b7 | 2012 | if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
6aa8b732 AK |
2013 | ar = 0; |
2014 | var->type = ar & 15; | |
2015 | var->s = (ar >> 4) & 1; | |
2016 | var->dpl = (ar >> 5) & 3; | |
2017 | var->present = (ar >> 7) & 1; | |
2018 | var->avl = (ar >> 12) & 1; | |
2019 | var->l = (ar >> 13) & 1; | |
2020 | var->db = (ar >> 14) & 1; | |
2021 | var->g = (ar >> 15) & 1; | |
2022 | var->unusable = (ar >> 16) & 1; | |
2023 | } | |
2024 | ||
2e4d2653 IE |
2025 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2026 | { | |
3eeb3288 | 2027 | if (!is_protmode(vcpu)) |
2e4d2653 IE |
2028 | return 0; |
2029 | ||
2030 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
2031 | return 3; | |
2032 | ||
eab4b8aa | 2033 | return vmcs_read16(GUEST_CS_SELECTOR) & 3; |
2e4d2653 IE |
2034 | } |
2035 | ||
653e3108 | 2036 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 2037 | { |
6aa8b732 AK |
2038 | u32 ar; |
2039 | ||
653e3108 | 2040 | if (var->unusable) |
6aa8b732 AK |
2041 | ar = 1 << 16; |
2042 | else { | |
2043 | ar = var->type & 15; | |
2044 | ar |= (var->s & 1) << 4; | |
2045 | ar |= (var->dpl & 3) << 5; | |
2046 | ar |= (var->present & 1) << 7; | |
2047 | ar |= (var->avl & 1) << 12; | |
2048 | ar |= (var->l & 1) << 13; | |
2049 | ar |= (var->db & 1) << 14; | |
2050 | ar |= (var->g & 1) << 15; | |
2051 | } | |
f7fbf1fd UL |
2052 | if (ar == 0) /* a 0 value means unusable */ |
2053 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
2054 | |
2055 | return ar; | |
2056 | } | |
2057 | ||
2058 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
2059 | struct kvm_segment *var, int seg) | |
2060 | { | |
7ffd92c5 | 2061 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
653e3108 AK |
2062 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
2063 | u32 ar; | |
2064 | ||
7ffd92c5 AK |
2065 | if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) { |
2066 | vmx->rmode.tr.selector = var->selector; | |
2067 | vmx->rmode.tr.base = var->base; | |
2068 | vmx->rmode.tr.limit = var->limit; | |
2069 | vmx->rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
2070 | return; |
2071 | } | |
2072 | vmcs_writel(sf->base, var->base); | |
2073 | vmcs_write32(sf->limit, var->limit); | |
2074 | vmcs_write16(sf->selector, var->selector); | |
7ffd92c5 | 2075 | if (vmx->rmode.vm86_active && var->s) { |
653e3108 AK |
2076 | /* |
2077 | * Hack real-mode segments into vm86 compatibility. | |
2078 | */ | |
2079 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
2080 | vmcs_writel(sf->base, 0xf0000); | |
2081 | ar = 0xf3; | |
2082 | } else | |
2083 | ar = vmx_segment_access_rights(var); | |
3a624e29 NK |
2084 | |
2085 | /* | |
2086 | * Fix the "Accessed" bit in AR field of segment registers for older | |
2087 | * qemu binaries. | |
2088 | * IA32 arch specifies that at the time of processor reset the | |
2089 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
2090 | * is setting it to 0 in the usedland code. This causes invalid guest | |
2091 | * state vmexit when "unrestricted guest" mode is turned on. | |
2092 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
2093 | * tree. Newer qemu binaries with that qemu fix would not need this | |
2094 | * kvm hack. | |
2095 | */ | |
2096 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
2097 | ar |= 0x1; /* Accessed */ | |
2098 | ||
6aa8b732 AK |
2099 | vmcs_write32(sf->ar_bytes, ar); |
2100 | } | |
2101 | ||
6aa8b732 AK |
2102 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
2103 | { | |
2104 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
2105 | ||
2106 | *db = (ar >> 14) & 1; | |
2107 | *l = (ar >> 13) & 1; | |
2108 | } | |
2109 | ||
89a27f4d | 2110 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2111 | { |
89a27f4d GN |
2112 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
2113 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
2114 | } |
2115 | ||
89a27f4d | 2116 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2117 | { |
89a27f4d GN |
2118 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
2119 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
2120 | } |
2121 | ||
89a27f4d | 2122 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2123 | { |
89a27f4d GN |
2124 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
2125 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
2126 | } |
2127 | ||
89a27f4d | 2128 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2129 | { |
89a27f4d GN |
2130 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
2131 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
2132 | } |
2133 | ||
648dfaa7 MG |
2134 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
2135 | { | |
2136 | struct kvm_segment var; | |
2137 | u32 ar; | |
2138 | ||
2139 | vmx_get_segment(vcpu, &var, seg); | |
2140 | ar = vmx_segment_access_rights(&var); | |
2141 | ||
2142 | if (var.base != (var.selector << 4)) | |
2143 | return false; | |
2144 | if (var.limit != 0xffff) | |
2145 | return false; | |
2146 | if (ar != 0xf3) | |
2147 | return false; | |
2148 | ||
2149 | return true; | |
2150 | } | |
2151 | ||
2152 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
2153 | { | |
2154 | struct kvm_segment cs; | |
2155 | unsigned int cs_rpl; | |
2156 | ||
2157 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2158 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
2159 | ||
1872a3f4 AK |
2160 | if (cs.unusable) |
2161 | return false; | |
648dfaa7 MG |
2162 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
2163 | return false; | |
2164 | if (!cs.s) | |
2165 | return false; | |
1872a3f4 | 2166 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
2167 | if (cs.dpl > cs_rpl) |
2168 | return false; | |
1872a3f4 | 2169 | } else { |
648dfaa7 MG |
2170 | if (cs.dpl != cs_rpl) |
2171 | return false; | |
2172 | } | |
2173 | if (!cs.present) | |
2174 | return false; | |
2175 | ||
2176 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
2177 | return true; | |
2178 | } | |
2179 | ||
2180 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
2181 | { | |
2182 | struct kvm_segment ss; | |
2183 | unsigned int ss_rpl; | |
2184 | ||
2185 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2186 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
2187 | ||
1872a3f4 AK |
2188 | if (ss.unusable) |
2189 | return true; | |
2190 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
2191 | return false; |
2192 | if (!ss.s) | |
2193 | return false; | |
2194 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
2195 | return false; | |
2196 | if (!ss.present) | |
2197 | return false; | |
2198 | ||
2199 | return true; | |
2200 | } | |
2201 | ||
2202 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
2203 | { | |
2204 | struct kvm_segment var; | |
2205 | unsigned int rpl; | |
2206 | ||
2207 | vmx_get_segment(vcpu, &var, seg); | |
2208 | rpl = var.selector & SELECTOR_RPL_MASK; | |
2209 | ||
1872a3f4 AK |
2210 | if (var.unusable) |
2211 | return true; | |
648dfaa7 MG |
2212 | if (!var.s) |
2213 | return false; | |
2214 | if (!var.present) | |
2215 | return false; | |
2216 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
2217 | if (var.dpl < rpl) /* DPL < RPL */ | |
2218 | return false; | |
2219 | } | |
2220 | ||
2221 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
2222 | * rights flags | |
2223 | */ | |
2224 | return true; | |
2225 | } | |
2226 | ||
2227 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
2228 | { | |
2229 | struct kvm_segment tr; | |
2230 | ||
2231 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
2232 | ||
1872a3f4 AK |
2233 | if (tr.unusable) |
2234 | return false; | |
648dfaa7 MG |
2235 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2236 | return false; | |
1872a3f4 | 2237 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
2238 | return false; |
2239 | if (!tr.present) | |
2240 | return false; | |
2241 | ||
2242 | return true; | |
2243 | } | |
2244 | ||
2245 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
2246 | { | |
2247 | struct kvm_segment ldtr; | |
2248 | ||
2249 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
2250 | ||
1872a3f4 AK |
2251 | if (ldtr.unusable) |
2252 | return true; | |
648dfaa7 MG |
2253 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2254 | return false; | |
2255 | if (ldtr.type != 2) | |
2256 | return false; | |
2257 | if (!ldtr.present) | |
2258 | return false; | |
2259 | ||
2260 | return true; | |
2261 | } | |
2262 | ||
2263 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
2264 | { | |
2265 | struct kvm_segment cs, ss; | |
2266 | ||
2267 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2268 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2269 | ||
2270 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
2271 | (ss.selector & SELECTOR_RPL_MASK)); | |
2272 | } | |
2273 | ||
2274 | /* | |
2275 | * Check if guest state is valid. Returns true if valid, false if | |
2276 | * not. | |
2277 | * We assume that registers are always usable | |
2278 | */ | |
2279 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
2280 | { | |
2281 | /* real mode guest state checks */ | |
3eeb3288 | 2282 | if (!is_protmode(vcpu)) { |
648dfaa7 MG |
2283 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
2284 | return false; | |
2285 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
2286 | return false; | |
2287 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
2288 | return false; | |
2289 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
2290 | return false; | |
2291 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
2292 | return false; | |
2293 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
2294 | return false; | |
2295 | } else { | |
2296 | /* protected mode guest state checks */ | |
2297 | if (!cs_ss_rpl_check(vcpu)) | |
2298 | return false; | |
2299 | if (!code_segment_valid(vcpu)) | |
2300 | return false; | |
2301 | if (!stack_segment_valid(vcpu)) | |
2302 | return false; | |
2303 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
2304 | return false; | |
2305 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
2306 | return false; | |
2307 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
2308 | return false; | |
2309 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
2310 | return false; | |
2311 | if (!tr_valid(vcpu)) | |
2312 | return false; | |
2313 | if (!ldtr_valid(vcpu)) | |
2314 | return false; | |
2315 | } | |
2316 | /* TODO: | |
2317 | * - Add checks on RIP | |
2318 | * - Add checks on RFLAGS | |
2319 | */ | |
2320 | ||
2321 | return true; | |
2322 | } | |
2323 | ||
d77c26fc | 2324 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 2325 | { |
6aa8b732 | 2326 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 2327 | u16 data = 0; |
10589a46 | 2328 | int ret = 0; |
195aefde | 2329 | int r; |
6aa8b732 | 2330 | |
195aefde IE |
2331 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2332 | if (r < 0) | |
10589a46 | 2333 | goto out; |
195aefde | 2334 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
2335 | r = kvm_write_guest_page(kvm, fn++, &data, |
2336 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 2337 | if (r < 0) |
10589a46 | 2338 | goto out; |
195aefde IE |
2339 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
2340 | if (r < 0) | |
10589a46 | 2341 | goto out; |
195aefde IE |
2342 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2343 | if (r < 0) | |
10589a46 | 2344 | goto out; |
195aefde | 2345 | data = ~0; |
10589a46 MT |
2346 | r = kvm_write_guest_page(kvm, fn, &data, |
2347 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
2348 | sizeof(u8)); | |
195aefde | 2349 | if (r < 0) |
10589a46 MT |
2350 | goto out; |
2351 | ||
2352 | ret = 1; | |
2353 | out: | |
10589a46 | 2354 | return ret; |
6aa8b732 AK |
2355 | } |
2356 | ||
b7ebfb05 SY |
2357 | static int init_rmode_identity_map(struct kvm *kvm) |
2358 | { | |
2359 | int i, r, ret; | |
2360 | pfn_t identity_map_pfn; | |
2361 | u32 tmp; | |
2362 | ||
089d034e | 2363 | if (!enable_ept) |
b7ebfb05 SY |
2364 | return 1; |
2365 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
2366 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
2367 | "haven't been allocated!\n"); | |
2368 | return 0; | |
2369 | } | |
2370 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
2371 | return 1; | |
2372 | ret = 0; | |
b927a3ce | 2373 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
b7ebfb05 SY |
2374 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
2375 | if (r < 0) | |
2376 | goto out; | |
2377 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
2378 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
2379 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
2380 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
2381 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
2382 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
2383 | if (r < 0) | |
2384 | goto out; | |
2385 | } | |
2386 | kvm->arch.ept_identity_pagetable_done = true; | |
2387 | ret = 1; | |
2388 | out: | |
2389 | return ret; | |
2390 | } | |
2391 | ||
6aa8b732 AK |
2392 | static void seg_setup(int seg) |
2393 | { | |
2394 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
3a624e29 | 2395 | unsigned int ar; |
6aa8b732 AK |
2396 | |
2397 | vmcs_write16(sf->selector, 0); | |
2398 | vmcs_writel(sf->base, 0); | |
2399 | vmcs_write32(sf->limit, 0xffff); | |
3a624e29 NK |
2400 | if (enable_unrestricted_guest) { |
2401 | ar = 0x93; | |
2402 | if (seg == VCPU_SREG_CS) | |
2403 | ar |= 0x08; /* code segment */ | |
2404 | } else | |
2405 | ar = 0xf3; | |
2406 | ||
2407 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
2408 | } |
2409 | ||
f78e0e2e SY |
2410 | static int alloc_apic_access_page(struct kvm *kvm) |
2411 | { | |
2412 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2413 | int r = 0; | |
2414 | ||
79fac95e | 2415 | mutex_lock(&kvm->slots_lock); |
bfc6d222 | 2416 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
2417 | goto out; |
2418 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
2419 | kvm_userspace_mem.flags = 0; | |
2420 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
2421 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2422 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2423 | if (r) | |
2424 | goto out; | |
72dc67a6 | 2425 | |
bfc6d222 | 2426 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 2427 | out: |
79fac95e | 2428 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
2429 | return r; |
2430 | } | |
2431 | ||
b7ebfb05 SY |
2432 | static int alloc_identity_pagetable(struct kvm *kvm) |
2433 | { | |
2434 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2435 | int r = 0; | |
2436 | ||
79fac95e | 2437 | mutex_lock(&kvm->slots_lock); |
b7ebfb05 SY |
2438 | if (kvm->arch.ept_identity_pagetable) |
2439 | goto out; | |
2440 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
2441 | kvm_userspace_mem.flags = 0; | |
b927a3ce SY |
2442 | kvm_userspace_mem.guest_phys_addr = |
2443 | kvm->arch.ept_identity_map_addr; | |
b7ebfb05 SY |
2444 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
2445 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2446 | if (r) | |
2447 | goto out; | |
2448 | ||
b7ebfb05 | 2449 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
b927a3ce | 2450 | kvm->arch.ept_identity_map_addr >> PAGE_SHIFT); |
b7ebfb05 | 2451 | out: |
79fac95e | 2452 | mutex_unlock(&kvm->slots_lock); |
b7ebfb05 SY |
2453 | return r; |
2454 | } | |
2455 | ||
2384d2b3 SY |
2456 | static void allocate_vpid(struct vcpu_vmx *vmx) |
2457 | { | |
2458 | int vpid; | |
2459 | ||
2460 | vmx->vpid = 0; | |
919818ab | 2461 | if (!enable_vpid) |
2384d2b3 SY |
2462 | return; |
2463 | spin_lock(&vmx_vpid_lock); | |
2464 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
2465 | if (vpid < VMX_NR_VPIDS) { | |
2466 | vmx->vpid = vpid; | |
2467 | __set_bit(vpid, vmx_vpid_bitmap); | |
2468 | } | |
2469 | spin_unlock(&vmx_vpid_lock); | |
2470 | } | |
2471 | ||
cdbecfc3 LJ |
2472 | static void free_vpid(struct vcpu_vmx *vmx) |
2473 | { | |
2474 | if (!enable_vpid) | |
2475 | return; | |
2476 | spin_lock(&vmx_vpid_lock); | |
2477 | if (vmx->vpid != 0) | |
2478 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
2479 | spin_unlock(&vmx_vpid_lock); | |
2480 | } | |
2481 | ||
5897297b | 2482 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) |
25c5f225 | 2483 | { |
3e7c73e9 | 2484 | int f = sizeof(unsigned long); |
25c5f225 SY |
2485 | |
2486 | if (!cpu_has_vmx_msr_bitmap()) | |
2487 | return; | |
2488 | ||
2489 | /* | |
2490 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
2491 | * have the write-low and read-high bitmap offsets the wrong way round. | |
2492 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
2493 | */ | |
25c5f225 | 2494 | if (msr <= 0x1fff) { |
3e7c73e9 AK |
2495 | __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */ |
2496 | __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */ | |
25c5f225 SY |
2497 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
2498 | msr &= 0x1fff; | |
3e7c73e9 AK |
2499 | __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */ |
2500 | __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */ | |
25c5f225 | 2501 | } |
25c5f225 SY |
2502 | } |
2503 | ||
5897297b AK |
2504 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
2505 | { | |
2506 | if (!longmode_only) | |
2507 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr); | |
2508 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr); | |
2509 | } | |
2510 | ||
6aa8b732 AK |
2511 | /* |
2512 | * Sets up the vmcs for emulated real mode. | |
2513 | */ | |
8b9cf98c | 2514 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 2515 | { |
468d472f | 2516 | u32 host_sysenter_cs, msr_low, msr_high; |
6aa8b732 | 2517 | u32 junk; |
53f658b3 | 2518 | u64 host_pat, tsc_this, tsc_base; |
6aa8b732 | 2519 | unsigned long a; |
89a27f4d | 2520 | struct desc_ptr dt; |
6aa8b732 | 2521 | int i; |
cd2276a7 | 2522 | unsigned long kvm_vmx_return; |
6e5d865c | 2523 | u32 exec_control; |
6aa8b732 | 2524 | |
6aa8b732 | 2525 | /* I/O */ |
3e7c73e9 AK |
2526 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
2527 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 2528 | |
25c5f225 | 2529 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 2530 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 2531 | |
6aa8b732 AK |
2532 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2533 | ||
6aa8b732 | 2534 | /* Control */ |
1c3d14fe YS |
2535 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
2536 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
2537 | |
2538 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
2539 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
2540 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2541 | #ifdef CONFIG_X86_64 | |
2542 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
2543 | CPU_BASED_CR8_LOAD_EXITING; | |
2544 | #endif | |
2545 | } | |
089d034e | 2546 | if (!enable_ept) |
d56f546d | 2547 | exec_control |= CPU_BASED_CR3_STORE_EXITING | |
83dbc83a MT |
2548 | CPU_BASED_CR3_LOAD_EXITING | |
2549 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 2550 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 2551 | |
83ff3b9d SY |
2552 | if (cpu_has_secondary_exec_ctrls()) { |
2553 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
2554 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2555 | exec_control &= | |
2556 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
2557 | if (vmx->vpid == 0) |
2558 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
046d8710 | 2559 | if (!enable_ept) { |
d56f546d | 2560 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; |
046d8710 SY |
2561 | enable_unrestricted_guest = 0; |
2562 | } | |
3a624e29 NK |
2563 | if (!enable_unrestricted_guest) |
2564 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4b8d54f9 ZE |
2565 | if (!ple_gap) |
2566 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
83ff3b9d SY |
2567 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2568 | } | |
f78e0e2e | 2569 | |
4b8d54f9 ZE |
2570 | if (ple_gap) { |
2571 | vmcs_write32(PLE_GAP, ple_gap); | |
2572 | vmcs_write32(PLE_WINDOW, ple_window); | |
2573 | } | |
2574 | ||
c7addb90 AK |
2575 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
2576 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
2577 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
2578 | ||
1c11e713 | 2579 | vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */ |
6aa8b732 AK |
2580 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ |
2581 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
2582 | ||
2583 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
2584 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
2585 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
9581d442 AK |
2586 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
2587 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
6aa8b732 | 2588 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 2589 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2590 | rdmsrl(MSR_FS_BASE, a); |
2591 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
2592 | rdmsrl(MSR_GS_BASE, a); | |
2593 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
2594 | #else | |
2595 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
2596 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
2597 | #endif | |
2598 | ||
2599 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
2600 | ||
ec68798c | 2601 | native_store_idt(&dt); |
89a27f4d | 2602 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
6aa8b732 | 2603 | |
d77c26fc | 2604 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 2605 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
2606 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
2607 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 2608 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 2609 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 2610 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 AK |
2611 | |
2612 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
2613 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
2614 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
2615 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
2616 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
2617 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
2618 | ||
468d472f SY |
2619 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { |
2620 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2621 | host_pat = msr_low | ((u64) msr_high << 32); | |
2622 | vmcs_write64(HOST_IA32_PAT, host_pat); | |
2623 | } | |
2624 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
2625 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2626 | host_pat = msr_low | ((u64) msr_high << 32); | |
2627 | /* Write the default value follow host pat */ | |
2628 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
2629 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
2630 | vmx->vcpu.arch.pat = host_pat; | |
2631 | } | |
2632 | ||
6aa8b732 AK |
2633 | for (i = 0; i < NR_VMX_MSR; ++i) { |
2634 | u32 index = vmx_msr_index[i]; | |
2635 | u32 data_low, data_high; | |
a2fa3e9f | 2636 | int j = vmx->nmsrs; |
6aa8b732 AK |
2637 | |
2638 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
2639 | continue; | |
432bd6cb AK |
2640 | if (wrmsr_safe(index, data_low, data_high) < 0) |
2641 | continue; | |
26bb0981 AK |
2642 | vmx->guest_msrs[j].index = i; |
2643 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 2644 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 2645 | ++vmx->nmsrs; |
6aa8b732 | 2646 | } |
6aa8b732 | 2647 | |
1c3d14fe | 2648 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2649 | |
2650 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2651 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2652 | ||
e00c8cf2 | 2653 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
4c38609a | 2654 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; |
ce03e4f2 AK |
2655 | if (enable_ept) |
2656 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
4c38609a | 2657 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
e00c8cf2 | 2658 | |
53f658b3 MT |
2659 | tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc; |
2660 | rdtscll(tsc_this); | |
2661 | if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc) | |
2662 | tsc_base = tsc_this; | |
2663 | ||
2664 | guest_write_tsc(0, tsc_base); | |
f78e0e2e | 2665 | |
e00c8cf2 AK |
2666 | return 0; |
2667 | } | |
2668 | ||
b7ebfb05 SY |
2669 | static int init_rmode(struct kvm *kvm) |
2670 | { | |
4b9d3a04 XG |
2671 | int idx, ret = 0; |
2672 | ||
2673 | idx = srcu_read_lock(&kvm->srcu); | |
b7ebfb05 | 2674 | if (!init_rmode_tss(kvm)) |
4b9d3a04 | 2675 | goto exit; |
b7ebfb05 | 2676 | if (!init_rmode_identity_map(kvm)) |
4b9d3a04 XG |
2677 | goto exit; |
2678 | ||
2679 | ret = 1; | |
2680 | exit: | |
2681 | srcu_read_unlock(&kvm->srcu, idx); | |
2682 | return ret; | |
b7ebfb05 SY |
2683 | } |
2684 | ||
e00c8cf2 AK |
2685 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2686 | { | |
2687 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2688 | u64 msr; | |
4b9d3a04 | 2689 | int ret; |
e00c8cf2 | 2690 | |
5fdbf976 | 2691 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
b7ebfb05 | 2692 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2693 | ret = -ENOMEM; |
2694 | goto out; | |
2695 | } | |
2696 | ||
7ffd92c5 | 2697 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 2698 | |
3b86cd99 JK |
2699 | vmx->soft_vnmi_blocked = 0; |
2700 | ||
ad312c7c | 2701 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2702 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 | 2703 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 2704 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
e00c8cf2 AK |
2705 | msr |= MSR_IA32_APICBASE_BSP; |
2706 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2707 | ||
10ab25cd JK |
2708 | ret = fx_init(&vmx->vcpu); |
2709 | if (ret != 0) | |
2710 | goto out; | |
e00c8cf2 | 2711 | |
5706be0d | 2712 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
2713 | /* |
2714 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2715 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2716 | */ | |
c5af89b6 | 2717 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) { |
e00c8cf2 AK |
2718 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
2719 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2720 | } else { | |
ad312c7c ZX |
2721 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2722 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 2723 | } |
e00c8cf2 AK |
2724 | |
2725 | seg_setup(VCPU_SREG_DS); | |
2726 | seg_setup(VCPU_SREG_ES); | |
2727 | seg_setup(VCPU_SREG_FS); | |
2728 | seg_setup(VCPU_SREG_GS); | |
2729 | seg_setup(VCPU_SREG_SS); | |
2730 | ||
2731 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2732 | vmcs_writel(GUEST_TR_BASE, 0); | |
2733 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2734 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2735 | ||
2736 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2737 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2738 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2739 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2740 | ||
2741 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2742 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2743 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2744 | ||
2745 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
c5af89b6 | 2746 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
5fdbf976 | 2747 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2748 | else |
5fdbf976 MT |
2749 | kvm_rip_write(vcpu, 0); |
2750 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 | 2751 | |
e00c8cf2 AK |
2752 | vmcs_writel(GUEST_DR7, 0x400); |
2753 | ||
2754 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2755 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2756 | ||
2757 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2758 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2759 | ||
2760 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2761 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2762 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2763 | ||
e00c8cf2 AK |
2764 | /* Special registers */ |
2765 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2766 | ||
2767 | setup_msrs(vmx); | |
2768 | ||
6aa8b732 AK |
2769 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2770 | ||
f78e0e2e SY |
2771 | if (cpu_has_vmx_tpr_shadow()) { |
2772 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2773 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2774 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2775 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2776 | vmcs_write32(TPR_THRESHOLD, 0); |
2777 | } | |
2778 | ||
2779 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2780 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2781 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2782 | |
2384d2b3 SY |
2783 | if (vmx->vpid != 0) |
2784 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2785 | ||
fa40052c | 2786 | vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
4d4ec087 | 2787 | vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */ |
8b9cf98c | 2788 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2789 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2790 | vmx_fpu_activate(&vmx->vcpu); |
2791 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2792 | |
b9d762fa | 2793 | vpid_sync_context(vmx); |
2384d2b3 | 2794 | |
3200f405 | 2795 | ret = 0; |
6aa8b732 | 2796 | |
a89a8fb9 MG |
2797 | /* HACK: Don't enable emulation on guest boot/reset */ |
2798 | vmx->emulation_required = 0; | |
2799 | ||
6aa8b732 AK |
2800 | out: |
2801 | return ret; | |
2802 | } | |
2803 | ||
3b86cd99 JK |
2804 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2805 | { | |
2806 | u32 cpu_based_vm_exec_control; | |
2807 | ||
2808 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2809 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2810 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2811 | } | |
2812 | ||
2813 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
2814 | { | |
2815 | u32 cpu_based_vm_exec_control; | |
2816 | ||
2817 | if (!cpu_has_virtual_nmis()) { | |
2818 | enable_irq_window(vcpu); | |
2819 | return; | |
2820 | } | |
2821 | ||
2822 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2823 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2824 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2825 | } | |
2826 | ||
66fd3f7f | 2827 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 2828 | { |
9c8cba37 | 2829 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
2830 | uint32_t intr; |
2831 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 2832 | |
229456fc | 2833 | trace_kvm_inj_virq(irq); |
2714d1d3 | 2834 | |
fa89a817 | 2835 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 2836 | if (vmx->rmode.vm86_active) { |
9c8cba37 AK |
2837 | vmx->rmode.irq.pending = true; |
2838 | vmx->rmode.irq.vector = irq; | |
5fdbf976 | 2839 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
ae0bb3e0 GN |
2840 | if (vcpu->arch.interrupt.soft) |
2841 | vmx->rmode.irq.rip += | |
2842 | vmx->vcpu.arch.event_exit_inst_len; | |
9c5623e3 AK |
2843 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2844 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2845 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
5fdbf976 | 2846 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2847 | return; |
2848 | } | |
66fd3f7f GN |
2849 | intr = irq | INTR_INFO_VALID_MASK; |
2850 | if (vcpu->arch.interrupt.soft) { | |
2851 | intr |= INTR_TYPE_SOFT_INTR; | |
2852 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2853 | vmx->vcpu.arch.event_exit_inst_len); | |
2854 | } else | |
2855 | intr |= INTR_TYPE_EXT_INTR; | |
2856 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
2857 | } |
2858 | ||
f08864b4 SY |
2859 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2860 | { | |
66a5a347 JK |
2861 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2862 | ||
3b86cd99 JK |
2863 | if (!cpu_has_virtual_nmis()) { |
2864 | /* | |
2865 | * Tracking the NMI-blocked state in software is built upon | |
2866 | * finding the next open IRQ window. This, in turn, depends on | |
2867 | * well-behaving guests: They have to keep IRQs disabled at | |
2868 | * least as long as the NMI handler runs. Otherwise we may | |
2869 | * cause NMI nesting, maybe breaking the guest. But as this is | |
2870 | * highly unlikely, we can live with the residual risk. | |
2871 | */ | |
2872 | vmx->soft_vnmi_blocked = 1; | |
2873 | vmx->vnmi_blocked_time = 0; | |
2874 | } | |
2875 | ||
487b391d | 2876 | ++vcpu->stat.nmi_injections; |
7ffd92c5 | 2877 | if (vmx->rmode.vm86_active) { |
66a5a347 JK |
2878 | vmx->rmode.irq.pending = true; |
2879 | vmx->rmode.irq.vector = NMI_VECTOR; | |
2880 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
2881 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2882 | NMI_VECTOR | INTR_TYPE_SOFT_INTR | | |
2883 | INTR_INFO_VALID_MASK); | |
2884 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
2885 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
2886 | return; | |
2887 | } | |
f08864b4 SY |
2888 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2889 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
2890 | } |
2891 | ||
c4282df9 | 2892 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
33f089ca | 2893 | { |
3b86cd99 | 2894 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
c4282df9 | 2895 | return 0; |
33f089ca | 2896 | |
c4282df9 | 2897 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
f8c5fae1 | 2898 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI)); |
33f089ca JK |
2899 | } |
2900 | ||
3cfc3092 JK |
2901 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
2902 | { | |
2903 | if (!cpu_has_virtual_nmis()) | |
2904 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
c332c83a | 2905 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
2906 | } |
2907 | ||
2908 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
2909 | { | |
2910 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2911 | ||
2912 | if (!cpu_has_virtual_nmis()) { | |
2913 | if (vmx->soft_vnmi_blocked != masked) { | |
2914 | vmx->soft_vnmi_blocked = masked; | |
2915 | vmx->vnmi_blocked_time = 0; | |
2916 | } | |
2917 | } else { | |
2918 | if (masked) | |
2919 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2920 | GUEST_INTR_STATE_NMI); | |
2921 | else | |
2922 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2923 | GUEST_INTR_STATE_NMI); | |
2924 | } | |
2925 | } | |
2926 | ||
78646121 GN |
2927 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
2928 | { | |
c4282df9 GN |
2929 | return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2930 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
2931 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
2932 | } |
2933 | ||
cbc94022 IE |
2934 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2935 | { | |
2936 | int ret; | |
2937 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 2938 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
2939 | .guest_phys_addr = addr, |
2940 | .memory_size = PAGE_SIZE * 3, | |
2941 | .flags = 0, | |
2942 | }; | |
2943 | ||
2944 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2945 | if (ret) | |
2946 | return ret; | |
bfc6d222 | 2947 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2948 | return 0; |
2949 | } | |
2950 | ||
6aa8b732 AK |
2951 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, |
2952 | int vec, u32 err_code) | |
2953 | { | |
b3f37707 NK |
2954 | /* |
2955 | * Instruction with address size override prefix opcode 0x67 | |
2956 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2957 | */ | |
2958 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
851ba692 | 2959 | if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 | 2960 | return 1; |
77ab6db0 JK |
2961 | /* |
2962 | * Forward all other exceptions that are valid in real mode. | |
2963 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
2964 | * the required debugging infrastructure rework. | |
2965 | */ | |
2966 | switch (vec) { | |
77ab6db0 | 2967 | case DB_VECTOR: |
d0bfb940 JK |
2968 | if (vcpu->guest_debug & |
2969 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
2970 | return 0; | |
2971 | kvm_queue_exception(vcpu, vec); | |
2972 | return 1; | |
77ab6db0 | 2973 | case BP_VECTOR: |
c573cd22 JK |
2974 | /* |
2975 | * Update instruction length as we may reinject the exception | |
2976 | * from user space while in guest debugging mode. | |
2977 | */ | |
2978 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
2979 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 JK |
2980 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
2981 | return 0; | |
2982 | /* fall through */ | |
2983 | case DE_VECTOR: | |
77ab6db0 JK |
2984 | case OF_VECTOR: |
2985 | case BR_VECTOR: | |
2986 | case UD_VECTOR: | |
2987 | case DF_VECTOR: | |
2988 | case SS_VECTOR: | |
2989 | case GP_VECTOR: | |
2990 | case MF_VECTOR: | |
2991 | kvm_queue_exception(vcpu, vec); | |
2992 | return 1; | |
2993 | } | |
6aa8b732 AK |
2994 | return 0; |
2995 | } | |
2996 | ||
a0861c02 AK |
2997 | /* |
2998 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
2999 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
3000 | * We pass a fake environment to the machine check handler because we want | |
3001 | * the guest to be always treated like user space, no matter what context | |
3002 | * it used internally. | |
3003 | */ | |
3004 | static void kvm_machine_check(void) | |
3005 | { | |
3006 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
3007 | struct pt_regs regs = { | |
3008 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
3009 | .flags = X86_EFLAGS_IF, | |
3010 | }; | |
3011 | ||
3012 | do_machine_check(®s, 0); | |
3013 | #endif | |
3014 | } | |
3015 | ||
851ba692 | 3016 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
3017 | { |
3018 | /* already handled by vcpu_run */ | |
3019 | return 1; | |
3020 | } | |
3021 | ||
851ba692 | 3022 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 3023 | { |
1155f76a | 3024 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 3025 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 3026 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 3027 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
3028 | u32 vect_info; |
3029 | enum emulation_result er; | |
3030 | ||
1155f76a | 3031 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
3032 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
3033 | ||
a0861c02 | 3034 | if (is_machine_check(intr_info)) |
851ba692 | 3035 | return handle_machine_check(vcpu); |
a0861c02 | 3036 | |
6aa8b732 | 3037 | if ((vect_info & VECTORING_INFO_VALID_MASK) && |
65ac7264 AK |
3038 | !is_page_fault(intr_info)) { |
3039 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3040 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
3041 | vcpu->run->internal.ndata = 2; | |
3042 | vcpu->run->internal.data[0] = vect_info; | |
3043 | vcpu->run->internal.data[1] = intr_info; | |
3044 | return 0; | |
3045 | } | |
6aa8b732 | 3046 | |
e4a41889 | 3047 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 3048 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
3049 | |
3050 | if (is_no_device(intr_info)) { | |
5fd86fcf | 3051 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
3052 | return 1; |
3053 | } | |
3054 | ||
7aa81cc0 | 3055 | if (is_invalid_opcode(intr_info)) { |
851ba692 | 3056 | er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 3057 | if (er != EMULATE_DONE) |
7ee5d940 | 3058 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
3059 | return 1; |
3060 | } | |
3061 | ||
6aa8b732 | 3062 | error_code = 0; |
5fdbf976 | 3063 | rip = kvm_rip_read(vcpu); |
2e11384c | 3064 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
3065 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
3066 | if (is_page_fault(intr_info)) { | |
1439442c | 3067 | /* EPT won't cause page fault directly */ |
089d034e | 3068 | if (enable_ept) |
1439442c | 3069 | BUG(); |
6aa8b732 | 3070 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
3071 | trace_kvm_page_fault(cr2, error_code); |
3072 | ||
3298b75c | 3073 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 3074 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
3067714c | 3075 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
3076 | } |
3077 | ||
7ffd92c5 | 3078 | if (vmx->rmode.vm86_active && |
6aa8b732 | 3079 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 3080 | error_code)) { |
ad312c7c ZX |
3081 | if (vcpu->arch.halt_request) { |
3082 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
3083 | return kvm_emulate_halt(vcpu); |
3084 | } | |
6aa8b732 | 3085 | return 1; |
72d6e5a0 | 3086 | } |
6aa8b732 | 3087 | |
d0bfb940 | 3088 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
42dbaa5a JK |
3089 | switch (ex_no) { |
3090 | case DB_VECTOR: | |
3091 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
3092 | if (!(vcpu->guest_debug & | |
3093 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
3094 | vcpu->arch.dr6 = dr6 | DR6_FIXED_1; | |
3095 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3096 | return 1; | |
3097 | } | |
3098 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
3099 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
3100 | /* fall through */ | |
3101 | case BP_VECTOR: | |
c573cd22 JK |
3102 | /* |
3103 | * Update instruction length as we may reinject #BP from | |
3104 | * user space while in guest debugging mode. Reading it for | |
3105 | * #DB as well causes no harm, it is not used in that case. | |
3106 | */ | |
3107 | vmx->vcpu.arch.event_exit_inst_len = | |
3108 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 3109 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
d0bfb940 JK |
3110 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
3111 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
3112 | break; |
3113 | default: | |
d0bfb940 JK |
3114 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
3115 | kvm_run->ex.exception = ex_no; | |
3116 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 3117 | break; |
6aa8b732 | 3118 | } |
6aa8b732 AK |
3119 | return 0; |
3120 | } | |
3121 | ||
851ba692 | 3122 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 3123 | { |
1165f5fe | 3124 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
3125 | return 1; |
3126 | } | |
3127 | ||
851ba692 | 3128 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 3129 | { |
851ba692 | 3130 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
3131 | return 0; |
3132 | } | |
6aa8b732 | 3133 | |
851ba692 | 3134 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 3135 | { |
bfdaab09 | 3136 | unsigned long exit_qualification; |
34c33d16 | 3137 | int size, in, string; |
039576c0 | 3138 | unsigned port; |
6aa8b732 | 3139 | |
bfdaab09 | 3140 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 3141 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 3142 | in = (exit_qualification & 8) != 0; |
e70669ab | 3143 | |
cf8f70bf | 3144 | ++vcpu->stat.io_exits; |
e70669ab | 3145 | |
cf8f70bf | 3146 | if (string || in) |
6d77dbfc | 3147 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; |
e70669ab | 3148 | |
cf8f70bf GN |
3149 | port = exit_qualification >> 16; |
3150 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 3151 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
3152 | |
3153 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
3154 | } |
3155 | ||
102d8325 IM |
3156 | static void |
3157 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3158 | { | |
3159 | /* | |
3160 | * Patch in the VMCALL instruction: | |
3161 | */ | |
3162 | hypercall[0] = 0x0f; | |
3163 | hypercall[1] = 0x01; | |
3164 | hypercall[2] = 0xc1; | |
102d8325 IM |
3165 | } |
3166 | ||
49a9b07e AK |
3167 | static void complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
3168 | { | |
3169 | if (err) | |
3170 | kvm_inject_gp(vcpu, 0); | |
3171 | else | |
3172 | skip_emulated_instruction(vcpu); | |
3173 | } | |
3174 | ||
851ba692 | 3175 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3176 | { |
229456fc | 3177 | unsigned long exit_qualification, val; |
6aa8b732 AK |
3178 | int cr; |
3179 | int reg; | |
49a9b07e | 3180 | int err; |
6aa8b732 | 3181 | |
bfdaab09 | 3182 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
3183 | cr = exit_qualification & 15; |
3184 | reg = (exit_qualification >> 8) & 15; | |
3185 | switch ((exit_qualification >> 4) & 3) { | |
3186 | case 0: /* mov to cr */ | |
229456fc MT |
3187 | val = kvm_register_read(vcpu, reg); |
3188 | trace_kvm_cr_write(cr, val); | |
6aa8b732 AK |
3189 | switch (cr) { |
3190 | case 0: | |
49a9b07e AK |
3191 | err = kvm_set_cr0(vcpu, val); |
3192 | complete_insn_gp(vcpu, err); | |
6aa8b732 AK |
3193 | return 1; |
3194 | case 3: | |
2390218b AK |
3195 | err = kvm_set_cr3(vcpu, val); |
3196 | complete_insn_gp(vcpu, err); | |
6aa8b732 AK |
3197 | return 1; |
3198 | case 4: | |
a83b29c6 AK |
3199 | err = kvm_set_cr4(vcpu, val); |
3200 | complete_insn_gp(vcpu, err); | |
6aa8b732 | 3201 | return 1; |
0a5fff19 GN |
3202 | case 8: { |
3203 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
3204 | u8 cr8 = kvm_register_read(vcpu, reg); | |
3205 | kvm_set_cr8(vcpu, cr8); | |
3206 | skip_emulated_instruction(vcpu); | |
3207 | if (irqchip_in_kernel(vcpu->kvm)) | |
3208 | return 1; | |
3209 | if (cr8_prev <= cr8) | |
3210 | return 1; | |
851ba692 | 3211 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
3212 | return 0; |
3213 | } | |
6aa8b732 AK |
3214 | }; |
3215 | break; | |
25c4c276 | 3216 | case 2: /* clts */ |
edcafe3c | 3217 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
4d4ec087 | 3218 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 3219 | skip_emulated_instruction(vcpu); |
6b52d186 | 3220 | vmx_fpu_activate(vcpu); |
25c4c276 | 3221 | return 1; |
6aa8b732 AK |
3222 | case 1: /*mov from cr*/ |
3223 | switch (cr) { | |
3224 | case 3: | |
5fdbf976 | 3225 | kvm_register_write(vcpu, reg, vcpu->arch.cr3); |
229456fc | 3226 | trace_kvm_cr_read(cr, vcpu->arch.cr3); |
6aa8b732 AK |
3227 | skip_emulated_instruction(vcpu); |
3228 | return 1; | |
3229 | case 8: | |
229456fc MT |
3230 | val = kvm_get_cr8(vcpu); |
3231 | kvm_register_write(vcpu, reg, val); | |
3232 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
3233 | skip_emulated_instruction(vcpu); |
3234 | return 1; | |
3235 | } | |
3236 | break; | |
3237 | case 3: /* lmsw */ | |
a1f83a74 | 3238 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 3239 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 3240 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
3241 | |
3242 | skip_emulated_instruction(vcpu); | |
3243 | return 1; | |
3244 | default: | |
3245 | break; | |
3246 | } | |
851ba692 | 3247 | vcpu->run->exit_reason = 0; |
f0242478 | 3248 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
3249 | (int)(exit_qualification >> 4) & 3, cr); |
3250 | return 0; | |
3251 | } | |
3252 | ||
851ba692 | 3253 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3254 | { |
bfdaab09 | 3255 | unsigned long exit_qualification; |
6aa8b732 AK |
3256 | int dr, reg; |
3257 | ||
f2483415 | 3258 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
3259 | if (!kvm_require_cpl(vcpu, 0)) |
3260 | return 1; | |
42dbaa5a JK |
3261 | dr = vmcs_readl(GUEST_DR7); |
3262 | if (dr & DR7_GD) { | |
3263 | /* | |
3264 | * As the vm-exit takes precedence over the debug trap, we | |
3265 | * need to emulate the latter, either for the host or the | |
3266 | * guest debugging itself. | |
3267 | */ | |
3268 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 AK |
3269 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
3270 | vcpu->run->debug.arch.dr7 = dr; | |
3271 | vcpu->run->debug.arch.pc = | |
42dbaa5a JK |
3272 | vmcs_readl(GUEST_CS_BASE) + |
3273 | vmcs_readl(GUEST_RIP); | |
851ba692 AK |
3274 | vcpu->run->debug.arch.exception = DB_VECTOR; |
3275 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
3276 | return 0; |
3277 | } else { | |
3278 | vcpu->arch.dr7 &= ~DR7_GD; | |
3279 | vcpu->arch.dr6 |= DR6_BD; | |
3280 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
3281 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3282 | return 1; | |
3283 | } | |
3284 | } | |
3285 | ||
bfdaab09 | 3286 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
42dbaa5a JK |
3287 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
3288 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); | |
3289 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 GN |
3290 | unsigned long val; |
3291 | if (!kvm_get_dr(vcpu, dr, &val)) | |
3292 | kvm_register_write(vcpu, reg, val); | |
3293 | } else | |
3294 | kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]); | |
6aa8b732 AK |
3295 | skip_emulated_instruction(vcpu); |
3296 | return 1; | |
3297 | } | |
3298 | ||
020df079 GN |
3299 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
3300 | { | |
3301 | vmcs_writel(GUEST_DR7, val); | |
3302 | } | |
3303 | ||
851ba692 | 3304 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 3305 | { |
06465c5a AK |
3306 | kvm_emulate_cpuid(vcpu); |
3307 | return 1; | |
6aa8b732 AK |
3308 | } |
3309 | ||
851ba692 | 3310 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3311 | { |
ad312c7c | 3312 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3313 | u64 data; |
3314 | ||
3315 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
59200273 | 3316 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3317 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3318 | return 1; |
3319 | } | |
3320 | ||
229456fc | 3321 | trace_kvm_msr_read(ecx, data); |
2714d1d3 | 3322 | |
6aa8b732 | 3323 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
3324 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
3325 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
3326 | skip_emulated_instruction(vcpu); |
3327 | return 1; | |
3328 | } | |
3329 | ||
851ba692 | 3330 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3331 | { |
ad312c7c ZX |
3332 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
3333 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
3334 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 AK |
3335 | |
3336 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
59200273 | 3337 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3338 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3339 | return 1; |
3340 | } | |
3341 | ||
59200273 | 3342 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
3343 | skip_emulated_instruction(vcpu); |
3344 | return 1; | |
3345 | } | |
3346 | ||
851ba692 | 3347 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c YS |
3348 | { |
3349 | return 1; | |
3350 | } | |
3351 | ||
851ba692 | 3352 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3353 | { |
85f455f7 ED |
3354 | u32 cpu_based_vm_exec_control; |
3355 | ||
3356 | /* clear pending irq */ | |
3357 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3358 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
3359 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 3360 | |
a26bf12a | 3361 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 3362 | |
c1150d8c DL |
3363 | /* |
3364 | * If the user space waits to inject interrupts, exit as soon as | |
3365 | * possible | |
3366 | */ | |
8061823a | 3367 | if (!irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 3368 | vcpu->run->request_interrupt_window && |
8061823a | 3369 | !kvm_cpu_has_interrupt(vcpu)) { |
851ba692 | 3370 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
3371 | return 0; |
3372 | } | |
6aa8b732 AK |
3373 | return 1; |
3374 | } | |
3375 | ||
851ba692 | 3376 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
3377 | { |
3378 | skip_emulated_instruction(vcpu); | |
d3bef15f | 3379 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
3380 | } |
3381 | ||
851ba692 | 3382 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 3383 | { |
510043da | 3384 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
3385 | kvm_emulate_hypercall(vcpu); |
3386 | return 1; | |
c21415e8 IM |
3387 | } |
3388 | ||
851ba692 | 3389 | static int handle_vmx_insn(struct kvm_vcpu *vcpu) |
e3c7cb6a AK |
3390 | { |
3391 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3392 | return 1; | |
3393 | } | |
3394 | ||
851ba692 | 3395 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 3396 | { |
f9c617f6 | 3397 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
3398 | |
3399 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
3400 | skip_emulated_instruction(vcpu); | |
3401 | return 1; | |
3402 | } | |
3403 | ||
851ba692 | 3404 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 ED |
3405 | { |
3406 | skip_emulated_instruction(vcpu); | |
f5f48ee1 | 3407 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
3408 | return 1; |
3409 | } | |
3410 | ||
2acf923e DC |
3411 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
3412 | { | |
3413 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
3414 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3415 | ||
3416 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
3417 | skip_emulated_instruction(vcpu); | |
3418 | return 1; | |
3419 | } | |
3420 | ||
851ba692 | 3421 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 3422 | { |
6d77dbfc | 3423 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; |
f78e0e2e SY |
3424 | } |
3425 | ||
851ba692 | 3426 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 3427 | { |
60637aac | 3428 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 3429 | unsigned long exit_qualification; |
e269fb21 JK |
3430 | bool has_error_code = false; |
3431 | u32 error_code = 0; | |
37817f29 | 3432 | u16 tss_selector; |
64a7ec06 GN |
3433 | int reason, type, idt_v; |
3434 | ||
3435 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
3436 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); | |
37817f29 IE |
3437 | |
3438 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
3439 | ||
3440 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
3441 | if (reason == TASK_SWITCH_GATE && idt_v) { |
3442 | switch (type) { | |
3443 | case INTR_TYPE_NMI_INTR: | |
3444 | vcpu->arch.nmi_injected = false; | |
3445 | if (cpu_has_virtual_nmis()) | |
3446 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3447 | GUEST_INTR_STATE_NMI); | |
3448 | break; | |
3449 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 3450 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
3451 | kvm_clear_interrupt_queue(vcpu); |
3452 | break; | |
3453 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
3454 | if (vmx->idt_vectoring_info & |
3455 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
3456 | has_error_code = true; | |
3457 | error_code = | |
3458 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
3459 | } | |
3460 | /* fall through */ | |
64a7ec06 GN |
3461 | case INTR_TYPE_SOFT_EXCEPTION: |
3462 | kvm_clear_exception_queue(vcpu); | |
3463 | break; | |
3464 | default: | |
3465 | break; | |
3466 | } | |
60637aac | 3467 | } |
37817f29 IE |
3468 | tss_selector = exit_qualification; |
3469 | ||
64a7ec06 GN |
3470 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
3471 | type != INTR_TYPE_EXT_INTR && | |
3472 | type != INTR_TYPE_NMI_INTR)) | |
3473 | skip_emulated_instruction(vcpu); | |
3474 | ||
acb54517 GN |
3475 | if (kvm_task_switch(vcpu, tss_selector, reason, |
3476 | has_error_code, error_code) == EMULATE_FAIL) { | |
3477 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3478 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3479 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 3480 | return 0; |
acb54517 | 3481 | } |
42dbaa5a JK |
3482 | |
3483 | /* clear all local breakpoint enable flags */ | |
3484 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); | |
3485 | ||
3486 | /* | |
3487 | * TODO: What about debug traps on tss switch? | |
3488 | * Are we supposed to inject them and update dr6? | |
3489 | */ | |
3490 | ||
3491 | return 1; | |
37817f29 IE |
3492 | } |
3493 | ||
851ba692 | 3494 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 3495 | { |
f9c617f6 | 3496 | unsigned long exit_qualification; |
1439442c | 3497 | gpa_t gpa; |
1439442c | 3498 | int gla_validity; |
1439442c | 3499 | |
f9c617f6 | 3500 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c SY |
3501 | |
3502 | if (exit_qualification & (1 << 6)) { | |
3503 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
7f582ab6 | 3504 | return -EINVAL; |
1439442c SY |
3505 | } |
3506 | ||
3507 | gla_validity = (exit_qualification >> 7) & 0x3; | |
3508 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
3509 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
3510 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
3511 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 3512 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
3513 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
3514 | (long unsigned int)exit_qualification); | |
851ba692 AK |
3515 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3516 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 3517 | return 0; |
1439442c SY |
3518 | } |
3519 | ||
3520 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
229456fc | 3521 | trace_kvm_page_fault(gpa, exit_qualification); |
49cd7d22 | 3522 | return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); |
1439442c SY |
3523 | } |
3524 | ||
68f89400 MT |
3525 | static u64 ept_rsvd_mask(u64 spte, int level) |
3526 | { | |
3527 | int i; | |
3528 | u64 mask = 0; | |
3529 | ||
3530 | for (i = 51; i > boot_cpu_data.x86_phys_bits; i--) | |
3531 | mask |= (1ULL << i); | |
3532 | ||
3533 | if (level > 2) | |
3534 | /* bits 7:3 reserved */ | |
3535 | mask |= 0xf8; | |
3536 | else if (level == 2) { | |
3537 | if (spte & (1ULL << 7)) | |
3538 | /* 2MB ref, bits 20:12 reserved */ | |
3539 | mask |= 0x1ff000; | |
3540 | else | |
3541 | /* bits 6:3 reserved */ | |
3542 | mask |= 0x78; | |
3543 | } | |
3544 | ||
3545 | return mask; | |
3546 | } | |
3547 | ||
3548 | static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte, | |
3549 | int level) | |
3550 | { | |
3551 | printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level); | |
3552 | ||
3553 | /* 010b (write-only) */ | |
3554 | WARN_ON((spte & 0x7) == 0x2); | |
3555 | ||
3556 | /* 110b (write/execute) */ | |
3557 | WARN_ON((spte & 0x7) == 0x6); | |
3558 | ||
3559 | /* 100b (execute-only) and value not supported by logical processor */ | |
3560 | if (!cpu_has_vmx_ept_execute_only()) | |
3561 | WARN_ON((spte & 0x7) == 0x4); | |
3562 | ||
3563 | /* not 000b */ | |
3564 | if ((spte & 0x7)) { | |
3565 | u64 rsvd_bits = spte & ept_rsvd_mask(spte, level); | |
3566 | ||
3567 | if (rsvd_bits != 0) { | |
3568 | printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n", | |
3569 | __func__, rsvd_bits); | |
3570 | WARN_ON(1); | |
3571 | } | |
3572 | ||
3573 | if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) { | |
3574 | u64 ept_mem_type = (spte & 0x38) >> 3; | |
3575 | ||
3576 | if (ept_mem_type == 2 || ept_mem_type == 3 || | |
3577 | ept_mem_type == 7) { | |
3578 | printk(KERN_ERR "%s: ept_mem_type=0x%llx\n", | |
3579 | __func__, ept_mem_type); | |
3580 | WARN_ON(1); | |
3581 | } | |
3582 | } | |
3583 | } | |
3584 | } | |
3585 | ||
851ba692 | 3586 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 MT |
3587 | { |
3588 | u64 sptes[4]; | |
3589 | int nr_sptes, i; | |
3590 | gpa_t gpa; | |
3591 | ||
3592 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
3593 | ||
3594 | printk(KERN_ERR "EPT: Misconfiguration.\n"); | |
3595 | printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa); | |
3596 | ||
3597 | nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes); | |
3598 | ||
3599 | for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i) | |
3600 | ept_misconfig_inspect_spte(vcpu, sptes[i-1], i); | |
3601 | ||
851ba692 AK |
3602 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3603 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
3604 | |
3605 | return 0; | |
3606 | } | |
3607 | ||
851ba692 | 3608 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
3609 | { |
3610 | u32 cpu_based_vm_exec_control; | |
3611 | ||
3612 | /* clear pending NMI */ | |
3613 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3614 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
3615 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3616 | ++vcpu->stat.nmi_window_exits; | |
3617 | ||
3618 | return 1; | |
3619 | } | |
3620 | ||
80ced186 | 3621 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 3622 | { |
8b3079a5 AK |
3623 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3624 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 3625 | int ret = 1; |
ea953ef0 MG |
3626 | |
3627 | while (!guest_state_valid(vcpu)) { | |
851ba692 | 3628 | err = emulate_instruction(vcpu, 0, 0, 0); |
ea953ef0 | 3629 | |
80ced186 MG |
3630 | if (err == EMULATE_DO_MMIO) { |
3631 | ret = 0; | |
3632 | goto out; | |
3633 | } | |
1d5a4d9b | 3634 | |
6d77dbfc GN |
3635 | if (err != EMULATE_DONE) |
3636 | return 0; | |
ea953ef0 MG |
3637 | |
3638 | if (signal_pending(current)) | |
80ced186 | 3639 | goto out; |
ea953ef0 MG |
3640 | if (need_resched()) |
3641 | schedule(); | |
3642 | } | |
3643 | ||
80ced186 MG |
3644 | vmx->emulation_required = 0; |
3645 | out: | |
3646 | return ret; | |
ea953ef0 MG |
3647 | } |
3648 | ||
4b8d54f9 ZE |
3649 | /* |
3650 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
3651 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
3652 | */ | |
9fb41ba8 | 3653 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 ZE |
3654 | { |
3655 | skip_emulated_instruction(vcpu); | |
3656 | kvm_vcpu_on_spin(vcpu); | |
3657 | ||
3658 | return 1; | |
3659 | } | |
3660 | ||
59708670 SY |
3661 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
3662 | { | |
3663 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3664 | return 1; | |
3665 | } | |
3666 | ||
6aa8b732 AK |
3667 | /* |
3668 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
3669 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
3670 | * to be done to userspace and return 0. | |
3671 | */ | |
851ba692 | 3672 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
3673 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
3674 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 3675 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 3676 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 3677 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
3678 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
3679 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
3680 | [EXIT_REASON_CPUID] = handle_cpuid, | |
3681 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
3682 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
3683 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
3684 | [EXIT_REASON_HLT] = handle_halt, | |
a7052897 | 3685 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 3686 | [EXIT_REASON_VMCALL] = handle_vmcall, |
e3c7cb6a AK |
3687 | [EXIT_REASON_VMCLEAR] = handle_vmx_insn, |
3688 | [EXIT_REASON_VMLAUNCH] = handle_vmx_insn, | |
3689 | [EXIT_REASON_VMPTRLD] = handle_vmx_insn, | |
3690 | [EXIT_REASON_VMPTRST] = handle_vmx_insn, | |
3691 | [EXIT_REASON_VMREAD] = handle_vmx_insn, | |
3692 | [EXIT_REASON_VMRESUME] = handle_vmx_insn, | |
3693 | [EXIT_REASON_VMWRITE] = handle_vmx_insn, | |
3694 | [EXIT_REASON_VMOFF] = handle_vmx_insn, | |
3695 | [EXIT_REASON_VMON] = handle_vmx_insn, | |
f78e0e2e SY |
3696 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
3697 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 3698 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 3699 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 3700 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 3701 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
3702 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
3703 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 3704 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
59708670 SY |
3705 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op, |
3706 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op, | |
6aa8b732 AK |
3707 | }; |
3708 | ||
3709 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 3710 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
3711 | |
3712 | /* | |
3713 | * The guest has exited. See if we can fix it or if we need userspace | |
3714 | * assistance. | |
3715 | */ | |
851ba692 | 3716 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3717 | { |
29bd8a78 | 3718 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 3719 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 3720 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 3721 | |
5bfd8b54 | 3722 | trace_kvm_exit(exit_reason, vcpu); |
2714d1d3 | 3723 | |
80ced186 MG |
3724 | /* If guest state is invalid, start emulating */ |
3725 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
3726 | return handle_invalid_guest_state(vcpu); | |
1d5a4d9b | 3727 | |
1439442c SY |
3728 | /* Access CR3 don't cause VMExit in paging mode, so we need |
3729 | * to sync with guest real CR3. */ | |
6de4f3ad | 3730 | if (enable_ept && is_paging(vcpu)) |
1439442c | 3731 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); |
1439442c | 3732 | |
5120702e MG |
3733 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
3734 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3735 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
3736 | = exit_reason; | |
3737 | return 0; | |
3738 | } | |
3739 | ||
29bd8a78 | 3740 | if (unlikely(vmx->fail)) { |
851ba692 AK |
3741 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
3742 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
3743 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
3744 | return 0; | |
3745 | } | |
6aa8b732 | 3746 | |
d77c26fc | 3747 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 3748 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
3749 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
3750 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
3751 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
3752 | "(0x%x) and exit reason is 0x%x\n", | |
3753 | __func__, vectoring_info, exit_reason); | |
3b86cd99 JK |
3754 | |
3755 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | |
c4282df9 | 3756 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 3757 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 3758 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 3759 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
3760 | /* |
3761 | * This CPU don't support us in finding the end of an | |
3762 | * NMI-blocked window if the guest runs with IRQs | |
3763 | * disabled. So we pull the trigger after 1 s of | |
3764 | * futile waiting, but inform the user about this. | |
3765 | */ | |
3766 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
3767 | "state on VCPU %d after 1 s timeout\n", | |
3768 | __func__, vcpu->vcpu_id); | |
3769 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 3770 | } |
3b86cd99 JK |
3771 | } |
3772 | ||
6aa8b732 AK |
3773 | if (exit_reason < kvm_vmx_max_exit_handlers |
3774 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 3775 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 3776 | else { |
851ba692 AK |
3777 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3778 | vcpu->run->hw.hardware_exit_reason = exit_reason; | |
6aa8b732 AK |
3779 | } |
3780 | return 0; | |
3781 | } | |
3782 | ||
95ba8273 | 3783 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 3784 | { |
95ba8273 | 3785 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
3786 | vmcs_write32(TPR_THRESHOLD, 0); |
3787 | return; | |
3788 | } | |
3789 | ||
95ba8273 | 3790 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
3791 | } |
3792 | ||
cf393f75 AK |
3793 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3794 | { | |
3795 | u32 exit_intr_info; | |
7b4a25cb | 3796 | u32 idt_vectoring_info = vmx->idt_vectoring_info; |
cf393f75 AK |
3797 | bool unblock_nmi; |
3798 | u8 vector; | |
668f612f AK |
3799 | int type; |
3800 | bool idtv_info_valid; | |
cf393f75 AK |
3801 | |
3802 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
20f65983 | 3803 | |
a0861c02 AK |
3804 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
3805 | ||
3806 | /* Handle machine checks before interrupts are enabled */ | |
3807 | if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) | |
3808 | || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI | |
3809 | && is_machine_check(exit_intr_info))) | |
3810 | kvm_machine_check(); | |
3811 | ||
20f65983 GN |
3812 | /* We need to handle NMIs before interrupts are enabled */ |
3813 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && | |
ff9d07a0 ZY |
3814 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
3815 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 3816 | asm("int $2"); |
ff9d07a0 ZY |
3817 | kvm_after_handle_nmi(&vmx->vcpu); |
3818 | } | |
20f65983 GN |
3819 | |
3820 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
3821 | ||
cf393f75 AK |
3822 | if (cpu_has_virtual_nmis()) { |
3823 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
3824 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
3825 | /* | |
7b4a25cb | 3826 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
3827 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
3828 | * a guest IRET fault. | |
7b4a25cb GN |
3829 | * SDM 3: 23.2.2 (September 2008) |
3830 | * Bit 12 is undefined in any of the following cases: | |
3831 | * If the VM exit sets the valid bit in the IDT-vectoring | |
3832 | * information field. | |
3833 | * If the VM exit is due to a double fault. | |
cf393f75 | 3834 | */ |
7b4a25cb GN |
3835 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
3836 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
3837 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
3838 | GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
3839 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
3840 | vmx->vnmi_blocked_time += | |
3841 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
668f612f | 3842 | |
37b96e98 GN |
3843 | vmx->vcpu.arch.nmi_injected = false; |
3844 | kvm_clear_exception_queue(&vmx->vcpu); | |
3845 | kvm_clear_interrupt_queue(&vmx->vcpu); | |
3846 | ||
3847 | if (!idtv_info_valid) | |
3848 | return; | |
3849 | ||
668f612f AK |
3850 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
3851 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 3852 | |
64a7ec06 | 3853 | switch (type) { |
37b96e98 GN |
3854 | case INTR_TYPE_NMI_INTR: |
3855 | vmx->vcpu.arch.nmi_injected = true; | |
668f612f | 3856 | /* |
7b4a25cb | 3857 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
3858 | * Clear bit "block by NMI" before VM entry if a NMI |
3859 | * delivery faulted. | |
668f612f | 3860 | */ |
37b96e98 GN |
3861 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, |
3862 | GUEST_INTR_STATE_NMI); | |
3863 | break; | |
37b96e98 | 3864 | case INTR_TYPE_SOFT_EXCEPTION: |
66fd3f7f GN |
3865 | vmx->vcpu.arch.event_exit_inst_len = |
3866 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
3867 | /* fall through */ | |
3868 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 3869 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
37b96e98 GN |
3870 | u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE); |
3871 | kvm_queue_exception_e(&vmx->vcpu, vector, err); | |
35920a35 AK |
3872 | } else |
3873 | kvm_queue_exception(&vmx->vcpu, vector); | |
37b96e98 | 3874 | break; |
66fd3f7f GN |
3875 | case INTR_TYPE_SOFT_INTR: |
3876 | vmx->vcpu.arch.event_exit_inst_len = | |
3877 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
3878 | /* fall through */ | |
37b96e98 | 3879 | case INTR_TYPE_EXT_INTR: |
66fd3f7f GN |
3880 | kvm_queue_interrupt(&vmx->vcpu, vector, |
3881 | type == INTR_TYPE_SOFT_INTR); | |
37b96e98 GN |
3882 | break; |
3883 | default: | |
3884 | break; | |
f7d9238f | 3885 | } |
cf393f75 AK |
3886 | } |
3887 | ||
9c8cba37 AK |
3888 | /* |
3889 | * Failure to inject an interrupt should give us the information | |
3890 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
3891 | * when fetching the interrupt redirection bitmap in the real-mode | |
3892 | * tss, this doesn't happen. So we do it ourselves. | |
3893 | */ | |
3894 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
3895 | { | |
3896 | vmx->rmode.irq.pending = 0; | |
5fdbf976 | 3897 | if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip) |
9c8cba37 | 3898 | return; |
5fdbf976 | 3899 | kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip); |
9c8cba37 AK |
3900 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { |
3901 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
3902 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
3903 | return; | |
3904 | } | |
3905 | vmx->idt_vectoring_info = | |
3906 | VECTORING_INFO_VALID_MASK | |
3907 | | INTR_TYPE_EXT_INTR | |
3908 | | vmx->rmode.irq.vector; | |
3909 | } | |
3910 | ||
c801949d AK |
3911 | #ifdef CONFIG_X86_64 |
3912 | #define R "r" | |
3913 | #define Q "q" | |
3914 | #else | |
3915 | #define R "e" | |
3916 | #define Q "l" | |
3917 | #endif | |
3918 | ||
851ba692 | 3919 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3920 | { |
a2fa3e9f | 3921 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
e6adf283 | 3922 | |
3b86cd99 JK |
3923 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
3924 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
3925 | vmx->entry_time = ktime_get(); | |
3926 | ||
80ced186 MG |
3927 | /* Don't enter VMX if guest state is invalid, let the exit handler |
3928 | start emulation until we arrive back to a valid state */ | |
3929 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
a89a8fb9 | 3930 | return; |
a89a8fb9 | 3931 | |
5fdbf976 MT |
3932 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
3933 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
3934 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
3935 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
3936 | ||
787ff736 GN |
3937 | /* When single-stepping over STI and MOV SS, we must clear the |
3938 | * corresponding interruptibility bits in the guest state. Otherwise | |
3939 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
3940 | * exceptions being set, but that's not correct for the guest debugging | |
3941 | * case. */ | |
3942 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
3943 | vmx_set_interrupt_shadow(vcpu, 0); | |
3944 | ||
d77c26fc | 3945 | asm( |
6aa8b732 | 3946 | /* Store host registers */ |
c801949d AK |
3947 | "push %%"R"dx; push %%"R"bp;" |
3948 | "push %%"R"cx \n\t" | |
313dbd49 AK |
3949 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
3950 | "je 1f \n\t" | |
3951 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 3952 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 3953 | "1: \n\t" |
d3edefc0 AK |
3954 | /* Reload cr2 if changed */ |
3955 | "mov %c[cr2](%0), %%"R"ax \n\t" | |
3956 | "mov %%cr2, %%"R"dx \n\t" | |
3957 | "cmp %%"R"ax, %%"R"dx \n\t" | |
3958 | "je 2f \n\t" | |
3959 | "mov %%"R"ax, %%cr2 \n\t" | |
3960 | "2: \n\t" | |
6aa8b732 | 3961 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 3962 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 3963 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
3964 | "mov %c[rax](%0), %%"R"ax \n\t" |
3965 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
3966 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
3967 | "mov %c[rsi](%0), %%"R"si \n\t" | |
3968 | "mov %c[rdi](%0), %%"R"di \n\t" | |
3969 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 3970 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3971 | "mov %c[r8](%0), %%r8 \n\t" |
3972 | "mov %c[r9](%0), %%r9 \n\t" | |
3973 | "mov %c[r10](%0), %%r10 \n\t" | |
3974 | "mov %c[r11](%0), %%r11 \n\t" | |
3975 | "mov %c[r12](%0), %%r12 \n\t" | |
3976 | "mov %c[r13](%0), %%r13 \n\t" | |
3977 | "mov %c[r14](%0), %%r14 \n\t" | |
3978 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 3979 | #endif |
c801949d AK |
3980 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
3981 | ||
6aa8b732 | 3982 | /* Enter guest mode */ |
cd2276a7 | 3983 | "jne .Llaunched \n\t" |
4ecac3fd | 3984 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 3985 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 3986 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 3987 | ".Lkvm_vmx_return: " |
6aa8b732 | 3988 | /* Save guest registers, load host registers, keep flags */ |
c801949d AK |
3989 | "xchg %0, (%%"R"sp) \n\t" |
3990 | "mov %%"R"ax, %c[rax](%0) \n\t" | |
3991 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
3992 | "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t" | |
3993 | "mov %%"R"dx, %c[rdx](%0) \n\t" | |
3994 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
3995 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
3996 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 3997 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3998 | "mov %%r8, %c[r8](%0) \n\t" |
3999 | "mov %%r9, %c[r9](%0) \n\t" | |
4000 | "mov %%r10, %c[r10](%0) \n\t" | |
4001 | "mov %%r11, %c[r11](%0) \n\t" | |
4002 | "mov %%r12, %c[r12](%0) \n\t" | |
4003 | "mov %%r13, %c[r13](%0) \n\t" | |
4004 | "mov %%r14, %c[r14](%0) \n\t" | |
4005 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 4006 | #endif |
c801949d AK |
4007 | "mov %%cr2, %%"R"ax \n\t" |
4008 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
4009 | ||
4010 | "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t" | |
e08aa78a AK |
4011 | "setbe %c[fail](%0) \n\t" |
4012 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
4013 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
4014 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 4015 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
4016 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
4017 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
4018 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4019 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4020 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4021 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4022 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 4023 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4024 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
4025 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
4026 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
4027 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
4028 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
4029 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
4030 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
4031 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 4032 | #endif |
ad312c7c | 4033 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 | 4034 | : "cc", "memory" |
c801949d | 4035 | , R"bx", R"di", R"si" |
c2036300 | 4036 | #ifdef CONFIG_X86_64 |
c2036300 LV |
4037 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
4038 | #endif | |
4039 | ); | |
6aa8b732 | 4040 | |
6de4f3ad AK |
4041 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
4042 | | (1 << VCPU_EXREG_PDPTR)); | |
5fdbf976 MT |
4043 | vcpu->arch.regs_dirty = 0; |
4044 | ||
1155f76a | 4045 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
4046 | if (vmx->rmode.irq.pending) |
4047 | fixup_rmode_irq(vmx); | |
1155f76a | 4048 | |
d77c26fc | 4049 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 4050 | vmx->launched = 1; |
1b6269db | 4051 | |
cf393f75 | 4052 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
4053 | } |
4054 | ||
c801949d AK |
4055 | #undef R |
4056 | #undef Q | |
4057 | ||
6aa8b732 AK |
4058 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
4059 | { | |
a2fa3e9f GH |
4060 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4061 | ||
4062 | if (vmx->vmcs) { | |
543e4243 | 4063 | vcpu_clear(vmx); |
a2fa3e9f GH |
4064 | free_vmcs(vmx->vmcs); |
4065 | vmx->vmcs = NULL; | |
6aa8b732 AK |
4066 | } |
4067 | } | |
4068 | ||
4069 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
4070 | { | |
fb3f0f51 RR |
4071 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4072 | ||
cdbecfc3 | 4073 | free_vpid(vmx); |
6aa8b732 | 4074 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
4075 | kfree(vmx->guest_msrs); |
4076 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 4077 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
4078 | } |
4079 | ||
4610c9cc DX |
4080 | static inline void vmcs_init(struct vmcs *vmcs) |
4081 | { | |
4082 | u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id())); | |
4083 | ||
4084 | if (!vmm_exclusive) | |
4085 | kvm_cpu_vmxon(phys_addr); | |
4086 | ||
4087 | vmcs_clear(vmcs); | |
4088 | ||
4089 | if (!vmm_exclusive) | |
4090 | kvm_cpu_vmxoff(); | |
4091 | } | |
4092 | ||
fb3f0f51 | 4093 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 4094 | { |
fb3f0f51 | 4095 | int err; |
c16f862d | 4096 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 4097 | int cpu; |
6aa8b732 | 4098 | |
a2fa3e9f | 4099 | if (!vmx) |
fb3f0f51 RR |
4100 | return ERR_PTR(-ENOMEM); |
4101 | ||
2384d2b3 SY |
4102 | allocate_vpid(vmx); |
4103 | ||
fb3f0f51 RR |
4104 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
4105 | if (err) | |
4106 | goto free_vcpu; | |
965b58a5 | 4107 | |
a2fa3e9f | 4108 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
4109 | if (!vmx->guest_msrs) { |
4110 | err = -ENOMEM; | |
4111 | goto uninit_vcpu; | |
4112 | } | |
965b58a5 | 4113 | |
a2fa3e9f GH |
4114 | vmx->vmcs = alloc_vmcs(); |
4115 | if (!vmx->vmcs) | |
fb3f0f51 | 4116 | goto free_msrs; |
a2fa3e9f | 4117 | |
4610c9cc | 4118 | vmcs_init(vmx->vmcs); |
a2fa3e9f | 4119 | |
15ad7146 AK |
4120 | cpu = get_cpu(); |
4121 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 4122 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 4123 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 4124 | put_cpu(); |
fb3f0f51 RR |
4125 | if (err) |
4126 | goto free_vmcs; | |
5e4a0b3c MT |
4127 | if (vm_need_virtualize_apic_accesses(kvm)) |
4128 | if (alloc_apic_access_page(kvm) != 0) | |
4129 | goto free_vmcs; | |
fb3f0f51 | 4130 | |
b927a3ce SY |
4131 | if (enable_ept) { |
4132 | if (!kvm->arch.ept_identity_map_addr) | |
4133 | kvm->arch.ept_identity_map_addr = | |
4134 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b7ebfb05 SY |
4135 | if (alloc_identity_pagetable(kvm) != 0) |
4136 | goto free_vmcs; | |
b927a3ce | 4137 | } |
b7ebfb05 | 4138 | |
fb3f0f51 RR |
4139 | return &vmx->vcpu; |
4140 | ||
4141 | free_vmcs: | |
4142 | free_vmcs(vmx->vmcs); | |
4143 | free_msrs: | |
fb3f0f51 RR |
4144 | kfree(vmx->guest_msrs); |
4145 | uninit_vcpu: | |
4146 | kvm_vcpu_uninit(&vmx->vcpu); | |
4147 | free_vcpu: | |
cdbecfc3 | 4148 | free_vpid(vmx); |
a4770347 | 4149 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 4150 | return ERR_PTR(err); |
6aa8b732 AK |
4151 | } |
4152 | ||
002c7f7c YS |
4153 | static void __init vmx_check_processor_compat(void *rtn) |
4154 | { | |
4155 | struct vmcs_config vmcs_conf; | |
4156 | ||
4157 | *(int *)rtn = 0; | |
4158 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
4159 | *(int *)rtn = -EIO; | |
4160 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
4161 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
4162 | smp_processor_id()); | |
4163 | *(int *)rtn = -EIO; | |
4164 | } | |
4165 | } | |
4166 | ||
67253af5 SY |
4167 | static int get_ept_level(void) |
4168 | { | |
4169 | return VMX_EPT_DEFAULT_GAW + 1; | |
4170 | } | |
4171 | ||
4b12f0de | 4172 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 4173 | { |
4b12f0de SY |
4174 | u64 ret; |
4175 | ||
522c68c4 SY |
4176 | /* For VT-d and EPT combination |
4177 | * 1. MMIO: always map as UC | |
4178 | * 2. EPT with VT-d: | |
4179 | * a. VT-d without snooping control feature: can't guarantee the | |
4180 | * result, try to trust guest. | |
4181 | * b. VT-d with snooping control feature: snooping control feature of | |
4182 | * VT-d engine can guarantee the cache correctness. Just set it | |
4183 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 4184 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
4185 | * consistent with host MTRR |
4186 | */ | |
4b12f0de SY |
4187 | if (is_mmio) |
4188 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | |
522c68c4 SY |
4189 | else if (vcpu->kvm->arch.iommu_domain && |
4190 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY)) | |
4191 | ret = kvm_get_guest_memory_type(vcpu, gfn) << | |
4192 | VMX_EPT_MT_EPTE_SHIFT; | |
4b12f0de | 4193 | else |
522c68c4 | 4194 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) |
a19a6d11 | 4195 | | VMX_EPT_IPAT_BIT; |
4b12f0de SY |
4196 | |
4197 | return ret; | |
64d4d521 SY |
4198 | } |
4199 | ||
f4c9e87c AK |
4200 | #define _ER(x) { EXIT_REASON_##x, #x } |
4201 | ||
229456fc | 4202 | static const struct trace_print_flags vmx_exit_reasons_str[] = { |
f4c9e87c AK |
4203 | _ER(EXCEPTION_NMI), |
4204 | _ER(EXTERNAL_INTERRUPT), | |
4205 | _ER(TRIPLE_FAULT), | |
4206 | _ER(PENDING_INTERRUPT), | |
4207 | _ER(NMI_WINDOW), | |
4208 | _ER(TASK_SWITCH), | |
4209 | _ER(CPUID), | |
4210 | _ER(HLT), | |
4211 | _ER(INVLPG), | |
4212 | _ER(RDPMC), | |
4213 | _ER(RDTSC), | |
4214 | _ER(VMCALL), | |
4215 | _ER(VMCLEAR), | |
4216 | _ER(VMLAUNCH), | |
4217 | _ER(VMPTRLD), | |
4218 | _ER(VMPTRST), | |
4219 | _ER(VMREAD), | |
4220 | _ER(VMRESUME), | |
4221 | _ER(VMWRITE), | |
4222 | _ER(VMOFF), | |
4223 | _ER(VMON), | |
4224 | _ER(CR_ACCESS), | |
4225 | _ER(DR_ACCESS), | |
4226 | _ER(IO_INSTRUCTION), | |
4227 | _ER(MSR_READ), | |
4228 | _ER(MSR_WRITE), | |
4229 | _ER(MWAIT_INSTRUCTION), | |
4230 | _ER(MONITOR_INSTRUCTION), | |
4231 | _ER(PAUSE_INSTRUCTION), | |
4232 | _ER(MCE_DURING_VMENTRY), | |
4233 | _ER(TPR_BELOW_THRESHOLD), | |
4234 | _ER(APIC_ACCESS), | |
4235 | _ER(EPT_VIOLATION), | |
4236 | _ER(EPT_MISCONFIG), | |
4237 | _ER(WBINVD), | |
229456fc MT |
4238 | { -1, NULL } |
4239 | }; | |
4240 | ||
f4c9e87c AK |
4241 | #undef _ER |
4242 | ||
17cc3935 | 4243 | static int vmx_get_lpage_level(void) |
344f414f | 4244 | { |
878403b7 SY |
4245 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
4246 | return PT_DIRECTORY_LEVEL; | |
4247 | else | |
4248 | /* For shadow and EPT supported 1GB page */ | |
4249 | return PT_PDPE_LEVEL; | |
344f414f JR |
4250 | } |
4251 | ||
4e47c7a6 SY |
4252 | static inline u32 bit(int bitno) |
4253 | { | |
4254 | return 1 << (bitno & 31); | |
4255 | } | |
4256 | ||
0e851880 SY |
4257 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
4258 | { | |
4e47c7a6 SY |
4259 | struct kvm_cpuid_entry2 *best; |
4260 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4261 | u32 exec_control; | |
4262 | ||
4263 | vmx->rdtscp_enabled = false; | |
4264 | if (vmx_rdtscp_supported()) { | |
4265 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
4266 | if (exec_control & SECONDARY_EXEC_RDTSCP) { | |
4267 | best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
4268 | if (best && (best->edx & bit(X86_FEATURE_RDTSCP))) | |
4269 | vmx->rdtscp_enabled = true; | |
4270 | else { | |
4271 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
4272 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
4273 | exec_control); | |
4274 | } | |
4275 | } | |
4276 | } | |
0e851880 SY |
4277 | } |
4278 | ||
d4330ef2 JR |
4279 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4280 | { | |
4281 | } | |
4282 | ||
cbdd1bea | 4283 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
4284 | .cpu_has_kvm_support = cpu_has_kvm_support, |
4285 | .disabled_by_bios = vmx_disabled_by_bios, | |
4286 | .hardware_setup = hardware_setup, | |
4287 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 4288 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
4289 | .hardware_enable = hardware_enable, |
4290 | .hardware_disable = hardware_disable, | |
04547156 | 4291 | .cpu_has_accelerated_tpr = report_flexpriority, |
6aa8b732 AK |
4292 | |
4293 | .vcpu_create = vmx_create_vcpu, | |
4294 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 4295 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 4296 | |
04d2cc77 | 4297 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
4298 | .vcpu_load = vmx_vcpu_load, |
4299 | .vcpu_put = vmx_vcpu_put, | |
4300 | ||
4301 | .set_guest_debug = set_guest_debug, | |
4302 | .get_msr = vmx_get_msr, | |
4303 | .set_msr = vmx_set_msr, | |
4304 | .get_segment_base = vmx_get_segment_base, | |
4305 | .get_segment = vmx_get_segment, | |
4306 | .set_segment = vmx_set_segment, | |
2e4d2653 | 4307 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 4308 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 4309 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
25c4c276 | 4310 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 4311 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
4312 | .set_cr3 = vmx_set_cr3, |
4313 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 4314 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
4315 | .get_idt = vmx_get_idt, |
4316 | .set_idt = vmx_set_idt, | |
4317 | .get_gdt = vmx_get_gdt, | |
4318 | .set_gdt = vmx_set_gdt, | |
020df079 | 4319 | .set_dr7 = vmx_set_dr7, |
5fdbf976 | 4320 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
4321 | .get_rflags = vmx_get_rflags, |
4322 | .set_rflags = vmx_set_rflags, | |
ebcbab4c | 4323 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 4324 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
4325 | |
4326 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 4327 | |
6aa8b732 | 4328 | .run = vmx_vcpu_run, |
6062d012 | 4329 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 4330 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4331 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
4332 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 4333 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 4334 | .set_irq = vmx_inject_irq, |
95ba8273 | 4335 | .set_nmi = vmx_inject_nmi, |
298101da | 4336 | .queue_exception = vmx_queue_exception, |
78646121 | 4337 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 4338 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
4339 | .get_nmi_mask = vmx_get_nmi_mask, |
4340 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
4341 | .enable_nmi_window = enable_nmi_window, |
4342 | .enable_irq_window = enable_irq_window, | |
4343 | .update_cr8_intercept = update_cr8_intercept, | |
95ba8273 | 4344 | |
cbc94022 | 4345 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 4346 | .get_tdp_level = get_ept_level, |
4b12f0de | 4347 | .get_mt_mask = vmx_get_mt_mask, |
229456fc MT |
4348 | |
4349 | .exit_reasons_str = vmx_exit_reasons_str, | |
17cc3935 | 4350 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
4351 | |
4352 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
4353 | |
4354 | .rdtscp_supported = vmx_rdtscp_supported, | |
d4330ef2 JR |
4355 | |
4356 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
4357 | |
4358 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
6aa8b732 AK |
4359 | }; |
4360 | ||
4361 | static int __init vmx_init(void) | |
4362 | { | |
26bb0981 AK |
4363 | int r, i; |
4364 | ||
4365 | rdmsrl_safe(MSR_EFER, &host_efer); | |
4366 | ||
4367 | for (i = 0; i < NR_VMX_MSR; ++i) | |
4368 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
fdef3ad1 | 4369 | |
3e7c73e9 | 4370 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
4371 | if (!vmx_io_bitmap_a) |
4372 | return -ENOMEM; | |
4373 | ||
3e7c73e9 | 4374 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
4375 | if (!vmx_io_bitmap_b) { |
4376 | r = -ENOMEM; | |
4377 | goto out; | |
4378 | } | |
4379 | ||
5897297b AK |
4380 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); |
4381 | if (!vmx_msr_bitmap_legacy) { | |
25c5f225 SY |
4382 | r = -ENOMEM; |
4383 | goto out1; | |
4384 | } | |
4385 | ||
5897297b AK |
4386 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); |
4387 | if (!vmx_msr_bitmap_longmode) { | |
4388 | r = -ENOMEM; | |
4389 | goto out2; | |
4390 | } | |
4391 | ||
fdef3ad1 HQ |
4392 | /* |
4393 | * Allow direct access to the PC debug port (it is often used for I/O | |
4394 | * delays, but the vmexits simply slow things down). | |
4395 | */ | |
3e7c73e9 AK |
4396 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
4397 | clear_bit(0x80, vmx_io_bitmap_a); | |
fdef3ad1 | 4398 | |
3e7c73e9 | 4399 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); |
fdef3ad1 | 4400 | |
5897297b AK |
4401 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); |
4402 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
25c5f225 | 4403 | |
2384d2b3 SY |
4404 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
4405 | ||
0ee75bea AK |
4406 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
4407 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 4408 | if (r) |
5897297b | 4409 | goto out3; |
25c5f225 | 4410 | |
5897297b AK |
4411 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
4412 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
4413 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
4414 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
4415 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
4416 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
fdef3ad1 | 4417 | |
089d034e | 4418 | if (enable_ept) { |
1439442c | 4419 | bypass_guest_pf = 0; |
5fdbcb9d | 4420 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
2aaf69dc | 4421 | VMX_EPT_WRITABLE_MASK); |
534e38b4 | 4422 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
4b12f0de | 4423 | VMX_EPT_EXECUTABLE_MASK); |
5fdbcb9d SY |
4424 | kvm_enable_tdp(); |
4425 | } else | |
4426 | kvm_disable_tdp(); | |
1439442c | 4427 | |
c7addb90 AK |
4428 | if (bypass_guest_pf) |
4429 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
4430 | ||
fdef3ad1 HQ |
4431 | return 0; |
4432 | ||
5897297b AK |
4433 | out3: |
4434 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
25c5f225 | 4435 | out2: |
5897297b | 4436 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
fdef3ad1 | 4437 | out1: |
3e7c73e9 | 4438 | free_page((unsigned long)vmx_io_bitmap_b); |
fdef3ad1 | 4439 | out: |
3e7c73e9 | 4440 | free_page((unsigned long)vmx_io_bitmap_a); |
fdef3ad1 | 4441 | return r; |
6aa8b732 AK |
4442 | } |
4443 | ||
4444 | static void __exit vmx_exit(void) | |
4445 | { | |
5897297b AK |
4446 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
4447 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
3e7c73e9 AK |
4448 | free_page((unsigned long)vmx_io_bitmap_b); |
4449 | free_page((unsigned long)vmx_io_bitmap_a); | |
fdef3ad1 | 4450 | |
cb498ea2 | 4451 | kvm_exit(); |
6aa8b732 AK |
4452 | } |
4453 | ||
4454 | module_init(vmx_init) | |
4455 | module_exit(vmx_exit) |