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KVM: x86: raise TSS exception for NULL CS and SS segments
[net-next-2.6.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
6de4f3ad 21#include "kvm_cache_regs.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732
AK		 24#include <linux/types.h>
25#include <linux/string.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/module.h>
448353ca 29#include <linux/swap.h>
05da4558 30#include <linux/hugetlb.h>
2f333bcb 31#include <linux/compiler.h>
6aa8b732 32
e495606d
AK		 33#include <asm/page.h>
34#include <asm/cmpxchg.h>
4e542370 35#include <asm/io.h>
13673a90 36#include <asm/vmx.h>
6aa8b732 37
18552672
JR		 38/*
39 * When setting this variable to true it enables Two-Dimensional-Paging
40 * where the hardware walks 2 page tables:
41 * 1. the guest-virtual to guest-physical
42 * 2. while doing 1. it walks guest-physical to host-physical
43 * If the hardware supports that we don't need to do shadow paging.
44 */
2f333bcb 45bool tdp_enabled = false;
18552672 46
37a7d8b0
AK		 47#undef MMU_DEBUG
48
49#undef AUDIT
50
51#ifdef AUDIT
52static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
53#else
54static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
55#endif
56
57#ifdef MMU_DEBUG
58
59#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
60#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
61
62#else
63
64#define pgprintk(x...) do { } while (0)
65#define rmap_printk(x...) do { } while (0)
66
67#endif
68
69#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 70static int dbg = 0;
71module_param(dbg, bool, 0644);
37a7d8b0 72#endif
6aa8b732 73
582801a9
MT		 74static int oos_shadow = 1;
75module_param(oos_shadow, bool, 0644);
76
d6c69ee9
YD		 77#ifndef MMU_DEBUG
78#define ASSERT(x) do { } while (0)
79#else
6aa8b732
AK		 80#define ASSERT(x) \
81 if (!(x)) { \
82 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
83 __FILE__, __LINE__, #x); \
84 }
d6c69ee9 85#endif
6aa8b732 86
6aa8b732
AK		 87#define PT_FIRST_AVAIL_BITS_SHIFT 9
88#define PT64_SECOND_AVAIL_BITS_SHIFT 52
89
6aa8b732
AK		 90#define VALID_PAGE(x) ((x) != INVALID_PAGE)
91
92#define PT64_LEVEL_BITS 9
93
94#define PT64_LEVEL_SHIFT(level) \
d77c26fc 95 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 96
97#define PT64_LEVEL_MASK(level) \
98 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
99
100#define PT64_INDEX(address, level)\
101 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
102
103
104#define PT32_LEVEL_BITS 10
105
106#define PT32_LEVEL_SHIFT(level) \
d77c26fc 107 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 108
109#define PT32_LEVEL_MASK(level) \
110 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 111#define PT32_LVL_OFFSET_MASK(level) \
112 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 114
115#define PT32_INDEX(address, level)\
116 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
117
118
27aba766 119#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 120#define PT64_DIR_BASE_ADDR_MASK \
121 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 122#define PT64_LVL_ADDR_MASK(level) \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT64_LEVEL_BITS))) - 1))
125#define PT64_LVL_OFFSET_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 128
129#define PT32_BASE_ADDR_MASK PAGE_MASK
130#define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 132#define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
6aa8b732 135
79539cec
AK		 136#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
137 | PT64_NX_MASK)
6aa8b732
AK		 138
139#define PFERR_PRESENT_MASK (1U << 0)
140#define PFERR_WRITE_MASK (1U << 1)
141#define PFERR_USER_MASK (1U << 2)
82725b20 142#define PFERR_RSVD_MASK (1U << 3)
73b1087e 143#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 144
e04da980 145#define PT_PDPE_LEVEL 3
6aa8b732
AK		 146#define PT_DIRECTORY_LEVEL 2
147#define PT_PAGE_TABLE_LEVEL 1
148
cd4a4e53
AK		 149#define RMAP_EXT 4
150
fe135d2c
AK		 151#define ACC_EXEC_MASK 1
152#define ACC_WRITE_MASK PT_WRITABLE_MASK
153#define ACC_USER_MASK PT_USER_MASK
154#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
155
07420171
AK		 156#define CREATE_TRACE_POINTS
157#include "mmutrace.h"
158
1403283a
IE		 159#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
160
135f8c2b
AK		 161#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
162
cd4a4e53 163struct kvm_rmap_desc {
d555c333 164 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 165 struct kvm_rmap_desc *more;
166};
167
2d11123a
AK		 168struct kvm_shadow_walk_iterator {
169 u64 addr;
170 hpa_t shadow_addr;
171 int level;
172 u64 *sptep;
173 unsigned index;
174};
175
176#define for_each_shadow_entry(_vcpu, _addr, _walker) \
177 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
178 shadow_walk_okay(&(_walker)); \
179 shadow_walk_next(&(_walker)))
180
181
4731d4c7
MT		 182struct kvm_unsync_walk {
183 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
184};
185
ad8cfbe3
MT		 186typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
187
b5a33a75
AK		 188static struct kmem_cache *pte_chain_cache;
189static struct kmem_cache *rmap_desc_cache;
d3d25b04 190static struct kmem_cache *mmu_page_header_cache;
b5a33a75 191
c7addb90
AK		 192static u64 __read_mostly shadow_trap_nonpresent_pte;
193static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 194static u64 __read_mostly shadow_base_present_pte;
195static u64 __read_mostly shadow_nx_mask;
196static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
197static u64 __read_mostly shadow_user_mask;
198static u64 __read_mostly shadow_accessed_mask;
199static u64 __read_mostly shadow_dirty_mask;
c7addb90 200
82725b20
DE		 201static inline u64 rsvd_bits(int s, int e)
202{
203 return ((1ULL << (e - s + 1)) - 1) << s;
204}
205
c7addb90
AK		 206void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
207{
208 shadow_trap_nonpresent_pte = trap_pte;
209 shadow_notrap_nonpresent_pte = notrap_pte;
210}
211EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
212
7b52345e
SY		 213void kvm_mmu_set_base_ptes(u64 base_pte)
214{
215 shadow_base_present_pte = base_pte;
216}
217EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
218
219void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 220 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 221{
222 shadow_user_mask = user_mask;
223 shadow_accessed_mask = accessed_mask;
224 shadow_dirty_mask = dirty_mask;
225 shadow_nx_mask = nx_mask;
226 shadow_x_mask = x_mask;
227}
228EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
229
6aa8b732
AK		 230static int is_write_protection(struct kvm_vcpu *vcpu)
231{
ad312c7c 232 return vcpu->arch.cr0 & X86_CR0_WP;
6aa8b732
AK		 233}
234
235static int is_cpuid_PSE36(void)
236{
237 return 1;
238}
239
73b1087e
AK		 240static int is_nx(struct kvm_vcpu *vcpu)
241{
ad312c7c 242 return vcpu->arch.shadow_efer & EFER_NX;
73b1087e
AK		 243}
244
c7addb90
AK		 245static int is_shadow_present_pte(u64 pte)
246{
c7addb90
AK		 247 return pte != shadow_trap_nonpresent_pte
248 && pte != shadow_notrap_nonpresent_pte;
249}
250
05da4558
MT		 251static int is_large_pte(u64 pte)
252{
253 return pte & PT_PAGE_SIZE_MASK;
254}
255
6aa8b732
AK		 256static int is_writeble_pte(unsigned long pte)
257{
258 return pte & PT_WRITABLE_MASK;
259}
260
43a3795a 261static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 262{
439e218a 263 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 264}
265
43a3795a 266static int is_rmap_spte(u64 pte)
cd4a4e53 267{
4b1a80fa 268 return is_shadow_present_pte(pte);
cd4a4e53
AK		 269}
270
776e6633
MT		 271static int is_last_spte(u64 pte, int level)
272{
273 if (level == PT_PAGE_TABLE_LEVEL)
274 return 1;
852e3c19 275 if (is_large_pte(pte))
776e6633
MT		 276 return 1;
277 return 0;
278}
279
35149e21 280static pfn_t spte_to_pfn(u64 pte)
0b49ea86 281{
35149e21 282 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 283}
284
da928521
AK		 285static gfn_t pse36_gfn_delta(u32 gpte)
286{
287 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
288
289 return (gpte & PT32_DIR_PSE36_MASK) << shift;
290}
291
d555c333 292static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 293{
294#ifdef CONFIG_X86_64
295 set_64bit((unsigned long *)sptep, spte);
296#else
297 set_64bit((unsigned long long *)sptep, spte);
298#endif
299}
300
e2dec939 301static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 302 struct kmem_cache *base_cache, int min)
714b93da
AK		 303{
304 void *obj;
305
306 if (cache->nobjs >= min)
e2dec939 307 return 0;
714b93da 308 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 309 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 310 if (!obj)
e2dec939 311 return -ENOMEM;
714b93da
AK		 312 cache->objects[cache->nobjs++] = obj;
313 }
e2dec939 314 return 0;
714b93da
AK		 315}
316
317static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
318{
319 while (mc->nobjs)
320 kfree(mc->objects[--mc->nobjs]);
321}
322
c1158e63 323static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 324 int min)
c1158e63
AK		 325{
326 struct page *page;
327
328 if (cache->nobjs >= min)
329 return 0;
330 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 331 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 332 if (!page)
333 return -ENOMEM;
334 set_page_private(page, 0);
335 cache->objects[cache->nobjs++] = page_address(page);
336 }
337 return 0;
338}
339
340static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
341{
342 while (mc->nobjs)
c4d198d5 343 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 344}
345
2e3e5882 346static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 347{
e2dec939
AK		 348 int r;
349
ad312c7c 350 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 351 pte_chain_cache, 4);
e2dec939
AK		 352 if (r)
353 goto out;
ad312c7c 354 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 355 rmap_desc_cache, 4);
d3d25b04
AK		 356 if (r)
357 goto out;
ad312c7c 358 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 359 if (r)
360 goto out;
ad312c7c 361 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 362 mmu_page_header_cache, 4);
e2dec939
AK		 363out:
364 return r;
714b93da
AK		 365}
366
367static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
368{
ad312c7c
ZX		 369 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
370 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
371 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
372 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 373}
374
375static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
376 size_t size)
377{
378 void *p;
379
380 BUG_ON(!mc->nobjs);
381 p = mc->objects[--mc->nobjs];
714b93da
AK		 382 return p;
383}
384
714b93da
AK		 385static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
386{
ad312c7c 387 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 388 sizeof(struct kvm_pte_chain));
389}
390
90cb0529 391static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 392{
90cb0529 393 kfree(pc);
714b93da
AK		 394}
395
396static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
397{
ad312c7c 398 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 399 sizeof(struct kvm_rmap_desc));
400}
401
90cb0529 402static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 403{
90cb0529 404 kfree(rd);
714b93da
AK		 405}
406
05da4558
MT		 407/*
408 * Return the pointer to the largepage write count for a given
409 * gfn, handling slots that are not large page aligned.
410 */
d25797b2
JR		 411static int *slot_largepage_idx(gfn_t gfn,
412 struct kvm_memory_slot *slot,
413 int level)
05da4558
MT		 414{
415 unsigned long idx;
416
d25797b2
JR		 417 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
418 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
419 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 420}
421
422static void account_shadowed(struct kvm *kvm, gfn_t gfn)
423{
d25797b2 424 struct kvm_memory_slot *slot;
05da4558 425 int *write_count;
d25797b2 426 int i;
05da4558 427
2843099f 428 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 429
430 slot = gfn_to_memslot_unaliased(kvm, gfn);
431 for (i = PT_DIRECTORY_LEVEL;
432 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
433 write_count = slot_largepage_idx(gfn, slot, i);
434 *write_count += 1;
435 }
05da4558
MT		 436}
437
438static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
439{
d25797b2 440 struct kvm_memory_slot *slot;
05da4558 441 int *write_count;
d25797b2 442 int i;
05da4558 443
2843099f 444 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 445 for (i = PT_DIRECTORY_LEVEL;
446 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
447 slot = gfn_to_memslot_unaliased(kvm, gfn);
448 write_count = slot_largepage_idx(gfn, slot, i);
449 *write_count -= 1;
450 WARN_ON(*write_count < 0);
451 }
05da4558
MT		 452}
453
d25797b2
JR		 454static int has_wrprotected_page(struct kvm *kvm,
455 gfn_t gfn,
456 int level)
05da4558 457{
2843099f 458 struct kvm_memory_slot *slot;
05da4558
MT		 459 int *largepage_idx;
460
2843099f
IE		 461 gfn = unalias_gfn(kvm, gfn);
462 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 463 if (slot) {
d25797b2 464 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 465 return *largepage_idx;
466 }
467
468 return 1;
469}
470
d25797b2 471static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 472{
d25797b2 473 unsigned long page_size = PAGE_SIZE;
05da4558
MT		 474 struct vm_area_struct *vma;
475 unsigned long addr;
d25797b2 476 int i, ret = 0;
05da4558
MT		 477
478 addr = gfn_to_hva(kvm, gfn);
479 if (kvm_is_error_hva(addr))
82b7005f 480 return PT_PAGE_TABLE_LEVEL;
05da4558 481
4c2155ce 482 down_read(&current->mm->mmap_sem);
05da4558 483 vma = find_vma(current->mm, addr);
d25797b2
JR		 484 if (!vma)
485 goto out;
486
487 page_size = vma_kernel_pagesize(vma);
488
489out:
4c2155ce 490 up_read(&current->mm->mmap_sem);
05da4558 491
d25797b2
JR		 492 for (i = PT_PAGE_TABLE_LEVEL;
493 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
494 if (page_size >= KVM_HPAGE_SIZE(i))
495 ret = i;
496 else
497 break;
498 }
499
4c2155ce 500 return ret;
05da4558
MT		 501}
502
d25797b2 503static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 504{
505 struct kvm_memory_slot *slot;
d25797b2
JR		 506 int host_level;
507 int level = PT_PAGE_TABLE_LEVEL;
05da4558
MT		 508
509 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
510 if (slot && slot->dirty_bitmap)
d25797b2 511 return PT_PAGE_TABLE_LEVEL;
05da4558 512
d25797b2
JR		 513 host_level = host_mapping_level(vcpu->kvm, large_gfn);
514
515 if (host_level == PT_PAGE_TABLE_LEVEL)
516 return host_level;
517
82b7005f 518 for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level)
d25797b2
JR		 519 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
520 break;
d25797b2
JR		 521
522 return level - 1;
05da4558
MT		 523}
524
290fc38d
IE		 525/*
526 * Take gfn and return the reverse mapping to it.
527 * Note: gfn must be unaliased before this function get called
528 */
529
44ad9944 530static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 531{
532 struct kvm_memory_slot *slot;
05da4558 533 unsigned long idx;
290fc38d
IE		 534
535 slot = gfn_to_memslot(kvm, gfn);
44ad9944 536 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 537 return &slot->rmap[gfn - slot->base_gfn];
538
44ad9944
JR		 539 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
540 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 541
44ad9944 542 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 543}
544
cd4a4e53
AK		 545/*
546 * Reverse mapping data structures:
547 *
290fc38d
IE		 548 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
549 * that points to page_address(page).
cd4a4e53 550 *
290fc38d
IE		 551 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
552 * containing more mappings.
53a27b39
MT		 553 *
554 * Returns the number of rmap entries before the spte was added or zero if
555 * the spte was not added.
556 *
cd4a4e53 557 */
44ad9944 558static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 559{
4db35314 560 struct kvm_mmu_page *sp;
cd4a4e53 561 struct kvm_rmap_desc *desc;
290fc38d 562 unsigned long *rmapp;
53a27b39 563 int i, count = 0;
cd4a4e53 564
43a3795a 565 if (!is_rmap_spte(*spte))
53a27b39 566 return count;
290fc38d 567 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 568 sp = page_header(__pa(spte));
569 sp->gfns[spte - sp->spt] = gfn;
44ad9944 570 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 571 if (!*rmapp) {
cd4a4e53 572 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 573 *rmapp = (unsigned long)spte;
574 } else if (!(*rmapp & 1)) {
cd4a4e53 575 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 576 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 577 desc->sptes[0] = (u64 *)*rmapp;
578 desc->sptes[1] = spte;
290fc38d 579 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 580 } else {
581 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 582 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 583 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 584 desc = desc->more;
53a27b39
MT		 585 count += RMAP_EXT;
586 }
d555c333 587 if (desc->sptes[RMAP_EXT-1]) {
714b93da 588 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 589 desc = desc->more;
590 }
d555c333 591 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 592 ;
d555c333 593 desc->sptes[i] = spte;
cd4a4e53 594 }
53a27b39 595 return count;
cd4a4e53
AK		 596}
597
290fc38d 598static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 599 struct kvm_rmap_desc *desc,
600 int i,
601 struct kvm_rmap_desc *prev_desc)
602{
603 int j;
604
d555c333 605 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 606 ;
d555c333
AK		 607 desc->sptes[i] = desc->sptes[j];
608 desc->sptes[j] = NULL;
cd4a4e53
AK		 609 if (j != 0)
610 return;
611 if (!prev_desc && !desc->more)
d555c333 612 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 613 else
614 if (prev_desc)
615 prev_desc->more = desc->more;
616 else
290fc38d 617 *rmapp = (unsigned long)desc->more | 1;
90cb0529 618 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 619}
620
290fc38d 621static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 622{
cd4a4e53
AK		 623 struct kvm_rmap_desc *desc;
624 struct kvm_rmap_desc *prev_desc;
4db35314 625 struct kvm_mmu_page *sp;
35149e21 626 pfn_t pfn;
290fc38d 627 unsigned long *rmapp;
cd4a4e53
AK		 628 int i;
629
43a3795a 630 if (!is_rmap_spte(*spte))
cd4a4e53 631 return;
4db35314 632 sp = page_header(__pa(spte));
35149e21 633 pfn = spte_to_pfn(*spte);
7b52345e 634 if (*spte & shadow_accessed_mask)
35149e21 635 kvm_set_pfn_accessed(pfn);
b4231d61 636 if (is_writeble_pte(*spte))
acb66dd0 637 kvm_set_pfn_dirty(pfn);
44ad9944 638 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 639 if (!*rmapp) {
cd4a4e53
AK		 640 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
641 BUG();
290fc38d 642 } else if (!(*rmapp & 1)) {
cd4a4e53 643 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 644 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 645 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
646 spte, *spte);
647 BUG();
648 }
290fc38d 649 *rmapp = 0;
cd4a4e53
AK		 650 } else {
651 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 652 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 653 prev_desc = NULL;
654 while (desc) {
d555c333
AK		 655 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
656 if (desc->sptes[i] == spte) {
290fc38d 657 rmap_desc_remove_entry(rmapp,
714b93da 658 desc, i,
cd4a4e53
AK		 659 prev_desc);
660 return;
661 }
662 prev_desc = desc;
663 desc = desc->more;
664 }
665 BUG();
666 }
667}
668
98348e95 669static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 670{
374cbac0 671 struct kvm_rmap_desc *desc;
98348e95
IE		 672 struct kvm_rmap_desc *prev_desc;
673 u64 *prev_spte;
674 int i;
675
676 if (!*rmapp)
677 return NULL;
678 else if (!(*rmapp & 1)) {
679 if (!spte)
680 return (u64 *)*rmapp;
681 return NULL;
682 }
683 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
684 prev_desc = NULL;
685 prev_spte = NULL;
686 while (desc) {
d555c333 687 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 688 if (prev_spte == spte)
d555c333
AK		 689 return desc->sptes[i];
690 prev_spte = desc->sptes[i];
98348e95
IE		 691 }
692 desc = desc->more;
693 }
694 return NULL;
695}
696
b1a36821 697static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 698{
290fc38d 699 unsigned long *rmapp;
374cbac0 700 u64 *spte;
44ad9944 701 int i, write_protected = 0;
374cbac0 702
4a4c9924 703 gfn = unalias_gfn(kvm, gfn);
44ad9944 704 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 705
98348e95
IE		 706 spte = rmap_next(kvm, rmapp, NULL);
707 while (spte) {
374cbac0 708 BUG_ON(!spte);
374cbac0 709 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 710 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 711 if (is_writeble_pte(*spte)) {
d555c333 712 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 713 write_protected = 1;
714 }
9647c14c 715 spte = rmap_next(kvm, rmapp, spte);
374cbac0 716 }
855149aa 717 if (write_protected) {
35149e21 718 pfn_t pfn;
855149aa
IE		 719
720 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 721 pfn = spte_to_pfn(*spte);
722 kvm_set_pfn_dirty(pfn);
855149aa
IE		 723 }
724
05da4558 725 /* check for huge page mappings */
44ad9944
JR		 726 for (i = PT_DIRECTORY_LEVEL;
727 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
728 rmapp = gfn_to_rmap(kvm, gfn, i);
729 spte = rmap_next(kvm, rmapp, NULL);
730 while (spte) {
731 BUG_ON(!spte);
732 BUG_ON(!(*spte & PT_PRESENT_MASK));
733 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
734 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
735 if (is_writeble_pte(*spte)) {
736 rmap_remove(kvm, spte);
737 --kvm->stat.lpages;
738 __set_spte(spte, shadow_trap_nonpresent_pte);
739 spte = NULL;
740 write_protected = 1;
741 }
742 spte = rmap_next(kvm, rmapp, spte);
05da4558 743 }
05da4558
MT		 744 }
745
b1a36821 746 return write_protected;
374cbac0
AK		 747}
748
8a8365c5
FD		 749static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
750 unsigned long data)
e930bffe
AA		 751{
752 u64 *spte;
753 int need_tlb_flush = 0;
754
755 while ((spte = rmap_next(kvm, rmapp, NULL))) {
756 BUG_ON(!(*spte & PT_PRESENT_MASK));
757 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
758 rmap_remove(kvm, spte);
d555c333 759 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 760 need_tlb_flush = 1;
761 }
762 return need_tlb_flush;
763}
764
8a8365c5
FD		 765static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
766 unsigned long data)
3da0dd43
IE		 767{
768 int need_flush = 0;
769 u64 *spte, new_spte;
770 pte_t *ptep = (pte_t *)data;
771 pfn_t new_pfn;
772
773 WARN_ON(pte_huge(*ptep));
774 new_pfn = pte_pfn(*ptep);
775 spte = rmap_next(kvm, rmapp, NULL);
776 while (spte) {
777 BUG_ON(!is_shadow_present_pte(*spte));
778 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
779 need_flush = 1;
780 if (pte_write(*ptep)) {
781 rmap_remove(kvm, spte);
782 __set_spte(spte, shadow_trap_nonpresent_pte);
783 spte = rmap_next(kvm, rmapp, NULL);
784 } else {
785 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
786 new_spte |= (u64)new_pfn << PAGE_SHIFT;
787
788 new_spte &= ~PT_WRITABLE_MASK;
789 new_spte &= ~SPTE_HOST_WRITEABLE;
790 if (is_writeble_pte(*spte))
791 kvm_set_pfn_dirty(spte_to_pfn(*spte));
792 __set_spte(spte, new_spte);
793 spte = rmap_next(kvm, rmapp, spte);
794 }
795 }
796 if (need_flush)
797 kvm_flush_remote_tlbs(kvm);
798
799 return 0;
800}
801
8a8365c5
FD		 802static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
803 unsigned long data,
3da0dd43 804 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 805 unsigned long data))
e930bffe 806{
852e3c19 807 int i, j;
e930bffe
AA		 808 int retval = 0;
809
810 /*
811 * If mmap_sem isn't taken, we can look the memslots with only
812 * the mmu_lock by skipping over the slots with userspace_addr == 0.
813 */
814 for (i = 0; i < kvm->nmemslots; i++) {
815 struct kvm_memory_slot *memslot = &kvm->memslots[i];
816 unsigned long start = memslot->userspace_addr;
817 unsigned long end;
818
819 /* mmu_lock protects userspace_addr */
820 if (!start)
821 continue;
822
823 end = start + (memslot->npages << PAGE_SHIFT);
824 if (hva >= start && hva < end) {
825 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 826
3da0dd43
IE		 827 retval |= handler(kvm, &memslot->rmap[gfn_offset],
828 data);
852e3c19
JR		 829
830 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
831 int idx = gfn_offset;
832 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
833 retval |= handler(kvm,
3da0dd43
IE		 834 &memslot->lpage_info[j][idx].rmap_pde,
835 data);
852e3c19 836 }
e930bffe
AA		 837 }
838 }
839
840 return retval;
841}
842
843int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
844{
3da0dd43
IE		 845 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
846}
847
848void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
849{
8a8365c5 850 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 851}
852
8a8365c5
FD		 853static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
854 unsigned long data)
e930bffe
AA		 855{
856 u64 *spte;
857 int young = 0;
858
534e38b4
SY		 859 /* always return old for EPT */
860 if (!shadow_accessed_mask)
861 return 0;
862
e930bffe
AA		 863 spte = rmap_next(kvm, rmapp, NULL);
864 while (spte) {
865 int _young;
866 u64 _spte = *spte;
867 BUG_ON(!(_spte & PT_PRESENT_MASK));
868 _young = _spte & PT_ACCESSED_MASK;
869 if (_young) {
870 young = 1;
871 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
872 }
873 spte = rmap_next(kvm, rmapp, spte);
874 }
875 return young;
876}
877
53a27b39
MT		 878#define RMAP_RECYCLE_THRESHOLD 1000
879
852e3c19 880static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 881{
882 unsigned long *rmapp;
852e3c19
JR		 883 struct kvm_mmu_page *sp;
884
885 sp = page_header(__pa(spte));
53a27b39
MT		 886
887 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 888 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 889
3da0dd43 890 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 891 kvm_flush_remote_tlbs(vcpu->kvm);
892}
893
e930bffe
AA		 894int kvm_age_hva(struct kvm *kvm, unsigned long hva)
895{
3da0dd43 896 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 897}
898
d6c69ee9 899#ifdef MMU_DEBUG
47ad8e68 900static int is_empty_shadow_page(u64 *spt)
6aa8b732 901{
139bdb2d
AK		 902 u64 *pos;
903 u64 *end;
904
47ad8e68 905 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 906 if (is_shadow_present_pte(*pos)) {
b8688d51 907 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 908 pos, *pos);
6aa8b732 909 return 0;
139bdb2d 910 }
6aa8b732
AK		 911 return 1;
912}
d6c69ee9 913#endif
6aa8b732 914
4db35314 915static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 916{
4db35314
AK		 917 ASSERT(is_empty_shadow_page(sp->spt));
918 list_del(&sp->link);
919 __free_page(virt_to_page(sp->spt));
920 __free_page(virt_to_page(sp->gfns));
921 kfree(sp);
f05e70ac 922 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 923}
924
cea0f0e7
AK		 925static unsigned kvm_page_table_hashfn(gfn_t gfn)
926{
1ae0a13d 927 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 928}
929
25c0de2c
AK		 930static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
931 u64 *parent_pte)
6aa8b732 932{
4db35314 933 struct kvm_mmu_page *sp;
6aa8b732 934
ad312c7c
ZX		 935 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
936 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
937 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 938 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 939 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 940 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 941 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 942 sp->multimapped = 0;
943 sp->parent_pte = parent_pte;
f05e70ac 944 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 945 return sp;
6aa8b732
AK		 946}
947
714b93da 948static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 949 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 950{
951 struct kvm_pte_chain *pte_chain;
952 struct hlist_node *node;
953 int i;
954
955 if (!parent_pte)
956 return;
4db35314
AK		 957 if (!sp->multimapped) {
958 u64 *old = sp->parent_pte;
cea0f0e7
AK		 959
960 if (!old) {
4db35314 961 sp->parent_pte = parent_pte;
cea0f0e7
AK		 962 return;
963 }
4db35314 964 sp->multimapped = 1;
714b93da 965 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 966 INIT_HLIST_HEAD(&sp->parent_ptes);
967 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 968 pte_chain->parent_ptes[0] = old;
969 }
4db35314 970 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 971 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
972 continue;
973 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
974 if (!pte_chain->parent_ptes[i]) {
975 pte_chain->parent_ptes[i] = parent_pte;
976 return;
977 }
978 }
714b93da 979 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 980 BUG_ON(!pte_chain);
4db35314 981 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 982 pte_chain->parent_ptes[0] = parent_pte;
983}
984
4db35314 985static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 986 u64 *parent_pte)
987{
988 struct kvm_pte_chain *pte_chain;
989 struct hlist_node *node;
990 int i;
991
4db35314
AK		 992 if (!sp->multimapped) {
993 BUG_ON(sp->parent_pte != parent_pte);
994 sp->parent_pte = NULL;
cea0f0e7
AK		 995 return;
996 }
4db35314 997 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 998 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
999 if (!pte_chain->parent_ptes[i])
1000 break;
1001 if (pte_chain->parent_ptes[i] != parent_pte)
1002 continue;
697fe2e2
AK		 1003 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1004 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 1005 pte_chain->parent_ptes[i]
1006 = pte_chain->parent_ptes[i + 1];
1007 ++i;
1008 }
1009 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 1010 if (i == 0) {
1011 hlist_del(&pte_chain->link);
90cb0529 1012 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1013 if (hlist_empty(&sp->parent_ptes)) {
1014 sp->multimapped = 0;
1015 sp->parent_pte = NULL;
697fe2e2
AK		 1016 }
1017 }
cea0f0e7
AK		 1018 return;
1019 }
1020 BUG();
1021}
1022
ad8cfbe3
MT		 1023
1024static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1025 mmu_parent_walk_fn fn)
1026{
1027 struct kvm_pte_chain *pte_chain;
1028 struct hlist_node *node;
1029 struct kvm_mmu_page *parent_sp;
1030 int i;
1031
1032 if (!sp->multimapped && sp->parent_pte) {
1033 parent_sp = page_header(__pa(sp->parent_pte));
1034 fn(vcpu, parent_sp);
1035 mmu_parent_walk(vcpu, parent_sp, fn);
1036 return;
1037 }
1038 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1039 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1040 if (!pte_chain->parent_ptes[i])
1041 break;
1042 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1043 fn(vcpu, parent_sp);
1044 mmu_parent_walk(vcpu, parent_sp, fn);
1045 }
1046}
1047
0074ff63
MT		 1048static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1049{
1050 unsigned int index;
1051 struct kvm_mmu_page *sp = page_header(__pa(spte));
1052
1053 index = spte - sp->spt;
60c8aec6
MT		 1054 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1055 sp->unsync_children++;
1056 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1057}
1058
1059static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1060{
1061 struct kvm_pte_chain *pte_chain;
1062 struct hlist_node *node;
1063 int i;
1064
1065 if (!sp->parent_pte)
1066 return;
1067
1068 if (!sp->multimapped) {
1069 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1070 return;
1071 }
1072
1073 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1074 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1075 if (!pte_chain->parent_ptes[i])
1076 break;
1077 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1078 }
1079}
1080
1081static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1082{
0074ff63
MT		 1083 kvm_mmu_update_parents_unsync(sp);
1084 return 1;
1085}
1086
1087static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1088 struct kvm_mmu_page *sp)
1089{
1090 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1091 kvm_mmu_update_parents_unsync(sp);
1092}
1093
d761a501
AK		 1094static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1095 struct kvm_mmu_page *sp)
1096{
1097 int i;
1098
1099 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1100 sp->spt[i] = shadow_trap_nonpresent_pte;
1101}
1102
e8bc217a
MT		 1103static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1104 struct kvm_mmu_page *sp)
1105{
1106 return 1;
1107}
1108
a7052897
MT		 1109static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1110{
1111}
1112
60c8aec6
MT		 1113#define KVM_PAGE_ARRAY_NR 16
1114
1115struct kvm_mmu_pages {
1116 struct mmu_page_and_offset {
1117 struct kvm_mmu_page *sp;
1118 unsigned int idx;
1119 } page[KVM_PAGE_ARRAY_NR];
1120 unsigned int nr;
1121};
1122
0074ff63
MT		 1123#define for_each_unsync_children(bitmap, idx) \
1124 for (idx = find_first_bit(bitmap, 512); \
1125 idx < 512; \
1126 idx = find_next_bit(bitmap, 512, idx+1))
1127
cded19f3
HE		 1128static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1129 int idx)
4731d4c7 1130{
60c8aec6 1131 int i;
4731d4c7 1132
60c8aec6
MT		 1133 if (sp->unsync)
1134 for (i=0; i < pvec->nr; i++)
1135 if (pvec->page[i].sp == sp)
1136 return 0;
1137
1138 pvec->page[pvec->nr].sp = sp;
1139 pvec->page[pvec->nr].idx = idx;
1140 pvec->nr++;
1141 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1142}
1143
1144static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1145 struct kvm_mmu_pages *pvec)
1146{
1147 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1148
0074ff63 1149 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1150 u64 ent = sp->spt[i];
1151
87917239 1152 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1153 struct kvm_mmu_page *child;
1154 child = page_header(ent & PT64_BASE_ADDR_MASK);
1155
1156 if (child->unsync_children) {
60c8aec6
MT		 1157 if (mmu_pages_add(pvec, child, i))
1158 return -ENOSPC;
1159
1160 ret = __mmu_unsync_walk(child, pvec);
1161 if (!ret)
1162 __clear_bit(i, sp->unsync_child_bitmap);
1163 else if (ret > 0)
1164 nr_unsync_leaf += ret;
1165 else
4731d4c7
MT		 1166 return ret;
1167 }
1168
1169 if (child->unsync) {
60c8aec6
MT		 1170 nr_unsync_leaf++;
1171 if (mmu_pages_add(pvec, child, i))
1172 return -ENOSPC;
4731d4c7
MT		 1173 }
1174 }
1175 }
1176
0074ff63 1177 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1178 sp->unsync_children = 0;
1179
60c8aec6
MT		 1180 return nr_unsync_leaf;
1181}
1182
1183static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1184 struct kvm_mmu_pages *pvec)
1185{
1186 if (!sp->unsync_children)
1187 return 0;
1188
1189 mmu_pages_add(pvec, sp, 0);
1190 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1191}
1192
4db35314 1193static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1194{
1195 unsigned index;
1196 struct hlist_head *bucket;
4db35314 1197 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1198 struct hlist_node *node;
1199
b8688d51 1200 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1201 index = kvm_page_table_hashfn(gfn);
f05e70ac 1202 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1203 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1204 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1205 && !sp->role.invalid) {
cea0f0e7 1206 pgprintk("%s: found role %x\n",
b8688d51 1207 __func__, sp->role.word);
4db35314 1208 return sp;
cea0f0e7
AK		 1209 }
1210 return NULL;
1211}
1212
4731d4c7
MT		 1213static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1214{
1215 WARN_ON(!sp->unsync);
1216 sp->unsync = 0;
1217 --kvm->stat.mmu_unsync;
1218}
1219
1220static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1221
1222static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1223{
1224 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1225 kvm_mmu_zap_page(vcpu->kvm, sp);
1226 return 1;
1227 }
1228
f691fe1d 1229 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1230 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1231 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1232 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1233 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1234 kvm_mmu_zap_page(vcpu->kvm, sp);
1235 return 1;
1236 }
1237
1238 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1239 return 0;
1240}
1241
60c8aec6
MT		 1242struct mmu_page_path {
1243 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1244 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1245};
1246
60c8aec6
MT		 1247#define for_each_sp(pvec, sp, parents, i) \
1248 for (i = mmu_pages_next(&pvec, &parents, -1), \
1249 sp = pvec.page[i].sp; \
1250 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1251 i = mmu_pages_next(&pvec, &parents, i))
1252
cded19f3
HE		 1253static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1254 struct mmu_page_path *parents,
1255 int i)
60c8aec6
MT		 1256{
1257 int n;
1258
1259 for (n = i+1; n < pvec->nr; n++) {
1260 struct kvm_mmu_page *sp = pvec->page[n].sp;
1261
1262 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1263 parents->idx[0] = pvec->page[n].idx;
1264 return n;
1265 }
1266
1267 parents->parent[sp->role.level-2] = sp;
1268 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1269 }
1270
1271 return n;
1272}
1273
cded19f3 1274static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1275{
60c8aec6
MT		 1276 struct kvm_mmu_page *sp;
1277 unsigned int level = 0;
1278
1279 do {
1280 unsigned int idx = parents->idx[level];
4731d4c7 1281
60c8aec6
MT		 1282 sp = parents->parent[level];
1283 if (!sp)
1284 return;
1285
1286 --sp->unsync_children;
1287 WARN_ON((int)sp->unsync_children < 0);
1288 __clear_bit(idx, sp->unsync_child_bitmap);
1289 level++;
1290 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1291}
1292
60c8aec6
MT		 1293static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1294 struct mmu_page_path *parents,
1295 struct kvm_mmu_pages *pvec)
4731d4c7 1296{
60c8aec6
MT		 1297 parents->parent[parent->role.level-1] = NULL;
1298 pvec->nr = 0;
1299}
4731d4c7 1300
60c8aec6
MT		 1301static void mmu_sync_children(struct kvm_vcpu *vcpu,
1302 struct kvm_mmu_page *parent)
1303{
1304 int i;
1305 struct kvm_mmu_page *sp;
1306 struct mmu_page_path parents;
1307 struct kvm_mmu_pages pages;
1308
1309 kvm_mmu_pages_init(parent, &parents, &pages);
1310 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1311 int protected = 0;
1312
1313 for_each_sp(pages, sp, parents, i)
1314 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1315
1316 if (protected)
1317 kvm_flush_remote_tlbs(vcpu->kvm);
1318
60c8aec6
MT		 1319 for_each_sp(pages, sp, parents, i) {
1320 kvm_sync_page(vcpu, sp);
1321 mmu_pages_clear_parents(&parents);
1322 }
4731d4c7 1323 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1324 kvm_mmu_pages_init(parent, &parents, &pages);
1325 }
4731d4c7
MT		 1326}
1327
cea0f0e7
AK		 1328static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1329 gfn_t gfn,
1330 gva_t gaddr,
1331 unsigned level,
f6e2c02b 1332 int direct,
41074d07 1333 unsigned access,
f7d9c7b7 1334 u64 *parent_pte)
cea0f0e7
AK		 1335{
1336 union kvm_mmu_page_role role;
1337 unsigned index;
1338 unsigned quadrant;
1339 struct hlist_head *bucket;
4db35314 1340 struct kvm_mmu_page *sp;
4731d4c7 1341 struct hlist_node *node, *tmp;
cea0f0e7 1342
a770f6f2 1343 role = vcpu->arch.mmu.base_role;
cea0f0e7 1344 role.level = level;
f6e2c02b 1345 role.direct = direct;
41074d07 1346 role.access = access;
ad312c7c 1347 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1348 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1349 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1350 role.quadrant = quadrant;
1351 }
1ae0a13d 1352 index = kvm_page_table_hashfn(gfn);
f05e70ac 1353 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1354 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1355 if (sp->gfn == gfn) {
1356 if (sp->unsync)
1357 if (kvm_sync_page(vcpu, sp))
1358 continue;
1359
1360 if (sp->role.word != role.word)
1361 continue;
1362
4db35314 1363 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1364 if (sp->unsync_children) {
1365 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1366 kvm_mmu_mark_parents_unsync(vcpu, sp);
1367 }
f691fe1d 1368 trace_kvm_mmu_get_page(sp, false);
4db35314 1369 return sp;
cea0f0e7 1370 }
dfc5aa00 1371 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1372 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1373 if (!sp)
1374 return sp;
4db35314
AK		 1375 sp->gfn = gfn;
1376 sp->role = role;
1377 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1378 if (!direct) {
b1a36821
MT		 1379 if (rmap_write_protect(vcpu->kvm, gfn))
1380 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1381 account_shadowed(vcpu->kvm, gfn);
1382 }
131d8279
AK		 1383 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1384 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1385 else
1386 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1387 trace_kvm_mmu_get_page(sp, true);
4db35314 1388 return sp;
cea0f0e7
AK		 1389}
1390
2d11123a
AK		 1391static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1392 struct kvm_vcpu *vcpu, u64 addr)
1393{
1394 iterator->addr = addr;
1395 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1396 iterator->level = vcpu->arch.mmu.shadow_root_level;
1397 if (iterator->level == PT32E_ROOT_LEVEL) {
1398 iterator->shadow_addr
1399 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1400 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1401 --iterator->level;
1402 if (!iterator->shadow_addr)
1403 iterator->level = 0;
1404 }
1405}
1406
1407static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1408{
1409 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1410 return false;
4d88954d
MT		 1411
1412 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1413 if (is_large_pte(*iterator->sptep))
1414 return false;
1415
2d11123a
AK		 1416 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1417 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1418 return true;
1419}
1420
1421static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1422{
1423 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1424 --iterator->level;
1425}
1426
90cb0529 1427static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1428 struct kvm_mmu_page *sp)
a436036b 1429{
697fe2e2
AK		 1430 unsigned i;
1431 u64 *pt;
1432 u64 ent;
1433
4db35314 1434 pt = sp->spt;
697fe2e2 1435
697fe2e2
AK		 1436 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1437 ent = pt[i];
1438
05da4558 1439 if (is_shadow_present_pte(ent)) {
776e6633 1440 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1441 ent &= PT64_BASE_ADDR_MASK;
1442 mmu_page_remove_parent_pte(page_header(ent),
1443 &pt[i]);
1444 } else {
776e6633
MT		 1445 if (is_large_pte(ent))
1446 --kvm->stat.lpages;
05da4558
MT		 1447 rmap_remove(kvm, &pt[i]);
1448 }
1449 }
c7addb90 1450 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1451 }
a436036b
AK		 1452}
1453
4db35314 1454static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1455{
4db35314 1456 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1457}
1458
12b7d28f
AK		 1459static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1460{
1461 int i;
988a2cae 1462 struct kvm_vcpu *vcpu;
12b7d28f 1463
988a2cae
GN		 1464 kvm_for_each_vcpu(i, vcpu, kvm)
1465 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1466}
1467
31aa2b44 1468static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1469{
1470 u64 *parent_pte;
1471
4db35314
AK		 1472 while (sp->multimapped || sp->parent_pte) {
1473 if (!sp->multimapped)
1474 parent_pte = sp->parent_pte;
a436036b
AK		 1475 else {
1476 struct kvm_pte_chain *chain;
1477
4db35314 1478 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1479 struct kvm_pte_chain, link);
1480 parent_pte = chain->parent_ptes[0];
1481 }
697fe2e2 1482 BUG_ON(!parent_pte);
4db35314 1483 kvm_mmu_put_page(sp, parent_pte);
d555c333 1484 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1485 }
31aa2b44
AK		 1486}
1487
60c8aec6
MT		 1488static int mmu_zap_unsync_children(struct kvm *kvm,
1489 struct kvm_mmu_page *parent)
4731d4c7 1490{
60c8aec6
MT		 1491 int i, zapped = 0;
1492 struct mmu_page_path parents;
1493 struct kvm_mmu_pages pages;
4731d4c7 1494
60c8aec6 1495 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1496 return 0;
60c8aec6
MT		 1497
1498 kvm_mmu_pages_init(parent, &parents, &pages);
1499 while (mmu_unsync_walk(parent, &pages)) {
1500 struct kvm_mmu_page *sp;
1501
1502 for_each_sp(pages, sp, parents, i) {
1503 kvm_mmu_zap_page(kvm, sp);
1504 mmu_pages_clear_parents(&parents);
1505 }
1506 zapped += pages.nr;
1507 kvm_mmu_pages_init(parent, &parents, &pages);
1508 }
1509
1510 return zapped;
4731d4c7
MT		 1511}
1512
07385413 1513static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1514{
4731d4c7 1515 int ret;
f691fe1d
AK		 1516
1517 trace_kvm_mmu_zap_page(sp);
31aa2b44 1518 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1519 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1520 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1521 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1522 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1523 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1524 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1525 if (sp->unsync)
1526 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1527 if (!sp->root_count) {
1528 hlist_del(&sp->hash_link);
1529 kvm_mmu_free_page(kvm, sp);
2e53d63a 1530 } else {
2e53d63a 1531 sp->role.invalid = 1;
5b5c6a5a 1532 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1533 kvm_reload_remote_mmus(kvm);
1534 }
12b7d28f 1535 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1536 return ret;
a436036b
AK		 1537}
1538
82ce2c96
IE		 1539/*
1540 * Changing the number of mmu pages allocated to the vm
1541 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1542 */
1543void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1544{
025dbbf3
MT		 1545 int used_pages;
1546
1547 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1548 used_pages = max(0, used_pages);
1549
82ce2c96
IE		 1550 /*
1551 * If we set the number of mmu pages to be smaller be than the
1552 * number of actived pages , we must to free some mmu pages before we
1553 * change the value
1554 */
1555
025dbbf3
MT		 1556 if (used_pages > kvm_nr_mmu_pages) {
1557 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1558 struct kvm_mmu_page *page;
1559
f05e70ac 1560 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1561 struct kvm_mmu_page, link);
1562 kvm_mmu_zap_page(kvm, page);
025dbbf3 1563 used_pages--;
82ce2c96 1564 }
f05e70ac 1565 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1566 }
1567 else
f05e70ac
ZX		 1568 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1569 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1570
f05e70ac 1571 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1572}
1573
f67a46f4 1574static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1575{
1576 unsigned index;
1577 struct hlist_head *bucket;
4db35314 1578 struct kvm_mmu_page *sp;
a436036b
AK		 1579 struct hlist_node *node, *n;
1580 int r;
1581
b8688d51 1582 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1583 r = 0;
1ae0a13d 1584 index = kvm_page_table_hashfn(gfn);
f05e70ac 1585 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1586 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1587 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1588 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1589 sp->role.word);
a436036b 1590 r = 1;
07385413
MT		 1591 if (kvm_mmu_zap_page(kvm, sp))
1592 n = bucket->first;
a436036b
AK		 1593 }
1594 return r;
cea0f0e7
AK		 1595}
1596
f67a46f4 1597static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1598{
4677a3b6
AK		 1599 unsigned index;
1600 struct hlist_head *bucket;
4db35314 1601 struct kvm_mmu_page *sp;
4677a3b6 1602 struct hlist_node *node, *nn;
97a0a01e 1603
4677a3b6
AK		 1604 index = kvm_page_table_hashfn(gfn);
1605 bucket = &kvm->arch.mmu_page_hash[index];
1606 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1607 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1608 && !sp->role.invalid) {
1609 pgprintk("%s: zap %lx %x\n",
1610 __func__, gfn, sp->role.word);
1611 kvm_mmu_zap_page(kvm, sp);
1612 }
97a0a01e
AK		 1613 }
1614}
1615
38c335f1 1616static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1617{
38c335f1 1618 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
4db35314 1619 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1620
291f26bc 1621 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1622}
1623
6844dec6
MT		 1624static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1625{
1626 int i;
1627 u64 *pt = sp->spt;
1628
1629 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1630 return;
1631
1632 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1633 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1634 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1635 }
1636}
1637
039576c0
AK		 1638struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1639{
72dc67a6
IE		 1640 struct page *page;
1641
ad312c7c 1642 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1643
1644 if (gpa == UNMAPPED_GVA)
1645 return NULL;
72dc67a6 1646
72dc67a6 1647 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1648
1649 return page;
039576c0
AK		 1650}
1651
74be52e3
SY		 1652/*
1653 * The function is based on mtrr_type_lookup() in
1654 * arch/x86/kernel/cpu/mtrr/generic.c
1655 */
1656static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1657 u64 start, u64 end)
1658{
1659 int i;
1660 u64 base, mask;
1661 u8 prev_match, curr_match;
1662 int num_var_ranges = KVM_NR_VAR_MTRR;
1663
1664 if (!mtrr_state->enabled)
1665 return 0xFF;
1666
1667 /* Make end inclusive end, instead of exclusive */
1668 end--;
1669
1670 /* Look in fixed ranges. Just return the type as per start */
1671 if (mtrr_state->have_fixed && (start < 0x100000)) {
1672 int idx;
1673
1674 if (start < 0x80000) {
1675 idx = 0;
1676 idx += (start >> 16);
1677 return mtrr_state->fixed_ranges[idx];
1678 } else if (start < 0xC0000) {
1679 idx = 1 * 8;
1680 idx += ((start - 0x80000) >> 14);
1681 return mtrr_state->fixed_ranges[idx];
1682 } else if (start < 0x1000000) {
1683 idx = 3 * 8;
1684 idx += ((start - 0xC0000) >> 12);
1685 return mtrr_state->fixed_ranges[idx];
1686 }
1687 }
1688
1689 /*
1690 * Look in variable ranges
1691 * Look of multiple ranges matching this address and pick type
1692 * as per MTRR precedence
1693 */
1694 if (!(mtrr_state->enabled & 2))
1695 return mtrr_state->def_type;
1696
1697 prev_match = 0xFF;
1698 for (i = 0; i < num_var_ranges; ++i) {
1699 unsigned short start_state, end_state;
1700
1701 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1702 continue;
1703
1704 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1705 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1706 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1707 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1708
1709 start_state = ((start & mask) == (base & mask));
1710 end_state = ((end & mask) == (base & mask));
1711 if (start_state != end_state)
1712 return 0xFE;
1713
1714 if ((start & mask) != (base & mask))
1715 continue;
1716
1717 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1718 if (prev_match == 0xFF) {
1719 prev_match = curr_match;
1720 continue;
1721 }
1722
1723 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1724 curr_match == MTRR_TYPE_UNCACHABLE)
1725 return MTRR_TYPE_UNCACHABLE;
1726
1727 if ((prev_match == MTRR_TYPE_WRBACK &&
1728 curr_match == MTRR_TYPE_WRTHROUGH) ||
1729 (prev_match == MTRR_TYPE_WRTHROUGH &&
1730 curr_match == MTRR_TYPE_WRBACK)) {
1731 prev_match = MTRR_TYPE_WRTHROUGH;
1732 curr_match = MTRR_TYPE_WRTHROUGH;
1733 }
1734
1735 if (prev_match != curr_match)
1736 return MTRR_TYPE_UNCACHABLE;
1737 }
1738
1739 if (prev_match != 0xFF)
1740 return prev_match;
1741
1742 return mtrr_state->def_type;
1743}
1744
4b12f0de 1745u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1746{
1747 u8 mtrr;
1748
1749 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1750 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1751 if (mtrr == 0xfe || mtrr == 0xff)
1752 mtrr = MTRR_TYPE_WRBACK;
1753 return mtrr;
1754}
4b12f0de 1755EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1756
4731d4c7
MT		 1757static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1758{
1759 unsigned index;
1760 struct hlist_head *bucket;
1761 struct kvm_mmu_page *s;
1762 struct hlist_node *node, *n;
1763
f691fe1d 1764 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1765 index = kvm_page_table_hashfn(sp->gfn);
1766 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1767 /* don't unsync if pagetable is shadowed with multiple roles */
1768 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1769 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1770 continue;
1771 if (s->role.word != sp->role.word)
1772 return 1;
1773 }
4731d4c7
MT		 1774 ++vcpu->kvm->stat.mmu_unsync;
1775 sp->unsync = 1;
6cffe8ca 1776
c2d0ee46 1777 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1778
4731d4c7
MT		 1779 mmu_convert_notrap(sp);
1780 return 0;
1781}
1782
1783static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1784 bool can_unsync)
1785{
1786 struct kvm_mmu_page *shadow;
1787
1788 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1789 if (shadow) {
1790 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1791 return 1;
1792 if (shadow->unsync)
1793 return 0;
582801a9 1794 if (can_unsync && oos_shadow)
4731d4c7
MT		 1795 return kvm_unsync_page(vcpu, shadow);
1796 return 1;
1797 }
1798 return 0;
1799}
1800
d555c333 1801static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1802 unsigned pte_access, int user_fault,
852e3c19 1803 int write_fault, int dirty, int level,
c2d0ee46 1804 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1805 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1806{
1807 u64 spte;
1e73f9dd 1808 int ret = 0;
64d4d521 1809
1c4f1fd6
AK		 1810 /*
1811 * We don't set the accessed bit, since we sometimes want to see
1812 * whether the guest actually used the pte (in order to detect
1813 * demand paging).
1814 */
7b52345e 1815 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1816 if (!speculative)
3201b5d9 1817 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1818 if (!dirty)
1819 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1820 if (pte_access & ACC_EXEC_MASK)
1821 spte |= shadow_x_mask;
1822 else
1823 spte |= shadow_nx_mask;
1c4f1fd6 1824 if (pte_access & ACC_USER_MASK)
7b52345e 1825 spte |= shadow_user_mask;
852e3c19 1826 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1827 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1828 if (tdp_enabled)
1829 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1830 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1831
1403283a
IE		 1832 if (reset_host_protection)
1833 spte |= SPTE_HOST_WRITEABLE;
1834
35149e21 1835 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1836
1837 if ((pte_access & ACC_WRITE_MASK)
1838 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1839
852e3c19
JR		 1840 if (level > PT_PAGE_TABLE_LEVEL &&
1841 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1842 ret = 1;
1843 spte = shadow_trap_nonpresent_pte;
1844 goto set_pte;
1845 }
1846
1c4f1fd6 1847 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1848
ecc5589f
MT		 1849 /*
1850 * Optimization: for pte sync, if spte was writable the hash
1851 * lookup is unnecessary (and expensive). Write protection
1852 * is responsibility of mmu_get_page / kvm_sync_page.
1853 * Same reasoning can be applied to dirty page accounting.
1854 */
d555c333 1855 if (!can_unsync && is_writeble_pte(*sptep))
ecc5589f
MT		 1856 goto set_pte;
1857
4731d4c7 1858 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1859 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1860 __func__, gfn);
1e73f9dd 1861 ret = 1;
1c4f1fd6 1862 pte_access &= ~ACC_WRITE_MASK;
a378b4e6 1863 if (is_writeble_pte(spte))
1c4f1fd6 1864 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1865 }
1866 }
1867
1c4f1fd6
AK		 1868 if (pte_access & ACC_WRITE_MASK)
1869 mark_page_dirty(vcpu->kvm, gfn);
1870
38187c83 1871set_pte:
d555c333 1872 __set_spte(sptep, spte);
1e73f9dd
MT		 1873 return ret;
1874}
1875
d555c333 1876static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1877 unsigned pt_access, unsigned pte_access,
1878 int user_fault, int write_fault, int dirty,
852e3c19 1879 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1880 pfn_t pfn, bool speculative,
1881 bool reset_host_protection)
1e73f9dd
MT		 1882{
1883 int was_rmapped = 0;
d555c333 1884 int was_writeble = is_writeble_pte(*sptep);
53a27b39 1885 int rmap_count;
1e73f9dd
MT		 1886
1887 pgprintk("%s: spte %llx access %x write_fault %d"
1888 " user_fault %d gfn %lx\n",
d555c333 1889 __func__, *sptep, pt_access,
1e73f9dd
MT		 1890 write_fault, user_fault, gfn);
1891
d555c333 1892 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1893 /*
1894 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1895 * the parent of the now unreachable PTE.
1896 */
852e3c19
JR		 1897 if (level > PT_PAGE_TABLE_LEVEL &&
1898 !is_large_pte(*sptep)) {
1e73f9dd 1899 struct kvm_mmu_page *child;
d555c333 1900 u64 pte = *sptep;
1e73f9dd
MT		 1901
1902 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1903 mmu_page_remove_parent_pte(child, sptep);
1904 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1905 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1906 spte_to_pfn(*sptep), pfn);
1907 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1908 } else
1909 was_rmapped = 1;
1e73f9dd 1910 }
852e3c19 1911
d555c333 1912 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1913 dirty, level, gfn, pfn, speculative, true,
1914 reset_host_protection)) {
1e73f9dd
MT		 1915 if (write_fault)
1916 *ptwrite = 1;
a378b4e6
MT		 1917 kvm_x86_ops->tlb_flush(vcpu);
1918 }
1e73f9dd 1919
d555c333 1920 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1921 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1922 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1923 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1924 *sptep, sptep);
d555c333 1925 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1926 ++vcpu->kvm->stat.lpages;
1927
d555c333 1928 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1929 if (!was_rmapped) {
44ad9944 1930 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1931 kvm_release_pfn_clean(pfn);
53a27b39 1932 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1933 rmap_recycle(vcpu, sptep, gfn);
75e68e60
IE		 1934 } else {
1935 if (was_writeble)
35149e21 1936 kvm_release_pfn_dirty(pfn);
75e68e60 1937 else
35149e21 1938 kvm_release_pfn_clean(pfn);
1c4f1fd6 1939 }
1b7fcd32 1940 if (speculative) {
d555c333 1941 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1942 vcpu->arch.last_pte_gfn = gfn;
1943 }
1c4f1fd6
AK		 1944}
1945
6aa8b732
AK		 1946static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1947{
1948}
1949
9f652d21 1950static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1951 int level, gfn_t gfn, pfn_t pfn)
140754bc 1952{
9f652d21 1953 struct kvm_shadow_walk_iterator iterator;
140754bc 1954 struct kvm_mmu_page *sp;
9f652d21 1955 int pt_write = 0;
140754bc 1956 gfn_t pseudo_gfn;
6aa8b732 1957
9f652d21 1958 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1959 if (iterator.level == level) {
9f652d21
AK		 1960 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1961 0, write, 1, &pt_write,
1403283a 1962 level, gfn, pfn, false, true);
9f652d21
AK		 1963 ++vcpu->stat.pf_fixed;
1964 break;
6aa8b732
AK		 1965 }
1966
9f652d21
AK		 1967 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1968 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1969 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1970 iterator.level - 1,
1971 1, ACC_ALL, iterator.sptep);
1972 if (!sp) {
1973 pgprintk("nonpaging_map: ENOMEM\n");
1974 kvm_release_pfn_clean(pfn);
1975 return -ENOMEM;
1976 }
140754bc 1977
d555c333
AK		 1978 __set_spte(iterator.sptep,
1979 __pa(sp->spt)
1980 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1981 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1982 }
1983 }
1984 return pt_write;
6aa8b732
AK		 1985}
1986
10589a46
MT		 1987static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1988{
1989 int r;
852e3c19 1990 int level;
35149e21 1991 pfn_t pfn;
e930bffe 1992 unsigned long mmu_seq;
aaee2c94 1993
852e3c19
JR		 1994 level = mapping_level(vcpu, gfn);
1995
1996 /*
1997 * This path builds a PAE pagetable - so we can map 2mb pages at
1998 * maximum. Therefore check if the level is larger than that.
1999 */
2000 if (level > PT_DIRECTORY_LEVEL)
2001 level = PT_DIRECTORY_LEVEL;
2002
2003 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2004
e930bffe 2005 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2006 smp_rmb();
35149e21 2007 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2008
d196e343 2009 /* mmio */
35149e21
AL		 2010 if (is_error_pfn(pfn)) {
2011 kvm_release_pfn_clean(pfn);
d196e343
AK		 2012 return 1;
2013 }
2014
aaee2c94 2015 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2016 if (mmu_notifier_retry(vcpu, mmu_seq))
2017 goto out_unlock;
eb787d10 2018 kvm_mmu_free_some_pages(vcpu);
852e3c19 2019 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2020 spin_unlock(&vcpu->kvm->mmu_lock);
2021
aaee2c94 2022
10589a46 2023 return r;
e930bffe
AA		 2024
2025out_unlock:
2026 spin_unlock(&vcpu->kvm->mmu_lock);
2027 kvm_release_pfn_clean(pfn);
2028 return 0;
10589a46
MT		 2029}
2030
2031
17ac10ad
AK		 2032static void mmu_free_roots(struct kvm_vcpu *vcpu)
2033{
2034 int i;
4db35314 2035 struct kvm_mmu_page *sp;
17ac10ad 2036
ad312c7c 2037 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2038 return;
aaee2c94 2039 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2040 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2041 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2042
4db35314
AK		 2043 sp = page_header(root);
2044 --sp->root_count;
2e53d63a
MT		 2045 if (!sp->root_count && sp->role.invalid)
2046 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2047 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2048 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2049 return;
2050 }
17ac10ad 2051 for (i = 0; i < 4; ++i) {
ad312c7c 2052 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2053
417726a3 2054 if (root) {
417726a3 2055 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2056 sp = page_header(root);
2057 --sp->root_count;
2e53d63a
MT		 2058 if (!sp->root_count && sp->role.invalid)
2059 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2060 }
ad312c7c 2061 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2062 }
aaee2c94 2063 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2064 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2065}
2066
8986ecc0
MT		 2067static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2068{
2069 int ret = 0;
2070
2071 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2072 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2073 ret = 1;
2074 }
2075
2076 return ret;
2077}
2078
2079static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2080{
2081 int i;
cea0f0e7 2082 gfn_t root_gfn;
4db35314 2083 struct kvm_mmu_page *sp;
f6e2c02b 2084 int direct = 0;
6de4f3ad 2085 u64 pdptr;
3bb65a22 2086
ad312c7c 2087 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2088
ad312c7c
ZX		 2089 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2090 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2091
2092 ASSERT(!VALID_PAGE(root));
fb72d167 2093 if (tdp_enabled)
f6e2c02b 2094 direct = 1;
8986ecc0
MT		 2095 if (mmu_check_root(vcpu, root_gfn))
2096 return 1;
4db35314 2097 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2098 PT64_ROOT_LEVEL, direct,
fb72d167 2099 ACC_ALL, NULL);
4db35314
AK		 2100 root = __pa(sp->spt);
2101 ++sp->root_count;
ad312c7c 2102 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2103 return 0;
17ac10ad 2104 }
f6e2c02b 2105 direct = !is_paging(vcpu);
fb72d167 2106 if (tdp_enabled)
f6e2c02b 2107 direct = 1;
17ac10ad 2108 for (i = 0; i < 4; ++i) {
ad312c7c 2109 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2110
2111 ASSERT(!VALID_PAGE(root));
ad312c7c 2112 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2113 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2114 if (!is_present_gpte(pdptr)) {
ad312c7c 2115 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2116 continue;
2117 }
6de4f3ad 2118 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2119 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2120 root_gfn = 0;
8986ecc0
MT		 2121 if (mmu_check_root(vcpu, root_gfn))
2122 return 1;
4db35314 2123 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2124 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2125 ACC_ALL, NULL);
4db35314
AK		 2126 root = __pa(sp->spt);
2127 ++sp->root_count;
ad312c7c 2128 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2129 }
ad312c7c 2130 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2131 return 0;
17ac10ad
AK		 2132}
2133
0ba73cda
MT		 2134static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2135{
2136 int i;
2137 struct kvm_mmu_page *sp;
2138
2139 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2140 return;
2141 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2142 hpa_t root = vcpu->arch.mmu.root_hpa;
2143 sp = page_header(root);
2144 mmu_sync_children(vcpu, sp);
2145 return;
2146 }
2147 for (i = 0; i < 4; ++i) {
2148 hpa_t root = vcpu->arch.mmu.pae_root[i];
2149
8986ecc0 2150 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2151 root &= PT64_BASE_ADDR_MASK;
2152 sp = page_header(root);
2153 mmu_sync_children(vcpu, sp);
2154 }
2155 }
2156}
2157
2158void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2159{
2160 spin_lock(&vcpu->kvm->mmu_lock);
2161 mmu_sync_roots(vcpu);
6cffe8ca 2162 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2163}
2164
6aa8b732
AK		 2165static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2166{
2167 return vaddr;
2168}
2169
2170static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2171 u32 error_code)
6aa8b732 2172{
e833240f 2173 gfn_t gfn;
e2dec939 2174 int r;
6aa8b732 2175
b8688d51 2176 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2177 r = mmu_topup_memory_caches(vcpu);
2178 if (r)
2179 return r;
714b93da 2180
6aa8b732 2181 ASSERT(vcpu);
ad312c7c 2182 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2183
e833240f 2184 gfn = gva >> PAGE_SHIFT;
6aa8b732 2185
e833240f
AK		 2186 return nonpaging_map(vcpu, gva & PAGE_MASK,
2187 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2188}
2189
fb72d167
JR		 2190static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2191 u32 error_code)
2192{
35149e21 2193 pfn_t pfn;
fb72d167 2194 int r;
852e3c19 2195 int level;
05da4558 2196 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2197 unsigned long mmu_seq;
fb72d167
JR		 2198
2199 ASSERT(vcpu);
2200 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2201
2202 r = mmu_topup_memory_caches(vcpu);
2203 if (r)
2204 return r;
2205
852e3c19
JR		 2206 level = mapping_level(vcpu, gfn);
2207
2208 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2209
e930bffe 2210 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2211 smp_rmb();
35149e21 2212 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2213 if (is_error_pfn(pfn)) {
2214 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2215 return 1;
2216 }
2217 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2218 if (mmu_notifier_retry(vcpu, mmu_seq))
2219 goto out_unlock;
fb72d167
JR		 2220 kvm_mmu_free_some_pages(vcpu);
2221 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2222 level, gfn, pfn);
fb72d167 2223 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2224
2225 return r;
e930bffe
AA		 2226
2227out_unlock:
2228 spin_unlock(&vcpu->kvm->mmu_lock);
2229 kvm_release_pfn_clean(pfn);
2230 return 0;
fb72d167
JR		 2231}
2232
6aa8b732
AK		 2233static void nonpaging_free(struct kvm_vcpu *vcpu)
2234{
17ac10ad 2235 mmu_free_roots(vcpu);
6aa8b732
AK		 2236}
2237
2238static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2239{
ad312c7c 2240 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2241
2242 context->new_cr3 = nonpaging_new_cr3;
2243 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2244 context->gva_to_gpa = nonpaging_gva_to_gpa;
2245 context->free = nonpaging_free;
c7addb90 2246 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2247 context->sync_page = nonpaging_sync_page;
a7052897 2248 context->invlpg = nonpaging_invlpg;
cea0f0e7 2249 context->root_level = 0;
6aa8b732 2250 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2251 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2252 return 0;
2253}
2254
d835dfec 2255void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2256{
1165f5fe 2257 ++vcpu->stat.tlb_flush;
cbdd1bea 2258 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2259}
2260
2261static void paging_new_cr3(struct kvm_vcpu *vcpu)
2262{
b8688d51 2263 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2264 mmu_free_roots(vcpu);
6aa8b732
AK		 2265}
2266
6aa8b732
AK		 2267static void inject_page_fault(struct kvm_vcpu *vcpu,
2268 u64 addr,
2269 u32 err_code)
2270{
c3c91fee 2271 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2272}
2273
6aa8b732
AK		 2274static void paging_free(struct kvm_vcpu *vcpu)
2275{
2276 nonpaging_free(vcpu);
2277}
2278
82725b20
DE		 2279static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2280{
2281 int bit7;
2282
2283 bit7 = (gpte >> 7) & 1;
2284 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2285}
2286
6aa8b732
AK		 2287#define PTTYPE 64
2288#include "paging_tmpl.h"
2289#undef PTTYPE
2290
2291#define PTTYPE 32
2292#include "paging_tmpl.h"
2293#undef PTTYPE
2294
82725b20
DE		 2295static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2296{
2297 struct kvm_mmu *context = &vcpu->arch.mmu;
2298 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2299 u64 exb_bit_rsvd = 0;
2300
2301 if (!is_nx(vcpu))
2302 exb_bit_rsvd = rsvd_bits(63, 63);
2303 switch (level) {
2304 case PT32_ROOT_LEVEL:
2305 /* no rsvd bits for 2 level 4K page table entries */
2306 context->rsvd_bits_mask[0][1] = 0;
2307 context->rsvd_bits_mask[0][0] = 0;
2308 if (is_cpuid_PSE36())
2309 /* 36bits PSE 4MB page */
2310 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2311 else
2312 /* 32 bits PSE 4MB page */
2313 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2314 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2315 break;
2316 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2317 context->rsvd_bits_mask[0][2] =
2318 rsvd_bits(maxphyaddr, 63) |
2319 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2320 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2321 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2322 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2323 rsvd_bits(maxphyaddr, 62); /* PTE */
2324 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2325 rsvd_bits(maxphyaddr, 62) |
2326 rsvd_bits(13, 20); /* large page */
29a4b933 2327 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2328 break;
2329 case PT64_ROOT_LEVEL:
2330 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2331 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2332 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2333 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2334 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2335 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2336 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2337 rsvd_bits(maxphyaddr, 51);
2338 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2339 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2340 rsvd_bits(maxphyaddr, 51) |
2341 rsvd_bits(13, 29);
82725b20 2342 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2343 rsvd_bits(maxphyaddr, 51) |
2344 rsvd_bits(13, 20); /* large page */
29a4b933 2345 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2346 break;
2347 }
2348}
2349
17ac10ad 2350static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2351{
ad312c7c 2352 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2353
2354 ASSERT(is_pae(vcpu));
2355 context->new_cr3 = paging_new_cr3;
2356 context->page_fault = paging64_page_fault;
6aa8b732 2357 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2358 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2359 context->sync_page = paging64_sync_page;
a7052897 2360 context->invlpg = paging64_invlpg;
6aa8b732 2361 context->free = paging_free;
17ac10ad
AK		 2362 context->root_level = level;
2363 context->shadow_root_level = level;
17c3ba9d 2364 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2365 return 0;
2366}
2367
17ac10ad
AK		 2368static int paging64_init_context(struct kvm_vcpu *vcpu)
2369{
82725b20 2370 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2371 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2372}
2373
6aa8b732
AK		 2374static int paging32_init_context(struct kvm_vcpu *vcpu)
2375{
ad312c7c 2376 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2377
82725b20 2378 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2379 context->new_cr3 = paging_new_cr3;
2380 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2381 context->gva_to_gpa = paging32_gva_to_gpa;
2382 context->free = paging_free;
c7addb90 2383 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2384 context->sync_page = paging32_sync_page;
a7052897 2385 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2386 context->root_level = PT32_ROOT_LEVEL;
2387 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2388 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2389 return 0;
2390}
2391
2392static int paging32E_init_context(struct kvm_vcpu *vcpu)
2393{
82725b20 2394 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2395 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2396}
2397
fb72d167
JR		 2398static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2399{
2400 struct kvm_mmu *context = &vcpu->arch.mmu;
2401
2402 context->new_cr3 = nonpaging_new_cr3;
2403 context->page_fault = tdp_page_fault;
2404 context->free = nonpaging_free;
2405 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2406 context->sync_page = nonpaging_sync_page;
a7052897 2407 context->invlpg = nonpaging_invlpg;
67253af5 2408 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2409 context->root_hpa = INVALID_PAGE;
2410
2411 if (!is_paging(vcpu)) {
2412 context->gva_to_gpa = nonpaging_gva_to_gpa;
2413 context->root_level = 0;
2414 } else if (is_long_mode(vcpu)) {
82725b20 2415 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2416 context->gva_to_gpa = paging64_gva_to_gpa;
2417 context->root_level = PT64_ROOT_LEVEL;
2418 } else if (is_pae(vcpu)) {
82725b20 2419 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2420 context->gva_to_gpa = paging64_gva_to_gpa;
2421 context->root_level = PT32E_ROOT_LEVEL;
2422 } else {
82725b20 2423 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2424 context->gva_to_gpa = paging32_gva_to_gpa;
2425 context->root_level = PT32_ROOT_LEVEL;
2426 }
2427
2428 return 0;
2429}
2430
2431static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2432{
a770f6f2
AK		 2433 int r;
2434
6aa8b732 2435 ASSERT(vcpu);
ad312c7c 2436 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2437
2438 if (!is_paging(vcpu))
a770f6f2 2439 r = nonpaging_init_context(vcpu);
a9058ecd 2440 else if (is_long_mode(vcpu))
a770f6f2 2441 r = paging64_init_context(vcpu);
6aa8b732 2442 else if (is_pae(vcpu))
a770f6f2 2443 r = paging32E_init_context(vcpu);
6aa8b732 2444 else
a770f6f2
AK		 2445 r = paging32_init_context(vcpu);
2446
2447 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2448
2449 return r;
6aa8b732
AK		 2450}
2451
fb72d167
JR		 2452static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2453{
35149e21
AL		 2454 vcpu->arch.update_pte.pfn = bad_pfn;
2455
fb72d167
JR		 2456 if (tdp_enabled)
2457 return init_kvm_tdp_mmu(vcpu);
2458 else
2459 return init_kvm_softmmu(vcpu);
2460}
2461
6aa8b732
AK		 2462static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2463{
2464 ASSERT(vcpu);
ad312c7c
ZX		 2465 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2466 vcpu->arch.mmu.free(vcpu);
2467 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2468 }
2469}
2470
2471int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2472{
2473 destroy_kvm_mmu(vcpu);
2474 return init_kvm_mmu(vcpu);
2475}
8668a3c4 2476EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2477
2478int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2479{
714b93da
AK		 2480 int r;
2481
e2dec939 2482 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2483 if (r)
2484 goto out;
aaee2c94 2485 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2486 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2487 r = mmu_alloc_roots(vcpu);
0ba73cda 2488 mmu_sync_roots(vcpu);
aaee2c94 2489 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2490 if (r)
2491 goto out;
3662cb1c 2492 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2493 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2494out:
2495 return r;
6aa8b732 2496}
17c3ba9d
AK		 2497EXPORT_SYMBOL_GPL(kvm_mmu_load);
2498
2499void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2500{
2501 mmu_free_roots(vcpu);
2502}
6aa8b732 2503
09072daf 2504static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2505 struct kvm_mmu_page *sp,
ac1b714e
AK		 2506 u64 *spte)
2507{
2508 u64 pte;
2509 struct kvm_mmu_page *child;
2510
2511 pte = *spte;
c7addb90 2512 if (is_shadow_present_pte(pte)) {
776e6633 2513 if (is_last_spte(pte, sp->role.level))
290fc38d 2514 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2515 else {
2516 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2517 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2518 }
2519 }
d555c333 2520 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2521 if (is_large_pte(pte))
2522 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2523}
2524
0028425f 2525static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2526 struct kvm_mmu_page *sp,
0028425f 2527 u64 *spte,
489f1d65 2528 const void *new)
0028425f 2529{
30945387 2530 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2531 ++vcpu->kvm->stat.mmu_pde_zapped;
2532 return;
30945387 2533 }
0028425f 2534
4cee5764 2535 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2536 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2537 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2538 else
489f1d65 2539 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2540}
2541
79539cec
AK		 2542static bool need_remote_flush(u64 old, u64 new)
2543{
2544 if (!is_shadow_present_pte(old))
2545 return false;
2546 if (!is_shadow_present_pte(new))
2547 return true;
2548 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2549 return true;
2550 old ^= PT64_NX_MASK;
2551 new ^= PT64_NX_MASK;
2552 return (old & ~new & PT64_PERM_MASK) != 0;
2553}
2554
2555static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2556{
2557 if (need_remote_flush(old, new))
2558 kvm_flush_remote_tlbs(vcpu->kvm);
2559 else
2560 kvm_mmu_flush_tlb(vcpu);
2561}
2562
12b7d28f
AK		 2563static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2564{
ad312c7c 2565 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2566
7b52345e 2567 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2568}
2569
d7824fff
AK		 2570static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2571 const u8 *new, int bytes)
2572{
2573 gfn_t gfn;
2574 int r;
2575 u64 gpte = 0;
35149e21 2576 pfn_t pfn;
d7824fff
AK		 2577
2578 if (bytes != 4 && bytes != 8)
2579 return;
2580
2581 /*
2582 * Assume that the pte write on a page table of the same type
2583 * as the current vcpu paging mode. This is nearly always true
2584 * (might be false while changing modes). Note it is verified later
2585 * by update_pte().
2586 */
2587 if (is_pae(vcpu)) {
2588 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2589 if ((bytes == 4) && (gpa % 4 == 0)) {
2590 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2591 if (r)
2592 return;
2593 memcpy((void *)&gpte + (gpa % 8), new, 4);
2594 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2595 memcpy((void *)&gpte, new, 8);
2596 }
2597 } else {
2598 if ((bytes == 4) && (gpa % 4 == 0))
2599 memcpy((void *)&gpte, new, 4);
2600 }
43a3795a 2601 if (!is_present_gpte(gpte))
d7824fff
AK		 2602 return;
2603 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2604
e930bffe 2605 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2606 smp_rmb();
35149e21 2607 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2608
35149e21
AL		 2609 if (is_error_pfn(pfn)) {
2610 kvm_release_pfn_clean(pfn);
d196e343
AK		 2611 return;
2612 }
d7824fff 2613 vcpu->arch.update_pte.gfn = gfn;
35149e21 2614 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2615}
2616
1b7fcd32
AK		 2617static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2618{
2619 u64 *spte = vcpu->arch.last_pte_updated;
2620
2621 if (spte
2622 && vcpu->arch.last_pte_gfn == gfn
2623 && shadow_accessed_mask
2624 && !(*spte & shadow_accessed_mask)
2625 && is_shadow_present_pte(*spte))
2626 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2627}
2628
09072daf 2629void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2630 const u8 *new, int bytes,
2631 bool guest_initiated)
da4a00f0 2632{
9b7a0325 2633 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2634 struct kvm_mmu_page *sp;
0e7bc4b9 2635 struct hlist_node *node, *n;
9b7a0325
AK		 2636 struct hlist_head *bucket;
2637 unsigned index;
489f1d65 2638 u64 entry, gentry;
9b7a0325 2639 u64 *spte;
9b7a0325 2640 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2641 unsigned pte_size;
9b7a0325 2642 unsigned page_offset;
0e7bc4b9 2643 unsigned misaligned;
fce0657f 2644 unsigned quadrant;
9b7a0325 2645 int level;
86a5ba02 2646 int flooded = 0;
ac1b714e 2647 int npte;
489f1d65 2648 int r;
9b7a0325 2649
b8688d51 2650 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2651 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2652 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2653 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2654 kvm_mmu_free_some_pages(vcpu);
4cee5764 2655 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2656 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2657 if (guest_initiated) {
2658 if (gfn == vcpu->arch.last_pt_write_gfn
2659 && !last_updated_pte_accessed(vcpu)) {
2660 ++vcpu->arch.last_pt_write_count;
2661 if (vcpu->arch.last_pt_write_count >= 3)
2662 flooded = 1;
2663 } else {
2664 vcpu->arch.last_pt_write_gfn = gfn;
2665 vcpu->arch.last_pt_write_count = 1;
2666 vcpu->arch.last_pte_updated = NULL;
2667 }
86a5ba02 2668 }
1ae0a13d 2669 index = kvm_page_table_hashfn(gfn);
f05e70ac 2670 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2671 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2672 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2673 continue;
4db35314 2674 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2675 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2676 misaligned |= bytes < 4;
86a5ba02 2677 if (misaligned || flooded) {
0e7bc4b9
AK		 2678 /*
2679 * Misaligned accesses are too much trouble to fix
2680 * up; also, they usually indicate a page is not used
2681 * as a page table.
86a5ba02
AK		 2682 *
2683 * If we're seeing too many writes to a page,
2684 * it may no longer be a page table, or we may be
2685 * forking, in which case it is better to unmap the
2686 * page.
0e7bc4b9
AK		 2687 */
2688 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2689 gpa, bytes, sp->role.word);
07385413
MT		 2690 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2691 n = bucket->first;
4cee5764 2692 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2693 continue;
2694 }
9b7a0325 2695 page_offset = offset;
4db35314 2696 level = sp->role.level;
ac1b714e 2697 npte = 1;
4db35314 2698 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2699 page_offset <<= 1; /* 32->64 */
2700 /*
2701 * A 32-bit pde maps 4MB while the shadow pdes map
2702 * only 2MB. So we need to double the offset again
2703 * and zap two pdes instead of one.
2704 */
2705 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2706 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2707 page_offset <<= 1;
2708 npte = 2;
2709 }
fce0657f 2710 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2711 page_offset &= ~PAGE_MASK;
4db35314 2712 if (quadrant != sp->role.quadrant)
fce0657f 2713 continue;
9b7a0325 2714 }
4db35314 2715 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2716 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2717 gentry = 0;
2718 r = kvm_read_guest_atomic(vcpu->kvm,
2719 gpa & ~(u64)(pte_size - 1),
2720 &gentry, pte_size);
2721 new = (const void *)&gentry;
2722 if (r < 0)
2723 new = NULL;
2724 }
ac1b714e 2725 while (npte--) {
79539cec 2726 entry = *spte;
4db35314 2727 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2728 if (new)
2729 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2730 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2731 ++spte;
9b7a0325 2732 }
9b7a0325 2733 }
c7addb90 2734 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2735 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2736 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2737 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2738 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2739 }
da4a00f0
AK		 2740}
2741
a436036b
AK		 2742int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2743{
10589a46
MT		 2744 gpa_t gpa;
2745 int r;
a436036b 2746
60f24784
AK		 2747 if (tdp_enabled)
2748 return 0;
2749
10589a46 2750 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2751
aaee2c94 2752 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2753 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2754 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2755 return r;
a436036b 2756}
577bdc49 2757EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2758
22d95b12 2759void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2760{
3b80fffe
IE		 2761 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2762 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2763 struct kvm_mmu_page *sp;
ebeace86 2764
f05e70ac 2765 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2766 struct kvm_mmu_page, link);
2767 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2768 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2769 }
2770}
ebeace86 2771
3067714c
AK		 2772int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2773{
2774 int r;
2775 enum emulation_result er;
2776
ad312c7c 2777 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2778 if (r < 0)
2779 goto out;
2780
2781 if (!r) {
2782 r = 1;
2783 goto out;
2784 }
2785
b733bfb5
AK		 2786 r = mmu_topup_memory_caches(vcpu);
2787 if (r)
2788 goto out;
2789
851ba692 2790 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2791
2792 switch (er) {
2793 case EMULATE_DONE:
2794 return 1;
2795 case EMULATE_DO_MMIO:
2796 ++vcpu->stat.mmio_exits;
2797 return 0;
2798 case EMULATE_FAIL:
3f5d18a9
AK		 2799 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2800 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2801 vcpu->run->internal.ndata = 0;
3f5d18a9 2802 return 0;
3067714c
AK		 2803 default:
2804 BUG();
2805 }
2806out:
3067714c
AK		 2807 return r;
2808}
2809EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2810
a7052897
MT		 2811void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2812{
a7052897 2813 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2814 kvm_mmu_flush_tlb(vcpu);
2815 ++vcpu->stat.invlpg;
2816}
2817EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2818
18552672
JR		 2819void kvm_enable_tdp(void)
2820{
2821 tdp_enabled = true;
2822}
2823EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2824
5f4cb662
JR		 2825void kvm_disable_tdp(void)
2826{
2827 tdp_enabled = false;
2828}
2829EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2830
6aa8b732
AK		 2831static void free_mmu_pages(struct kvm_vcpu *vcpu)
2832{
ad312c7c 2833 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2834}
2835
2836static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2837{
17ac10ad 2838 struct page *page;
6aa8b732
AK		 2839 int i;
2840
2841 ASSERT(vcpu);
2842
17ac10ad
AK		 2843 /*
2844 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2845 * Therefore we need to allocate shadow page tables in the first
2846 * 4GB of memory, which happens to fit the DMA32 zone.
2847 */
2848 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2849 if (!page)
2850 goto error_1;
ad312c7c 2851 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2852 for (i = 0; i < 4; ++i)
ad312c7c 2853 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2854
6aa8b732
AK		 2855 return 0;
2856
2857error_1:
2858 free_mmu_pages(vcpu);
2859 return -ENOMEM;
2860}
2861
8018c27b 2862int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2863{
6aa8b732 2864 ASSERT(vcpu);
ad312c7c 2865 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2866
8018c27b
IM		 2867 return alloc_mmu_pages(vcpu);
2868}
6aa8b732 2869
8018c27b
IM		 2870int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2871{
2872 ASSERT(vcpu);
ad312c7c 2873 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2874
8018c27b 2875 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2876}
2877
2878void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2879{
2880 ASSERT(vcpu);
2881
2882 destroy_kvm_mmu(vcpu);
2883 free_mmu_pages(vcpu);
714b93da 2884 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2885}
2886
90cb0529 2887void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2888{
4db35314 2889 struct kvm_mmu_page *sp;
6aa8b732 2890
f05e70ac 2891 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2892 int i;
2893 u64 *pt;
2894
291f26bc 2895 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2896 continue;
2897
4db35314 2898 pt = sp->spt;
6aa8b732
AK		 2899 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2900 /* avoid RMW */
9647c14c 2901 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2902 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2903 }
171d595d 2904 kvm_flush_remote_tlbs(kvm);
6aa8b732 2905}
37a7d8b0 2906
90cb0529 2907void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2908{
4db35314 2909 struct kvm_mmu_page *sp, *node;
e0fa826f 2910
aaee2c94 2911 spin_lock(&kvm->mmu_lock);
f05e70ac 2912 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2913 if (kvm_mmu_zap_page(kvm, sp))
2914 node = container_of(kvm->arch.active_mmu_pages.next,
2915 struct kvm_mmu_page, link);
aaee2c94 2916 spin_unlock(&kvm->mmu_lock);
e0fa826f 2917
90cb0529 2918 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2919}
2920
8b2cf73c 2921static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2922{
2923 struct kvm_mmu_page *page;
2924
2925 page = container_of(kvm->arch.active_mmu_pages.prev,
2926 struct kvm_mmu_page, link);
2927 kvm_mmu_zap_page(kvm, page);
2928}
2929
2930static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2931{
2932 struct kvm *kvm;
2933 struct kvm *kvm_freed = NULL;
2934 int cache_count = 0;
2935
2936 spin_lock(&kvm_lock);
2937
2938 list_for_each_entry(kvm, &vm_list, vm_list) {
2939 int npages;
2940
5a4c9288
MT		 2941 if (!down_read_trylock(&kvm->slots_lock))
2942 continue;
3ee16c81
IE		 2943 spin_lock(&kvm->mmu_lock);
2944 npages = kvm->arch.n_alloc_mmu_pages -
2945 kvm->arch.n_free_mmu_pages;
2946 cache_count += npages;
2947 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2948 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2949 cache_count--;
2950 kvm_freed = kvm;
2951 }
2952 nr_to_scan--;
2953
2954 spin_unlock(&kvm->mmu_lock);
5a4c9288 2955 up_read(&kvm->slots_lock);
3ee16c81
IE		 2956 }
2957 if (kvm_freed)
2958 list_move_tail(&kvm_freed->vm_list, &vm_list);
2959
2960 spin_unlock(&kvm_lock);
2961
2962 return cache_count;
2963}
2964
2965static struct shrinker mmu_shrinker = {
2966 .shrink = mmu_shrink,
2967 .seeks = DEFAULT_SEEKS * 10,
2968};
2969
2ddfd20e 2970static void mmu_destroy_caches(void)
b5a33a75
AK		 2971{
2972 if (pte_chain_cache)
2973 kmem_cache_destroy(pte_chain_cache);
2974 if (rmap_desc_cache)
2975 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2976 if (mmu_page_header_cache)
2977 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2978}
2979
3ee16c81
IE		 2980void kvm_mmu_module_exit(void)
2981{
2982 mmu_destroy_caches();
2983 unregister_shrinker(&mmu_shrinker);
2984}
2985
b5a33a75
AK		 2986int kvm_mmu_module_init(void)
2987{
2988 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2989 sizeof(struct kvm_pte_chain),
20c2df83 2990 0, 0, NULL);
b5a33a75
AK		 2991 if (!pte_chain_cache)
2992 goto nomem;
2993 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2994 sizeof(struct kvm_rmap_desc),
20c2df83 2995 0, 0, NULL);
b5a33a75
AK		 2996 if (!rmap_desc_cache)
2997 goto nomem;
2998
d3d25b04
AK		 2999 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3000 sizeof(struct kvm_mmu_page),
20c2df83 3001 0, 0, NULL);
d3d25b04
AK		 3002 if (!mmu_page_header_cache)
3003 goto nomem;
3004
3ee16c81
IE		 3005 register_shrinker(&mmu_shrinker);
3006
b5a33a75
AK		 3007 return 0;
3008
3009nomem:
3ee16c81 3010 mmu_destroy_caches();
b5a33a75
AK		 3011 return -ENOMEM;
3012}
3013
3ad82a7e
ZX		 3014/*
3015 * Caculate mmu pages needed for kvm.
3016 */
3017unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3018{
3019 int i;
3020 unsigned int nr_mmu_pages;
3021 unsigned int nr_pages = 0;
3022
3023 for (i = 0; i < kvm->nmemslots; i++)
3024 nr_pages += kvm->memslots[i].npages;
3025
3026 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3027 nr_mmu_pages = max(nr_mmu_pages,
3028 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3029
3030 return nr_mmu_pages;
3031}
3032
2f333bcb
MT		 3033static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3034 unsigned len)
3035{
3036 if (len > buffer->len)
3037 return NULL;
3038 return buffer->ptr;
3039}
3040
3041static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3042 unsigned len)
3043{
3044 void *ret;
3045
3046 ret = pv_mmu_peek_buffer(buffer, len);
3047 if (!ret)
3048 return ret;
3049 buffer->ptr += len;
3050 buffer->len -= len;
3051 buffer->processed += len;
3052 return ret;
3053}
3054
3055static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3056 gpa_t addr, gpa_t value)
3057{
3058 int bytes = 8;
3059 int r;
3060
3061 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3062 bytes = 4;
3063
3064 r = mmu_topup_memory_caches(vcpu);
3065 if (r)
3066 return r;
3067
3200f405 3068 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3069 return -EFAULT;
3070
3071 return 1;
3072}
3073
3074static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3075{
a8cd0244 3076 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3077 return 1;
3078}
3079
3080static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3081{
3082 spin_lock(&vcpu->kvm->mmu_lock);
3083 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3084 spin_unlock(&vcpu->kvm->mmu_lock);
3085 return 1;
3086}
3087
3088static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3089 struct kvm_pv_mmu_op_buffer *buffer)
3090{
3091 struct kvm_mmu_op_header *header;
3092
3093 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3094 if (!header)
3095 return 0;
3096 switch (header->op) {
3097 case KVM_MMU_OP_WRITE_PTE: {
3098 struct kvm_mmu_op_write_pte *wpte;
3099
3100 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3101 if (!wpte)
3102 return 0;
3103 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3104 wpte->pte_val);
3105 }
3106 case KVM_MMU_OP_FLUSH_TLB: {
3107 struct kvm_mmu_op_flush_tlb *ftlb;
3108
3109 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3110 if (!ftlb)
3111 return 0;
3112 return kvm_pv_mmu_flush_tlb(vcpu);
3113 }
3114 case KVM_MMU_OP_RELEASE_PT: {
3115 struct kvm_mmu_op_release_pt *rpt;
3116
3117 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3118 if (!rpt)
3119 return 0;
3120 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3121 }
3122 default: return 0;
3123 }
3124}
3125
3126int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3127 gpa_t addr, unsigned long *ret)
3128{
3129 int r;
6ad18fba 3130 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3131
6ad18fba
DH		 3132 buffer->ptr = buffer->buf;
3133 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3134 buffer->processed = 0;
2f333bcb 3135
6ad18fba 3136 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3137 if (r)
3138 goto out;
3139
6ad18fba
DH		 3140 while (buffer->len) {
3141 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3142 if (r < 0)
3143 goto out;
3144 if (r == 0)
3145 break;
3146 }
3147
3148 r = 1;
3149out:
6ad18fba 3150 *ret = buffer->processed;
2f333bcb
MT		 3151 return r;
3152}
3153
94d8b056
MT		 3154int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3155{
3156 struct kvm_shadow_walk_iterator iterator;
3157 int nr_sptes = 0;
3158
3159 spin_lock(&vcpu->kvm->mmu_lock);
3160 for_each_shadow_entry(vcpu, addr, iterator) {
3161 sptes[iterator.level-1] = *iterator.sptep;
3162 nr_sptes++;
3163 if (!is_shadow_present_pte(*iterator.sptep))
3164 break;
3165 }
3166 spin_unlock(&vcpu->kvm->mmu_lock);
3167
3168 return nr_sptes;
3169}
3170EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3171
37a7d8b0
AK		 3172#ifdef AUDIT
3173
3174static const char *audit_msg;
3175
3176static gva_t canonicalize(gva_t gva)
3177{
3178#ifdef CONFIG_X86_64
3179 gva = (long long)(gva << 16) >> 16;
3180#endif
3181 return gva;
3182}
3183
08a3732b
MT		 3184
3185typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3186 u64 *sptep);
3187
3188static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3189 inspect_spte_fn fn)
3190{
3191 int i;
3192
3193 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3194 u64 ent = sp->spt[i];
3195
3196 if (is_shadow_present_pte(ent)) {
2920d728 3197 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3198 struct kvm_mmu_page *child;
3199 child = page_header(ent & PT64_BASE_ADDR_MASK);
3200 __mmu_spte_walk(kvm, child, fn);
2920d728 3201 } else
08a3732b
MT		 3202 fn(kvm, sp, &sp->spt[i]);
3203 }
3204 }
3205}
3206
3207static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3208{
3209 int i;
3210 struct kvm_mmu_page *sp;
3211
3212 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3213 return;
3214 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3215 hpa_t root = vcpu->arch.mmu.root_hpa;
3216 sp = page_header(root);
3217 __mmu_spte_walk(vcpu->kvm, sp, fn);
3218 return;
3219 }
3220 for (i = 0; i < 4; ++i) {
3221 hpa_t root = vcpu->arch.mmu.pae_root[i];
3222
3223 if (root && VALID_PAGE(root)) {
3224 root &= PT64_BASE_ADDR_MASK;
3225 sp = page_header(root);
3226 __mmu_spte_walk(vcpu->kvm, sp, fn);
3227 }
3228 }
3229 return;
3230}
3231
37a7d8b0
AK		 3232static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3233 gva_t va, int level)
3234{
3235 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3236 int i;
3237 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3238
3239 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3240 u64 ent = pt[i];
3241
c7addb90 3242 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3243 continue;
3244
3245 va = canonicalize(va);
2920d728
MT		 3246 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3247 audit_mappings_page(vcpu, ent, va, level - 1);
3248 else {
ad312c7c 3249 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3250 gfn_t gfn = gpa >> PAGE_SHIFT;
3251 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3252 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3253
2aaf65e8
MT		 3254 if (is_error_pfn(pfn)) {
3255 kvm_release_pfn_clean(pfn);
3256 continue;
3257 }
3258
c7addb90 3259 if (is_shadow_present_pte(ent)
37a7d8b0 3260 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3261 printk(KERN_ERR "xx audit error: (%s) levels %d"
3262 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3263 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3264 va, gpa, hpa, ent,
3265 is_shadow_present_pte(ent));
c7addb90
AK		 3266 else if (ent == shadow_notrap_nonpresent_pte
3267 && !is_error_hpa(hpa))
3268 printk(KERN_ERR "audit: (%s) notrap shadow,"
3269 " valid guest gva %lx\n", audit_msg, va);
35149e21 3270 kvm_release_pfn_clean(pfn);
c7addb90 3271
37a7d8b0
AK		 3272 }
3273 }
3274}
3275
3276static void audit_mappings(struct kvm_vcpu *vcpu)
3277{
1ea252af 3278 unsigned i;
37a7d8b0 3279
ad312c7c
ZX		 3280 if (vcpu->arch.mmu.root_level == 4)
3281 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3282 else
3283 for (i = 0; i < 4; ++i)
ad312c7c 3284 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3285 audit_mappings_page(vcpu,
ad312c7c 3286 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3287 i << 30,
3288 2);
3289}
3290
3291static int count_rmaps(struct kvm_vcpu *vcpu)
3292{
3293 int nmaps = 0;
3294 int i, j, k;
3295
3296 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3297 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
3298 struct kvm_rmap_desc *d;
3299
3300 for (j = 0; j < m->npages; ++j) {
290fc38d 3301 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3302
290fc38d 3303 if (!*rmapp)
37a7d8b0 3304 continue;
290fc38d 3305 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3306 ++nmaps;
3307 continue;
3308 }
290fc38d 3309 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3310 while (d) {
3311 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3312 if (d->sptes[k])
37a7d8b0
AK		 3313 ++nmaps;
3314 else
3315 break;
3316 d = d->more;
3317 }
3318 }
3319 }
3320 return nmaps;
3321}
3322
08a3732b
MT		 3323void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3324{
3325 unsigned long *rmapp;
3326 struct kvm_mmu_page *rev_sp;
3327 gfn_t gfn;
3328
3329 if (*sptep & PT_WRITABLE_MASK) {
3330 rev_sp = page_header(__pa(sptep));
3331 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3332
3333 if (!gfn_to_memslot(kvm, gfn)) {
3334 if (!printk_ratelimit())
3335 return;
3336 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3337 audit_msg, gfn);
3338 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3339 audit_msg, sptep - rev_sp->spt,
3340 rev_sp->gfn);
3341 dump_stack();
3342 return;
3343 }
3344
2920d728
MT		 3345 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3346 is_large_pte(*sptep));
08a3732b
MT		 3347 if (!*rmapp) {
3348 if (!printk_ratelimit())
3349 return;
3350 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3351 audit_msg, *sptep);
3352 dump_stack();
3353 }
3354 }
3355
3356}
3357
3358void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3359{
3360 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3361}
3362
3363static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3364{
4db35314 3365 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3366 int i;
3367
f05e70ac 3368 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3369 u64 *pt = sp->spt;
37a7d8b0 3370
4db35314 3371 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3372 continue;
3373
3374 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3375 u64 ent = pt[i];
3376
3377 if (!(ent & PT_PRESENT_MASK))
3378 continue;
3379 if (!(ent & PT_WRITABLE_MASK))
3380 continue;
08a3732b 3381 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3382 }
3383 }
08a3732b 3384 return;
37a7d8b0
AK		 3385}
3386
3387static void audit_rmap(struct kvm_vcpu *vcpu)
3388{
08a3732b
MT		 3389 check_writable_mappings_rmap(vcpu);
3390 count_rmaps(vcpu);
37a7d8b0
AK		 3391}
3392
3393static void audit_write_protection(struct kvm_vcpu *vcpu)
3394{
4db35314 3395 struct kvm_mmu_page *sp;
290fc38d
IE		 3396 struct kvm_memory_slot *slot;
3397 unsigned long *rmapp;
e58b0f9e 3398 u64 *spte;
290fc38d 3399 gfn_t gfn;
37a7d8b0 3400
f05e70ac 3401 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3402 if (sp->role.direct)
37a7d8b0 3403 continue;
e58b0f9e
MT		 3404 if (sp->unsync)
3405 continue;
37a7d8b0 3406
4db35314 3407 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3408 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3409 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3410
3411 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3412 while (spte) {
3413 if (*spte & PT_WRITABLE_MASK)
3414 printk(KERN_ERR "%s: (%s) shadow page has "
3415 "writable mappings: gfn %lx role %x\n",
b8688d51 3416 __func__, audit_msg, sp->gfn,
4db35314 3417 sp->role.word);
e58b0f9e
MT		 3418 spte = rmap_next(vcpu->kvm, rmapp, spte);
3419 }
37a7d8b0
AK		 3420 }
3421}
3422
3423static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3424{
3425 int olddbg = dbg;
3426
3427 dbg = 0;
3428 audit_msg = msg;
3429 audit_rmap(vcpu);
3430 audit_write_protection(vcpu);
2aaf65e8
MT		 3431 if (strcmp("pre pte write", audit_msg) != 0)
3432 audit_mappings(vcpu);
08a3732b 3433 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3434 dbg = olddbg;
3435}
3436
3437#endif
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