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KVM: MMU: Consolidate two guest pte reads in kvm_mmu_pte_write()
[net-next-2.6.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
5a0e3ad6 34#include <linux/slab.h>
6aa8b732 35
e495606d
AK		 36#include <asm/page.h>
37#include <asm/cmpxchg.h>
4e542370 38#include <asm/io.h>
13673a90 39#include <asm/vmx.h>
6aa8b732 40
18552672
JR		 41/*
42 * When setting this variable to true it enables Two-Dimensional-Paging
43 * where the hardware walks 2 page tables:
44 * 1. the guest-virtual to guest-physical
45 * 2. while doing 1. it walks guest-physical to host-physical
46 * If the hardware supports that we don't need to do shadow paging.
47 */
2f333bcb 48bool tdp_enabled = false;
18552672 49
37a7d8b0
AK		 50#undef MMU_DEBUG
51
52#undef AUDIT
53
54#ifdef AUDIT
55static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
56#else
57static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
58#endif
59
60#ifdef MMU_DEBUG
61
62#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
63#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
64
65#else
66
67#define pgprintk(x...) do { } while (0)
68#define rmap_printk(x...) do { } while (0)
69
70#endif
71
72#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 73static int dbg = 0;
74module_param(dbg, bool, 0644);
37a7d8b0 75#endif
6aa8b732 76
582801a9
MT		 77static int oos_shadow = 1;
78module_param(oos_shadow, bool, 0644);
79
d6c69ee9
YD		 80#ifndef MMU_DEBUG
81#define ASSERT(x) do { } while (0)
82#else
6aa8b732
AK		 83#define ASSERT(x) \
84 if (!(x)) { \
85 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
86 __FILE__, __LINE__, #x); \
87 }
d6c69ee9 88#endif
6aa8b732 89
6aa8b732
AK		 90#define PT_FIRST_AVAIL_BITS_SHIFT 9
91#define PT64_SECOND_AVAIL_BITS_SHIFT 52
92
6aa8b732
AK		 93#define VALID_PAGE(x) ((x) != INVALID_PAGE)
94
95#define PT64_LEVEL_BITS 9
96
97#define PT64_LEVEL_SHIFT(level) \
d77c26fc 98 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 99
100#define PT64_LEVEL_MASK(level) \
101 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
102
103#define PT64_INDEX(address, level)\
104 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105
106
107#define PT32_LEVEL_BITS 10
108
109#define PT32_LEVEL_SHIFT(level) \
d77c26fc 110 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 111
112#define PT32_LEVEL_MASK(level) \
113 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 114#define PT32_LVL_OFFSET_MASK(level) \
115 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 117
118#define PT32_INDEX(address, level)\
119 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
120
121
27aba766 122#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 123#define PT64_DIR_BASE_ADDR_MASK \
124 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 125#define PT64_LVL_ADDR_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
128#define PT64_LVL_OFFSET_MASK(level) \
129 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 131
132#define PT32_BASE_ADDR_MASK PAGE_MASK
133#define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 135#define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
6aa8b732 138
79539cec
AK		 139#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
140 | PT64_NX_MASK)
6aa8b732 141
cd4a4e53
AK		 142#define RMAP_EXT 4
143
fe135d2c
AK		 144#define ACC_EXEC_MASK 1
145#define ACC_WRITE_MASK PT_WRITABLE_MASK
146#define ACC_USER_MASK PT_USER_MASK
147#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
148
90bb6fc5
AK		 149#include <trace/events/kvm.h>
150
07420171
AK		 151#define CREATE_TRACE_POINTS
152#include "mmutrace.h"
153
1403283a
IE		 154#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
155
135f8c2b
AK		 156#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
157
cd4a4e53 158struct kvm_rmap_desc {
d555c333 159 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 160 struct kvm_rmap_desc *more;
161};
162
2d11123a
AK		 163struct kvm_shadow_walk_iterator {
164 u64 addr;
165 hpa_t shadow_addr;
166 int level;
167 u64 *sptep;
168 unsigned index;
169};
170
171#define for_each_shadow_entry(_vcpu, _addr, _walker) \
172 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
173 shadow_walk_okay(&(_walker)); \
174 shadow_walk_next(&(_walker)))
175
176
4731d4c7
MT		 177struct kvm_unsync_walk {
178 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
179};
180
ad8cfbe3
MT		 181typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
182
b5a33a75
AK		 183static struct kmem_cache *pte_chain_cache;
184static struct kmem_cache *rmap_desc_cache;
d3d25b04 185static struct kmem_cache *mmu_page_header_cache;
b5a33a75 186
c7addb90
AK		 187static u64 __read_mostly shadow_trap_nonpresent_pte;
188static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 189static u64 __read_mostly shadow_base_present_pte;
190static u64 __read_mostly shadow_nx_mask;
191static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
192static u64 __read_mostly shadow_user_mask;
193static u64 __read_mostly shadow_accessed_mask;
194static u64 __read_mostly shadow_dirty_mask;
c7addb90 195
82725b20
DE		 196static inline u64 rsvd_bits(int s, int e)
197{
198 return ((1ULL << (e - s + 1)) - 1) << s;
199}
200
c7addb90
AK		 201void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
202{
203 shadow_trap_nonpresent_pte = trap_pte;
204 shadow_notrap_nonpresent_pte = notrap_pte;
205}
206EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
207
7b52345e
SY		 208void kvm_mmu_set_base_ptes(u64 base_pte)
209{
210 shadow_base_present_pte = base_pte;
211}
212EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
213
214void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 215 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 216{
217 shadow_user_mask = user_mask;
218 shadow_accessed_mask = accessed_mask;
219 shadow_dirty_mask = dirty_mask;
220 shadow_nx_mask = nx_mask;
221 shadow_x_mask = x_mask;
222}
223EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
224
6aa8b732
AK		 225static int is_write_protection(struct kvm_vcpu *vcpu)
226{
4d4ec087 227 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 228}
229
230static int is_cpuid_PSE36(void)
231{
232 return 1;
233}
234
73b1087e
AK		 235static int is_nx(struct kvm_vcpu *vcpu)
236{
f6801dff 237 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 238}
239
c7addb90
AK		 240static int is_shadow_present_pte(u64 pte)
241{
c7addb90
AK		 242 return pte != shadow_trap_nonpresent_pte
243 && pte != shadow_notrap_nonpresent_pte;
244}
245
05da4558
MT		 246static int is_large_pte(u64 pte)
247{
248 return pte & PT_PAGE_SIZE_MASK;
249}
250
8dae4445 251static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 252{
253 return pte & PT_WRITABLE_MASK;
254}
255
43a3795a 256static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 257{
439e218a 258 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 259}
260
43a3795a 261static int is_rmap_spte(u64 pte)
cd4a4e53 262{
4b1a80fa 263 return is_shadow_present_pte(pte);
cd4a4e53
AK		 264}
265
776e6633
MT		 266static int is_last_spte(u64 pte, int level)
267{
268 if (level == PT_PAGE_TABLE_LEVEL)
269 return 1;
852e3c19 270 if (is_large_pte(pte))
776e6633
MT		 271 return 1;
272 return 0;
273}
274
35149e21 275static pfn_t spte_to_pfn(u64 pte)
0b49ea86 276{
35149e21 277 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 278}
279
da928521
AK		 280static gfn_t pse36_gfn_delta(u32 gpte)
281{
282 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
283
284 return (gpte & PT32_DIR_PSE36_MASK) << shift;
285}
286
d555c333 287static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 288{
289#ifdef CONFIG_X86_64
290 set_64bit((unsigned long *)sptep, spte);
291#else
292 set_64bit((unsigned long long *)sptep, spte);
293#endif
294}
295
e2dec939 296static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 297 struct kmem_cache *base_cache, int min)
714b93da
AK		 298{
299 void *obj;
300
301 if (cache->nobjs >= min)
e2dec939 302 return 0;
714b93da 303 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 304 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 305 if (!obj)
e2dec939 306 return -ENOMEM;
714b93da
AK		 307 cache->objects[cache->nobjs++] = obj;
308 }
e2dec939 309 return 0;
714b93da
AK		 310}
311
312static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
313{
314 while (mc->nobjs)
315 kfree(mc->objects[--mc->nobjs]);
316}
317
c1158e63 318static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 319 int min)
c1158e63
AK		 320{
321 struct page *page;
322
323 if (cache->nobjs >= min)
324 return 0;
325 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 326 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 327 if (!page)
328 return -ENOMEM;
c1158e63
AK		 329 cache->objects[cache->nobjs++] = page_address(page);
330 }
331 return 0;
332}
333
334static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
335{
336 while (mc->nobjs)
c4d198d5 337 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 338}
339
2e3e5882 340static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 341{
e2dec939
AK		 342 int r;
343
ad312c7c 344 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 345 pte_chain_cache, 4);
e2dec939
AK		 346 if (r)
347 goto out;
ad312c7c 348 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 349 rmap_desc_cache, 4);
d3d25b04
AK		 350 if (r)
351 goto out;
ad312c7c 352 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 353 if (r)
354 goto out;
ad312c7c 355 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 356 mmu_page_header_cache, 4);
e2dec939
AK		 357out:
358 return r;
714b93da
AK		 359}
360
361static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
362{
ad312c7c
ZX		 363 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
364 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
365 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
366 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 367}
368
369static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
370 size_t size)
371{
372 void *p;
373
374 BUG_ON(!mc->nobjs);
375 p = mc->objects[--mc->nobjs];
714b93da
AK		 376 return p;
377}
378
714b93da
AK		 379static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
380{
ad312c7c 381 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 382 sizeof(struct kvm_pte_chain));
383}
384
90cb0529 385static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 386{
90cb0529 387 kfree(pc);
714b93da
AK		 388}
389
390static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
391{
ad312c7c 392 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 393 sizeof(struct kvm_rmap_desc));
394}
395
90cb0529 396static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 397{
90cb0529 398 kfree(rd);
714b93da
AK		 399}
400
05da4558
MT		 401/*
402 * Return the pointer to the largepage write count for a given
403 * gfn, handling slots that are not large page aligned.
404 */
d25797b2
JR		 405static int *slot_largepage_idx(gfn_t gfn,
406 struct kvm_memory_slot *slot,
407 int level)
05da4558
MT		 408{
409 unsigned long idx;
410
d25797b2
JR		 411 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
412 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
413 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 414}
415
416static void account_shadowed(struct kvm *kvm, gfn_t gfn)
417{
d25797b2 418 struct kvm_memory_slot *slot;
05da4558 419 int *write_count;
d25797b2 420 int i;
05da4558 421
2843099f 422 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 423
424 slot = gfn_to_memslot_unaliased(kvm, gfn);
425 for (i = PT_DIRECTORY_LEVEL;
426 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
427 write_count = slot_largepage_idx(gfn, slot, i);
428 *write_count += 1;
429 }
05da4558
MT		 430}
431
432static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
433{
d25797b2 434 struct kvm_memory_slot *slot;
05da4558 435 int *write_count;
d25797b2 436 int i;
05da4558 437
2843099f 438 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 439 for (i = PT_DIRECTORY_LEVEL;
440 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
441 slot = gfn_to_memslot_unaliased(kvm, gfn);
442 write_count = slot_largepage_idx(gfn, slot, i);
443 *write_count -= 1;
444 WARN_ON(*write_count < 0);
445 }
05da4558
MT		 446}
447
d25797b2
JR		 448static int has_wrprotected_page(struct kvm *kvm,
449 gfn_t gfn,
450 int level)
05da4558 451{
2843099f 452 struct kvm_memory_slot *slot;
05da4558
MT		 453 int *largepage_idx;
454
2843099f
IE		 455 gfn = unalias_gfn(kvm, gfn);
456 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 457 if (slot) {
d25797b2 458 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 459 return *largepage_idx;
460 }
461
462 return 1;
463}
464
d25797b2 465static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 466{
8f0b1ab6 467 unsigned long page_size;
d25797b2 468 int i, ret = 0;
05da4558 469
8f0b1ab6 470 page_size = kvm_host_page_size(kvm, gfn);
05da4558 471
d25797b2
JR		 472 for (i = PT_PAGE_TABLE_LEVEL;
473 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
474 if (page_size >= KVM_HPAGE_SIZE(i))
475 ret = i;
476 else
477 break;
478 }
479
4c2155ce 480 return ret;
05da4558
MT		 481}
482
d25797b2 483static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 484{
485 struct kvm_memory_slot *slot;
878403b7 486 int host_level, level, max_level;
05da4558
MT		 487
488 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
489 if (slot && slot->dirty_bitmap)
d25797b2 490 return PT_PAGE_TABLE_LEVEL;
05da4558 491
d25797b2
JR		 492 host_level = host_mapping_level(vcpu->kvm, large_gfn);
493
494 if (host_level == PT_PAGE_TABLE_LEVEL)
495 return host_level;
496
878403b7
SY		 497 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
498 kvm_x86_ops->get_lpage_level() : host_level;
499
500 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 501 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
502 break;
d25797b2
JR		 503
504 return level - 1;
05da4558
MT		 505}
506
290fc38d
IE		 507/*
508 * Take gfn and return the reverse mapping to it.
509 * Note: gfn must be unaliased before this function get called
510 */
511
44ad9944 512static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 513{
514 struct kvm_memory_slot *slot;
05da4558 515 unsigned long idx;
290fc38d
IE		 516
517 slot = gfn_to_memslot(kvm, gfn);
44ad9944 518 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 519 return &slot->rmap[gfn - slot->base_gfn];
520
44ad9944
JR		 521 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
522 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 523
44ad9944 524 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 525}
526
cd4a4e53
AK		 527/*
528 * Reverse mapping data structures:
529 *
290fc38d
IE		 530 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
531 * that points to page_address(page).
cd4a4e53 532 *
290fc38d
IE		 533 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
534 * containing more mappings.
53a27b39
MT		 535 *
536 * Returns the number of rmap entries before the spte was added or zero if
537 * the spte was not added.
538 *
cd4a4e53 539 */
44ad9944 540static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 541{
4db35314 542 struct kvm_mmu_page *sp;
cd4a4e53 543 struct kvm_rmap_desc *desc;
290fc38d 544 unsigned long *rmapp;
53a27b39 545 int i, count = 0;
cd4a4e53 546
43a3795a 547 if (!is_rmap_spte(*spte))
53a27b39 548 return count;
290fc38d 549 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 550 sp = page_header(__pa(spte));
551 sp->gfns[spte - sp->spt] = gfn;
44ad9944 552 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 553 if (!*rmapp) {
cd4a4e53 554 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 555 *rmapp = (unsigned long)spte;
556 } else if (!(*rmapp & 1)) {
cd4a4e53 557 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 558 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 559 desc->sptes[0] = (u64 *)*rmapp;
560 desc->sptes[1] = spte;
290fc38d 561 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 562 } else {
563 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 564 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 565 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 566 desc = desc->more;
53a27b39
MT		 567 count += RMAP_EXT;
568 }
d555c333 569 if (desc->sptes[RMAP_EXT-1]) {
714b93da 570 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 571 desc = desc->more;
572 }
d555c333 573 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 574 ;
d555c333 575 desc->sptes[i] = spte;
cd4a4e53 576 }
53a27b39 577 return count;
cd4a4e53
AK		 578}
579
290fc38d 580static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 581 struct kvm_rmap_desc *desc,
582 int i,
583 struct kvm_rmap_desc *prev_desc)
584{
585 int j;
586
d555c333 587 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 588 ;
d555c333
AK		 589 desc->sptes[i] = desc->sptes[j];
590 desc->sptes[j] = NULL;
cd4a4e53
AK		 591 if (j != 0)
592 return;
593 if (!prev_desc && !desc->more)
d555c333 594 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 595 else
596 if (prev_desc)
597 prev_desc->more = desc->more;
598 else
290fc38d 599 *rmapp = (unsigned long)desc->more | 1;
90cb0529 600 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 601}
602
290fc38d 603static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 604{
cd4a4e53
AK		 605 struct kvm_rmap_desc *desc;
606 struct kvm_rmap_desc *prev_desc;
4db35314 607 struct kvm_mmu_page *sp;
35149e21 608 pfn_t pfn;
290fc38d 609 unsigned long *rmapp;
cd4a4e53
AK		 610 int i;
611
43a3795a 612 if (!is_rmap_spte(*spte))
cd4a4e53 613 return;
4db35314 614 sp = page_header(__pa(spte));
35149e21 615 pfn = spte_to_pfn(*spte);
7b52345e 616 if (*spte & shadow_accessed_mask)
35149e21 617 kvm_set_pfn_accessed(pfn);
8dae4445 618 if (is_writable_pte(*spte))
acb66dd0 619 kvm_set_pfn_dirty(pfn);
44ad9944 620 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 621 if (!*rmapp) {
cd4a4e53
AK		 622 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
623 BUG();
290fc38d 624 } else if (!(*rmapp & 1)) {
cd4a4e53 625 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 626 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 627 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
628 spte, *spte);
629 BUG();
630 }
290fc38d 631 *rmapp = 0;
cd4a4e53
AK		 632 } else {
633 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 634 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 635 prev_desc = NULL;
636 while (desc) {
d555c333
AK		 637 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
638 if (desc->sptes[i] == spte) {
290fc38d 639 rmap_desc_remove_entry(rmapp,
714b93da 640 desc, i,
cd4a4e53
AK		 641 prev_desc);
642 return;
643 }
644 prev_desc = desc;
645 desc = desc->more;
646 }
186a3e52 647 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 648 BUG();
649 }
650}
651
98348e95 652static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 653{
374cbac0 654 struct kvm_rmap_desc *desc;
98348e95
IE		 655 struct kvm_rmap_desc *prev_desc;
656 u64 *prev_spte;
657 int i;
658
659 if (!*rmapp)
660 return NULL;
661 else if (!(*rmapp & 1)) {
662 if (!spte)
663 return (u64 *)*rmapp;
664 return NULL;
665 }
666 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
667 prev_desc = NULL;
668 prev_spte = NULL;
669 while (desc) {
d555c333 670 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 671 if (prev_spte == spte)
d555c333
AK		 672 return desc->sptes[i];
673 prev_spte = desc->sptes[i];
98348e95
IE		 674 }
675 desc = desc->more;
676 }
677 return NULL;
678}
679
b1a36821 680static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 681{
290fc38d 682 unsigned long *rmapp;
374cbac0 683 u64 *spte;
44ad9944 684 int i, write_protected = 0;
374cbac0 685
4a4c9924 686 gfn = unalias_gfn(kvm, gfn);
44ad9944 687 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 688
98348e95
IE		 689 spte = rmap_next(kvm, rmapp, NULL);
690 while (spte) {
374cbac0 691 BUG_ON(!spte);
374cbac0 692 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 693 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 694 if (is_writable_pte(*spte)) {
d555c333 695 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 696 write_protected = 1;
697 }
9647c14c 698 spte = rmap_next(kvm, rmapp, spte);
374cbac0 699 }
855149aa 700 if (write_protected) {
35149e21 701 pfn_t pfn;
855149aa
IE		 702
703 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 704 pfn = spte_to_pfn(*spte);
705 kvm_set_pfn_dirty(pfn);
855149aa
IE		 706 }
707
05da4558 708 /* check for huge page mappings */
44ad9944
JR		 709 for (i = PT_DIRECTORY_LEVEL;
710 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
711 rmapp = gfn_to_rmap(kvm, gfn, i);
712 spte = rmap_next(kvm, rmapp, NULL);
713 while (spte) {
714 BUG_ON(!spte);
715 BUG_ON(!(*spte & PT_PRESENT_MASK));
716 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
717 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 718 if (is_writable_pte(*spte)) {
44ad9944
JR		 719 rmap_remove(kvm, spte);
720 --kvm->stat.lpages;
721 __set_spte(spte, shadow_trap_nonpresent_pte);
722 spte = NULL;
723 write_protected = 1;
724 }
725 spte = rmap_next(kvm, rmapp, spte);
05da4558 726 }
05da4558
MT		 727 }
728
b1a36821 729 return write_protected;
374cbac0
AK		 730}
731
8a8365c5
FD		 732static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
733 unsigned long data)
e930bffe
AA		 734{
735 u64 *spte;
736 int need_tlb_flush = 0;
737
738 while ((spte = rmap_next(kvm, rmapp, NULL))) {
739 BUG_ON(!(*spte & PT_PRESENT_MASK));
740 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
741 rmap_remove(kvm, spte);
d555c333 742 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 743 need_tlb_flush = 1;
744 }
745 return need_tlb_flush;
746}
747
8a8365c5
FD		 748static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
749 unsigned long data)
3da0dd43
IE		 750{
751 int need_flush = 0;
752 u64 *spte, new_spte;
753 pte_t *ptep = (pte_t *)data;
754 pfn_t new_pfn;
755
756 WARN_ON(pte_huge(*ptep));
757 new_pfn = pte_pfn(*ptep);
758 spte = rmap_next(kvm, rmapp, NULL);
759 while (spte) {
760 BUG_ON(!is_shadow_present_pte(*spte));
761 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
762 need_flush = 1;
763 if (pte_write(*ptep)) {
764 rmap_remove(kvm, spte);
765 __set_spte(spte, shadow_trap_nonpresent_pte);
766 spte = rmap_next(kvm, rmapp, NULL);
767 } else {
768 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
769 new_spte |= (u64)new_pfn << PAGE_SHIFT;
770
771 new_spte &= ~PT_WRITABLE_MASK;
772 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 773 if (is_writable_pte(*spte))
3da0dd43
IE		 774 kvm_set_pfn_dirty(spte_to_pfn(*spte));
775 __set_spte(spte, new_spte);
776 spte = rmap_next(kvm, rmapp, spte);
777 }
778 }
779 if (need_flush)
780 kvm_flush_remote_tlbs(kvm);
781
782 return 0;
783}
784
8a8365c5
FD		 785static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
786 unsigned long data,
3da0dd43 787 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 788 unsigned long data))
e930bffe 789{
852e3c19 790 int i, j;
90bb6fc5 791 int ret;
e930bffe 792 int retval = 0;
bc6678a3
MT		 793 struct kvm_memslots *slots;
794
795 slots = rcu_dereference(kvm->memslots);
e930bffe 796
46a26bf5
MT		 797 for (i = 0; i < slots->nmemslots; i++) {
798 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 799 unsigned long start = memslot->userspace_addr;
800 unsigned long end;
801
e930bffe
AA		 802 end = start + (memslot->npages << PAGE_SHIFT);
803 if (hva >= start && hva < end) {
804 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 805
90bb6fc5 806 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 807
808 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
809 int idx = gfn_offset;
810 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 811 ret |= handler(kvm,
3da0dd43
IE		 812 &memslot->lpage_info[j][idx].rmap_pde,
813 data);
852e3c19 814 }
90bb6fc5
AK		 815 trace_kvm_age_page(hva, memslot, ret);
816 retval |= ret;
e930bffe
AA		 817 }
818 }
819
820 return retval;
821}
822
823int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
824{
3da0dd43
IE		 825 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
826}
827
828void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
829{
8a8365c5 830 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 831}
832
8a8365c5
FD		 833static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
834 unsigned long data)
e930bffe
AA		 835{
836 u64 *spte;
837 int young = 0;
838
6316e1c8
RR		 839 /*
840 * Emulate the accessed bit for EPT, by checking if this page has
841 * an EPT mapping, and clearing it if it does. On the next access,
842 * a new EPT mapping will be established.
843 * This has some overhead, but not as much as the cost of swapping
844 * out actively used pages or breaking up actively used hugepages.
845 */
534e38b4 846 if (!shadow_accessed_mask)
6316e1c8 847 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 848
e930bffe
AA		 849 spte = rmap_next(kvm, rmapp, NULL);
850 while (spte) {
851 int _young;
852 u64 _spte = *spte;
853 BUG_ON(!(_spte & PT_PRESENT_MASK));
854 _young = _spte & PT_ACCESSED_MASK;
855 if (_young) {
856 young = 1;
857 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
858 }
859 spte = rmap_next(kvm, rmapp, spte);
860 }
861 return young;
862}
863
53a27b39
MT		 864#define RMAP_RECYCLE_THRESHOLD 1000
865
852e3c19 866static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 867{
868 unsigned long *rmapp;
852e3c19
JR		 869 struct kvm_mmu_page *sp;
870
871 sp = page_header(__pa(spte));
53a27b39
MT		 872
873 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 874 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 875
3da0dd43 876 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 877 kvm_flush_remote_tlbs(vcpu->kvm);
878}
879
e930bffe
AA		 880int kvm_age_hva(struct kvm *kvm, unsigned long hva)
881{
3da0dd43 882 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 883}
884
d6c69ee9 885#ifdef MMU_DEBUG
47ad8e68 886static int is_empty_shadow_page(u64 *spt)
6aa8b732 887{
139bdb2d
AK		 888 u64 *pos;
889 u64 *end;
890
47ad8e68 891 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 892 if (is_shadow_present_pte(*pos)) {
b8688d51 893 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 894 pos, *pos);
6aa8b732 895 return 0;
139bdb2d 896 }
6aa8b732
AK		 897 return 1;
898}
d6c69ee9 899#endif
6aa8b732 900
4db35314 901static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 902{
4db35314
AK		 903 ASSERT(is_empty_shadow_page(sp->spt));
904 list_del(&sp->link);
905 __free_page(virt_to_page(sp->spt));
906 __free_page(virt_to_page(sp->gfns));
907 kfree(sp);
f05e70ac 908 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 909}
910
cea0f0e7
AK		 911static unsigned kvm_page_table_hashfn(gfn_t gfn)
912{
1ae0a13d 913 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 914}
915
25c0de2c
AK		 916static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
917 u64 *parent_pte)
6aa8b732 918{
4db35314 919 struct kvm_mmu_page *sp;
6aa8b732 920
ad312c7c
ZX		 921 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
922 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
923 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 924 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 925 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 926 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 927 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 928 sp->multimapped = 0;
929 sp->parent_pte = parent_pte;
f05e70ac 930 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 931 return sp;
6aa8b732
AK		 932}
933
714b93da 934static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 935 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 936{
937 struct kvm_pte_chain *pte_chain;
938 struct hlist_node *node;
939 int i;
940
941 if (!parent_pte)
942 return;
4db35314
AK		 943 if (!sp->multimapped) {
944 u64 *old = sp->parent_pte;
cea0f0e7
AK		 945
946 if (!old) {
4db35314 947 sp->parent_pte = parent_pte;
cea0f0e7
AK		 948 return;
949 }
4db35314 950 sp->multimapped = 1;
714b93da 951 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 952 INIT_HLIST_HEAD(&sp->parent_ptes);
953 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 954 pte_chain->parent_ptes[0] = old;
955 }
4db35314 956 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 957 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
958 continue;
959 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
960 if (!pte_chain->parent_ptes[i]) {
961 pte_chain->parent_ptes[i] = parent_pte;
962 return;
963 }
964 }
714b93da 965 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 966 BUG_ON(!pte_chain);
4db35314 967 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 968 pte_chain->parent_ptes[0] = parent_pte;
969}
970
4db35314 971static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 972 u64 *parent_pte)
973{
974 struct kvm_pte_chain *pte_chain;
975 struct hlist_node *node;
976 int i;
977
4db35314
AK		 978 if (!sp->multimapped) {
979 BUG_ON(sp->parent_pte != parent_pte);
980 sp->parent_pte = NULL;
cea0f0e7
AK		 981 return;
982 }
4db35314 983 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 984 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
985 if (!pte_chain->parent_ptes[i])
986 break;
987 if (pte_chain->parent_ptes[i] != parent_pte)
988 continue;
697fe2e2
AK		 989 while (i + 1 < NR_PTE_CHAIN_ENTRIES
990 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 991 pte_chain->parent_ptes[i]
992 = pte_chain->parent_ptes[i + 1];
993 ++i;
994 }
995 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 996 if (i == 0) {
997 hlist_del(&pte_chain->link);
90cb0529 998 mmu_free_pte_chain(pte_chain);
4db35314
AK		 999 if (hlist_empty(&sp->parent_ptes)) {
1000 sp->multimapped = 0;
1001 sp->parent_pte = NULL;
697fe2e2
AK		 1002 }
1003 }
cea0f0e7
AK		 1004 return;
1005 }
1006 BUG();
1007}
1008
ad8cfbe3
MT		 1009
1010static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1011 mmu_parent_walk_fn fn)
1012{
1013 struct kvm_pte_chain *pte_chain;
1014 struct hlist_node *node;
1015 struct kvm_mmu_page *parent_sp;
1016 int i;
1017
1018 if (!sp->multimapped && sp->parent_pte) {
1019 parent_sp = page_header(__pa(sp->parent_pte));
1020 fn(vcpu, parent_sp);
1021 mmu_parent_walk(vcpu, parent_sp, fn);
1022 return;
1023 }
1024 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1025 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1026 if (!pte_chain->parent_ptes[i])
1027 break;
1028 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1029 fn(vcpu, parent_sp);
1030 mmu_parent_walk(vcpu, parent_sp, fn);
1031 }
1032}
1033
0074ff63
MT		 1034static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1035{
1036 unsigned int index;
1037 struct kvm_mmu_page *sp = page_header(__pa(spte));
1038
1039 index = spte - sp->spt;
60c8aec6
MT		 1040 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1041 sp->unsync_children++;
1042 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1043}
1044
1045static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1046{
1047 struct kvm_pte_chain *pte_chain;
1048 struct hlist_node *node;
1049 int i;
1050
1051 if (!sp->parent_pte)
1052 return;
1053
1054 if (!sp->multimapped) {
1055 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1056 return;
1057 }
1058
1059 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1060 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1061 if (!pte_chain->parent_ptes[i])
1062 break;
1063 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1064 }
1065}
1066
1067static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1068{
0074ff63
MT		 1069 kvm_mmu_update_parents_unsync(sp);
1070 return 1;
1071}
1072
1073static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1074 struct kvm_mmu_page *sp)
1075{
1076 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1077 kvm_mmu_update_parents_unsync(sp);
1078}
1079
d761a501
AK		 1080static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1081 struct kvm_mmu_page *sp)
1082{
1083 int i;
1084
1085 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1086 sp->spt[i] = shadow_trap_nonpresent_pte;
1087}
1088
e8bc217a
MT		 1089static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1090 struct kvm_mmu_page *sp)
1091{
1092 return 1;
1093}
1094
a7052897
MT		 1095static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1096{
1097}
1098
60c8aec6
MT		 1099#define KVM_PAGE_ARRAY_NR 16
1100
1101struct kvm_mmu_pages {
1102 struct mmu_page_and_offset {
1103 struct kvm_mmu_page *sp;
1104 unsigned int idx;
1105 } page[KVM_PAGE_ARRAY_NR];
1106 unsigned int nr;
1107};
1108
0074ff63
MT		 1109#define for_each_unsync_children(bitmap, idx) \
1110 for (idx = find_first_bit(bitmap, 512); \
1111 idx < 512; \
1112 idx = find_next_bit(bitmap, 512, idx+1))
1113
cded19f3
HE		 1114static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1115 int idx)
4731d4c7 1116{
60c8aec6 1117 int i;
4731d4c7 1118
60c8aec6
MT		 1119 if (sp->unsync)
1120 for (i=0; i < pvec->nr; i++)
1121 if (pvec->page[i].sp == sp)
1122 return 0;
1123
1124 pvec->page[pvec->nr].sp = sp;
1125 pvec->page[pvec->nr].idx = idx;
1126 pvec->nr++;
1127 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1128}
1129
1130static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1131 struct kvm_mmu_pages *pvec)
1132{
1133 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1134
0074ff63 1135 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1136 u64 ent = sp->spt[i];
1137
87917239 1138 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1139 struct kvm_mmu_page *child;
1140 child = page_header(ent & PT64_BASE_ADDR_MASK);
1141
1142 if (child->unsync_children) {
60c8aec6
MT		 1143 if (mmu_pages_add(pvec, child, i))
1144 return -ENOSPC;
1145
1146 ret = __mmu_unsync_walk(child, pvec);
1147 if (!ret)
1148 __clear_bit(i, sp->unsync_child_bitmap);
1149 else if (ret > 0)
1150 nr_unsync_leaf += ret;
1151 else
4731d4c7
MT		 1152 return ret;
1153 }
1154
1155 if (child->unsync) {
60c8aec6
MT		 1156 nr_unsync_leaf++;
1157 if (mmu_pages_add(pvec, child, i))
1158 return -ENOSPC;
4731d4c7
MT		 1159 }
1160 }
1161 }
1162
0074ff63 1163 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1164 sp->unsync_children = 0;
1165
60c8aec6
MT		 1166 return nr_unsync_leaf;
1167}
1168
1169static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1170 struct kvm_mmu_pages *pvec)
1171{
1172 if (!sp->unsync_children)
1173 return 0;
1174
1175 mmu_pages_add(pvec, sp, 0);
1176 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1177}
1178
4db35314 1179static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1180{
1181 unsigned index;
1182 struct hlist_head *bucket;
4db35314 1183 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1184 struct hlist_node *node;
1185
b8688d51 1186 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1187 index = kvm_page_table_hashfn(gfn);
f05e70ac 1188 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1189 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1190 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1191 && !sp->role.invalid) {
cea0f0e7 1192 pgprintk("%s: found role %x\n",
b8688d51 1193 __func__, sp->role.word);
4db35314 1194 return sp;
cea0f0e7
AK		 1195 }
1196 return NULL;
1197}
1198
4731d4c7
MT		 1199static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1200{
1201 WARN_ON(!sp->unsync);
1202 sp->unsync = 0;
1203 --kvm->stat.mmu_unsync;
1204}
1205
1206static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1207
1208static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1209{
1210 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1211 kvm_mmu_zap_page(vcpu->kvm, sp);
1212 return 1;
1213 }
1214
f691fe1d 1215 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1216 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1217 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1218 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1219 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1220 kvm_mmu_zap_page(vcpu->kvm, sp);
1221 return 1;
1222 }
1223
1224 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1225 return 0;
1226}
1227
60c8aec6
MT		 1228struct mmu_page_path {
1229 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1230 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1231};
1232
60c8aec6
MT		 1233#define for_each_sp(pvec, sp, parents, i) \
1234 for (i = mmu_pages_next(&pvec, &parents, -1), \
1235 sp = pvec.page[i].sp; \
1236 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1237 i = mmu_pages_next(&pvec, &parents, i))
1238
cded19f3
HE		 1239static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1240 struct mmu_page_path *parents,
1241 int i)
60c8aec6
MT		 1242{
1243 int n;
1244
1245 for (n = i+1; n < pvec->nr; n++) {
1246 struct kvm_mmu_page *sp = pvec->page[n].sp;
1247
1248 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1249 parents->idx[0] = pvec->page[n].idx;
1250 return n;
1251 }
1252
1253 parents->parent[sp->role.level-2] = sp;
1254 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1255 }
1256
1257 return n;
1258}
1259
cded19f3 1260static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1261{
60c8aec6
MT		 1262 struct kvm_mmu_page *sp;
1263 unsigned int level = 0;
1264
1265 do {
1266 unsigned int idx = parents->idx[level];
4731d4c7 1267
60c8aec6
MT		 1268 sp = parents->parent[level];
1269 if (!sp)
1270 return;
1271
1272 --sp->unsync_children;
1273 WARN_ON((int)sp->unsync_children < 0);
1274 __clear_bit(idx, sp->unsync_child_bitmap);
1275 level++;
1276 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1277}
1278
60c8aec6
MT		 1279static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1280 struct mmu_page_path *parents,
1281 struct kvm_mmu_pages *pvec)
4731d4c7 1282{
60c8aec6
MT		 1283 parents->parent[parent->role.level-1] = NULL;
1284 pvec->nr = 0;
1285}
4731d4c7 1286
60c8aec6
MT		 1287static void mmu_sync_children(struct kvm_vcpu *vcpu,
1288 struct kvm_mmu_page *parent)
1289{
1290 int i;
1291 struct kvm_mmu_page *sp;
1292 struct mmu_page_path parents;
1293 struct kvm_mmu_pages pages;
1294
1295 kvm_mmu_pages_init(parent, &parents, &pages);
1296 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1297 int protected = 0;
1298
1299 for_each_sp(pages, sp, parents, i)
1300 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1301
1302 if (protected)
1303 kvm_flush_remote_tlbs(vcpu->kvm);
1304
60c8aec6
MT		 1305 for_each_sp(pages, sp, parents, i) {
1306 kvm_sync_page(vcpu, sp);
1307 mmu_pages_clear_parents(&parents);
1308 }
4731d4c7 1309 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1310 kvm_mmu_pages_init(parent, &parents, &pages);
1311 }
4731d4c7
MT		 1312}
1313
cea0f0e7
AK		 1314static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1315 gfn_t gfn,
1316 gva_t gaddr,
1317 unsigned level,
f6e2c02b 1318 int direct,
41074d07 1319 unsigned access,
f7d9c7b7 1320 u64 *parent_pte)
cea0f0e7
AK		 1321{
1322 union kvm_mmu_page_role role;
1323 unsigned index;
1324 unsigned quadrant;
1325 struct hlist_head *bucket;
4db35314 1326 struct kvm_mmu_page *sp;
4731d4c7 1327 struct hlist_node *node, *tmp;
cea0f0e7 1328
a770f6f2 1329 role = vcpu->arch.mmu.base_role;
cea0f0e7 1330 role.level = level;
f6e2c02b 1331 role.direct = direct;
41074d07 1332 role.access = access;
ad312c7c 1333 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1334 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1335 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1336 role.quadrant = quadrant;
1337 }
1ae0a13d 1338 index = kvm_page_table_hashfn(gfn);
f05e70ac 1339 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1340 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1341 if (sp->gfn == gfn) {
1342 if (sp->unsync)
1343 if (kvm_sync_page(vcpu, sp))
1344 continue;
1345
1346 if (sp->role.word != role.word)
1347 continue;
1348
4db35314 1349 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1350 if (sp->unsync_children) {
1351 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1352 kvm_mmu_mark_parents_unsync(vcpu, sp);
1353 }
f691fe1d 1354 trace_kvm_mmu_get_page(sp, false);
4db35314 1355 return sp;
cea0f0e7 1356 }
dfc5aa00 1357 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1358 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1359 if (!sp)
1360 return sp;
4db35314
AK		 1361 sp->gfn = gfn;
1362 sp->role = role;
1363 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1364 if (!direct) {
b1a36821
MT		 1365 if (rmap_write_protect(vcpu->kvm, gfn))
1366 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1367 account_shadowed(vcpu->kvm, gfn);
1368 }
131d8279
AK		 1369 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1370 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1371 else
1372 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1373 trace_kvm_mmu_get_page(sp, true);
4db35314 1374 return sp;
cea0f0e7
AK		 1375}
1376
2d11123a
AK		 1377static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1378 struct kvm_vcpu *vcpu, u64 addr)
1379{
1380 iterator->addr = addr;
1381 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1382 iterator->level = vcpu->arch.mmu.shadow_root_level;
1383 if (iterator->level == PT32E_ROOT_LEVEL) {
1384 iterator->shadow_addr
1385 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1386 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1387 --iterator->level;
1388 if (!iterator->shadow_addr)
1389 iterator->level = 0;
1390 }
1391}
1392
1393static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1394{
1395 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1396 return false;
4d88954d
MT		 1397
1398 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1399 if (is_large_pte(*iterator->sptep))
1400 return false;
1401
2d11123a
AK		 1402 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1403 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1404 return true;
1405}
1406
1407static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1408{
1409 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1410 --iterator->level;
1411}
1412
90cb0529 1413static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1414 struct kvm_mmu_page *sp)
a436036b 1415{
697fe2e2
AK		 1416 unsigned i;
1417 u64 *pt;
1418 u64 ent;
1419
4db35314 1420 pt = sp->spt;
697fe2e2 1421
697fe2e2
AK		 1422 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1423 ent = pt[i];
1424
05da4558 1425 if (is_shadow_present_pte(ent)) {
776e6633 1426 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1427 ent &= PT64_BASE_ADDR_MASK;
1428 mmu_page_remove_parent_pte(page_header(ent),
1429 &pt[i]);
1430 } else {
776e6633
MT		 1431 if (is_large_pte(ent))
1432 --kvm->stat.lpages;
05da4558
MT		 1433 rmap_remove(kvm, &pt[i]);
1434 }
1435 }
c7addb90 1436 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1437 }
a436036b
AK		 1438}
1439
4db35314 1440static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1441{
4db35314 1442 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1443}
1444
12b7d28f
AK		 1445static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1446{
1447 int i;
988a2cae 1448 struct kvm_vcpu *vcpu;
12b7d28f 1449
988a2cae
GN		 1450 kvm_for_each_vcpu(i, vcpu, kvm)
1451 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1452}
1453
31aa2b44 1454static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1455{
1456 u64 *parent_pte;
1457
4db35314
AK		 1458 while (sp->multimapped || sp->parent_pte) {
1459 if (!sp->multimapped)
1460 parent_pte = sp->parent_pte;
a436036b
AK		 1461 else {
1462 struct kvm_pte_chain *chain;
1463
4db35314 1464 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1465 struct kvm_pte_chain, link);
1466 parent_pte = chain->parent_ptes[0];
1467 }
697fe2e2 1468 BUG_ON(!parent_pte);
4db35314 1469 kvm_mmu_put_page(sp, parent_pte);
d555c333 1470 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1471 }
31aa2b44
AK		 1472}
1473
60c8aec6
MT		 1474static int mmu_zap_unsync_children(struct kvm *kvm,
1475 struct kvm_mmu_page *parent)
4731d4c7 1476{
60c8aec6
MT		 1477 int i, zapped = 0;
1478 struct mmu_page_path parents;
1479 struct kvm_mmu_pages pages;
4731d4c7 1480
60c8aec6 1481 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1482 return 0;
60c8aec6
MT		 1483
1484 kvm_mmu_pages_init(parent, &parents, &pages);
1485 while (mmu_unsync_walk(parent, &pages)) {
1486 struct kvm_mmu_page *sp;
1487
1488 for_each_sp(pages, sp, parents, i) {
1489 kvm_mmu_zap_page(kvm, sp);
1490 mmu_pages_clear_parents(&parents);
77662e00 1491 zapped++;
60c8aec6 1492 }
60c8aec6
MT		 1493 kvm_mmu_pages_init(parent, &parents, &pages);
1494 }
1495
1496 return zapped;
4731d4c7
MT		 1497}
1498
07385413 1499static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1500{
4731d4c7 1501 int ret;
f691fe1d
AK		 1502
1503 trace_kvm_mmu_zap_page(sp);
31aa2b44 1504 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1505 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1506 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1507 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1508 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1509 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1510 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1511 if (sp->unsync)
1512 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1513 if (!sp->root_count) {
1514 hlist_del(&sp->hash_link);
1515 kvm_mmu_free_page(kvm, sp);
2e53d63a 1516 } else {
2e53d63a 1517 sp->role.invalid = 1;
5b5c6a5a 1518 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1519 kvm_reload_remote_mmus(kvm);
1520 }
12b7d28f 1521 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1522 return ret;
a436036b
AK		 1523}
1524
82ce2c96
IE		 1525/*
1526 * Changing the number of mmu pages allocated to the vm
1527 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1528 */
1529void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1530{
025dbbf3
MT		 1531 int used_pages;
1532
1533 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1534 used_pages = max(0, used_pages);
1535
82ce2c96
IE		 1536 /*
1537 * If we set the number of mmu pages to be smaller be than the
1538 * number of actived pages , we must to free some mmu pages before we
1539 * change the value
1540 */
1541
025dbbf3 1542 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1543 while (used_pages > kvm_nr_mmu_pages &&
1544 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1545 struct kvm_mmu_page *page;
1546
f05e70ac 1547 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1548 struct kvm_mmu_page, link);
77662e00 1549 used_pages -= kvm_mmu_zap_page(kvm, page);
025dbbf3 1550 used_pages--;
82ce2c96 1551 }
77662e00 1552 kvm_nr_mmu_pages = used_pages;
f05e70ac 1553 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1554 }
1555 else
f05e70ac
ZX		 1556 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1557 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1558
f05e70ac 1559 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1560}
1561
f67a46f4 1562static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1563{
1564 unsigned index;
1565 struct hlist_head *bucket;
4db35314 1566 struct kvm_mmu_page *sp;
a436036b
AK		 1567 struct hlist_node *node, *n;
1568 int r;
1569
b8688d51 1570 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1571 r = 0;
1ae0a13d 1572 index = kvm_page_table_hashfn(gfn);
f05e70ac 1573 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1574 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1575 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1576 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1577 sp->role.word);
a436036b 1578 r = 1;
07385413
MT		 1579 if (kvm_mmu_zap_page(kvm, sp))
1580 n = bucket->first;
a436036b
AK		 1581 }
1582 return r;
cea0f0e7
AK		 1583}
1584
f67a46f4 1585static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1586{
4677a3b6
AK		 1587 unsigned index;
1588 struct hlist_head *bucket;
4db35314 1589 struct kvm_mmu_page *sp;
4677a3b6 1590 struct hlist_node *node, *nn;
97a0a01e 1591
4677a3b6
AK		 1592 index = kvm_page_table_hashfn(gfn);
1593 bucket = &kvm->arch.mmu_page_hash[index];
1594 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1595 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1596 && !sp->role.invalid) {
1597 pgprintk("%s: zap %lx %x\n",
1598 __func__, gfn, sp->role.word);
77662e00
XG		 1599 if (kvm_mmu_zap_page(kvm, sp))
1600 nn = bucket->first;
4677a3b6 1601 }
97a0a01e
AK		 1602 }
1603}
1604
38c335f1 1605static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1606{
bc6678a3 1607 int slot = memslot_id(kvm, gfn);
4db35314 1608 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1609
291f26bc 1610 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1611}
1612
6844dec6
MT		 1613static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1614{
1615 int i;
1616 u64 *pt = sp->spt;
1617
1618 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1619 return;
1620
1621 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1622 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1623 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1624 }
1625}
1626
039576c0
AK		 1627struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1628{
72dc67a6
IE		 1629 struct page *page;
1630
1871c602 1631 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
039576c0
AK		 1632
1633 if (gpa == UNMAPPED_GVA)
1634 return NULL;
72dc67a6 1635
72dc67a6 1636 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1637
1638 return page;
039576c0
AK		 1639}
1640
74be52e3
SY		 1641/*
1642 * The function is based on mtrr_type_lookup() in
1643 * arch/x86/kernel/cpu/mtrr/generic.c
1644 */
1645static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1646 u64 start, u64 end)
1647{
1648 int i;
1649 u64 base, mask;
1650 u8 prev_match, curr_match;
1651 int num_var_ranges = KVM_NR_VAR_MTRR;
1652
1653 if (!mtrr_state->enabled)
1654 return 0xFF;
1655
1656 /* Make end inclusive end, instead of exclusive */
1657 end--;
1658
1659 /* Look in fixed ranges. Just return the type as per start */
1660 if (mtrr_state->have_fixed && (start < 0x100000)) {
1661 int idx;
1662
1663 if (start < 0x80000) {
1664 idx = 0;
1665 idx += (start >> 16);
1666 return mtrr_state->fixed_ranges[idx];
1667 } else if (start < 0xC0000) {
1668 idx = 1 * 8;
1669 idx += ((start - 0x80000) >> 14);
1670 return mtrr_state->fixed_ranges[idx];
1671 } else if (start < 0x1000000) {
1672 idx = 3 * 8;
1673 idx += ((start - 0xC0000) >> 12);
1674 return mtrr_state->fixed_ranges[idx];
1675 }
1676 }
1677
1678 /*
1679 * Look in variable ranges
1680 * Look of multiple ranges matching this address and pick type
1681 * as per MTRR precedence
1682 */
1683 if (!(mtrr_state->enabled & 2))
1684 return mtrr_state->def_type;
1685
1686 prev_match = 0xFF;
1687 for (i = 0; i < num_var_ranges; ++i) {
1688 unsigned short start_state, end_state;
1689
1690 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1691 continue;
1692
1693 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1694 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1695 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1696 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1697
1698 start_state = ((start & mask) == (base & mask));
1699 end_state = ((end & mask) == (base & mask));
1700 if (start_state != end_state)
1701 return 0xFE;
1702
1703 if ((start & mask) != (base & mask))
1704 continue;
1705
1706 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1707 if (prev_match == 0xFF) {
1708 prev_match = curr_match;
1709 continue;
1710 }
1711
1712 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1713 curr_match == MTRR_TYPE_UNCACHABLE)
1714 return MTRR_TYPE_UNCACHABLE;
1715
1716 if ((prev_match == MTRR_TYPE_WRBACK &&
1717 curr_match == MTRR_TYPE_WRTHROUGH) ||
1718 (prev_match == MTRR_TYPE_WRTHROUGH &&
1719 curr_match == MTRR_TYPE_WRBACK)) {
1720 prev_match = MTRR_TYPE_WRTHROUGH;
1721 curr_match = MTRR_TYPE_WRTHROUGH;
1722 }
1723
1724 if (prev_match != curr_match)
1725 return MTRR_TYPE_UNCACHABLE;
1726 }
1727
1728 if (prev_match != 0xFF)
1729 return prev_match;
1730
1731 return mtrr_state->def_type;
1732}
1733
4b12f0de 1734u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1735{
1736 u8 mtrr;
1737
1738 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1739 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1740 if (mtrr == 0xfe || mtrr == 0xff)
1741 mtrr = MTRR_TYPE_WRBACK;
1742 return mtrr;
1743}
4b12f0de 1744EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1745
4731d4c7
MT		 1746static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1747{
1748 unsigned index;
1749 struct hlist_head *bucket;
1750 struct kvm_mmu_page *s;
1751 struct hlist_node *node, *n;
1752
f691fe1d 1753 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1754 index = kvm_page_table_hashfn(sp->gfn);
1755 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1756 /* don't unsync if pagetable is shadowed with multiple roles */
1757 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1758 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1759 continue;
1760 if (s->role.word != sp->role.word)
1761 return 1;
1762 }
4731d4c7
MT		 1763 ++vcpu->kvm->stat.mmu_unsync;
1764 sp->unsync = 1;
6cffe8ca 1765
c2d0ee46 1766 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1767
4731d4c7
MT		 1768 mmu_convert_notrap(sp);
1769 return 0;
1770}
1771
1772static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1773 bool can_unsync)
1774{
1775 struct kvm_mmu_page *shadow;
1776
1777 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1778 if (shadow) {
1779 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1780 return 1;
1781 if (shadow->unsync)
1782 return 0;
582801a9 1783 if (can_unsync && oos_shadow)
4731d4c7
MT		 1784 return kvm_unsync_page(vcpu, shadow);
1785 return 1;
1786 }
1787 return 0;
1788}
1789
d555c333 1790static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1791 unsigned pte_access, int user_fault,
852e3c19 1792 int write_fault, int dirty, int level,
c2d0ee46 1793 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1794 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1795{
1796 u64 spte;
1e73f9dd 1797 int ret = 0;
64d4d521 1798
1c4f1fd6
AK		 1799 /*
1800 * We don't set the accessed bit, since we sometimes want to see
1801 * whether the guest actually used the pte (in order to detect
1802 * demand paging).
1803 */
7b52345e 1804 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1805 if (!speculative)
3201b5d9 1806 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1807 if (!dirty)
1808 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1809 if (pte_access & ACC_EXEC_MASK)
1810 spte |= shadow_x_mask;
1811 else
1812 spte |= shadow_nx_mask;
1c4f1fd6 1813 if (pte_access & ACC_USER_MASK)
7b52345e 1814 spte |= shadow_user_mask;
852e3c19 1815 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1816 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1817 if (tdp_enabled)
1818 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1819 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1820
1403283a
IE		 1821 if (reset_host_protection)
1822 spte |= SPTE_HOST_WRITEABLE;
1823
35149e21 1824 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1825
1826 if ((pte_access & ACC_WRITE_MASK)
1827 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1828
852e3c19
JR		 1829 if (level > PT_PAGE_TABLE_LEVEL &&
1830 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1831 ret = 1;
1832 spte = shadow_trap_nonpresent_pte;
1833 goto set_pte;
1834 }
1835
1c4f1fd6 1836 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1837
ecc5589f
MT		 1838 /*
1839 * Optimization: for pte sync, if spte was writable the hash
1840 * lookup is unnecessary (and expensive). Write protection
1841 * is responsibility of mmu_get_page / kvm_sync_page.
1842 * Same reasoning can be applied to dirty page accounting.
1843 */
8dae4445 1844 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1845 goto set_pte;
1846
4731d4c7 1847 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1848 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1849 __func__, gfn);
1e73f9dd 1850 ret = 1;
1c4f1fd6 1851 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1852 if (is_writable_pte(spte))
1c4f1fd6 1853 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1854 }
1855 }
1856
1c4f1fd6
AK		 1857 if (pte_access & ACC_WRITE_MASK)
1858 mark_page_dirty(vcpu->kvm, gfn);
1859
38187c83 1860set_pte:
d555c333 1861 __set_spte(sptep, spte);
1e73f9dd
MT		 1862 return ret;
1863}
1864
d555c333 1865static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1866 unsigned pt_access, unsigned pte_access,
1867 int user_fault, int write_fault, int dirty,
852e3c19 1868 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1869 pfn_t pfn, bool speculative,
1870 bool reset_host_protection)
1e73f9dd
MT		 1871{
1872 int was_rmapped = 0;
8dae4445 1873 int was_writable = is_writable_pte(*sptep);
53a27b39 1874 int rmap_count;
1e73f9dd
MT		 1875
1876 pgprintk("%s: spte %llx access %x write_fault %d"
1877 " user_fault %d gfn %lx\n",
d555c333 1878 __func__, *sptep, pt_access,
1e73f9dd
MT		 1879 write_fault, user_fault, gfn);
1880
d555c333 1881 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1882 /*
1883 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1884 * the parent of the now unreachable PTE.
1885 */
852e3c19
JR		 1886 if (level > PT_PAGE_TABLE_LEVEL &&
1887 !is_large_pte(*sptep)) {
1e73f9dd 1888 struct kvm_mmu_page *child;
d555c333 1889 u64 pte = *sptep;
1e73f9dd
MT		 1890
1891 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1892 mmu_page_remove_parent_pte(child, sptep);
1893 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1894 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1895 spte_to_pfn(*sptep), pfn);
1896 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1897 } else
1898 was_rmapped = 1;
1e73f9dd 1899 }
852e3c19 1900
d555c333 1901 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1902 dirty, level, gfn, pfn, speculative, true,
1903 reset_host_protection)) {
1e73f9dd
MT		 1904 if (write_fault)
1905 *ptwrite = 1;
a378b4e6
MT		 1906 kvm_x86_ops->tlb_flush(vcpu);
1907 }
1e73f9dd 1908
d555c333 1909 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1910 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1911 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1912 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1913 *sptep, sptep);
d555c333 1914 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1915 ++vcpu->kvm->stat.lpages;
1916
d555c333 1917 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1918 if (!was_rmapped) {
44ad9944 1919 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1920 kvm_release_pfn_clean(pfn);
53a27b39 1921 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1922 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1923 } else {
8dae4445 1924 if (was_writable)
35149e21 1925 kvm_release_pfn_dirty(pfn);
75e68e60 1926 else
35149e21 1927 kvm_release_pfn_clean(pfn);
1c4f1fd6 1928 }
1b7fcd32 1929 if (speculative) {
d555c333 1930 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1931 vcpu->arch.last_pte_gfn = gfn;
1932 }
1c4f1fd6
AK		 1933}
1934
6aa8b732
AK		 1935static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1936{
1937}
1938
9f652d21 1939static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1940 int level, gfn_t gfn, pfn_t pfn)
140754bc 1941{
9f652d21 1942 struct kvm_shadow_walk_iterator iterator;
140754bc 1943 struct kvm_mmu_page *sp;
9f652d21 1944 int pt_write = 0;
140754bc 1945 gfn_t pseudo_gfn;
6aa8b732 1946
9f652d21 1947 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1948 if (iterator.level == level) {
9f652d21
AK		 1949 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1950 0, write, 1, &pt_write,
1403283a 1951 level, gfn, pfn, false, true);
9f652d21
AK		 1952 ++vcpu->stat.pf_fixed;
1953 break;
6aa8b732
AK		 1954 }
1955
9f652d21
AK		 1956 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1957 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1958 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1959 iterator.level - 1,
1960 1, ACC_ALL, iterator.sptep);
1961 if (!sp) {
1962 pgprintk("nonpaging_map: ENOMEM\n");
1963 kvm_release_pfn_clean(pfn);
1964 return -ENOMEM;
1965 }
140754bc 1966
d555c333
AK		 1967 __set_spte(iterator.sptep,
1968 __pa(sp->spt)
1969 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1970 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1971 }
1972 }
1973 return pt_write;
6aa8b732
AK		 1974}
1975
10589a46
MT		 1976static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1977{
1978 int r;
852e3c19 1979 int level;
35149e21 1980 pfn_t pfn;
e930bffe 1981 unsigned long mmu_seq;
aaee2c94 1982
852e3c19
JR		 1983 level = mapping_level(vcpu, gfn);
1984
1985 /*
1986 * This path builds a PAE pagetable - so we can map 2mb pages at
1987 * maximum. Therefore check if the level is larger than that.
1988 */
1989 if (level > PT_DIRECTORY_LEVEL)
1990 level = PT_DIRECTORY_LEVEL;
1991
1992 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 1993
e930bffe 1994 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 1995 smp_rmb();
35149e21 1996 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 1997
d196e343 1998 /* mmio */
35149e21
AL		 1999 if (is_error_pfn(pfn)) {
2000 kvm_release_pfn_clean(pfn);
d196e343
AK		 2001 return 1;
2002 }
2003
aaee2c94 2004 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2005 if (mmu_notifier_retry(vcpu, mmu_seq))
2006 goto out_unlock;
eb787d10 2007 kvm_mmu_free_some_pages(vcpu);
852e3c19 2008 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2009 spin_unlock(&vcpu->kvm->mmu_lock);
2010
aaee2c94 2011
10589a46 2012 return r;
e930bffe
AA		 2013
2014out_unlock:
2015 spin_unlock(&vcpu->kvm->mmu_lock);
2016 kvm_release_pfn_clean(pfn);
2017 return 0;
10589a46
MT		 2018}
2019
2020
17ac10ad
AK		 2021static void mmu_free_roots(struct kvm_vcpu *vcpu)
2022{
2023 int i;
4db35314 2024 struct kvm_mmu_page *sp;
17ac10ad 2025
ad312c7c 2026 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2027 return;
aaee2c94 2028 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2029 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2030 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2031
4db35314
AK		 2032 sp = page_header(root);
2033 --sp->root_count;
2e53d63a
MT		 2034 if (!sp->root_count && sp->role.invalid)
2035 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2036 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2037 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2038 return;
2039 }
17ac10ad 2040 for (i = 0; i < 4; ++i) {
ad312c7c 2041 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2042
417726a3 2043 if (root) {
417726a3 2044 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2045 sp = page_header(root);
2046 --sp->root_count;
2e53d63a
MT		 2047 if (!sp->root_count && sp->role.invalid)
2048 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2049 }
ad312c7c 2050 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2051 }
aaee2c94 2052 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2053 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2054}
2055
8986ecc0
MT		 2056static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2057{
2058 int ret = 0;
2059
2060 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2061 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2062 ret = 1;
2063 }
2064
2065 return ret;
2066}
2067
2068static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2069{
2070 int i;
cea0f0e7 2071 gfn_t root_gfn;
4db35314 2072 struct kvm_mmu_page *sp;
f6e2c02b 2073 int direct = 0;
6de4f3ad 2074 u64 pdptr;
3bb65a22 2075
ad312c7c 2076 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2077
ad312c7c
ZX		 2078 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2079 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2080
2081 ASSERT(!VALID_PAGE(root));
fb72d167 2082 if (tdp_enabled)
f6e2c02b 2083 direct = 1;
8986ecc0
MT		 2084 if (mmu_check_root(vcpu, root_gfn))
2085 return 1;
4db35314 2086 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2087 PT64_ROOT_LEVEL, direct,
fb72d167 2088 ACC_ALL, NULL);
4db35314
AK		 2089 root = __pa(sp->spt);
2090 ++sp->root_count;
ad312c7c 2091 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2092 return 0;
17ac10ad 2093 }
f6e2c02b 2094 direct = !is_paging(vcpu);
fb72d167 2095 if (tdp_enabled)
f6e2c02b 2096 direct = 1;
17ac10ad 2097 for (i = 0; i < 4; ++i) {
ad312c7c 2098 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2099
2100 ASSERT(!VALID_PAGE(root));
ad312c7c 2101 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2102 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2103 if (!is_present_gpte(pdptr)) {
ad312c7c 2104 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2105 continue;
2106 }
6de4f3ad 2107 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2108 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2109 root_gfn = 0;
8986ecc0
MT		 2110 if (mmu_check_root(vcpu, root_gfn))
2111 return 1;
4db35314 2112 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2113 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2114 ACC_ALL, NULL);
4db35314
AK		 2115 root = __pa(sp->spt);
2116 ++sp->root_count;
ad312c7c 2117 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2118 }
ad312c7c 2119 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2120 return 0;
17ac10ad
AK		 2121}
2122
0ba73cda
MT		 2123static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2124{
2125 int i;
2126 struct kvm_mmu_page *sp;
2127
2128 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2129 return;
2130 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2131 hpa_t root = vcpu->arch.mmu.root_hpa;
2132 sp = page_header(root);
2133 mmu_sync_children(vcpu, sp);
2134 return;
2135 }
2136 for (i = 0; i < 4; ++i) {
2137 hpa_t root = vcpu->arch.mmu.pae_root[i];
2138
8986ecc0 2139 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2140 root &= PT64_BASE_ADDR_MASK;
2141 sp = page_header(root);
2142 mmu_sync_children(vcpu, sp);
2143 }
2144 }
2145}
2146
2147void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2148{
2149 spin_lock(&vcpu->kvm->mmu_lock);
2150 mmu_sync_roots(vcpu);
6cffe8ca 2151 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2152}
2153
1871c602
GN		 2154static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2155 u32 access, u32 *error)
6aa8b732 2156{
1871c602
GN		 2157 if (error)
2158 *error = 0;
6aa8b732
AK		 2159 return vaddr;
2160}
2161
2162static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2163 u32 error_code)
6aa8b732 2164{
e833240f 2165 gfn_t gfn;
e2dec939 2166 int r;
6aa8b732 2167
b8688d51 2168 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2169 r = mmu_topup_memory_caches(vcpu);
2170 if (r)
2171 return r;
714b93da 2172
6aa8b732 2173 ASSERT(vcpu);
ad312c7c 2174 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2175
e833240f 2176 gfn = gva >> PAGE_SHIFT;
6aa8b732 2177
e833240f
AK		 2178 return nonpaging_map(vcpu, gva & PAGE_MASK,
2179 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2180}
2181
fb72d167
JR		 2182static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2183 u32 error_code)
2184{
35149e21 2185 pfn_t pfn;
fb72d167 2186 int r;
852e3c19 2187 int level;
05da4558 2188 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2189 unsigned long mmu_seq;
fb72d167
JR		 2190
2191 ASSERT(vcpu);
2192 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2193
2194 r = mmu_topup_memory_caches(vcpu);
2195 if (r)
2196 return r;
2197
852e3c19
JR		 2198 level = mapping_level(vcpu, gfn);
2199
2200 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2201
e930bffe 2202 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2203 smp_rmb();
35149e21 2204 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2205 if (is_error_pfn(pfn)) {
2206 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2207 return 1;
2208 }
2209 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2210 if (mmu_notifier_retry(vcpu, mmu_seq))
2211 goto out_unlock;
fb72d167
JR		 2212 kvm_mmu_free_some_pages(vcpu);
2213 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2214 level, gfn, pfn);
fb72d167 2215 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2216
2217 return r;
e930bffe
AA		 2218
2219out_unlock:
2220 spin_unlock(&vcpu->kvm->mmu_lock);
2221 kvm_release_pfn_clean(pfn);
2222 return 0;
fb72d167
JR		 2223}
2224
6aa8b732
AK		 2225static void nonpaging_free(struct kvm_vcpu *vcpu)
2226{
17ac10ad 2227 mmu_free_roots(vcpu);
6aa8b732
AK		 2228}
2229
2230static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2231{
ad312c7c 2232 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2233
2234 context->new_cr3 = nonpaging_new_cr3;
2235 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2236 context->gva_to_gpa = nonpaging_gva_to_gpa;
2237 context->free = nonpaging_free;
c7addb90 2238 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2239 context->sync_page = nonpaging_sync_page;
a7052897 2240 context->invlpg = nonpaging_invlpg;
cea0f0e7 2241 context->root_level = 0;
6aa8b732 2242 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2243 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2244 return 0;
2245}
2246
d835dfec 2247void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2248{
1165f5fe 2249 ++vcpu->stat.tlb_flush;
cbdd1bea 2250 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2251}
2252
2253static void paging_new_cr3(struct kvm_vcpu *vcpu)
2254{
b8688d51 2255 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2256 mmu_free_roots(vcpu);
6aa8b732
AK		 2257}
2258
6aa8b732
AK		 2259static void inject_page_fault(struct kvm_vcpu *vcpu,
2260 u64 addr,
2261 u32 err_code)
2262{
c3c91fee 2263 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2264}
2265
6aa8b732
AK		 2266static void paging_free(struct kvm_vcpu *vcpu)
2267{
2268 nonpaging_free(vcpu);
2269}
2270
82725b20
DE		 2271static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2272{
2273 int bit7;
2274
2275 bit7 = (gpte >> 7) & 1;
2276 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2277}
2278
6aa8b732
AK		 2279#define PTTYPE 64
2280#include "paging_tmpl.h"
2281#undef PTTYPE
2282
2283#define PTTYPE 32
2284#include "paging_tmpl.h"
2285#undef PTTYPE
2286
82725b20
DE		 2287static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2288{
2289 struct kvm_mmu *context = &vcpu->arch.mmu;
2290 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2291 u64 exb_bit_rsvd = 0;
2292
2293 if (!is_nx(vcpu))
2294 exb_bit_rsvd = rsvd_bits(63, 63);
2295 switch (level) {
2296 case PT32_ROOT_LEVEL:
2297 /* no rsvd bits for 2 level 4K page table entries */
2298 context->rsvd_bits_mask[0][1] = 0;
2299 context->rsvd_bits_mask[0][0] = 0;
2300 if (is_cpuid_PSE36())
2301 /* 36bits PSE 4MB page */
2302 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2303 else
2304 /* 32 bits PSE 4MB page */
2305 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2306 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2307 break;
2308 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2309 context->rsvd_bits_mask[0][2] =
2310 rsvd_bits(maxphyaddr, 63) |
2311 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2312 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2313 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2314 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2315 rsvd_bits(maxphyaddr, 62); /* PTE */
2316 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2317 rsvd_bits(maxphyaddr, 62) |
2318 rsvd_bits(13, 20); /* large page */
29a4b933 2319 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2320 break;
2321 case PT64_ROOT_LEVEL:
2322 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2323 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2324 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2325 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2326 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2327 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2328 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2329 rsvd_bits(maxphyaddr, 51);
2330 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2331 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2332 rsvd_bits(maxphyaddr, 51) |
2333 rsvd_bits(13, 29);
82725b20 2334 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2335 rsvd_bits(maxphyaddr, 51) |
2336 rsvd_bits(13, 20); /* large page */
29a4b933 2337 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2338 break;
2339 }
2340}
2341
17ac10ad 2342static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2343{
ad312c7c 2344 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2345
2346 ASSERT(is_pae(vcpu));
2347 context->new_cr3 = paging_new_cr3;
2348 context->page_fault = paging64_page_fault;
6aa8b732 2349 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2350 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2351 context->sync_page = paging64_sync_page;
a7052897 2352 context->invlpg = paging64_invlpg;
6aa8b732 2353 context->free = paging_free;
17ac10ad
AK		 2354 context->root_level = level;
2355 context->shadow_root_level = level;
17c3ba9d 2356 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2357 return 0;
2358}
2359
17ac10ad
AK		 2360static int paging64_init_context(struct kvm_vcpu *vcpu)
2361{
82725b20 2362 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2363 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2364}
2365
6aa8b732
AK		 2366static int paging32_init_context(struct kvm_vcpu *vcpu)
2367{
ad312c7c 2368 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2369
82725b20 2370 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2371 context->new_cr3 = paging_new_cr3;
2372 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2373 context->gva_to_gpa = paging32_gva_to_gpa;
2374 context->free = paging_free;
c7addb90 2375 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2376 context->sync_page = paging32_sync_page;
a7052897 2377 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2378 context->root_level = PT32_ROOT_LEVEL;
2379 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2380 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2381 return 0;
2382}
2383
2384static int paging32E_init_context(struct kvm_vcpu *vcpu)
2385{
82725b20 2386 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2387 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2388}
2389
fb72d167
JR		 2390static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2391{
2392 struct kvm_mmu *context = &vcpu->arch.mmu;
2393
2394 context->new_cr3 = nonpaging_new_cr3;
2395 context->page_fault = tdp_page_fault;
2396 context->free = nonpaging_free;
2397 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2398 context->sync_page = nonpaging_sync_page;
a7052897 2399 context->invlpg = nonpaging_invlpg;
67253af5 2400 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2401 context->root_hpa = INVALID_PAGE;
2402
2403 if (!is_paging(vcpu)) {
2404 context->gva_to_gpa = nonpaging_gva_to_gpa;
2405 context->root_level = 0;
2406 } else if (is_long_mode(vcpu)) {
82725b20 2407 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2408 context->gva_to_gpa = paging64_gva_to_gpa;
2409 context->root_level = PT64_ROOT_LEVEL;
2410 } else if (is_pae(vcpu)) {
82725b20 2411 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2412 context->gva_to_gpa = paging64_gva_to_gpa;
2413 context->root_level = PT32E_ROOT_LEVEL;
2414 } else {
82725b20 2415 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2416 context->gva_to_gpa = paging32_gva_to_gpa;
2417 context->root_level = PT32_ROOT_LEVEL;
2418 }
2419
2420 return 0;
2421}
2422
2423static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2424{
a770f6f2
AK		 2425 int r;
2426
6aa8b732 2427 ASSERT(vcpu);
ad312c7c 2428 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2429
2430 if (!is_paging(vcpu))
a770f6f2 2431 r = nonpaging_init_context(vcpu);
a9058ecd 2432 else if (is_long_mode(vcpu))
a770f6f2 2433 r = paging64_init_context(vcpu);
6aa8b732 2434 else if (is_pae(vcpu))
a770f6f2 2435 r = paging32E_init_context(vcpu);
6aa8b732 2436 else
a770f6f2
AK		 2437 r = paging32_init_context(vcpu);
2438
2439 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2440
2441 return r;
6aa8b732
AK		 2442}
2443
fb72d167
JR		 2444static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2445{
35149e21
AL		 2446 vcpu->arch.update_pte.pfn = bad_pfn;
2447
fb72d167
JR		 2448 if (tdp_enabled)
2449 return init_kvm_tdp_mmu(vcpu);
2450 else
2451 return init_kvm_softmmu(vcpu);
2452}
2453
6aa8b732
AK		 2454static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2455{
2456 ASSERT(vcpu);
ad312c7c
ZX		 2457 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2458 vcpu->arch.mmu.free(vcpu);
2459 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2460 }
2461}
2462
2463int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2464{
2465 destroy_kvm_mmu(vcpu);
2466 return init_kvm_mmu(vcpu);
2467}
8668a3c4 2468EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2469
2470int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2471{
714b93da
AK		 2472 int r;
2473
e2dec939 2474 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2475 if (r)
2476 goto out;
aaee2c94 2477 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2478 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2479 r = mmu_alloc_roots(vcpu);
0ba73cda 2480 mmu_sync_roots(vcpu);
aaee2c94 2481 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2482 if (r)
2483 goto out;
3662cb1c 2484 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2485 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2486out:
2487 return r;
6aa8b732 2488}
17c3ba9d
AK		 2489EXPORT_SYMBOL_GPL(kvm_mmu_load);
2490
2491void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2492{
2493 mmu_free_roots(vcpu);
2494}
6aa8b732 2495
09072daf 2496static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2497 struct kvm_mmu_page *sp,
ac1b714e
AK		 2498 u64 *spte)
2499{
2500 u64 pte;
2501 struct kvm_mmu_page *child;
2502
2503 pte = *spte;
c7addb90 2504 if (is_shadow_present_pte(pte)) {
776e6633 2505 if (is_last_spte(pte, sp->role.level))
290fc38d 2506 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2507 else {
2508 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2509 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2510 }
2511 }
d555c333 2512 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2513 if (is_large_pte(pte))
2514 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2515}
2516
0028425f 2517static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2518 struct kvm_mmu_page *sp,
0028425f 2519 u64 *spte,
489f1d65 2520 const void *new)
0028425f 2521{
30945387 2522 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2523 ++vcpu->kvm->stat.mmu_pde_zapped;
2524 return;
30945387 2525 }
0028425f 2526
4cee5764 2527 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2528 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2529 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2530 else
489f1d65 2531 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2532}
2533
79539cec
AK		 2534static bool need_remote_flush(u64 old, u64 new)
2535{
2536 if (!is_shadow_present_pte(old))
2537 return false;
2538 if (!is_shadow_present_pte(new))
2539 return true;
2540 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2541 return true;
2542 old ^= PT64_NX_MASK;
2543 new ^= PT64_NX_MASK;
2544 return (old & ~new & PT64_PERM_MASK) != 0;
2545}
2546
2547static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2548{
2549 if (need_remote_flush(old, new))
2550 kvm_flush_remote_tlbs(vcpu->kvm);
2551 else
2552 kvm_mmu_flush_tlb(vcpu);
2553}
2554
12b7d28f
AK		 2555static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2556{
ad312c7c 2557 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2558
7b52345e 2559 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2560}
2561
d7824fff 2562static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2563 u64 gpte)
d7824fff
AK		 2564{
2565 gfn_t gfn;
35149e21 2566 pfn_t pfn;
d7824fff 2567
43a3795a 2568 if (!is_present_gpte(gpte))
d7824fff
AK		 2569 return;
2570 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2571
e930bffe 2572 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2573 smp_rmb();
35149e21 2574 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2575
35149e21
AL		 2576 if (is_error_pfn(pfn)) {
2577 kvm_release_pfn_clean(pfn);
d196e343
AK		 2578 return;
2579 }
d7824fff 2580 vcpu->arch.update_pte.gfn = gfn;
35149e21 2581 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2582}
2583
1b7fcd32
AK		 2584static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2585{
2586 u64 *spte = vcpu->arch.last_pte_updated;
2587
2588 if (spte
2589 && vcpu->arch.last_pte_gfn == gfn
2590 && shadow_accessed_mask
2591 && !(*spte & shadow_accessed_mask)
2592 && is_shadow_present_pte(*spte))
2593 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2594}
2595
09072daf 2596void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2597 const u8 *new, int bytes,
2598 bool guest_initiated)
da4a00f0 2599{
9b7a0325 2600 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2601 struct kvm_mmu_page *sp;
0e7bc4b9 2602 struct hlist_node *node, *n;
9b7a0325
AK		 2603 struct hlist_head *bucket;
2604 unsigned index;
489f1d65 2605 u64 entry, gentry;
9b7a0325 2606 u64 *spte;
9b7a0325 2607 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2608 unsigned pte_size;
9b7a0325 2609 unsigned page_offset;
0e7bc4b9 2610 unsigned misaligned;
fce0657f 2611 unsigned quadrant;
9b7a0325 2612 int level;
86a5ba02 2613 int flooded = 0;
ac1b714e 2614 int npte;
489f1d65 2615 int r;
9b7a0325 2616
b8688d51 2617 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a
AK		 2618
2619 switch (bytes) {
2620 case 4:
2621 gentry = *(const u32 *)new;
2622 break;
2623 case 8:
2624 gentry = *(const u64 *)new;
2625 break;
2626 default:
2627 gentry = 0;
2628 break;
2629 }
2630
2631 /*
2632 * Assume that the pte write on a page table of the same type
2633 * as the current vcpu paging mode. This is nearly always true
2634 * (might be false while changing modes). Note it is verified later
2635 * by update_pte().
2636 */
2637 if (is_pae(vcpu) && bytes == 4) {
2638 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2639 gpa &= ~(gpa_t)7;
2640 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, 8);
2641 if (r)
2642 gentry = 0;
2643 }
2644
2645 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2646 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2647 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2648 kvm_mmu_free_some_pages(vcpu);
4cee5764 2649 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2650 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2651 if (guest_initiated) {
2652 if (gfn == vcpu->arch.last_pt_write_gfn
2653 && !last_updated_pte_accessed(vcpu)) {
2654 ++vcpu->arch.last_pt_write_count;
2655 if (vcpu->arch.last_pt_write_count >= 3)
2656 flooded = 1;
2657 } else {
2658 vcpu->arch.last_pt_write_gfn = gfn;
2659 vcpu->arch.last_pt_write_count = 1;
2660 vcpu->arch.last_pte_updated = NULL;
2661 }
86a5ba02 2662 }
1ae0a13d 2663 index = kvm_page_table_hashfn(gfn);
f05e70ac 2664 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2665 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2666 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2667 continue;
4db35314 2668 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2669 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2670 misaligned |= bytes < 4;
86a5ba02 2671 if (misaligned || flooded) {
0e7bc4b9
AK		 2672 /*
2673 * Misaligned accesses are too much trouble to fix
2674 * up; also, they usually indicate a page is not used
2675 * as a page table.
86a5ba02
AK		 2676 *
2677 * If we're seeing too many writes to a page,
2678 * it may no longer be a page table, or we may be
2679 * forking, in which case it is better to unmap the
2680 * page.
0e7bc4b9
AK		 2681 */
2682 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2683 gpa, bytes, sp->role.word);
07385413
MT		 2684 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2685 n = bucket->first;
4cee5764 2686 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2687 continue;
2688 }
9b7a0325 2689 page_offset = offset;
4db35314 2690 level = sp->role.level;
ac1b714e 2691 npte = 1;
4db35314 2692 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2693 page_offset <<= 1; /* 32->64 */
2694 /*
2695 * A 32-bit pde maps 4MB while the shadow pdes map
2696 * only 2MB. So we need to double the offset again
2697 * and zap two pdes instead of one.
2698 */
2699 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2700 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2701 page_offset <<= 1;
2702 npte = 2;
2703 }
fce0657f 2704 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2705 page_offset &= ~PAGE_MASK;
4db35314 2706 if (quadrant != sp->role.quadrant)
fce0657f 2707 continue;
9b7a0325 2708 }
4db35314 2709 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2710 while (npte--) {
79539cec 2711 entry = *spte;
4db35314 2712 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2713 if (gentry)
2714 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2715 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2716 ++spte;
9b7a0325 2717 }
9b7a0325 2718 }
c7addb90 2719 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2720 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2721 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2722 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2723 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2724 }
da4a00f0
AK		 2725}
2726
a436036b
AK		 2727int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2728{
10589a46
MT		 2729 gpa_t gpa;
2730 int r;
a436036b 2731
60f24784
AK		 2732 if (tdp_enabled)
2733 return 0;
2734
1871c602 2735 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2736
aaee2c94 2737 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2738 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2739 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2740 return r;
a436036b 2741}
577bdc49 2742EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2743
22d95b12 2744void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2745{
3b80fffe
IE		 2746 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2747 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2748 struct kvm_mmu_page *sp;
ebeace86 2749
f05e70ac 2750 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2751 struct kvm_mmu_page, link);
2752 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2753 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2754 }
2755}
ebeace86 2756
3067714c
AK		 2757int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2758{
2759 int r;
2760 enum emulation_result er;
2761
ad312c7c 2762 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2763 if (r < 0)
2764 goto out;
2765
2766 if (!r) {
2767 r = 1;
2768 goto out;
2769 }
2770
b733bfb5
AK		 2771 r = mmu_topup_memory_caches(vcpu);
2772 if (r)
2773 goto out;
2774
851ba692 2775 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2776
2777 switch (er) {
2778 case EMULATE_DONE:
2779 return 1;
2780 case EMULATE_DO_MMIO:
2781 ++vcpu->stat.mmio_exits;
2782 return 0;
2783 case EMULATE_FAIL:
3f5d18a9
AK		 2784 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2785 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2786 vcpu->run->internal.ndata = 0;
3f5d18a9 2787 return 0;
3067714c
AK		 2788 default:
2789 BUG();
2790 }
2791out:
3067714c
AK		 2792 return r;
2793}
2794EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2795
a7052897
MT		 2796void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2797{
a7052897 2798 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2799 kvm_mmu_flush_tlb(vcpu);
2800 ++vcpu->stat.invlpg;
2801}
2802EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2803
18552672
JR		 2804void kvm_enable_tdp(void)
2805{
2806 tdp_enabled = true;
2807}
2808EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2809
5f4cb662
JR		 2810void kvm_disable_tdp(void)
2811{
2812 tdp_enabled = false;
2813}
2814EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2815
6aa8b732
AK		 2816static void free_mmu_pages(struct kvm_vcpu *vcpu)
2817{
ad312c7c 2818 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2819}
2820
2821static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2822{
17ac10ad 2823 struct page *page;
6aa8b732
AK		 2824 int i;
2825
2826 ASSERT(vcpu);
2827
17ac10ad
AK		 2828 /*
2829 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2830 * Therefore we need to allocate shadow page tables in the first
2831 * 4GB of memory, which happens to fit the DMA32 zone.
2832 */
2833 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2834 if (!page)
d7fa6ab2
WY		 2835 return -ENOMEM;
2836
ad312c7c 2837 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2838 for (i = 0; i < 4; ++i)
ad312c7c 2839 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2840
6aa8b732 2841 return 0;
6aa8b732
AK		 2842}
2843
8018c27b 2844int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2845{
6aa8b732 2846 ASSERT(vcpu);
ad312c7c 2847 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2848
8018c27b
IM		 2849 return alloc_mmu_pages(vcpu);
2850}
6aa8b732 2851
8018c27b
IM		 2852int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2853{
2854 ASSERT(vcpu);
ad312c7c 2855 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2856
8018c27b 2857 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2858}
2859
2860void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2861{
2862 ASSERT(vcpu);
2863
2864 destroy_kvm_mmu(vcpu);
2865 free_mmu_pages(vcpu);
714b93da 2866 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2867}
2868
90cb0529 2869void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2870{
4db35314 2871 struct kvm_mmu_page *sp;
6aa8b732 2872
f05e70ac 2873 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2874 int i;
2875 u64 *pt;
2876
291f26bc 2877 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2878 continue;
2879
4db35314 2880 pt = sp->spt;
6aa8b732
AK		 2881 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2882 /* avoid RMW */
9647c14c 2883 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2884 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2885 }
171d595d 2886 kvm_flush_remote_tlbs(kvm);
6aa8b732 2887}
37a7d8b0 2888
90cb0529 2889void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2890{
4db35314 2891 struct kvm_mmu_page *sp, *node;
e0fa826f 2892
aaee2c94 2893 spin_lock(&kvm->mmu_lock);
f05e70ac 2894 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2895 if (kvm_mmu_zap_page(kvm, sp))
2896 node = container_of(kvm->arch.active_mmu_pages.next,
2897 struct kvm_mmu_page, link);
aaee2c94 2898 spin_unlock(&kvm->mmu_lock);
e0fa826f 2899
90cb0529 2900 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2901}
2902
8b2cf73c 2903static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2904{
2905 struct kvm_mmu_page *page;
2906
2907 page = container_of(kvm->arch.active_mmu_pages.prev,
2908 struct kvm_mmu_page, link);
2909 kvm_mmu_zap_page(kvm, page);
2910}
2911
2912static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2913{
2914 struct kvm *kvm;
2915 struct kvm *kvm_freed = NULL;
2916 int cache_count = 0;
2917
2918 spin_lock(&kvm_lock);
2919
2920 list_for_each_entry(kvm, &vm_list, vm_list) {
f656ce01 2921 int npages, idx;
3ee16c81 2922
f656ce01 2923 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2924 spin_lock(&kvm->mmu_lock);
2925 npages = kvm->arch.n_alloc_mmu_pages -
2926 kvm->arch.n_free_mmu_pages;
2927 cache_count += npages;
2928 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2929 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2930 cache_count--;
2931 kvm_freed = kvm;
2932 }
2933 nr_to_scan--;
2934
2935 spin_unlock(&kvm->mmu_lock);
f656ce01 2936 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2937 }
2938 if (kvm_freed)
2939 list_move_tail(&kvm_freed->vm_list, &vm_list);
2940
2941 spin_unlock(&kvm_lock);
2942
2943 return cache_count;
2944}
2945
2946static struct shrinker mmu_shrinker = {
2947 .shrink = mmu_shrink,
2948 .seeks = DEFAULT_SEEKS * 10,
2949};
2950
2ddfd20e 2951static void mmu_destroy_caches(void)
b5a33a75
AK		 2952{
2953 if (pte_chain_cache)
2954 kmem_cache_destroy(pte_chain_cache);
2955 if (rmap_desc_cache)
2956 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2957 if (mmu_page_header_cache)
2958 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2959}
2960
3ee16c81
IE		 2961void kvm_mmu_module_exit(void)
2962{
2963 mmu_destroy_caches();
2964 unregister_shrinker(&mmu_shrinker);
2965}
2966
b5a33a75
AK		 2967int kvm_mmu_module_init(void)
2968{
2969 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2970 sizeof(struct kvm_pte_chain),
20c2df83 2971 0, 0, NULL);
b5a33a75
AK		 2972 if (!pte_chain_cache)
2973 goto nomem;
2974 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2975 sizeof(struct kvm_rmap_desc),
20c2df83 2976 0, 0, NULL);
b5a33a75
AK		 2977 if (!rmap_desc_cache)
2978 goto nomem;
2979
d3d25b04
AK		 2980 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2981 sizeof(struct kvm_mmu_page),
20c2df83 2982 0, 0, NULL);
d3d25b04
AK		 2983 if (!mmu_page_header_cache)
2984 goto nomem;
2985
3ee16c81
IE		 2986 register_shrinker(&mmu_shrinker);
2987
b5a33a75
AK		 2988 return 0;
2989
2990nomem:
3ee16c81 2991 mmu_destroy_caches();
b5a33a75
AK		 2992 return -ENOMEM;
2993}
2994
3ad82a7e
ZX		 2995/*
2996 * Caculate mmu pages needed for kvm.
2997 */
2998unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
2999{
3000 int i;
3001 unsigned int nr_mmu_pages;
3002 unsigned int nr_pages = 0;
bc6678a3 3003 struct kvm_memslots *slots;
3ad82a7e 3004
bc6678a3
MT		 3005 slots = rcu_dereference(kvm->memslots);
3006 for (i = 0; i < slots->nmemslots; i++)
3007 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3008
3009 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3010 nr_mmu_pages = max(nr_mmu_pages,
3011 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3012
3013 return nr_mmu_pages;
3014}
3015
2f333bcb
MT		 3016static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3017 unsigned len)
3018{
3019 if (len > buffer->len)
3020 return NULL;
3021 return buffer->ptr;
3022}
3023
3024static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3025 unsigned len)
3026{
3027 void *ret;
3028
3029 ret = pv_mmu_peek_buffer(buffer, len);
3030 if (!ret)
3031 return ret;
3032 buffer->ptr += len;
3033 buffer->len -= len;
3034 buffer->processed += len;
3035 return ret;
3036}
3037
3038static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3039 gpa_t addr, gpa_t value)
3040{
3041 int bytes = 8;
3042 int r;
3043
3044 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3045 bytes = 4;
3046
3047 r = mmu_topup_memory_caches(vcpu);
3048 if (r)
3049 return r;
3050
3200f405 3051 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3052 return -EFAULT;
3053
3054 return 1;
3055}
3056
3057static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3058{
a8cd0244 3059 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3060 return 1;
3061}
3062
3063static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3064{
3065 spin_lock(&vcpu->kvm->mmu_lock);
3066 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3067 spin_unlock(&vcpu->kvm->mmu_lock);
3068 return 1;
3069}
3070
3071static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3072 struct kvm_pv_mmu_op_buffer *buffer)
3073{
3074 struct kvm_mmu_op_header *header;
3075
3076 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3077 if (!header)
3078 return 0;
3079 switch (header->op) {
3080 case KVM_MMU_OP_WRITE_PTE: {
3081 struct kvm_mmu_op_write_pte *wpte;
3082
3083 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3084 if (!wpte)
3085 return 0;
3086 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3087 wpte->pte_val);
3088 }
3089 case KVM_MMU_OP_FLUSH_TLB: {
3090 struct kvm_mmu_op_flush_tlb *ftlb;
3091
3092 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3093 if (!ftlb)
3094 return 0;
3095 return kvm_pv_mmu_flush_tlb(vcpu);
3096 }
3097 case KVM_MMU_OP_RELEASE_PT: {
3098 struct kvm_mmu_op_release_pt *rpt;
3099
3100 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3101 if (!rpt)
3102 return 0;
3103 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3104 }
3105 default: return 0;
3106 }
3107}
3108
3109int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3110 gpa_t addr, unsigned long *ret)
3111{
3112 int r;
6ad18fba 3113 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3114
6ad18fba
DH		 3115 buffer->ptr = buffer->buf;
3116 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3117 buffer->processed = 0;
2f333bcb 3118
6ad18fba 3119 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3120 if (r)
3121 goto out;
3122
6ad18fba
DH		 3123 while (buffer->len) {
3124 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3125 if (r < 0)
3126 goto out;
3127 if (r == 0)
3128 break;
3129 }
3130
3131 r = 1;
3132out:
6ad18fba 3133 *ret = buffer->processed;
2f333bcb
MT		 3134 return r;
3135}
3136
94d8b056
MT		 3137int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3138{
3139 struct kvm_shadow_walk_iterator iterator;
3140 int nr_sptes = 0;
3141
3142 spin_lock(&vcpu->kvm->mmu_lock);
3143 for_each_shadow_entry(vcpu, addr, iterator) {
3144 sptes[iterator.level-1] = *iterator.sptep;
3145 nr_sptes++;
3146 if (!is_shadow_present_pte(*iterator.sptep))
3147 break;
3148 }
3149 spin_unlock(&vcpu->kvm->mmu_lock);
3150
3151 return nr_sptes;
3152}
3153EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3154
37a7d8b0
AK		 3155#ifdef AUDIT
3156
3157static const char *audit_msg;
3158
3159static gva_t canonicalize(gva_t gva)
3160{
3161#ifdef CONFIG_X86_64
3162 gva = (long long)(gva << 16) >> 16;
3163#endif
3164 return gva;
3165}
3166
08a3732b
MT		 3167
3168typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3169 u64 *sptep);
3170
3171static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3172 inspect_spte_fn fn)
3173{
3174 int i;
3175
3176 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3177 u64 ent = sp->spt[i];
3178
3179 if (is_shadow_present_pte(ent)) {
2920d728 3180 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3181 struct kvm_mmu_page *child;
3182 child = page_header(ent & PT64_BASE_ADDR_MASK);
3183 __mmu_spte_walk(kvm, child, fn);
2920d728 3184 } else
08a3732b
MT		 3185 fn(kvm, sp, &sp->spt[i]);
3186 }
3187 }
3188}
3189
3190static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3191{
3192 int i;
3193 struct kvm_mmu_page *sp;
3194
3195 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3196 return;
3197 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3198 hpa_t root = vcpu->arch.mmu.root_hpa;
3199 sp = page_header(root);
3200 __mmu_spte_walk(vcpu->kvm, sp, fn);
3201 return;
3202 }
3203 for (i = 0; i < 4; ++i) {
3204 hpa_t root = vcpu->arch.mmu.pae_root[i];
3205
3206 if (root && VALID_PAGE(root)) {
3207 root &= PT64_BASE_ADDR_MASK;
3208 sp = page_header(root);
3209 __mmu_spte_walk(vcpu->kvm, sp, fn);
3210 }
3211 }
3212 return;
3213}
3214
37a7d8b0
AK		 3215static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3216 gva_t va, int level)
3217{
3218 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3219 int i;
3220 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3221
3222 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3223 u64 ent = pt[i];
3224
c7addb90 3225 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3226 continue;
3227
3228 va = canonicalize(va);
2920d728
MT		 3229 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3230 audit_mappings_page(vcpu, ent, va, level - 1);
3231 else {
1871c602 3232 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3233 gfn_t gfn = gpa >> PAGE_SHIFT;
3234 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3235 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3236
2aaf65e8
MT		 3237 if (is_error_pfn(pfn)) {
3238 kvm_release_pfn_clean(pfn);
3239 continue;
3240 }
3241
c7addb90 3242 if (is_shadow_present_pte(ent)
37a7d8b0 3243 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3244 printk(KERN_ERR "xx audit error: (%s) levels %d"
3245 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3246 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3247 va, gpa, hpa, ent,
3248 is_shadow_present_pte(ent));
c7addb90
AK		 3249 else if (ent == shadow_notrap_nonpresent_pte
3250 && !is_error_hpa(hpa))
3251 printk(KERN_ERR "audit: (%s) notrap shadow,"
3252 " valid guest gva %lx\n", audit_msg, va);
35149e21 3253 kvm_release_pfn_clean(pfn);
c7addb90 3254
37a7d8b0
AK		 3255 }
3256 }
3257}
3258
3259static void audit_mappings(struct kvm_vcpu *vcpu)
3260{
1ea252af 3261 unsigned i;
37a7d8b0 3262
ad312c7c
ZX		 3263 if (vcpu->arch.mmu.root_level == 4)
3264 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3265 else
3266 for (i = 0; i < 4; ++i)
ad312c7c 3267 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3268 audit_mappings_page(vcpu,
ad312c7c 3269 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3270 i << 30,
3271 2);
3272}
3273
3274static int count_rmaps(struct kvm_vcpu *vcpu)
3275{
3276 int nmaps = 0;
bc6678a3 3277 int i, j, k, idx;
37a7d8b0 3278
bc6678a3
MT		 3279 idx = srcu_read_lock(&kvm->srcu);
3280 slots = rcu_dereference(kvm->memslots);
37a7d8b0 3281 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3282 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3283 struct kvm_rmap_desc *d;
3284
3285 for (j = 0; j < m->npages; ++j) {
290fc38d 3286 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3287
290fc38d 3288 if (!*rmapp)
37a7d8b0 3289 continue;
290fc38d 3290 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3291 ++nmaps;
3292 continue;
3293 }
290fc38d 3294 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3295 while (d) {
3296 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3297 if (d->sptes[k])
37a7d8b0
AK		 3298 ++nmaps;
3299 else
3300 break;
3301 d = d->more;
3302 }
3303 }
3304 }
bc6678a3 3305 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3306 return nmaps;
3307}
3308
08a3732b
MT		 3309void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3310{
3311 unsigned long *rmapp;
3312 struct kvm_mmu_page *rev_sp;
3313 gfn_t gfn;
3314
3315 if (*sptep & PT_WRITABLE_MASK) {
3316 rev_sp = page_header(__pa(sptep));
3317 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3318
3319 if (!gfn_to_memslot(kvm, gfn)) {
3320 if (!printk_ratelimit())
3321 return;
3322 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3323 audit_msg, gfn);
3324 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3325 audit_msg, sptep - rev_sp->spt,
3326 rev_sp->gfn);
3327 dump_stack();
3328 return;
3329 }
3330
2920d728
MT		 3331 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3332 is_large_pte(*sptep));
08a3732b
MT		 3333 if (!*rmapp) {
3334 if (!printk_ratelimit())
3335 return;
3336 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3337 audit_msg, *sptep);
3338 dump_stack();
3339 }
3340 }
3341
3342}
3343
3344void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3345{
3346 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3347}
3348
3349static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3350{
4db35314 3351 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3352 int i;
3353
f05e70ac 3354 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3355 u64 *pt = sp->spt;
37a7d8b0 3356
4db35314 3357 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3358 continue;
3359
3360 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3361 u64 ent = pt[i];
3362
3363 if (!(ent & PT_PRESENT_MASK))
3364 continue;
3365 if (!(ent & PT_WRITABLE_MASK))
3366 continue;
08a3732b 3367 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3368 }
3369 }
08a3732b 3370 return;
37a7d8b0
AK		 3371}
3372
3373static void audit_rmap(struct kvm_vcpu *vcpu)
3374{
08a3732b
MT		 3375 check_writable_mappings_rmap(vcpu);
3376 count_rmaps(vcpu);
37a7d8b0
AK		 3377}
3378
3379static void audit_write_protection(struct kvm_vcpu *vcpu)
3380{
4db35314 3381 struct kvm_mmu_page *sp;
290fc38d
IE		 3382 struct kvm_memory_slot *slot;
3383 unsigned long *rmapp;
e58b0f9e 3384 u64 *spte;
290fc38d 3385 gfn_t gfn;
37a7d8b0 3386
f05e70ac 3387 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3388 if (sp->role.direct)
37a7d8b0 3389 continue;
e58b0f9e
MT		 3390 if (sp->unsync)
3391 continue;
37a7d8b0 3392
4db35314 3393 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3394 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3395 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3396
3397 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3398 while (spte) {
3399 if (*spte & PT_WRITABLE_MASK)
3400 printk(KERN_ERR "%s: (%s) shadow page has "
3401 "writable mappings: gfn %lx role %x\n",
b8688d51 3402 __func__, audit_msg, sp->gfn,
4db35314 3403 sp->role.word);
e58b0f9e
MT		 3404 spte = rmap_next(vcpu->kvm, rmapp, spte);
3405 }
37a7d8b0
AK		 3406 }
3407}
3408
3409static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3410{
3411 int olddbg = dbg;
3412
3413 dbg = 0;
3414 audit_msg = msg;
3415 audit_rmap(vcpu);
3416 audit_write_protection(vcpu);
2aaf65e8
MT		 3417 if (strcmp("pre pte write", audit_msg) != 0)
3418 audit_mappings(vcpu);
08a3732b 3419 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3420 dbg = olddbg;
3421}
3422
3423#endif
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