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KVM: trace guest fpu loads and unloads
[net-next-2.6.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
6aa8b732 34
e495606d
AK		 35#include <asm/page.h>
36#include <asm/cmpxchg.h>
4e542370 37#include <asm/io.h>
13673a90 38#include <asm/vmx.h>
6aa8b732 39
18552672
JR		 40/*
41 * When setting this variable to true it enables Two-Dimensional-Paging
42 * where the hardware walks 2 page tables:
43 * 1. the guest-virtual to guest-physical
44 * 2. while doing 1. it walks guest-physical to host-physical
45 * If the hardware supports that we don't need to do shadow paging.
46 */
2f333bcb 47bool tdp_enabled = false;
18552672 48
37a7d8b0
AK		 49#undef MMU_DEBUG
50
51#undef AUDIT
52
53#ifdef AUDIT
54static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
55#else
56static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
57#endif
58
59#ifdef MMU_DEBUG
60
61#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
62#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
63
64#else
65
66#define pgprintk(x...) do { } while (0)
67#define rmap_printk(x...) do { } while (0)
68
69#endif
70
71#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 72static int dbg = 0;
73module_param(dbg, bool, 0644);
37a7d8b0 74#endif
6aa8b732 75
582801a9
MT		 76static int oos_shadow = 1;
77module_param(oos_shadow, bool, 0644);
78
d6c69ee9
YD		 79#ifndef MMU_DEBUG
80#define ASSERT(x) do { } while (0)
81#else
6aa8b732
AK		 82#define ASSERT(x) \
83 if (!(x)) { \
84 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
85 __FILE__, __LINE__, #x); \
86 }
d6c69ee9 87#endif
6aa8b732 88
6aa8b732
AK		 89#define PT_FIRST_AVAIL_BITS_SHIFT 9
90#define PT64_SECOND_AVAIL_BITS_SHIFT 52
91
6aa8b732
AK		 92#define VALID_PAGE(x) ((x) != INVALID_PAGE)
93
94#define PT64_LEVEL_BITS 9
95
96#define PT64_LEVEL_SHIFT(level) \
d77c26fc 97 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 98
99#define PT64_LEVEL_MASK(level) \
100 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
101
102#define PT64_INDEX(address, level)\
103 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
104
105
106#define PT32_LEVEL_BITS 10
107
108#define PT32_LEVEL_SHIFT(level) \
d77c26fc 109 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 110
111#define PT32_LEVEL_MASK(level) \
112 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 113#define PT32_LVL_OFFSET_MASK(level) \
114 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 116
117#define PT32_INDEX(address, level)\
118 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
119
120
27aba766 121#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 122#define PT64_DIR_BASE_ADDR_MASK \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 124#define PT64_LVL_ADDR_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
127#define PT64_LVL_OFFSET_MASK(level) \
128 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
129 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 130
131#define PT32_BASE_ADDR_MASK PAGE_MASK
132#define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 134#define PT32_LVL_ADDR_MASK(level) \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT32_LEVEL_BITS))) - 1))
6aa8b732 137
79539cec
AK		 138#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
139 | PT64_NX_MASK)
6aa8b732
AK		 140
141#define PFERR_PRESENT_MASK (1U << 0)
142#define PFERR_WRITE_MASK (1U << 1)
143#define PFERR_USER_MASK (1U << 2)
82725b20 144#define PFERR_RSVD_MASK (1U << 3)
73b1087e 145#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 146
cd4a4e53
AK		 147#define RMAP_EXT 4
148
fe135d2c
AK		 149#define ACC_EXEC_MASK 1
150#define ACC_WRITE_MASK PT_WRITABLE_MASK
151#define ACC_USER_MASK PT_USER_MASK
152#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
153
07420171
AK		 154#define CREATE_TRACE_POINTS
155#include "mmutrace.h"
156
1403283a
IE		 157#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
158
135f8c2b
AK		 159#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
160
cd4a4e53 161struct kvm_rmap_desc {
d555c333 162 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 163 struct kvm_rmap_desc *more;
164};
165
2d11123a
AK		 166struct kvm_shadow_walk_iterator {
167 u64 addr;
168 hpa_t shadow_addr;
169 int level;
170 u64 *sptep;
171 unsigned index;
172};
173
174#define for_each_shadow_entry(_vcpu, _addr, _walker) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)); \
177 shadow_walk_next(&(_walker)))
178
179
4731d4c7
MT		 180struct kvm_unsync_walk {
181 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
182};
183
ad8cfbe3
MT		 184typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
185
b5a33a75
AK		 186static struct kmem_cache *pte_chain_cache;
187static struct kmem_cache *rmap_desc_cache;
d3d25b04 188static struct kmem_cache *mmu_page_header_cache;
b5a33a75 189
c7addb90
AK		 190static u64 __read_mostly shadow_trap_nonpresent_pte;
191static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 192static u64 __read_mostly shadow_base_present_pte;
193static u64 __read_mostly shadow_nx_mask;
194static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
195static u64 __read_mostly shadow_user_mask;
196static u64 __read_mostly shadow_accessed_mask;
197static u64 __read_mostly shadow_dirty_mask;
c7addb90 198
82725b20
DE		 199static inline u64 rsvd_bits(int s, int e)
200{
201 return ((1ULL << (e - s + 1)) - 1) << s;
202}
203
c7addb90
AK		 204void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
205{
206 shadow_trap_nonpresent_pte = trap_pte;
207 shadow_notrap_nonpresent_pte = notrap_pte;
208}
209EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
210
7b52345e
SY		 211void kvm_mmu_set_base_ptes(u64 base_pte)
212{
213 shadow_base_present_pte = base_pte;
214}
215EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
216
217void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 218 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 219{
220 shadow_user_mask = user_mask;
221 shadow_accessed_mask = accessed_mask;
222 shadow_dirty_mask = dirty_mask;
223 shadow_nx_mask = nx_mask;
224 shadow_x_mask = x_mask;
225}
226EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
227
6aa8b732
AK		 228static int is_write_protection(struct kvm_vcpu *vcpu)
229{
4d4ec087 230 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 231}
232
233static int is_cpuid_PSE36(void)
234{
235 return 1;
236}
237
73b1087e
AK		 238static int is_nx(struct kvm_vcpu *vcpu)
239{
f6801dff 240 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 241}
242
c7addb90
AK		 243static int is_shadow_present_pte(u64 pte)
244{
c7addb90
AK		 245 return pte != shadow_trap_nonpresent_pte
246 && pte != shadow_notrap_nonpresent_pte;
247}
248
05da4558
MT		 249static int is_large_pte(u64 pte)
250{
251 return pte & PT_PAGE_SIZE_MASK;
252}
253
8dae4445 254static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 255{
256 return pte & PT_WRITABLE_MASK;
257}
258
43a3795a 259static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 260{
439e218a 261 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 262}
263
43a3795a 264static int is_rmap_spte(u64 pte)
cd4a4e53 265{
4b1a80fa 266 return is_shadow_present_pte(pte);
cd4a4e53
AK		 267}
268
776e6633
MT		 269static int is_last_spte(u64 pte, int level)
270{
271 if (level == PT_PAGE_TABLE_LEVEL)
272 return 1;
852e3c19 273 if (is_large_pte(pte))
776e6633
MT		 274 return 1;
275 return 0;
276}
277
35149e21 278static pfn_t spte_to_pfn(u64 pte)
0b49ea86 279{
35149e21 280 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 281}
282
da928521
AK		 283static gfn_t pse36_gfn_delta(u32 gpte)
284{
285 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
286
287 return (gpte & PT32_DIR_PSE36_MASK) << shift;
288}
289
d555c333 290static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 291{
292#ifdef CONFIG_X86_64
293 set_64bit((unsigned long *)sptep, spte);
294#else
295 set_64bit((unsigned long long *)sptep, spte);
296#endif
297}
298
e2dec939 299static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 300 struct kmem_cache *base_cache, int min)
714b93da
AK		 301{
302 void *obj;
303
304 if (cache->nobjs >= min)
e2dec939 305 return 0;
714b93da 306 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 307 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 308 if (!obj)
e2dec939 309 return -ENOMEM;
714b93da
AK		 310 cache->objects[cache->nobjs++] = obj;
311 }
e2dec939 312 return 0;
714b93da
AK		 313}
314
315static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
316{
317 while (mc->nobjs)
318 kfree(mc->objects[--mc->nobjs]);
319}
320
c1158e63 321static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 322 int min)
c1158e63
AK		 323{
324 struct page *page;
325
326 if (cache->nobjs >= min)
327 return 0;
328 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 329 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 330 if (!page)
331 return -ENOMEM;
332 set_page_private(page, 0);
333 cache->objects[cache->nobjs++] = page_address(page);
334 }
335 return 0;
336}
337
338static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
339{
340 while (mc->nobjs)
c4d198d5 341 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 342}
343
2e3e5882 344static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 345{
e2dec939
AK		 346 int r;
347
ad312c7c 348 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 349 pte_chain_cache, 4);
e2dec939
AK		 350 if (r)
351 goto out;
ad312c7c 352 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 353 rmap_desc_cache, 4);
d3d25b04
AK		 354 if (r)
355 goto out;
ad312c7c 356 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 357 if (r)
358 goto out;
ad312c7c 359 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 360 mmu_page_header_cache, 4);
e2dec939
AK		 361out:
362 return r;
714b93da
AK		 363}
364
365static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
366{
ad312c7c
ZX		 367 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
368 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
369 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
370 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 371}
372
373static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
374 size_t size)
375{
376 void *p;
377
378 BUG_ON(!mc->nobjs);
379 p = mc->objects[--mc->nobjs];
714b93da
AK		 380 return p;
381}
382
714b93da
AK		 383static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
384{
ad312c7c 385 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 386 sizeof(struct kvm_pte_chain));
387}
388
90cb0529 389static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 390{
90cb0529 391 kfree(pc);
714b93da
AK		 392}
393
394static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
395{
ad312c7c 396 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 397 sizeof(struct kvm_rmap_desc));
398}
399
90cb0529 400static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 401{
90cb0529 402 kfree(rd);
714b93da
AK		 403}
404
05da4558
MT		 405/*
406 * Return the pointer to the largepage write count for a given
407 * gfn, handling slots that are not large page aligned.
408 */
d25797b2
JR		 409static int *slot_largepage_idx(gfn_t gfn,
410 struct kvm_memory_slot *slot,
411 int level)
05da4558
MT		 412{
413 unsigned long idx;
414
d25797b2
JR		 415 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
416 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
417 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 418}
419
420static void account_shadowed(struct kvm *kvm, gfn_t gfn)
421{
d25797b2 422 struct kvm_memory_slot *slot;
05da4558 423 int *write_count;
d25797b2 424 int i;
05da4558 425
2843099f 426 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 427
428 slot = gfn_to_memslot_unaliased(kvm, gfn);
429 for (i = PT_DIRECTORY_LEVEL;
430 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
431 write_count = slot_largepage_idx(gfn, slot, i);
432 *write_count += 1;
433 }
05da4558
MT		 434}
435
436static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
437{
d25797b2 438 struct kvm_memory_slot *slot;
05da4558 439 int *write_count;
d25797b2 440 int i;
05da4558 441
2843099f 442 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 443 for (i = PT_DIRECTORY_LEVEL;
444 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
445 slot = gfn_to_memslot_unaliased(kvm, gfn);
446 write_count = slot_largepage_idx(gfn, slot, i);
447 *write_count -= 1;
448 WARN_ON(*write_count < 0);
449 }
05da4558
MT		 450}
451
d25797b2
JR		 452static int has_wrprotected_page(struct kvm *kvm,
453 gfn_t gfn,
454 int level)
05da4558 455{
2843099f 456 struct kvm_memory_slot *slot;
05da4558
MT		 457 int *largepage_idx;
458
2843099f
IE		 459 gfn = unalias_gfn(kvm, gfn);
460 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 461 if (slot) {
d25797b2 462 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 463 return *largepage_idx;
464 }
465
466 return 1;
467}
468
d25797b2 469static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 470{
d25797b2 471 unsigned long page_size = PAGE_SIZE;
05da4558
MT		 472 struct vm_area_struct *vma;
473 unsigned long addr;
d25797b2 474 int i, ret = 0;
05da4558
MT		 475
476 addr = gfn_to_hva(kvm, gfn);
477 if (kvm_is_error_hva(addr))
82b7005f 478 return PT_PAGE_TABLE_LEVEL;
05da4558 479
4c2155ce 480 down_read(&current->mm->mmap_sem);
05da4558 481 vma = find_vma(current->mm, addr);
d25797b2
JR		 482 if (!vma)
483 goto out;
484
485 page_size = vma_kernel_pagesize(vma);
486
487out:
4c2155ce 488 up_read(&current->mm->mmap_sem);
05da4558 489
d25797b2
JR		 490 for (i = PT_PAGE_TABLE_LEVEL;
491 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
492 if (page_size >= KVM_HPAGE_SIZE(i))
493 ret = i;
494 else
495 break;
496 }
497
4c2155ce 498 return ret;
05da4558
MT		 499}
500
d25797b2 501static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 502{
503 struct kvm_memory_slot *slot;
878403b7 504 int host_level, level, max_level;
05da4558
MT		 505
506 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
507 if (slot && slot->dirty_bitmap)
d25797b2 508 return PT_PAGE_TABLE_LEVEL;
05da4558 509
d25797b2
JR		 510 host_level = host_mapping_level(vcpu->kvm, large_gfn);
511
512 if (host_level == PT_PAGE_TABLE_LEVEL)
513 return host_level;
514
878403b7
SY		 515 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
516 kvm_x86_ops->get_lpage_level() : host_level;
517
518 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 519 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
520 break;
d25797b2
JR		 521
522 return level - 1;
05da4558
MT		 523}
524
290fc38d
IE		 525/*
526 * Take gfn and return the reverse mapping to it.
527 * Note: gfn must be unaliased before this function get called
528 */
529
44ad9944 530static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 531{
532 struct kvm_memory_slot *slot;
05da4558 533 unsigned long idx;
290fc38d
IE		 534
535 slot = gfn_to_memslot(kvm, gfn);
44ad9944 536 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 537 return &slot->rmap[gfn - slot->base_gfn];
538
44ad9944
JR		 539 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
540 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 541
44ad9944 542 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 543}
544
cd4a4e53
AK		 545/*
546 * Reverse mapping data structures:
547 *
290fc38d
IE		 548 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
549 * that points to page_address(page).
cd4a4e53 550 *
290fc38d
IE		 551 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
552 * containing more mappings.
53a27b39
MT		 553 *
554 * Returns the number of rmap entries before the spte was added or zero if
555 * the spte was not added.
556 *
cd4a4e53 557 */
44ad9944 558static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 559{
4db35314 560 struct kvm_mmu_page *sp;
cd4a4e53 561 struct kvm_rmap_desc *desc;
290fc38d 562 unsigned long *rmapp;
53a27b39 563 int i, count = 0;
cd4a4e53 564
43a3795a 565 if (!is_rmap_spte(*spte))
53a27b39 566 return count;
290fc38d 567 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 568 sp = page_header(__pa(spte));
569 sp->gfns[spte - sp->spt] = gfn;
44ad9944 570 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 571 if (!*rmapp) {
cd4a4e53 572 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 573 *rmapp = (unsigned long)spte;
574 } else if (!(*rmapp & 1)) {
cd4a4e53 575 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 576 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 577 desc->sptes[0] = (u64 *)*rmapp;
578 desc->sptes[1] = spte;
290fc38d 579 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 580 } else {
581 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 582 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 583 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 584 desc = desc->more;
53a27b39
MT		 585 count += RMAP_EXT;
586 }
d555c333 587 if (desc->sptes[RMAP_EXT-1]) {
714b93da 588 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 589 desc = desc->more;
590 }
d555c333 591 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 592 ;
d555c333 593 desc->sptes[i] = spte;
cd4a4e53 594 }
53a27b39 595 return count;
cd4a4e53
AK		 596}
597
290fc38d 598static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 599 struct kvm_rmap_desc *desc,
600 int i,
601 struct kvm_rmap_desc *prev_desc)
602{
603 int j;
604
d555c333 605 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 606 ;
d555c333
AK		 607 desc->sptes[i] = desc->sptes[j];
608 desc->sptes[j] = NULL;
cd4a4e53
AK		 609 if (j != 0)
610 return;
611 if (!prev_desc && !desc->more)
d555c333 612 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 613 else
614 if (prev_desc)
615 prev_desc->more = desc->more;
616 else
290fc38d 617 *rmapp = (unsigned long)desc->more | 1;
90cb0529 618 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 619}
620
290fc38d 621static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 622{
cd4a4e53
AK		 623 struct kvm_rmap_desc *desc;
624 struct kvm_rmap_desc *prev_desc;
4db35314 625 struct kvm_mmu_page *sp;
35149e21 626 pfn_t pfn;
290fc38d 627 unsigned long *rmapp;
cd4a4e53
AK		 628 int i;
629
43a3795a 630 if (!is_rmap_spte(*spte))
cd4a4e53 631 return;
4db35314 632 sp = page_header(__pa(spte));
35149e21 633 pfn = spte_to_pfn(*spte);
7b52345e 634 if (*spte & shadow_accessed_mask)
35149e21 635 kvm_set_pfn_accessed(pfn);
8dae4445 636 if (is_writable_pte(*spte))
acb66dd0 637 kvm_set_pfn_dirty(pfn);
44ad9944 638 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 639 if (!*rmapp) {
cd4a4e53
AK		 640 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
641 BUG();
290fc38d 642 } else if (!(*rmapp & 1)) {
cd4a4e53 643 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 644 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 645 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
646 spte, *spte);
647 BUG();
648 }
290fc38d 649 *rmapp = 0;
cd4a4e53
AK		 650 } else {
651 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 652 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 653 prev_desc = NULL;
654 while (desc) {
d555c333
AK		 655 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
656 if (desc->sptes[i] == spte) {
290fc38d 657 rmap_desc_remove_entry(rmapp,
714b93da 658 desc, i,
cd4a4e53
AK		 659 prev_desc);
660 return;
661 }
662 prev_desc = desc;
663 desc = desc->more;
664 }
186a3e52 665 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 666 BUG();
667 }
668}
669
98348e95 670static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 671{
374cbac0 672 struct kvm_rmap_desc *desc;
98348e95
IE		 673 struct kvm_rmap_desc *prev_desc;
674 u64 *prev_spte;
675 int i;
676
677 if (!*rmapp)
678 return NULL;
679 else if (!(*rmapp & 1)) {
680 if (!spte)
681 return (u64 *)*rmapp;
682 return NULL;
683 }
684 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
685 prev_desc = NULL;
686 prev_spte = NULL;
687 while (desc) {
d555c333 688 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 689 if (prev_spte == spte)
d555c333
AK		 690 return desc->sptes[i];
691 prev_spte = desc->sptes[i];
98348e95
IE		 692 }
693 desc = desc->more;
694 }
695 return NULL;
696}
697
b1a36821 698static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 699{
290fc38d 700 unsigned long *rmapp;
374cbac0 701 u64 *spte;
44ad9944 702 int i, write_protected = 0;
374cbac0 703
4a4c9924 704 gfn = unalias_gfn(kvm, gfn);
44ad9944 705 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 706
98348e95
IE		 707 spte = rmap_next(kvm, rmapp, NULL);
708 while (spte) {
374cbac0 709 BUG_ON(!spte);
374cbac0 710 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 711 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 712 if (is_writable_pte(*spte)) {
d555c333 713 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 714 write_protected = 1;
715 }
9647c14c 716 spte = rmap_next(kvm, rmapp, spte);
374cbac0 717 }
855149aa 718 if (write_protected) {
35149e21 719 pfn_t pfn;
855149aa
IE		 720
721 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 722 pfn = spte_to_pfn(*spte);
723 kvm_set_pfn_dirty(pfn);
855149aa
IE		 724 }
725
05da4558 726 /* check for huge page mappings */
44ad9944
JR		 727 for (i = PT_DIRECTORY_LEVEL;
728 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
729 rmapp = gfn_to_rmap(kvm, gfn, i);
730 spte = rmap_next(kvm, rmapp, NULL);
731 while (spte) {
732 BUG_ON(!spte);
733 BUG_ON(!(*spte & PT_PRESENT_MASK));
734 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
735 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 736 if (is_writable_pte(*spte)) {
44ad9944
JR		 737 rmap_remove(kvm, spte);
738 --kvm->stat.lpages;
739 __set_spte(spte, shadow_trap_nonpresent_pte);
740 spte = NULL;
741 write_protected = 1;
742 }
743 spte = rmap_next(kvm, rmapp, spte);
05da4558 744 }
05da4558
MT		 745 }
746
b1a36821 747 return write_protected;
374cbac0
AK		 748}
749
8a8365c5
FD		 750static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
751 unsigned long data)
e930bffe
AA		 752{
753 u64 *spte;
754 int need_tlb_flush = 0;
755
756 while ((spte = rmap_next(kvm, rmapp, NULL))) {
757 BUG_ON(!(*spte & PT_PRESENT_MASK));
758 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
759 rmap_remove(kvm, spte);
d555c333 760 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 761 need_tlb_flush = 1;
762 }
763 return need_tlb_flush;
764}
765
8a8365c5
FD		 766static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
767 unsigned long data)
3da0dd43
IE		 768{
769 int need_flush = 0;
770 u64 *spte, new_spte;
771 pte_t *ptep = (pte_t *)data;
772 pfn_t new_pfn;
773
774 WARN_ON(pte_huge(*ptep));
775 new_pfn = pte_pfn(*ptep);
776 spte = rmap_next(kvm, rmapp, NULL);
777 while (spte) {
778 BUG_ON(!is_shadow_present_pte(*spte));
779 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
780 need_flush = 1;
781 if (pte_write(*ptep)) {
782 rmap_remove(kvm, spte);
783 __set_spte(spte, shadow_trap_nonpresent_pte);
784 spte = rmap_next(kvm, rmapp, NULL);
785 } else {
786 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
787 new_spte |= (u64)new_pfn << PAGE_SHIFT;
788
789 new_spte &= ~PT_WRITABLE_MASK;
790 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 791 if (is_writable_pte(*spte))
3da0dd43
IE		 792 kvm_set_pfn_dirty(spte_to_pfn(*spte));
793 __set_spte(spte, new_spte);
794 spte = rmap_next(kvm, rmapp, spte);
795 }
796 }
797 if (need_flush)
798 kvm_flush_remote_tlbs(kvm);
799
800 return 0;
801}
802
8a8365c5
FD		 803static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
804 unsigned long data,
3da0dd43 805 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 806 unsigned long data))
e930bffe 807{
852e3c19 808 int i, j;
e930bffe 809 int retval = 0;
bc6678a3
MT		 810 struct kvm_memslots *slots;
811
812 slots = rcu_dereference(kvm->memslots);
e930bffe 813
46a26bf5
MT		 814 for (i = 0; i < slots->nmemslots; i++) {
815 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 816 unsigned long start = memslot->userspace_addr;
817 unsigned long end;
818
e930bffe
AA		 819 end = start + (memslot->npages << PAGE_SHIFT);
820 if (hva >= start && hva < end) {
821 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 822
3da0dd43
IE		 823 retval |= handler(kvm, &memslot->rmap[gfn_offset],
824 data);
852e3c19
JR		 825
826 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
827 int idx = gfn_offset;
828 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
829 retval |= handler(kvm,
3da0dd43
IE		 830 &memslot->lpage_info[j][idx].rmap_pde,
831 data);
852e3c19 832 }
e930bffe
AA		 833 }
834 }
835
836 return retval;
837}
838
839int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
840{
3da0dd43
IE		 841 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
842}
843
844void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
845{
8a8365c5 846 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 847}
848
8a8365c5
FD		 849static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
850 unsigned long data)
e930bffe
AA		 851{
852 u64 *spte;
853 int young = 0;
854
534e38b4
SY		 855 /* always return old for EPT */
856 if (!shadow_accessed_mask)
857 return 0;
858
e930bffe
AA		 859 spte = rmap_next(kvm, rmapp, NULL);
860 while (spte) {
861 int _young;
862 u64 _spte = *spte;
863 BUG_ON(!(_spte & PT_PRESENT_MASK));
864 _young = _spte & PT_ACCESSED_MASK;
865 if (_young) {
866 young = 1;
867 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
868 }
869 spte = rmap_next(kvm, rmapp, spte);
870 }
871 return young;
872}
873
53a27b39
MT		 874#define RMAP_RECYCLE_THRESHOLD 1000
875
852e3c19 876static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 877{
878 unsigned long *rmapp;
852e3c19
JR		 879 struct kvm_mmu_page *sp;
880
881 sp = page_header(__pa(spte));
53a27b39
MT		 882
883 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 884 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 885
3da0dd43 886 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 887 kvm_flush_remote_tlbs(vcpu->kvm);
888}
889
e930bffe
AA		 890int kvm_age_hva(struct kvm *kvm, unsigned long hva)
891{
3da0dd43 892 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 893}
894
d6c69ee9 895#ifdef MMU_DEBUG
47ad8e68 896static int is_empty_shadow_page(u64 *spt)
6aa8b732 897{
139bdb2d
AK		 898 u64 *pos;
899 u64 *end;
900
47ad8e68 901 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 902 if (is_shadow_present_pte(*pos)) {
b8688d51 903 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 904 pos, *pos);
6aa8b732 905 return 0;
139bdb2d 906 }
6aa8b732
AK		 907 return 1;
908}
d6c69ee9 909#endif
6aa8b732 910
4db35314 911static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 912{
4db35314
AK		 913 ASSERT(is_empty_shadow_page(sp->spt));
914 list_del(&sp->link);
915 __free_page(virt_to_page(sp->spt));
916 __free_page(virt_to_page(sp->gfns));
917 kfree(sp);
f05e70ac 918 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 919}
920
cea0f0e7
AK		 921static unsigned kvm_page_table_hashfn(gfn_t gfn)
922{
1ae0a13d 923 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 924}
925
25c0de2c
AK		 926static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
927 u64 *parent_pte)
6aa8b732 928{
4db35314 929 struct kvm_mmu_page *sp;
6aa8b732 930
ad312c7c
ZX		 931 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
932 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
933 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 934 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 935 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 936 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 937 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 938 sp->multimapped = 0;
939 sp->parent_pte = parent_pte;
f05e70ac 940 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 941 return sp;
6aa8b732
AK		 942}
943
714b93da 944static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 945 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 946{
947 struct kvm_pte_chain *pte_chain;
948 struct hlist_node *node;
949 int i;
950
951 if (!parent_pte)
952 return;
4db35314
AK		 953 if (!sp->multimapped) {
954 u64 *old = sp->parent_pte;
cea0f0e7
AK		 955
956 if (!old) {
4db35314 957 sp->parent_pte = parent_pte;
cea0f0e7
AK		 958 return;
959 }
4db35314 960 sp->multimapped = 1;
714b93da 961 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 962 INIT_HLIST_HEAD(&sp->parent_ptes);
963 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 964 pte_chain->parent_ptes[0] = old;
965 }
4db35314 966 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 967 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
968 continue;
969 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
970 if (!pte_chain->parent_ptes[i]) {
971 pte_chain->parent_ptes[i] = parent_pte;
972 return;
973 }
974 }
714b93da 975 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 976 BUG_ON(!pte_chain);
4db35314 977 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 978 pte_chain->parent_ptes[0] = parent_pte;
979}
980
4db35314 981static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 982 u64 *parent_pte)
983{
984 struct kvm_pte_chain *pte_chain;
985 struct hlist_node *node;
986 int i;
987
4db35314
AK		 988 if (!sp->multimapped) {
989 BUG_ON(sp->parent_pte != parent_pte);
990 sp->parent_pte = NULL;
cea0f0e7
AK		 991 return;
992 }
4db35314 993 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 994 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
995 if (!pte_chain->parent_ptes[i])
996 break;
997 if (pte_chain->parent_ptes[i] != parent_pte)
998 continue;
697fe2e2
AK		 999 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1000 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 1001 pte_chain->parent_ptes[i]
1002 = pte_chain->parent_ptes[i + 1];
1003 ++i;
1004 }
1005 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 1006 if (i == 0) {
1007 hlist_del(&pte_chain->link);
90cb0529 1008 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1009 if (hlist_empty(&sp->parent_ptes)) {
1010 sp->multimapped = 0;
1011 sp->parent_pte = NULL;
697fe2e2
AK		 1012 }
1013 }
cea0f0e7
AK		 1014 return;
1015 }
1016 BUG();
1017}
1018
ad8cfbe3
MT		 1019
1020static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1021 mmu_parent_walk_fn fn)
1022{
1023 struct kvm_pte_chain *pte_chain;
1024 struct hlist_node *node;
1025 struct kvm_mmu_page *parent_sp;
1026 int i;
1027
1028 if (!sp->multimapped && sp->parent_pte) {
1029 parent_sp = page_header(__pa(sp->parent_pte));
1030 fn(vcpu, parent_sp);
1031 mmu_parent_walk(vcpu, parent_sp, fn);
1032 return;
1033 }
1034 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1035 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1036 if (!pte_chain->parent_ptes[i])
1037 break;
1038 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1039 fn(vcpu, parent_sp);
1040 mmu_parent_walk(vcpu, parent_sp, fn);
1041 }
1042}
1043
0074ff63
MT		 1044static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1045{
1046 unsigned int index;
1047 struct kvm_mmu_page *sp = page_header(__pa(spte));
1048
1049 index = spte - sp->spt;
60c8aec6
MT		 1050 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1051 sp->unsync_children++;
1052 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1053}
1054
1055static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1056{
1057 struct kvm_pte_chain *pte_chain;
1058 struct hlist_node *node;
1059 int i;
1060
1061 if (!sp->parent_pte)
1062 return;
1063
1064 if (!sp->multimapped) {
1065 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1066 return;
1067 }
1068
1069 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1070 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1071 if (!pte_chain->parent_ptes[i])
1072 break;
1073 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1074 }
1075}
1076
1077static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1078{
0074ff63
MT		 1079 kvm_mmu_update_parents_unsync(sp);
1080 return 1;
1081}
1082
1083static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1084 struct kvm_mmu_page *sp)
1085{
1086 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1087 kvm_mmu_update_parents_unsync(sp);
1088}
1089
d761a501
AK		 1090static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1091 struct kvm_mmu_page *sp)
1092{
1093 int i;
1094
1095 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1096 sp->spt[i] = shadow_trap_nonpresent_pte;
1097}
1098
e8bc217a
MT		 1099static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1100 struct kvm_mmu_page *sp)
1101{
1102 return 1;
1103}
1104
a7052897
MT		 1105static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1106{
1107}
1108
60c8aec6
MT		 1109#define KVM_PAGE_ARRAY_NR 16
1110
1111struct kvm_mmu_pages {
1112 struct mmu_page_and_offset {
1113 struct kvm_mmu_page *sp;
1114 unsigned int idx;
1115 } page[KVM_PAGE_ARRAY_NR];
1116 unsigned int nr;
1117};
1118
0074ff63
MT		 1119#define for_each_unsync_children(bitmap, idx) \
1120 for (idx = find_first_bit(bitmap, 512); \
1121 idx < 512; \
1122 idx = find_next_bit(bitmap, 512, idx+1))
1123
cded19f3
HE		 1124static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1125 int idx)
4731d4c7 1126{
60c8aec6 1127 int i;
4731d4c7 1128
60c8aec6
MT		 1129 if (sp->unsync)
1130 for (i=0; i < pvec->nr; i++)
1131 if (pvec->page[i].sp == sp)
1132 return 0;
1133
1134 pvec->page[pvec->nr].sp = sp;
1135 pvec->page[pvec->nr].idx = idx;
1136 pvec->nr++;
1137 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1138}
1139
1140static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1141 struct kvm_mmu_pages *pvec)
1142{
1143 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1144
0074ff63 1145 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1146 u64 ent = sp->spt[i];
1147
87917239 1148 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1149 struct kvm_mmu_page *child;
1150 child = page_header(ent & PT64_BASE_ADDR_MASK);
1151
1152 if (child->unsync_children) {
60c8aec6
MT		 1153 if (mmu_pages_add(pvec, child, i))
1154 return -ENOSPC;
1155
1156 ret = __mmu_unsync_walk(child, pvec);
1157 if (!ret)
1158 __clear_bit(i, sp->unsync_child_bitmap);
1159 else if (ret > 0)
1160 nr_unsync_leaf += ret;
1161 else
4731d4c7
MT		 1162 return ret;
1163 }
1164
1165 if (child->unsync) {
60c8aec6
MT		 1166 nr_unsync_leaf++;
1167 if (mmu_pages_add(pvec, child, i))
1168 return -ENOSPC;
4731d4c7
MT		 1169 }
1170 }
1171 }
1172
0074ff63 1173 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1174 sp->unsync_children = 0;
1175
60c8aec6
MT		 1176 return nr_unsync_leaf;
1177}
1178
1179static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1180 struct kvm_mmu_pages *pvec)
1181{
1182 if (!sp->unsync_children)
1183 return 0;
1184
1185 mmu_pages_add(pvec, sp, 0);
1186 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1187}
1188
4db35314 1189static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1190{
1191 unsigned index;
1192 struct hlist_head *bucket;
4db35314 1193 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1194 struct hlist_node *node;
1195
b8688d51 1196 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1197 index = kvm_page_table_hashfn(gfn);
f05e70ac 1198 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1199 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1200 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1201 && !sp->role.invalid) {
cea0f0e7 1202 pgprintk("%s: found role %x\n",
b8688d51 1203 __func__, sp->role.word);
4db35314 1204 return sp;
cea0f0e7
AK		 1205 }
1206 return NULL;
1207}
1208
4731d4c7
MT		 1209static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1210{
1211 WARN_ON(!sp->unsync);
1212 sp->unsync = 0;
1213 --kvm->stat.mmu_unsync;
1214}
1215
1216static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1217
1218static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1219{
1220 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1221 kvm_mmu_zap_page(vcpu->kvm, sp);
1222 return 1;
1223 }
1224
f691fe1d 1225 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1226 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1227 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1228 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1229 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1230 kvm_mmu_zap_page(vcpu->kvm, sp);
1231 return 1;
1232 }
1233
1234 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1235 return 0;
1236}
1237
60c8aec6
MT		 1238struct mmu_page_path {
1239 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1240 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1241};
1242
60c8aec6
MT		 1243#define for_each_sp(pvec, sp, parents, i) \
1244 for (i = mmu_pages_next(&pvec, &parents, -1), \
1245 sp = pvec.page[i].sp; \
1246 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1247 i = mmu_pages_next(&pvec, &parents, i))
1248
cded19f3
HE		 1249static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1250 struct mmu_page_path *parents,
1251 int i)
60c8aec6
MT		 1252{
1253 int n;
1254
1255 for (n = i+1; n < pvec->nr; n++) {
1256 struct kvm_mmu_page *sp = pvec->page[n].sp;
1257
1258 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1259 parents->idx[0] = pvec->page[n].idx;
1260 return n;
1261 }
1262
1263 parents->parent[sp->role.level-2] = sp;
1264 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1265 }
1266
1267 return n;
1268}
1269
cded19f3 1270static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1271{
60c8aec6
MT		 1272 struct kvm_mmu_page *sp;
1273 unsigned int level = 0;
1274
1275 do {
1276 unsigned int idx = parents->idx[level];
4731d4c7 1277
60c8aec6
MT		 1278 sp = parents->parent[level];
1279 if (!sp)
1280 return;
1281
1282 --sp->unsync_children;
1283 WARN_ON((int)sp->unsync_children < 0);
1284 __clear_bit(idx, sp->unsync_child_bitmap);
1285 level++;
1286 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1287}
1288
60c8aec6
MT		 1289static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1290 struct mmu_page_path *parents,
1291 struct kvm_mmu_pages *pvec)
4731d4c7 1292{
60c8aec6
MT		 1293 parents->parent[parent->role.level-1] = NULL;
1294 pvec->nr = 0;
1295}
4731d4c7 1296
60c8aec6
MT		 1297static void mmu_sync_children(struct kvm_vcpu *vcpu,
1298 struct kvm_mmu_page *parent)
1299{
1300 int i;
1301 struct kvm_mmu_page *sp;
1302 struct mmu_page_path parents;
1303 struct kvm_mmu_pages pages;
1304
1305 kvm_mmu_pages_init(parent, &parents, &pages);
1306 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1307 int protected = 0;
1308
1309 for_each_sp(pages, sp, parents, i)
1310 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1311
1312 if (protected)
1313 kvm_flush_remote_tlbs(vcpu->kvm);
1314
60c8aec6
MT		 1315 for_each_sp(pages, sp, parents, i) {
1316 kvm_sync_page(vcpu, sp);
1317 mmu_pages_clear_parents(&parents);
1318 }
4731d4c7 1319 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1320 kvm_mmu_pages_init(parent, &parents, &pages);
1321 }
4731d4c7
MT		 1322}
1323
cea0f0e7
AK		 1324static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1325 gfn_t gfn,
1326 gva_t gaddr,
1327 unsigned level,
f6e2c02b 1328 int direct,
41074d07 1329 unsigned access,
f7d9c7b7 1330 u64 *parent_pte)
cea0f0e7
AK		 1331{
1332 union kvm_mmu_page_role role;
1333 unsigned index;
1334 unsigned quadrant;
1335 struct hlist_head *bucket;
4db35314 1336 struct kvm_mmu_page *sp;
4731d4c7 1337 struct hlist_node *node, *tmp;
cea0f0e7 1338
a770f6f2 1339 role = vcpu->arch.mmu.base_role;
cea0f0e7 1340 role.level = level;
f6e2c02b 1341 role.direct = direct;
41074d07 1342 role.access = access;
ad312c7c 1343 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1344 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1345 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1346 role.quadrant = quadrant;
1347 }
1ae0a13d 1348 index = kvm_page_table_hashfn(gfn);
f05e70ac 1349 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1350 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1351 if (sp->gfn == gfn) {
1352 if (sp->unsync)
1353 if (kvm_sync_page(vcpu, sp))
1354 continue;
1355
1356 if (sp->role.word != role.word)
1357 continue;
1358
4db35314 1359 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1360 if (sp->unsync_children) {
1361 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1362 kvm_mmu_mark_parents_unsync(vcpu, sp);
1363 }
f691fe1d 1364 trace_kvm_mmu_get_page(sp, false);
4db35314 1365 return sp;
cea0f0e7 1366 }
dfc5aa00 1367 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1368 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1369 if (!sp)
1370 return sp;
4db35314
AK		 1371 sp->gfn = gfn;
1372 sp->role = role;
1373 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1374 if (!direct) {
b1a36821
MT		 1375 if (rmap_write_protect(vcpu->kvm, gfn))
1376 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1377 account_shadowed(vcpu->kvm, gfn);
1378 }
131d8279
AK		 1379 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1380 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1381 else
1382 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1383 trace_kvm_mmu_get_page(sp, true);
4db35314 1384 return sp;
cea0f0e7
AK		 1385}
1386
2d11123a
AK		 1387static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1388 struct kvm_vcpu *vcpu, u64 addr)
1389{
1390 iterator->addr = addr;
1391 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1392 iterator->level = vcpu->arch.mmu.shadow_root_level;
1393 if (iterator->level == PT32E_ROOT_LEVEL) {
1394 iterator->shadow_addr
1395 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1396 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1397 --iterator->level;
1398 if (!iterator->shadow_addr)
1399 iterator->level = 0;
1400 }
1401}
1402
1403static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1404{
1405 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1406 return false;
4d88954d
MT		 1407
1408 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1409 if (is_large_pte(*iterator->sptep))
1410 return false;
1411
2d11123a
AK		 1412 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1413 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1414 return true;
1415}
1416
1417static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1418{
1419 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1420 --iterator->level;
1421}
1422
90cb0529 1423static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1424 struct kvm_mmu_page *sp)
a436036b 1425{
697fe2e2
AK		 1426 unsigned i;
1427 u64 *pt;
1428 u64 ent;
1429
4db35314 1430 pt = sp->spt;
697fe2e2 1431
697fe2e2
AK		 1432 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1433 ent = pt[i];
1434
05da4558 1435 if (is_shadow_present_pte(ent)) {
776e6633 1436 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1437 ent &= PT64_BASE_ADDR_MASK;
1438 mmu_page_remove_parent_pte(page_header(ent),
1439 &pt[i]);
1440 } else {
776e6633
MT		 1441 if (is_large_pte(ent))
1442 --kvm->stat.lpages;
05da4558
MT		 1443 rmap_remove(kvm, &pt[i]);
1444 }
1445 }
c7addb90 1446 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1447 }
a436036b
AK		 1448}
1449
4db35314 1450static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1451{
4db35314 1452 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1453}
1454
12b7d28f
AK		 1455static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1456{
1457 int i;
988a2cae 1458 struct kvm_vcpu *vcpu;
12b7d28f 1459
988a2cae
GN		 1460 kvm_for_each_vcpu(i, vcpu, kvm)
1461 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1462}
1463
31aa2b44 1464static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1465{
1466 u64 *parent_pte;
1467
4db35314
AK		 1468 while (sp->multimapped || sp->parent_pte) {
1469 if (!sp->multimapped)
1470 parent_pte = sp->parent_pte;
a436036b
AK		 1471 else {
1472 struct kvm_pte_chain *chain;
1473
4db35314 1474 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1475 struct kvm_pte_chain, link);
1476 parent_pte = chain->parent_ptes[0];
1477 }
697fe2e2 1478 BUG_ON(!parent_pte);
4db35314 1479 kvm_mmu_put_page(sp, parent_pte);
d555c333 1480 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1481 }
31aa2b44
AK		 1482}
1483
60c8aec6
MT		 1484static int mmu_zap_unsync_children(struct kvm *kvm,
1485 struct kvm_mmu_page *parent)
4731d4c7 1486{
60c8aec6
MT		 1487 int i, zapped = 0;
1488 struct mmu_page_path parents;
1489 struct kvm_mmu_pages pages;
4731d4c7 1490
60c8aec6 1491 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1492 return 0;
60c8aec6
MT		 1493
1494 kvm_mmu_pages_init(parent, &parents, &pages);
1495 while (mmu_unsync_walk(parent, &pages)) {
1496 struct kvm_mmu_page *sp;
1497
1498 for_each_sp(pages, sp, parents, i) {
1499 kvm_mmu_zap_page(kvm, sp);
1500 mmu_pages_clear_parents(&parents);
1501 }
1502 zapped += pages.nr;
1503 kvm_mmu_pages_init(parent, &parents, &pages);
1504 }
1505
1506 return zapped;
4731d4c7
MT		 1507}
1508
07385413 1509static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1510{
4731d4c7 1511 int ret;
f691fe1d
AK		 1512
1513 trace_kvm_mmu_zap_page(sp);
31aa2b44 1514 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1515 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1516 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1517 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1518 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1519 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1520 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1521 if (sp->unsync)
1522 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1523 if (!sp->root_count) {
1524 hlist_del(&sp->hash_link);
1525 kvm_mmu_free_page(kvm, sp);
2e53d63a 1526 } else {
2e53d63a 1527 sp->role.invalid = 1;
5b5c6a5a 1528 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1529 kvm_reload_remote_mmus(kvm);
1530 }
12b7d28f 1531 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1532 return ret;
a436036b
AK		 1533}
1534
82ce2c96
IE		 1535/*
1536 * Changing the number of mmu pages allocated to the vm
1537 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1538 */
1539void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1540{
025dbbf3
MT		 1541 int used_pages;
1542
1543 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1544 used_pages = max(0, used_pages);
1545
82ce2c96
IE		 1546 /*
1547 * If we set the number of mmu pages to be smaller be than the
1548 * number of actived pages , we must to free some mmu pages before we
1549 * change the value
1550 */
1551
025dbbf3
MT		 1552 if (used_pages > kvm_nr_mmu_pages) {
1553 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1554 struct kvm_mmu_page *page;
1555
f05e70ac 1556 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1557 struct kvm_mmu_page, link);
1558 kvm_mmu_zap_page(kvm, page);
025dbbf3 1559 used_pages--;
82ce2c96 1560 }
f05e70ac 1561 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1562 }
1563 else
f05e70ac
ZX		 1564 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1565 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1566
f05e70ac 1567 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1568}
1569
f67a46f4 1570static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1571{
1572 unsigned index;
1573 struct hlist_head *bucket;
4db35314 1574 struct kvm_mmu_page *sp;
a436036b
AK		 1575 struct hlist_node *node, *n;
1576 int r;
1577
b8688d51 1578 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1579 r = 0;
1ae0a13d 1580 index = kvm_page_table_hashfn(gfn);
f05e70ac 1581 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1582 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1583 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1584 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1585 sp->role.word);
a436036b 1586 r = 1;
07385413
MT		 1587 if (kvm_mmu_zap_page(kvm, sp))
1588 n = bucket->first;
a436036b
AK		 1589 }
1590 return r;
cea0f0e7
AK		 1591}
1592
f67a46f4 1593static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1594{
4677a3b6
AK		 1595 unsigned index;
1596 struct hlist_head *bucket;
4db35314 1597 struct kvm_mmu_page *sp;
4677a3b6 1598 struct hlist_node *node, *nn;
97a0a01e 1599
4677a3b6
AK		 1600 index = kvm_page_table_hashfn(gfn);
1601 bucket = &kvm->arch.mmu_page_hash[index];
1602 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1603 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1604 && !sp->role.invalid) {
1605 pgprintk("%s: zap %lx %x\n",
1606 __func__, gfn, sp->role.word);
1607 kvm_mmu_zap_page(kvm, sp);
1608 }
97a0a01e
AK		 1609 }
1610}
1611
38c335f1 1612static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1613{
bc6678a3 1614 int slot = memslot_id(kvm, gfn);
4db35314 1615 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1616
291f26bc 1617 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1618}
1619
6844dec6
MT		 1620static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1621{
1622 int i;
1623 u64 *pt = sp->spt;
1624
1625 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1626 return;
1627
1628 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1629 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1630 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1631 }
1632}
1633
039576c0
AK		 1634struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1635{
72dc67a6
IE		 1636 struct page *page;
1637
ad312c7c 1638 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1639
1640 if (gpa == UNMAPPED_GVA)
1641 return NULL;
72dc67a6 1642
72dc67a6 1643 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1644
1645 return page;
039576c0
AK		 1646}
1647
74be52e3
SY		 1648/*
1649 * The function is based on mtrr_type_lookup() in
1650 * arch/x86/kernel/cpu/mtrr/generic.c
1651 */
1652static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1653 u64 start, u64 end)
1654{
1655 int i;
1656 u64 base, mask;
1657 u8 prev_match, curr_match;
1658 int num_var_ranges = KVM_NR_VAR_MTRR;
1659
1660 if (!mtrr_state->enabled)
1661 return 0xFF;
1662
1663 /* Make end inclusive end, instead of exclusive */
1664 end--;
1665
1666 /* Look in fixed ranges. Just return the type as per start */
1667 if (mtrr_state->have_fixed && (start < 0x100000)) {
1668 int idx;
1669
1670 if (start < 0x80000) {
1671 idx = 0;
1672 idx += (start >> 16);
1673 return mtrr_state->fixed_ranges[idx];
1674 } else if (start < 0xC0000) {
1675 idx = 1 * 8;
1676 idx += ((start - 0x80000) >> 14);
1677 return mtrr_state->fixed_ranges[idx];
1678 } else if (start < 0x1000000) {
1679 idx = 3 * 8;
1680 idx += ((start - 0xC0000) >> 12);
1681 return mtrr_state->fixed_ranges[idx];
1682 }
1683 }
1684
1685 /*
1686 * Look in variable ranges
1687 * Look of multiple ranges matching this address and pick type
1688 * as per MTRR precedence
1689 */
1690 if (!(mtrr_state->enabled & 2))
1691 return mtrr_state->def_type;
1692
1693 prev_match = 0xFF;
1694 for (i = 0; i < num_var_ranges; ++i) {
1695 unsigned short start_state, end_state;
1696
1697 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1698 continue;
1699
1700 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1701 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1702 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1703 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1704
1705 start_state = ((start & mask) == (base & mask));
1706 end_state = ((end & mask) == (base & mask));
1707 if (start_state != end_state)
1708 return 0xFE;
1709
1710 if ((start & mask) != (base & mask))
1711 continue;
1712
1713 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1714 if (prev_match == 0xFF) {
1715 prev_match = curr_match;
1716 continue;
1717 }
1718
1719 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1720 curr_match == MTRR_TYPE_UNCACHABLE)
1721 return MTRR_TYPE_UNCACHABLE;
1722
1723 if ((prev_match == MTRR_TYPE_WRBACK &&
1724 curr_match == MTRR_TYPE_WRTHROUGH) ||
1725 (prev_match == MTRR_TYPE_WRTHROUGH &&
1726 curr_match == MTRR_TYPE_WRBACK)) {
1727 prev_match = MTRR_TYPE_WRTHROUGH;
1728 curr_match = MTRR_TYPE_WRTHROUGH;
1729 }
1730
1731 if (prev_match != curr_match)
1732 return MTRR_TYPE_UNCACHABLE;
1733 }
1734
1735 if (prev_match != 0xFF)
1736 return prev_match;
1737
1738 return mtrr_state->def_type;
1739}
1740
4b12f0de 1741u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1742{
1743 u8 mtrr;
1744
1745 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1746 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1747 if (mtrr == 0xfe || mtrr == 0xff)
1748 mtrr = MTRR_TYPE_WRBACK;
1749 return mtrr;
1750}
4b12f0de 1751EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1752
4731d4c7
MT		 1753static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1754{
1755 unsigned index;
1756 struct hlist_head *bucket;
1757 struct kvm_mmu_page *s;
1758 struct hlist_node *node, *n;
1759
f691fe1d 1760 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1761 index = kvm_page_table_hashfn(sp->gfn);
1762 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1763 /* don't unsync if pagetable is shadowed with multiple roles */
1764 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1765 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1766 continue;
1767 if (s->role.word != sp->role.word)
1768 return 1;
1769 }
4731d4c7
MT		 1770 ++vcpu->kvm->stat.mmu_unsync;
1771 sp->unsync = 1;
6cffe8ca 1772
c2d0ee46 1773 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1774
4731d4c7
MT		 1775 mmu_convert_notrap(sp);
1776 return 0;
1777}
1778
1779static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1780 bool can_unsync)
1781{
1782 struct kvm_mmu_page *shadow;
1783
1784 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1785 if (shadow) {
1786 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1787 return 1;
1788 if (shadow->unsync)
1789 return 0;
582801a9 1790 if (can_unsync && oos_shadow)
4731d4c7
MT		 1791 return kvm_unsync_page(vcpu, shadow);
1792 return 1;
1793 }
1794 return 0;
1795}
1796
d555c333 1797static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1798 unsigned pte_access, int user_fault,
852e3c19 1799 int write_fault, int dirty, int level,
c2d0ee46 1800 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1801 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1802{
1803 u64 spte;
1e73f9dd 1804 int ret = 0;
64d4d521 1805
1c4f1fd6
AK		 1806 /*
1807 * We don't set the accessed bit, since we sometimes want to see
1808 * whether the guest actually used the pte (in order to detect
1809 * demand paging).
1810 */
7b52345e 1811 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1812 if (!speculative)
3201b5d9 1813 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1814 if (!dirty)
1815 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1816 if (pte_access & ACC_EXEC_MASK)
1817 spte |= shadow_x_mask;
1818 else
1819 spte |= shadow_nx_mask;
1c4f1fd6 1820 if (pte_access & ACC_USER_MASK)
7b52345e 1821 spte |= shadow_user_mask;
852e3c19 1822 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1823 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1824 if (tdp_enabled)
1825 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1826 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1827
1403283a
IE		 1828 if (reset_host_protection)
1829 spte |= SPTE_HOST_WRITEABLE;
1830
35149e21 1831 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1832
1833 if ((pte_access & ACC_WRITE_MASK)
1834 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1835
852e3c19
JR		 1836 if (level > PT_PAGE_TABLE_LEVEL &&
1837 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1838 ret = 1;
1839 spte = shadow_trap_nonpresent_pte;
1840 goto set_pte;
1841 }
1842
1c4f1fd6 1843 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1844
ecc5589f
MT		 1845 /*
1846 * Optimization: for pte sync, if spte was writable the hash
1847 * lookup is unnecessary (and expensive). Write protection
1848 * is responsibility of mmu_get_page / kvm_sync_page.
1849 * Same reasoning can be applied to dirty page accounting.
1850 */
8dae4445 1851 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1852 goto set_pte;
1853
4731d4c7 1854 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1855 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1856 __func__, gfn);
1e73f9dd 1857 ret = 1;
1c4f1fd6 1858 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1859 if (is_writable_pte(spte))
1c4f1fd6 1860 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1861 }
1862 }
1863
1c4f1fd6
AK		 1864 if (pte_access & ACC_WRITE_MASK)
1865 mark_page_dirty(vcpu->kvm, gfn);
1866
38187c83 1867set_pte:
d555c333 1868 __set_spte(sptep, spte);
1e73f9dd
MT		 1869 return ret;
1870}
1871
d555c333 1872static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1873 unsigned pt_access, unsigned pte_access,
1874 int user_fault, int write_fault, int dirty,
852e3c19 1875 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1876 pfn_t pfn, bool speculative,
1877 bool reset_host_protection)
1e73f9dd
MT		 1878{
1879 int was_rmapped = 0;
8dae4445 1880 int was_writable = is_writable_pte(*sptep);
53a27b39 1881 int rmap_count;
1e73f9dd
MT		 1882
1883 pgprintk("%s: spte %llx access %x write_fault %d"
1884 " user_fault %d gfn %lx\n",
d555c333 1885 __func__, *sptep, pt_access,
1e73f9dd
MT		 1886 write_fault, user_fault, gfn);
1887
d555c333 1888 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1889 /*
1890 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1891 * the parent of the now unreachable PTE.
1892 */
852e3c19
JR		 1893 if (level > PT_PAGE_TABLE_LEVEL &&
1894 !is_large_pte(*sptep)) {
1e73f9dd 1895 struct kvm_mmu_page *child;
d555c333 1896 u64 pte = *sptep;
1e73f9dd
MT		 1897
1898 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1899 mmu_page_remove_parent_pte(child, sptep);
1900 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1901 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1902 spte_to_pfn(*sptep), pfn);
1903 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1904 } else
1905 was_rmapped = 1;
1e73f9dd 1906 }
852e3c19 1907
d555c333 1908 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1909 dirty, level, gfn, pfn, speculative, true,
1910 reset_host_protection)) {
1e73f9dd
MT		 1911 if (write_fault)
1912 *ptwrite = 1;
a378b4e6
MT		 1913 kvm_x86_ops->tlb_flush(vcpu);
1914 }
1e73f9dd 1915
d555c333 1916 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1917 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1918 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1919 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1920 *sptep, sptep);
d555c333 1921 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1922 ++vcpu->kvm->stat.lpages;
1923
d555c333 1924 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1925 if (!was_rmapped) {
44ad9944 1926 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1927 kvm_release_pfn_clean(pfn);
53a27b39 1928 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1929 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1930 } else {
8dae4445 1931 if (was_writable)
35149e21 1932 kvm_release_pfn_dirty(pfn);
75e68e60 1933 else
35149e21 1934 kvm_release_pfn_clean(pfn);
1c4f1fd6 1935 }
1b7fcd32 1936 if (speculative) {
d555c333 1937 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1938 vcpu->arch.last_pte_gfn = gfn;
1939 }
1c4f1fd6
AK		 1940}
1941
6aa8b732
AK		 1942static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1943{
1944}
1945
9f652d21 1946static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1947 int level, gfn_t gfn, pfn_t pfn)
140754bc 1948{
9f652d21 1949 struct kvm_shadow_walk_iterator iterator;
140754bc 1950 struct kvm_mmu_page *sp;
9f652d21 1951 int pt_write = 0;
140754bc 1952 gfn_t pseudo_gfn;
6aa8b732 1953
9f652d21 1954 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1955 if (iterator.level == level) {
9f652d21
AK		 1956 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1957 0, write, 1, &pt_write,
1403283a 1958 level, gfn, pfn, false, true);
9f652d21
AK		 1959 ++vcpu->stat.pf_fixed;
1960 break;
6aa8b732
AK		 1961 }
1962
9f652d21
AK		 1963 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1964 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1965 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1966 iterator.level - 1,
1967 1, ACC_ALL, iterator.sptep);
1968 if (!sp) {
1969 pgprintk("nonpaging_map: ENOMEM\n");
1970 kvm_release_pfn_clean(pfn);
1971 return -ENOMEM;
1972 }
140754bc 1973
d555c333
AK		 1974 __set_spte(iterator.sptep,
1975 __pa(sp->spt)
1976 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1977 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1978 }
1979 }
1980 return pt_write;
6aa8b732
AK		 1981}
1982
10589a46
MT		 1983static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1984{
1985 int r;
852e3c19 1986 int level;
35149e21 1987 pfn_t pfn;
e930bffe 1988 unsigned long mmu_seq;
aaee2c94 1989
852e3c19
JR		 1990 level = mapping_level(vcpu, gfn);
1991
1992 /*
1993 * This path builds a PAE pagetable - so we can map 2mb pages at
1994 * maximum. Therefore check if the level is larger than that.
1995 */
1996 if (level > PT_DIRECTORY_LEVEL)
1997 level = PT_DIRECTORY_LEVEL;
1998
1999 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2000
e930bffe 2001 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2002 smp_rmb();
35149e21 2003 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2004
d196e343 2005 /* mmio */
35149e21
AL		 2006 if (is_error_pfn(pfn)) {
2007 kvm_release_pfn_clean(pfn);
d196e343
AK		 2008 return 1;
2009 }
2010
aaee2c94 2011 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2012 if (mmu_notifier_retry(vcpu, mmu_seq))
2013 goto out_unlock;
eb787d10 2014 kvm_mmu_free_some_pages(vcpu);
852e3c19 2015 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2016 spin_unlock(&vcpu->kvm->mmu_lock);
2017
aaee2c94 2018
10589a46 2019 return r;
e930bffe
AA		 2020
2021out_unlock:
2022 spin_unlock(&vcpu->kvm->mmu_lock);
2023 kvm_release_pfn_clean(pfn);
2024 return 0;
10589a46
MT		 2025}
2026
2027
17ac10ad
AK		 2028static void mmu_free_roots(struct kvm_vcpu *vcpu)
2029{
2030 int i;
4db35314 2031 struct kvm_mmu_page *sp;
17ac10ad 2032
ad312c7c 2033 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2034 return;
aaee2c94 2035 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2036 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2037 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2038
4db35314
AK		 2039 sp = page_header(root);
2040 --sp->root_count;
2e53d63a
MT		 2041 if (!sp->root_count && sp->role.invalid)
2042 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2043 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2044 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2045 return;
2046 }
17ac10ad 2047 for (i = 0; i < 4; ++i) {
ad312c7c 2048 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2049
417726a3 2050 if (root) {
417726a3 2051 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2052 sp = page_header(root);
2053 --sp->root_count;
2e53d63a
MT		 2054 if (!sp->root_count && sp->role.invalid)
2055 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2056 }
ad312c7c 2057 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2058 }
aaee2c94 2059 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2060 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2061}
2062
8986ecc0
MT		 2063static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2064{
2065 int ret = 0;
2066
2067 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2068 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2069 ret = 1;
2070 }
2071
2072 return ret;
2073}
2074
2075static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2076{
2077 int i;
cea0f0e7 2078 gfn_t root_gfn;
4db35314 2079 struct kvm_mmu_page *sp;
f6e2c02b 2080 int direct = 0;
6de4f3ad 2081 u64 pdptr;
3bb65a22 2082
ad312c7c 2083 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2084
ad312c7c
ZX		 2085 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2086 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2087
2088 ASSERT(!VALID_PAGE(root));
fb72d167 2089 if (tdp_enabled)
f6e2c02b 2090 direct = 1;
8986ecc0
MT		 2091 if (mmu_check_root(vcpu, root_gfn))
2092 return 1;
4db35314 2093 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2094 PT64_ROOT_LEVEL, direct,
fb72d167 2095 ACC_ALL, NULL);
4db35314
AK		 2096 root = __pa(sp->spt);
2097 ++sp->root_count;
ad312c7c 2098 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2099 return 0;
17ac10ad 2100 }
f6e2c02b 2101 direct = !is_paging(vcpu);
fb72d167 2102 if (tdp_enabled)
f6e2c02b 2103 direct = 1;
17ac10ad 2104 for (i = 0; i < 4; ++i) {
ad312c7c 2105 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2106
2107 ASSERT(!VALID_PAGE(root));
ad312c7c 2108 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2109 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2110 if (!is_present_gpte(pdptr)) {
ad312c7c 2111 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2112 continue;
2113 }
6de4f3ad 2114 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2115 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2116 root_gfn = 0;
8986ecc0
MT		 2117 if (mmu_check_root(vcpu, root_gfn))
2118 return 1;
4db35314 2119 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2120 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2121 ACC_ALL, NULL);
4db35314
AK		 2122 root = __pa(sp->spt);
2123 ++sp->root_count;
ad312c7c 2124 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2125 }
ad312c7c 2126 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2127 return 0;
17ac10ad
AK		 2128}
2129
0ba73cda
MT		 2130static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2131{
2132 int i;
2133 struct kvm_mmu_page *sp;
2134
2135 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2136 return;
2137 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2138 hpa_t root = vcpu->arch.mmu.root_hpa;
2139 sp = page_header(root);
2140 mmu_sync_children(vcpu, sp);
2141 return;
2142 }
2143 for (i = 0; i < 4; ++i) {
2144 hpa_t root = vcpu->arch.mmu.pae_root[i];
2145
8986ecc0 2146 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2147 root &= PT64_BASE_ADDR_MASK;
2148 sp = page_header(root);
2149 mmu_sync_children(vcpu, sp);
2150 }
2151 }
2152}
2153
2154void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2155{
2156 spin_lock(&vcpu->kvm->mmu_lock);
2157 mmu_sync_roots(vcpu);
6cffe8ca 2158 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2159}
2160
6aa8b732
AK		 2161static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2162{
2163 return vaddr;
2164}
2165
2166static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2167 u32 error_code)
6aa8b732 2168{
e833240f 2169 gfn_t gfn;
e2dec939 2170 int r;
6aa8b732 2171
b8688d51 2172 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2173 r = mmu_topup_memory_caches(vcpu);
2174 if (r)
2175 return r;
714b93da 2176
6aa8b732 2177 ASSERT(vcpu);
ad312c7c 2178 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2179
e833240f 2180 gfn = gva >> PAGE_SHIFT;
6aa8b732 2181
e833240f
AK		 2182 return nonpaging_map(vcpu, gva & PAGE_MASK,
2183 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2184}
2185
fb72d167
JR		 2186static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2187 u32 error_code)
2188{
35149e21 2189 pfn_t pfn;
fb72d167 2190 int r;
852e3c19 2191 int level;
05da4558 2192 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2193 unsigned long mmu_seq;
fb72d167
JR		 2194
2195 ASSERT(vcpu);
2196 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2197
2198 r = mmu_topup_memory_caches(vcpu);
2199 if (r)
2200 return r;
2201
852e3c19
JR		 2202 level = mapping_level(vcpu, gfn);
2203
2204 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2205
e930bffe 2206 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2207 smp_rmb();
35149e21 2208 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2209 if (is_error_pfn(pfn)) {
2210 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2211 return 1;
2212 }
2213 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2214 if (mmu_notifier_retry(vcpu, mmu_seq))
2215 goto out_unlock;
fb72d167
JR		 2216 kvm_mmu_free_some_pages(vcpu);
2217 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2218 level, gfn, pfn);
fb72d167 2219 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2220
2221 return r;
e930bffe
AA		 2222
2223out_unlock:
2224 spin_unlock(&vcpu->kvm->mmu_lock);
2225 kvm_release_pfn_clean(pfn);
2226 return 0;
fb72d167
JR		 2227}
2228
6aa8b732
AK		 2229static void nonpaging_free(struct kvm_vcpu *vcpu)
2230{
17ac10ad 2231 mmu_free_roots(vcpu);
6aa8b732
AK		 2232}
2233
2234static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2235{
ad312c7c 2236 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2237
2238 context->new_cr3 = nonpaging_new_cr3;
2239 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2240 context->gva_to_gpa = nonpaging_gva_to_gpa;
2241 context->free = nonpaging_free;
c7addb90 2242 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2243 context->sync_page = nonpaging_sync_page;
a7052897 2244 context->invlpg = nonpaging_invlpg;
cea0f0e7 2245 context->root_level = 0;
6aa8b732 2246 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2247 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2248 return 0;
2249}
2250
d835dfec 2251void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2252{
1165f5fe 2253 ++vcpu->stat.tlb_flush;
cbdd1bea 2254 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2255}
2256
2257static void paging_new_cr3(struct kvm_vcpu *vcpu)
2258{
b8688d51 2259 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2260 mmu_free_roots(vcpu);
6aa8b732
AK		 2261}
2262
6aa8b732
AK		 2263static void inject_page_fault(struct kvm_vcpu *vcpu,
2264 u64 addr,
2265 u32 err_code)
2266{
c3c91fee 2267 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2268}
2269
6aa8b732
AK		 2270static void paging_free(struct kvm_vcpu *vcpu)
2271{
2272 nonpaging_free(vcpu);
2273}
2274
82725b20
DE		 2275static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2276{
2277 int bit7;
2278
2279 bit7 = (gpte >> 7) & 1;
2280 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2281}
2282
6aa8b732
AK		 2283#define PTTYPE 64
2284#include "paging_tmpl.h"
2285#undef PTTYPE
2286
2287#define PTTYPE 32
2288#include "paging_tmpl.h"
2289#undef PTTYPE
2290
82725b20
DE		 2291static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2292{
2293 struct kvm_mmu *context = &vcpu->arch.mmu;
2294 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2295 u64 exb_bit_rsvd = 0;
2296
2297 if (!is_nx(vcpu))
2298 exb_bit_rsvd = rsvd_bits(63, 63);
2299 switch (level) {
2300 case PT32_ROOT_LEVEL:
2301 /* no rsvd bits for 2 level 4K page table entries */
2302 context->rsvd_bits_mask[0][1] = 0;
2303 context->rsvd_bits_mask[0][0] = 0;
2304 if (is_cpuid_PSE36())
2305 /* 36bits PSE 4MB page */
2306 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2307 else
2308 /* 32 bits PSE 4MB page */
2309 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2310 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2311 break;
2312 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2313 context->rsvd_bits_mask[0][2] =
2314 rsvd_bits(maxphyaddr, 63) |
2315 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2316 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2317 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2318 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2319 rsvd_bits(maxphyaddr, 62); /* PTE */
2320 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2321 rsvd_bits(maxphyaddr, 62) |
2322 rsvd_bits(13, 20); /* large page */
29a4b933 2323 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2324 break;
2325 case PT64_ROOT_LEVEL:
2326 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2327 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2328 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2329 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2330 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2331 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2332 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2333 rsvd_bits(maxphyaddr, 51);
2334 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2335 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2336 rsvd_bits(maxphyaddr, 51) |
2337 rsvd_bits(13, 29);
82725b20 2338 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2339 rsvd_bits(maxphyaddr, 51) |
2340 rsvd_bits(13, 20); /* large page */
29a4b933 2341 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2342 break;
2343 }
2344}
2345
17ac10ad 2346static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2347{
ad312c7c 2348 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2349
2350 ASSERT(is_pae(vcpu));
2351 context->new_cr3 = paging_new_cr3;
2352 context->page_fault = paging64_page_fault;
6aa8b732 2353 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2354 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2355 context->sync_page = paging64_sync_page;
a7052897 2356 context->invlpg = paging64_invlpg;
6aa8b732 2357 context->free = paging_free;
17ac10ad
AK		 2358 context->root_level = level;
2359 context->shadow_root_level = level;
17c3ba9d 2360 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2361 return 0;
2362}
2363
17ac10ad
AK		 2364static int paging64_init_context(struct kvm_vcpu *vcpu)
2365{
82725b20 2366 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2367 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2368}
2369
6aa8b732
AK		 2370static int paging32_init_context(struct kvm_vcpu *vcpu)
2371{
ad312c7c 2372 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2373
82725b20 2374 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2375 context->new_cr3 = paging_new_cr3;
2376 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2377 context->gva_to_gpa = paging32_gva_to_gpa;
2378 context->free = paging_free;
c7addb90 2379 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2380 context->sync_page = paging32_sync_page;
a7052897 2381 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2382 context->root_level = PT32_ROOT_LEVEL;
2383 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2384 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2385 return 0;
2386}
2387
2388static int paging32E_init_context(struct kvm_vcpu *vcpu)
2389{
82725b20 2390 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2391 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2392}
2393
fb72d167
JR		 2394static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2395{
2396 struct kvm_mmu *context = &vcpu->arch.mmu;
2397
2398 context->new_cr3 = nonpaging_new_cr3;
2399 context->page_fault = tdp_page_fault;
2400 context->free = nonpaging_free;
2401 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2402 context->sync_page = nonpaging_sync_page;
a7052897 2403 context->invlpg = nonpaging_invlpg;
67253af5 2404 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2405 context->root_hpa = INVALID_PAGE;
2406
2407 if (!is_paging(vcpu)) {
2408 context->gva_to_gpa = nonpaging_gva_to_gpa;
2409 context->root_level = 0;
2410 } else if (is_long_mode(vcpu)) {
82725b20 2411 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2412 context->gva_to_gpa = paging64_gva_to_gpa;
2413 context->root_level = PT64_ROOT_LEVEL;
2414 } else if (is_pae(vcpu)) {
82725b20 2415 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2416 context->gva_to_gpa = paging64_gva_to_gpa;
2417 context->root_level = PT32E_ROOT_LEVEL;
2418 } else {
82725b20 2419 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2420 context->gva_to_gpa = paging32_gva_to_gpa;
2421 context->root_level = PT32_ROOT_LEVEL;
2422 }
2423
2424 return 0;
2425}
2426
2427static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2428{
a770f6f2
AK		 2429 int r;
2430
6aa8b732 2431 ASSERT(vcpu);
ad312c7c 2432 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2433
2434 if (!is_paging(vcpu))
a770f6f2 2435 r = nonpaging_init_context(vcpu);
a9058ecd 2436 else if (is_long_mode(vcpu))
a770f6f2 2437 r = paging64_init_context(vcpu);
6aa8b732 2438 else if (is_pae(vcpu))
a770f6f2 2439 r = paging32E_init_context(vcpu);
6aa8b732 2440 else
a770f6f2
AK		 2441 r = paging32_init_context(vcpu);
2442
2443 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2444
2445 return r;
6aa8b732
AK		 2446}
2447
fb72d167
JR		 2448static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2449{
35149e21
AL		 2450 vcpu->arch.update_pte.pfn = bad_pfn;
2451
fb72d167
JR		 2452 if (tdp_enabled)
2453 return init_kvm_tdp_mmu(vcpu);
2454 else
2455 return init_kvm_softmmu(vcpu);
2456}
2457
6aa8b732
AK		 2458static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2459{
2460 ASSERT(vcpu);
ad312c7c
ZX		 2461 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2462 vcpu->arch.mmu.free(vcpu);
2463 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2464 }
2465}
2466
2467int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2468{
2469 destroy_kvm_mmu(vcpu);
2470 return init_kvm_mmu(vcpu);
2471}
8668a3c4 2472EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2473
2474int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2475{
714b93da
AK		 2476 int r;
2477
e2dec939 2478 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2479 if (r)
2480 goto out;
aaee2c94 2481 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2482 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2483 r = mmu_alloc_roots(vcpu);
0ba73cda 2484 mmu_sync_roots(vcpu);
aaee2c94 2485 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2486 if (r)
2487 goto out;
3662cb1c 2488 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2489 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2490out:
2491 return r;
6aa8b732 2492}
17c3ba9d
AK		 2493EXPORT_SYMBOL_GPL(kvm_mmu_load);
2494
2495void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2496{
2497 mmu_free_roots(vcpu);
2498}
6aa8b732 2499
09072daf 2500static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2501 struct kvm_mmu_page *sp,
ac1b714e
AK		 2502 u64 *spte)
2503{
2504 u64 pte;
2505 struct kvm_mmu_page *child;
2506
2507 pte = *spte;
c7addb90 2508 if (is_shadow_present_pte(pte)) {
776e6633 2509 if (is_last_spte(pte, sp->role.level))
290fc38d 2510 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2511 else {
2512 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2513 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2514 }
2515 }
d555c333 2516 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2517 if (is_large_pte(pte))
2518 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2519}
2520
0028425f 2521static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2522 struct kvm_mmu_page *sp,
0028425f 2523 u64 *spte,
489f1d65 2524 const void *new)
0028425f 2525{
30945387 2526 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2527 ++vcpu->kvm->stat.mmu_pde_zapped;
2528 return;
30945387 2529 }
0028425f 2530
4cee5764 2531 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2532 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2533 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2534 else
489f1d65 2535 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2536}
2537
79539cec
AK		 2538static bool need_remote_flush(u64 old, u64 new)
2539{
2540 if (!is_shadow_present_pte(old))
2541 return false;
2542 if (!is_shadow_present_pte(new))
2543 return true;
2544 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2545 return true;
2546 old ^= PT64_NX_MASK;
2547 new ^= PT64_NX_MASK;
2548 return (old & ~new & PT64_PERM_MASK) != 0;
2549}
2550
2551static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2552{
2553 if (need_remote_flush(old, new))
2554 kvm_flush_remote_tlbs(vcpu->kvm);
2555 else
2556 kvm_mmu_flush_tlb(vcpu);
2557}
2558
12b7d28f
AK		 2559static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2560{
ad312c7c 2561 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2562
7b52345e 2563 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2564}
2565
d7824fff
AK		 2566static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2567 const u8 *new, int bytes)
2568{
2569 gfn_t gfn;
2570 int r;
2571 u64 gpte = 0;
35149e21 2572 pfn_t pfn;
d7824fff
AK		 2573
2574 if (bytes != 4 && bytes != 8)
2575 return;
2576
2577 /*
2578 * Assume that the pte write on a page table of the same type
2579 * as the current vcpu paging mode. This is nearly always true
2580 * (might be false while changing modes). Note it is verified later
2581 * by update_pte().
2582 */
2583 if (is_pae(vcpu)) {
2584 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2585 if ((bytes == 4) && (gpa % 4 == 0)) {
2586 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2587 if (r)
2588 return;
2589 memcpy((void *)&gpte + (gpa % 8), new, 4);
2590 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2591 memcpy((void *)&gpte, new, 8);
2592 }
2593 } else {
2594 if ((bytes == 4) && (gpa % 4 == 0))
2595 memcpy((void *)&gpte, new, 4);
2596 }
43a3795a 2597 if (!is_present_gpte(gpte))
d7824fff
AK		 2598 return;
2599 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2600
e930bffe 2601 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2602 smp_rmb();
35149e21 2603 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2604
35149e21
AL		 2605 if (is_error_pfn(pfn)) {
2606 kvm_release_pfn_clean(pfn);
d196e343
AK		 2607 return;
2608 }
d7824fff 2609 vcpu->arch.update_pte.gfn = gfn;
35149e21 2610 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2611}
2612
1b7fcd32
AK		 2613static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2614{
2615 u64 *spte = vcpu->arch.last_pte_updated;
2616
2617 if (spte
2618 && vcpu->arch.last_pte_gfn == gfn
2619 && shadow_accessed_mask
2620 && !(*spte & shadow_accessed_mask)
2621 && is_shadow_present_pte(*spte))
2622 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2623}
2624
09072daf 2625void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2626 const u8 *new, int bytes,
2627 bool guest_initiated)
da4a00f0 2628{
9b7a0325 2629 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2630 struct kvm_mmu_page *sp;
0e7bc4b9 2631 struct hlist_node *node, *n;
9b7a0325
AK		 2632 struct hlist_head *bucket;
2633 unsigned index;
489f1d65 2634 u64 entry, gentry;
9b7a0325 2635 u64 *spte;
9b7a0325 2636 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2637 unsigned pte_size;
9b7a0325 2638 unsigned page_offset;
0e7bc4b9 2639 unsigned misaligned;
fce0657f 2640 unsigned quadrant;
9b7a0325 2641 int level;
86a5ba02 2642 int flooded = 0;
ac1b714e 2643 int npte;
489f1d65 2644 int r;
9b7a0325 2645
b8688d51 2646 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2647 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2648 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2649 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2650 kvm_mmu_free_some_pages(vcpu);
4cee5764 2651 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2652 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2653 if (guest_initiated) {
2654 if (gfn == vcpu->arch.last_pt_write_gfn
2655 && !last_updated_pte_accessed(vcpu)) {
2656 ++vcpu->arch.last_pt_write_count;
2657 if (vcpu->arch.last_pt_write_count >= 3)
2658 flooded = 1;
2659 } else {
2660 vcpu->arch.last_pt_write_gfn = gfn;
2661 vcpu->arch.last_pt_write_count = 1;
2662 vcpu->arch.last_pte_updated = NULL;
2663 }
86a5ba02 2664 }
1ae0a13d 2665 index = kvm_page_table_hashfn(gfn);
f05e70ac 2666 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2667 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2668 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2669 continue;
4db35314 2670 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2671 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2672 misaligned |= bytes < 4;
86a5ba02 2673 if (misaligned || flooded) {
0e7bc4b9
AK		 2674 /*
2675 * Misaligned accesses are too much trouble to fix
2676 * up; also, they usually indicate a page is not used
2677 * as a page table.
86a5ba02
AK		 2678 *
2679 * If we're seeing too many writes to a page,
2680 * it may no longer be a page table, or we may be
2681 * forking, in which case it is better to unmap the
2682 * page.
0e7bc4b9
AK		 2683 */
2684 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2685 gpa, bytes, sp->role.word);
07385413
MT		 2686 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2687 n = bucket->first;
4cee5764 2688 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2689 continue;
2690 }
9b7a0325 2691 page_offset = offset;
4db35314 2692 level = sp->role.level;
ac1b714e 2693 npte = 1;
4db35314 2694 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2695 page_offset <<= 1; /* 32->64 */
2696 /*
2697 * A 32-bit pde maps 4MB while the shadow pdes map
2698 * only 2MB. So we need to double the offset again
2699 * and zap two pdes instead of one.
2700 */
2701 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2702 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2703 page_offset <<= 1;
2704 npte = 2;
2705 }
fce0657f 2706 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2707 page_offset &= ~PAGE_MASK;
4db35314 2708 if (quadrant != sp->role.quadrant)
fce0657f 2709 continue;
9b7a0325 2710 }
4db35314 2711 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2712 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2713 gentry = 0;
2714 r = kvm_read_guest_atomic(vcpu->kvm,
2715 gpa & ~(u64)(pte_size - 1),
2716 &gentry, pte_size);
2717 new = (const void *)&gentry;
2718 if (r < 0)
2719 new = NULL;
2720 }
ac1b714e 2721 while (npte--) {
79539cec 2722 entry = *spte;
4db35314 2723 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2724 if (new)
2725 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2726 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2727 ++spte;
9b7a0325 2728 }
9b7a0325 2729 }
c7addb90 2730 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2731 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2732 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2733 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2734 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2735 }
da4a00f0
AK		 2736}
2737
a436036b
AK		 2738int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2739{
10589a46
MT		 2740 gpa_t gpa;
2741 int r;
a436036b 2742
60f24784
AK		 2743 if (tdp_enabled)
2744 return 0;
2745
10589a46 2746 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2747
aaee2c94 2748 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2749 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2750 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2751 return r;
a436036b 2752}
577bdc49 2753EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2754
22d95b12 2755void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2756{
3b80fffe
IE		 2757 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2758 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2759 struct kvm_mmu_page *sp;
ebeace86 2760
f05e70ac 2761 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2762 struct kvm_mmu_page, link);
2763 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2764 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2765 }
2766}
ebeace86 2767
3067714c
AK		 2768int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2769{
2770 int r;
2771 enum emulation_result er;
2772
ad312c7c 2773 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2774 if (r < 0)
2775 goto out;
2776
2777 if (!r) {
2778 r = 1;
2779 goto out;
2780 }
2781
b733bfb5
AK		 2782 r = mmu_topup_memory_caches(vcpu);
2783 if (r)
2784 goto out;
2785
851ba692 2786 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2787
2788 switch (er) {
2789 case EMULATE_DONE:
2790 return 1;
2791 case EMULATE_DO_MMIO:
2792 ++vcpu->stat.mmio_exits;
2793 return 0;
2794 case EMULATE_FAIL:
3f5d18a9
AK		 2795 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2796 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2797 vcpu->run->internal.ndata = 0;
3f5d18a9 2798 return 0;
3067714c
AK		 2799 default:
2800 BUG();
2801 }
2802out:
3067714c
AK		 2803 return r;
2804}
2805EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2806
a7052897
MT		 2807void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2808{
a7052897 2809 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2810 kvm_mmu_flush_tlb(vcpu);
2811 ++vcpu->stat.invlpg;
2812}
2813EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2814
18552672
JR		 2815void kvm_enable_tdp(void)
2816{
2817 tdp_enabled = true;
2818}
2819EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2820
5f4cb662
JR		 2821void kvm_disable_tdp(void)
2822{
2823 tdp_enabled = false;
2824}
2825EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2826
6aa8b732
AK		 2827static void free_mmu_pages(struct kvm_vcpu *vcpu)
2828{
ad312c7c 2829 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2830}
2831
2832static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2833{
17ac10ad 2834 struct page *page;
6aa8b732
AK		 2835 int i;
2836
2837 ASSERT(vcpu);
2838
17ac10ad
AK		 2839 /*
2840 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2841 * Therefore we need to allocate shadow page tables in the first
2842 * 4GB of memory, which happens to fit the DMA32 zone.
2843 */
2844 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2845 if (!page)
2846 goto error_1;
ad312c7c 2847 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2848 for (i = 0; i < 4; ++i)
ad312c7c 2849 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2850
6aa8b732
AK		 2851 return 0;
2852
2853error_1:
2854 free_mmu_pages(vcpu);
2855 return -ENOMEM;
2856}
2857
8018c27b 2858int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2859{
6aa8b732 2860 ASSERT(vcpu);
ad312c7c 2861 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2862
8018c27b
IM		 2863 return alloc_mmu_pages(vcpu);
2864}
6aa8b732 2865
8018c27b
IM		 2866int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2867{
2868 ASSERT(vcpu);
ad312c7c 2869 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2870
8018c27b 2871 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2872}
2873
2874void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2875{
2876 ASSERT(vcpu);
2877
2878 destroy_kvm_mmu(vcpu);
2879 free_mmu_pages(vcpu);
714b93da 2880 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2881}
2882
90cb0529 2883void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2884{
4db35314 2885 struct kvm_mmu_page *sp;
6aa8b732 2886
f05e70ac 2887 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2888 int i;
2889 u64 *pt;
2890
291f26bc 2891 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2892 continue;
2893
4db35314 2894 pt = sp->spt;
6aa8b732
AK		 2895 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2896 /* avoid RMW */
9647c14c 2897 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2898 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2899 }
171d595d 2900 kvm_flush_remote_tlbs(kvm);
6aa8b732 2901}
37a7d8b0 2902
90cb0529 2903void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2904{
4db35314 2905 struct kvm_mmu_page *sp, *node;
e0fa826f 2906
aaee2c94 2907 spin_lock(&kvm->mmu_lock);
f05e70ac 2908 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2909 if (kvm_mmu_zap_page(kvm, sp))
2910 node = container_of(kvm->arch.active_mmu_pages.next,
2911 struct kvm_mmu_page, link);
aaee2c94 2912 spin_unlock(&kvm->mmu_lock);
e0fa826f 2913
90cb0529 2914 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2915}
2916
8b2cf73c 2917static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2918{
2919 struct kvm_mmu_page *page;
2920
2921 page = container_of(kvm->arch.active_mmu_pages.prev,
2922 struct kvm_mmu_page, link);
2923 kvm_mmu_zap_page(kvm, page);
2924}
2925
2926static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2927{
2928 struct kvm *kvm;
2929 struct kvm *kvm_freed = NULL;
2930 int cache_count = 0;
2931
2932 spin_lock(&kvm_lock);
2933
2934 list_for_each_entry(kvm, &vm_list, vm_list) {
f656ce01 2935 int npages, idx;
3ee16c81 2936
f656ce01 2937 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2938 spin_lock(&kvm->mmu_lock);
2939 npages = kvm->arch.n_alloc_mmu_pages -
2940 kvm->arch.n_free_mmu_pages;
2941 cache_count += npages;
2942 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2943 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2944 cache_count--;
2945 kvm_freed = kvm;
2946 }
2947 nr_to_scan--;
2948
2949 spin_unlock(&kvm->mmu_lock);
f656ce01 2950 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2951 }
2952 if (kvm_freed)
2953 list_move_tail(&kvm_freed->vm_list, &vm_list);
2954
2955 spin_unlock(&kvm_lock);
2956
2957 return cache_count;
2958}
2959
2960static struct shrinker mmu_shrinker = {
2961 .shrink = mmu_shrink,
2962 .seeks = DEFAULT_SEEKS * 10,
2963};
2964
2ddfd20e 2965static void mmu_destroy_caches(void)
b5a33a75
AK		 2966{
2967 if (pte_chain_cache)
2968 kmem_cache_destroy(pte_chain_cache);
2969 if (rmap_desc_cache)
2970 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2971 if (mmu_page_header_cache)
2972 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2973}
2974
3ee16c81
IE		 2975void kvm_mmu_module_exit(void)
2976{
2977 mmu_destroy_caches();
2978 unregister_shrinker(&mmu_shrinker);
2979}
2980
b5a33a75
AK		 2981int kvm_mmu_module_init(void)
2982{
2983 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2984 sizeof(struct kvm_pte_chain),
20c2df83 2985 0, 0, NULL);
b5a33a75
AK		 2986 if (!pte_chain_cache)
2987 goto nomem;
2988 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2989 sizeof(struct kvm_rmap_desc),
20c2df83 2990 0, 0, NULL);
b5a33a75
AK		 2991 if (!rmap_desc_cache)
2992 goto nomem;
2993
d3d25b04
AK		 2994 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2995 sizeof(struct kvm_mmu_page),
20c2df83 2996 0, 0, NULL);
d3d25b04
AK		 2997 if (!mmu_page_header_cache)
2998 goto nomem;
2999
3ee16c81
IE		 3000 register_shrinker(&mmu_shrinker);
3001
b5a33a75
AK		 3002 return 0;
3003
3004nomem:
3ee16c81 3005 mmu_destroy_caches();
b5a33a75
AK		 3006 return -ENOMEM;
3007}
3008
3ad82a7e
ZX		 3009/*
3010 * Caculate mmu pages needed for kvm.
3011 */
3012unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3013{
3014 int i;
3015 unsigned int nr_mmu_pages;
3016 unsigned int nr_pages = 0;
bc6678a3 3017 struct kvm_memslots *slots;
3ad82a7e 3018
bc6678a3
MT		 3019 slots = rcu_dereference(kvm->memslots);
3020 for (i = 0; i < slots->nmemslots; i++)
3021 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3022
3023 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3024 nr_mmu_pages = max(nr_mmu_pages,
3025 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3026
3027 return nr_mmu_pages;
3028}
3029
2f333bcb
MT		 3030static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3031 unsigned len)
3032{
3033 if (len > buffer->len)
3034 return NULL;
3035 return buffer->ptr;
3036}
3037
3038static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3039 unsigned len)
3040{
3041 void *ret;
3042
3043 ret = pv_mmu_peek_buffer(buffer, len);
3044 if (!ret)
3045 return ret;
3046 buffer->ptr += len;
3047 buffer->len -= len;
3048 buffer->processed += len;
3049 return ret;
3050}
3051
3052static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3053 gpa_t addr, gpa_t value)
3054{
3055 int bytes = 8;
3056 int r;
3057
3058 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3059 bytes = 4;
3060
3061 r = mmu_topup_memory_caches(vcpu);
3062 if (r)
3063 return r;
3064
3200f405 3065 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3066 return -EFAULT;
3067
3068 return 1;
3069}
3070
3071static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3072{
a8cd0244 3073 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3074 return 1;
3075}
3076
3077static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3078{
3079 spin_lock(&vcpu->kvm->mmu_lock);
3080 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3081 spin_unlock(&vcpu->kvm->mmu_lock);
3082 return 1;
3083}
3084
3085static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3086 struct kvm_pv_mmu_op_buffer *buffer)
3087{
3088 struct kvm_mmu_op_header *header;
3089
3090 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3091 if (!header)
3092 return 0;
3093 switch (header->op) {
3094 case KVM_MMU_OP_WRITE_PTE: {
3095 struct kvm_mmu_op_write_pte *wpte;
3096
3097 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3098 if (!wpte)
3099 return 0;
3100 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3101 wpte->pte_val);
3102 }
3103 case KVM_MMU_OP_FLUSH_TLB: {
3104 struct kvm_mmu_op_flush_tlb *ftlb;
3105
3106 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3107 if (!ftlb)
3108 return 0;
3109 return kvm_pv_mmu_flush_tlb(vcpu);
3110 }
3111 case KVM_MMU_OP_RELEASE_PT: {
3112 struct kvm_mmu_op_release_pt *rpt;
3113
3114 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3115 if (!rpt)
3116 return 0;
3117 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3118 }
3119 default: return 0;
3120 }
3121}
3122
3123int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3124 gpa_t addr, unsigned long *ret)
3125{
3126 int r;
6ad18fba 3127 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3128
6ad18fba
DH		 3129 buffer->ptr = buffer->buf;
3130 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3131 buffer->processed = 0;
2f333bcb 3132
6ad18fba 3133 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3134 if (r)
3135 goto out;
3136
6ad18fba
DH		 3137 while (buffer->len) {
3138 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3139 if (r < 0)
3140 goto out;
3141 if (r == 0)
3142 break;
3143 }
3144
3145 r = 1;
3146out:
6ad18fba 3147 *ret = buffer->processed;
2f333bcb
MT		 3148 return r;
3149}
3150
94d8b056
MT		 3151int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3152{
3153 struct kvm_shadow_walk_iterator iterator;
3154 int nr_sptes = 0;
3155
3156 spin_lock(&vcpu->kvm->mmu_lock);
3157 for_each_shadow_entry(vcpu, addr, iterator) {
3158 sptes[iterator.level-1] = *iterator.sptep;
3159 nr_sptes++;
3160 if (!is_shadow_present_pte(*iterator.sptep))
3161 break;
3162 }
3163 spin_unlock(&vcpu->kvm->mmu_lock);
3164
3165 return nr_sptes;
3166}
3167EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3168
37a7d8b0
AK		 3169#ifdef AUDIT
3170
3171static const char *audit_msg;
3172
3173static gva_t canonicalize(gva_t gva)
3174{
3175#ifdef CONFIG_X86_64
3176 gva = (long long)(gva << 16) >> 16;
3177#endif
3178 return gva;
3179}
3180
08a3732b
MT		 3181
3182typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3183 u64 *sptep);
3184
3185static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3186 inspect_spte_fn fn)
3187{
3188 int i;
3189
3190 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3191 u64 ent = sp->spt[i];
3192
3193 if (is_shadow_present_pte(ent)) {
2920d728 3194 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3195 struct kvm_mmu_page *child;
3196 child = page_header(ent & PT64_BASE_ADDR_MASK);
3197 __mmu_spte_walk(kvm, child, fn);
2920d728 3198 } else
08a3732b
MT		 3199 fn(kvm, sp, &sp->spt[i]);
3200 }
3201 }
3202}
3203
3204static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3205{
3206 int i;
3207 struct kvm_mmu_page *sp;
3208
3209 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3210 return;
3211 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3212 hpa_t root = vcpu->arch.mmu.root_hpa;
3213 sp = page_header(root);
3214 __mmu_spte_walk(vcpu->kvm, sp, fn);
3215 return;
3216 }
3217 for (i = 0; i < 4; ++i) {
3218 hpa_t root = vcpu->arch.mmu.pae_root[i];
3219
3220 if (root && VALID_PAGE(root)) {
3221 root &= PT64_BASE_ADDR_MASK;
3222 sp = page_header(root);
3223 __mmu_spte_walk(vcpu->kvm, sp, fn);
3224 }
3225 }
3226 return;
3227}
3228
37a7d8b0
AK		 3229static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3230 gva_t va, int level)
3231{
3232 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3233 int i;
3234 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3235
3236 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3237 u64 ent = pt[i];
3238
c7addb90 3239 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3240 continue;
3241
3242 va = canonicalize(va);
2920d728
MT		 3243 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3244 audit_mappings_page(vcpu, ent, va, level - 1);
3245 else {
ad312c7c 3246 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3247 gfn_t gfn = gpa >> PAGE_SHIFT;
3248 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3249 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3250
2aaf65e8
MT		 3251 if (is_error_pfn(pfn)) {
3252 kvm_release_pfn_clean(pfn);
3253 continue;
3254 }
3255
c7addb90 3256 if (is_shadow_present_pte(ent)
37a7d8b0 3257 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3258 printk(KERN_ERR "xx audit error: (%s) levels %d"
3259 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3260 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3261 va, gpa, hpa, ent,
3262 is_shadow_present_pte(ent));
c7addb90
AK		 3263 else if (ent == shadow_notrap_nonpresent_pte
3264 && !is_error_hpa(hpa))
3265 printk(KERN_ERR "audit: (%s) notrap shadow,"
3266 " valid guest gva %lx\n", audit_msg, va);
35149e21 3267 kvm_release_pfn_clean(pfn);
c7addb90 3268
37a7d8b0
AK		 3269 }
3270 }
3271}
3272
3273static void audit_mappings(struct kvm_vcpu *vcpu)
3274{
1ea252af 3275 unsigned i;
37a7d8b0 3276
ad312c7c
ZX		 3277 if (vcpu->arch.mmu.root_level == 4)
3278 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3279 else
3280 for (i = 0; i < 4; ++i)
ad312c7c 3281 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3282 audit_mappings_page(vcpu,
ad312c7c 3283 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3284 i << 30,
3285 2);
3286}
3287
3288static int count_rmaps(struct kvm_vcpu *vcpu)
3289{
3290 int nmaps = 0;
bc6678a3 3291 int i, j, k, idx;
37a7d8b0 3292
bc6678a3
MT		 3293 idx = srcu_read_lock(&kvm->srcu);
3294 slots = rcu_dereference(kvm->memslots);
37a7d8b0 3295 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3296 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3297 struct kvm_rmap_desc *d;
3298
3299 for (j = 0; j < m->npages; ++j) {
290fc38d 3300 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3301
290fc38d 3302 if (!*rmapp)
37a7d8b0 3303 continue;
290fc38d 3304 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3305 ++nmaps;
3306 continue;
3307 }
290fc38d 3308 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3309 while (d) {
3310 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3311 if (d->sptes[k])
37a7d8b0
AK		 3312 ++nmaps;
3313 else
3314 break;
3315 d = d->more;
3316 }
3317 }
3318 }
bc6678a3 3319 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3320 return nmaps;
3321}
3322
08a3732b
MT		 3323void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3324{
3325 unsigned long *rmapp;
3326 struct kvm_mmu_page *rev_sp;
3327 gfn_t gfn;
3328
3329 if (*sptep & PT_WRITABLE_MASK) {
3330 rev_sp = page_header(__pa(sptep));
3331 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3332
3333 if (!gfn_to_memslot(kvm, gfn)) {
3334 if (!printk_ratelimit())
3335 return;
3336 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3337 audit_msg, gfn);
3338 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3339 audit_msg, sptep - rev_sp->spt,
3340 rev_sp->gfn);
3341 dump_stack();
3342 return;
3343 }
3344
2920d728
MT		 3345 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3346 is_large_pte(*sptep));
08a3732b
MT		 3347 if (!*rmapp) {
3348 if (!printk_ratelimit())
3349 return;
3350 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3351 audit_msg, *sptep);
3352 dump_stack();
3353 }
3354 }
3355
3356}
3357
3358void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3359{
3360 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3361}
3362
3363static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3364{
4db35314 3365 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3366 int i;
3367
f05e70ac 3368 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3369 u64 *pt = sp->spt;
37a7d8b0 3370
4db35314 3371 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3372 continue;
3373
3374 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3375 u64 ent = pt[i];
3376
3377 if (!(ent & PT_PRESENT_MASK))
3378 continue;
3379 if (!(ent & PT_WRITABLE_MASK))
3380 continue;
08a3732b 3381 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3382 }
3383 }
08a3732b 3384 return;
37a7d8b0
AK		 3385}
3386
3387static void audit_rmap(struct kvm_vcpu *vcpu)
3388{
08a3732b
MT		 3389 check_writable_mappings_rmap(vcpu);
3390 count_rmaps(vcpu);
37a7d8b0
AK		 3391}
3392
3393static void audit_write_protection(struct kvm_vcpu *vcpu)
3394{
4db35314 3395 struct kvm_mmu_page *sp;
290fc38d
IE		 3396 struct kvm_memory_slot *slot;
3397 unsigned long *rmapp;
e58b0f9e 3398 u64 *spte;
290fc38d 3399 gfn_t gfn;
37a7d8b0 3400
f05e70ac 3401 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3402 if (sp->role.direct)
37a7d8b0 3403 continue;
e58b0f9e
MT		 3404 if (sp->unsync)
3405 continue;
37a7d8b0 3406
4db35314 3407 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3408 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3409 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3410
3411 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3412 while (spte) {
3413 if (*spte & PT_WRITABLE_MASK)
3414 printk(KERN_ERR "%s: (%s) shadow page has "
3415 "writable mappings: gfn %lx role %x\n",
b8688d51 3416 __func__, audit_msg, sp->gfn,
4db35314 3417 sp->role.word);
e58b0f9e
MT		 3418 spte = rmap_next(vcpu->kvm, rmapp, spte);
3419 }
37a7d8b0
AK		 3420 }
3421}
3422
3423static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3424{
3425 int olddbg = dbg;
3426
3427 dbg = 0;
3428 audit_msg = msg;
3429 audit_rmap(vcpu);
3430 audit_write_protection(vcpu);
2aaf65e8
MT		 3431 if (strcmp("pre pte write", audit_msg) != 0)
3432 audit_mappings(vcpu);
08a3732b 3433 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3434 dbg = olddbg;
3435}
3436
3437#endif
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