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Merge branch 'ebt_config_compat_v4' of git://git.breakpoint.cc/fw/nf-next-2.6
[net-next-2.6.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
edf88417 20#include <linux/kvm_host.h>
97222cc8
ED		 21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
6f6d6a1a 28#include <linux/math64.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
34#include <asm/atomic.h>
5fdbf976 35#include "kvm_cache_regs.h"
97222cc8 36#include "irq.h"
229456fc 37#include "trace.h"
fc61b800 38#include "x86.h"
97222cc8 39
b682b814
MT		 40#ifndef CONFIG_X86_64
41#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
42#else
43#define mod_64(x, y) ((x) % (y))
44#endif
45
97222cc8
ED		 46#define PRId64 "d"
47#define PRIx64 "llx"
48#define PRIu64 "u"
49#define PRIo64 "o"
50
51#define APIC_BUS_CYCLE_NS 1
52
53/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
54#define apic_debug(fmt, arg...)
55
56#define APIC_LVT_NUM 6
57/* 14 is the version for Xeon and Pentium 8.4.8*/
58#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
59#define LAPIC_MMIO_LENGTH (1 << 12)
60/* followed define is not in apicdef.h */
61#define APIC_SHORT_MASK 0xc0000
62#define APIC_DEST_NOSHORT 0x0
63#define APIC_DEST_MASK 0x800
64#define MAX_APIC_VECTOR 256
65
66#define VEC_POS(v) ((v) & (32 - 1))
67#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 68
97222cc8
ED		 69static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
70{
71 return *((u32 *) (apic->regs + reg_off));
72}
73
74static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
75{
76 *((u32 *) (apic->regs + reg_off)) = val;
77}
78
79static inline int apic_test_and_set_vector(int vec, void *bitmap)
80{
81 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82}
83
84static inline int apic_test_and_clear_vector(int vec, void *bitmap)
85{
86 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline void apic_set_vector(int vec, void *bitmap)
90{
91 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92}
93
94static inline void apic_clear_vector(int vec, void *bitmap)
95{
96 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97}
98
99static inline int apic_hw_enabled(struct kvm_lapic *apic)
100{
ad312c7c 101 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 102}
103
104static inline int apic_sw_enabled(struct kvm_lapic *apic)
105{
106 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
107}
108
109static inline int apic_enabled(struct kvm_lapic *apic)
110{
111 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
112}
113
114#define LVT_MASK \
115 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
116
117#define LINT_MASK \
118 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
119 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
120
121static inline int kvm_apic_id(struct kvm_lapic *apic)
122{
123 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
124}
125
126static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
127{
128 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
129}
130
131static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
132{
133 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
134}
135
136static inline int apic_lvtt_period(struct kvm_lapic *apic)
137{
138 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
139}
140
cc6e462c
JK		 141static inline int apic_lvt_nmi_mode(u32 lvt_val)
142{
143 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
144}
145
fc61b800
GN		 146void kvm_apic_set_version(struct kvm_vcpu *vcpu)
147{
148 struct kvm_lapic *apic = vcpu->arch.apic;
149 struct kvm_cpuid_entry2 *feat;
150 u32 v = APIC_VERSION;
151
152 if (!irqchip_in_kernel(vcpu->kvm))
153 return;
154
155 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
156 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
157 v |= APIC_LVR_DIRECTED_EOI;
158 apic_set_reg(apic, APIC_LVR, v);
159}
160
0105d1a5
GN		 161static inline int apic_x2apic_mode(struct kvm_lapic *apic)
162{
163 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
164}
165
97222cc8
ED		 166static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
167 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
168 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
169 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
170 LINT_MASK, LINT_MASK, /* LVT0-1 */
171 LVT_MASK /* LVTERR */
172};
173
174static int find_highest_vector(void *bitmap)
175{
176 u32 *word = bitmap;
177 int word_offset = MAX_APIC_VECTOR >> 5;
178
179 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
180 continue;
181
182 if (likely(!word_offset && !word[0]))
183 return -1;
184 else
185 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
186}
187
188static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
189{
33e4c686 190 apic->irr_pending = true;
97222cc8
ED		 191 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
192}
193
33e4c686 194static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 195{
33e4c686 196 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 197}
198
199static inline int apic_find_highest_irr(struct kvm_lapic *apic)
200{
201 int result;
202
33e4c686
GN		 203 if (!apic->irr_pending)
204 return -1;
205
206 result = apic_search_irr(apic);
97222cc8
ED		 207 ASSERT(result == -1 || result >= 16);
208
209 return result;
210}
211
33e4c686
GN		 212static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
213{
214 apic->irr_pending = false;
215 apic_clear_vector(vec, apic->regs + APIC_IRR);
216 if (apic_search_irr(apic) != -1)
217 apic->irr_pending = true;
218}
219
6e5d865c
YS		 220int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
221{
ad312c7c 222 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 223 int highest_irr;
224
33e4c686
GN		 225 /* This may race with setting of irr in __apic_accept_irq() and
226 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
227 * will cause vmexit immediately and the value will be recalculated
228 * on the next vmentry.
229 */
6e5d865c
YS		 230 if (!apic)
231 return 0;
232 highest_irr = apic_find_highest_irr(apic);
233
234 return highest_irr;
235}
6e5d865c 236
6da7e3f6
GN		 237static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
238 int vector, int level, int trig_mode);
239
58c2dde1 240int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
97222cc8 241{
ad312c7c 242 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 243
58c2dde1
GN		 244 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
245 irq->level, irq->trig_mode);
97222cc8
ED		 246}
247
248static inline int apic_find_highest_isr(struct kvm_lapic *apic)
249{
250 int result;
251
252 result = find_highest_vector(apic->regs + APIC_ISR);
253 ASSERT(result == -1 || result >= 16);
254
255 return result;
256}
257
258static void apic_update_ppr(struct kvm_lapic *apic)
259{
260 u32 tpr, isrv, ppr;
261 int isr;
262
263 tpr = apic_get_reg(apic, APIC_TASKPRI);
264 isr = apic_find_highest_isr(apic);
265 isrv = (isr != -1) ? isr : 0;
266
267 if ((tpr & 0xf0) >= (isrv & 0xf0))
268 ppr = tpr & 0xff;
269 else
270 ppr = isrv & 0xf0;
271
272 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
273 apic, ppr, isr, isrv);
274
275 apic_set_reg(apic, APIC_PROCPRI, ppr);
276}
277
278static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
279{
280 apic_set_reg(apic, APIC_TASKPRI, tpr);
281 apic_update_ppr(apic);
282}
283
284int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
285{
343f94fe 286 return dest == 0xff || kvm_apic_id(apic) == dest;
97222cc8
ED		 287}
288
289int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
290{
291 int result = 0;
0105d1a5
GN		 292 u32 logical_id;
293
294 if (apic_x2apic_mode(apic)) {
295 logical_id = apic_get_reg(apic, APIC_LDR);
296 return logical_id & mda;
297 }
97222cc8
ED		 298
299 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
300
301 switch (apic_get_reg(apic, APIC_DFR)) {
302 case APIC_DFR_FLAT:
303 if (logical_id & mda)
304 result = 1;
305 break;
306 case APIC_DFR_CLUSTER:
307 if (((logical_id >> 4) == (mda >> 0x4))
308 && (logical_id & mda & 0xf))
309 result = 1;
310 break;
311 default:
312 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
313 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
314 break;
315 }
316
317 return result;
318}
319
343f94fe 320int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
97222cc8
ED		 321 int short_hand, int dest, int dest_mode)
322{
323 int result = 0;
ad312c7c 324 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 325
326 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 327 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 328 target, source, dest, dest_mode, short_hand);
329
330 ASSERT(!target);
331 switch (short_hand) {
332 case APIC_DEST_NOSHORT:
343f94fe 333 if (dest_mode == 0)
97222cc8 334 /* Physical mode. */
343f94fe
GN		 335 result = kvm_apic_match_physical_addr(target, dest);
336 else
97222cc8
ED		 337 /* Logical mode. */
338 result = kvm_apic_match_logical_addr(target, dest);
339 break;
340 case APIC_DEST_SELF:
343f94fe 341 result = (target == source);
97222cc8
ED		 342 break;
343 case APIC_DEST_ALLINC:
344 result = 1;
345 break;
346 case APIC_DEST_ALLBUT:
343f94fe 347 result = (target != source);
97222cc8
ED		 348 break;
349 default:
350 printk(KERN_WARNING "Bad dest shorthand value %x\n",
351 short_hand);
352 break;
353 }
354
355 return result;
356}
357
358/*
359 * Add a pending IRQ into lapic.
360 * Return 1 if successfully added and 0 if discarded.
361 */
362static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
363 int vector, int level, int trig_mode)
364{
6da7e3f6 365 int result = 0;
c5ec1534 366 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 367
368 switch (delivery_mode) {
97222cc8 369 case APIC_DM_LOWEST:
e1035715
GN		 370 vcpu->arch.apic_arb_prio++;
371 case APIC_DM_FIXED:
97222cc8
ED		 372 /* FIXME add logic for vcpu on reset */
373 if (unlikely(!apic_enabled(apic)))
374 break;
375
a5d36f82
AK		 376 if (trig_mode) {
377 apic_debug("level trig mode for vector %d", vector);
378 apic_set_vector(vector, apic->regs + APIC_TMR);
379 } else
380 apic_clear_vector(vector, apic->regs + APIC_TMR);
381
6da7e3f6 382 result = !apic_test_and_set_irr(vector, apic);
1000ff8d 383 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
4da74896 384 trig_mode, vector, !result);
6da7e3f6
GN		 385 if (!result) {
386 if (trig_mode)
387 apic_debug("level trig mode repeatedly for "
388 "vector %d", vector);
97222cc8
ED		 389 break;
390 }
391
d7690175 392 kvm_vcpu_kick(vcpu);
97222cc8
ED		 393 break;
394
395 case APIC_DM_REMRD:
396 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
397 break;
398
399 case APIC_DM_SMI:
400 printk(KERN_DEBUG "Ignoring guest SMI\n");
401 break;
3419ffc8 402
97222cc8 403 case APIC_DM_NMI:
6da7e3f6 404 result = 1;
3419ffc8 405 kvm_inject_nmi(vcpu);
26df99c6 406 kvm_vcpu_kick(vcpu);
97222cc8
ED		 407 break;
408
409 case APIC_DM_INIT:
c5ec1534 410 if (level) {
6da7e3f6 411 result = 1;
a4535290 412 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534
HQ		 413 printk(KERN_DEBUG
414 "INIT on a runnable vcpu %d\n",
415 vcpu->vcpu_id);
a4535290 416 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
c5ec1534
HQ		 417 kvm_vcpu_kick(vcpu);
418 } else {
1b10bf31
JK		 419 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
420 vcpu->vcpu_id);
c5ec1534 421 }
97222cc8
ED		 422 break;
423
424 case APIC_DM_STARTUP:
1b10bf31
JK		 425 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
426 vcpu->vcpu_id, vector);
a4535290 427 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6da7e3f6 428 result = 1;
ad312c7c 429 vcpu->arch.sipi_vector = vector;
a4535290 430 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
d7690175 431 kvm_vcpu_kick(vcpu);
c5ec1534 432 }
97222cc8
ED		 433 break;
434
23930f95
JK		 435 case APIC_DM_EXTINT:
436 /*
437 * Should only be called by kvm_apic_local_deliver() with LVT0,
438 * before NMI watchdog was enabled. Already handled by
439 * kvm_apic_accept_pic_intr().
440 */
441 break;
442
97222cc8
ED		 443 default:
444 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
445 delivery_mode);
446 break;
447 }
448 return result;
449}
450
e1035715 451int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 452{
e1035715 453 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 454}
455
97222cc8
ED		 456static void apic_set_eoi(struct kvm_lapic *apic)
457{
458 int vector = apic_find_highest_isr(apic);
f5244726 459 int trigger_mode;
97222cc8
ED		 460 /*
461 * Not every write EOI will has corresponding ISR,
462 * one example is when Kernel check timer on setup_IO_APIC
463 */
464 if (vector == -1)
465 return;
466
467 apic_clear_vector(vector, apic->regs + APIC_ISR);
468 apic_update_ppr(apic);
469
470 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 471 trigger_mode = IOAPIC_LEVEL_TRIG;
472 else
473 trigger_mode = IOAPIC_EDGE_TRIG;
eba0226b 474 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
fc61b800 475 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
97222cc8
ED		 476}
477
478static void apic_send_ipi(struct kvm_lapic *apic)
479{
480 u32 icr_low = apic_get_reg(apic, APIC_ICR);
481 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
58c2dde1 482 struct kvm_lapic_irq irq;
97222cc8 483
58c2dde1
GN		 484 irq.vector = icr_low & APIC_VECTOR_MASK;
485 irq.delivery_mode = icr_low & APIC_MODE_MASK;
486 irq.dest_mode = icr_low & APIC_DEST_MASK;
487 irq.level = icr_low & APIC_INT_ASSERT;
488 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
489 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 490 if (apic_x2apic_mode(apic))
491 irq.dest_id = icr_high;
492 else
493 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 494
1000ff8d
GN		 495 trace_kvm_apic_ipi(icr_low, irq.dest_id);
496
97222cc8
ED		 497 apic_debug("icr_high 0x%x, icr_low 0x%x, "
498 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
499 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 500 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 501 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
502 irq.vector);
503
504 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
97222cc8
ED		 505}
506
507static u32 apic_get_tmcct(struct kvm_lapic *apic)
508{
b682b814
MT		 509 ktime_t remaining;
510 s64 ns;
9da8f4e8 511 u32 tmcct;
97222cc8
ED		 512
513 ASSERT(apic != NULL);
514
9da8f4e8 515 /* if initial count is 0, current count should also be 0 */
b682b814 516 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 517 return 0;
518
ace15464 519 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 520 if (ktime_to_ns(remaining) < 0)
521 remaining = ktime_set(0, 0);
522
d3c7b77d
MT		 523 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
524 tmcct = div64_u64(ns,
525 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 526
527 return tmcct;
528}
529
b209749f
AK		 530static void __report_tpr_access(struct kvm_lapic *apic, bool write)
531{
532 struct kvm_vcpu *vcpu = apic->vcpu;
533 struct kvm_run *run = vcpu->run;
534
535 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
5fdbf976 536 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 537 run->tpr_access.is_write = write;
538}
539
540static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
541{
542 if (apic->vcpu->arch.tpr_access_reporting)
543 __report_tpr_access(apic, write);
544}
545
97222cc8
ED		 546static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
547{
548 u32 val = 0;
549
550 if (offset >= LAPIC_MMIO_LENGTH)
551 return 0;
552
553 switch (offset) {
0105d1a5
GN		 554 case APIC_ID:
555 if (apic_x2apic_mode(apic))
556 val = kvm_apic_id(apic);
557 else
558 val = kvm_apic_id(apic) << 24;
559 break;
97222cc8
ED		 560 case APIC_ARBPRI:
561 printk(KERN_WARNING "Access APIC ARBPRI register "
562 "which is for P6\n");
563 break;
564
565 case APIC_TMCCT: /* Timer CCR */
566 val = apic_get_tmcct(apic);
567 break;
568
b209749f
AK		 569 case APIC_TASKPRI:
570 report_tpr_access(apic, false);
571 /* fall thru */
97222cc8 572 default:
6e5d865c 573 apic_update_ppr(apic);
97222cc8
ED		 574 val = apic_get_reg(apic, offset);
575 break;
576 }
577
578 return val;
579}
580
d76685c4
GH		 581static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
582{
583 return container_of(dev, struct kvm_lapic, dev);
584}
585
0105d1a5
GN		 586static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
587 void *data)
97222cc8 588{
97222cc8
ED		 589 unsigned char alignment = offset & 0xf;
590 u32 result;
0105d1a5
GN		 591 /* this bitmask has a bit cleared for each reserver register */
592 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 593
594 if ((alignment + len) > 4) {
4088bb3c
GN		 595 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
596 offset, len);
0105d1a5 597 return 1;
97222cc8 598 }
0105d1a5
GN		 599
600 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 601 apic_debug("KVM_APIC_READ: read reserved register %x\n",
602 offset);
0105d1a5
GN		 603 return 1;
604 }
605
97222cc8
ED		 606 result = __apic_read(apic, offset & ~0xf);
607
229456fc
MT		 608 trace_kvm_apic_read(offset, result);
609
97222cc8
ED		 610 switch (len) {
611 case 1:
612 case 2:
613 case 4:
614 memcpy(data, (char *)&result + alignment, len);
615 break;
616 default:
617 printk(KERN_ERR "Local APIC read with len = %x, "
618 "should be 1,2, or 4 instead\n", len);
619 break;
620 }
bda9020e 621 return 0;
97222cc8
ED		 622}
623
0105d1a5
GN		 624static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
625{
626 return apic_hw_enabled(apic) &&
627 addr >= apic->base_address &&
628 addr < apic->base_address + LAPIC_MMIO_LENGTH;
629}
630
631static int apic_mmio_read(struct kvm_io_device *this,
632 gpa_t address, int len, void *data)
633{
634 struct kvm_lapic *apic = to_lapic(this);
635 u32 offset = address - apic->base_address;
636
637 if (!apic_mmio_in_range(apic, address))
638 return -EOPNOTSUPP;
639
640 apic_reg_read(apic, offset, len, data);
641
642 return 0;
643}
644
97222cc8
ED		 645static void update_divide_count(struct kvm_lapic *apic)
646{
647 u32 tmp1, tmp2, tdcr;
648
649 tdcr = apic_get_reg(apic, APIC_TDCR);
650 tmp1 = tdcr & 0xf;
651 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 652 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 653
654 apic_debug("timer divide count is 0x%x\n",
9b5843dd 655 apic->divide_count);
97222cc8
ED		 656}
657
658static void start_apic_timer(struct kvm_lapic *apic)
659{
d3c7b77d 660 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 661
b2d83cfa 662 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
d3c7b77d
MT		 663 APIC_BUS_CYCLE_NS * apic->divide_count;
664 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 665
d3c7b77d 666 if (!apic->lapic_timer.period)
0b975a3c 667 return;
1444885a
MT		 668 /*
669 * Do not allow the guest to program periodic timers with small
670 * interval, since the hrtimers are not throttled by the host
671 * scheduler.
672 */
673 if (apic_lvtt_period(apic)) {
674 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
675 apic->lapic_timer.period = NSEC_PER_MSEC/2;
676 }
0b975a3c 677
d3c7b77d
MT		 678 hrtimer_start(&apic->lapic_timer.timer,
679 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 680 HRTIMER_MODE_ABS);
681
682 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
683 PRIx64 ", "
684 "timer initial count 0x%x, period %lldns, "
b8688d51 685 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 686 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
687 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 688 apic->lapic_timer.period,
97222cc8 689 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 690 apic->lapic_timer.period)));
97222cc8
ED		 691}
692
cc6e462c
JK		 693static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
694{
695 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
696
697 if (apic_lvt_nmi_mode(lvt0_val)) {
698 if (!nmi_wd_enabled) {
699 apic_debug("Receive NMI setting on APIC_LVT0 "
700 "for cpu %d\n", apic->vcpu->vcpu_id);
701 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
702 }
703 } else if (nmi_wd_enabled)
704 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
705}
706
0105d1a5 707static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 708{
0105d1a5 709 int ret = 0;
97222cc8 710
0105d1a5 711 trace_kvm_apic_write(reg, val);
97222cc8 712
0105d1a5 713 switch (reg) {
97222cc8 714 case APIC_ID: /* Local APIC ID */
0105d1a5
GN		 715 if (!apic_x2apic_mode(apic))
716 apic_set_reg(apic, APIC_ID, val);
717 else
718 ret = 1;
97222cc8
ED		 719 break;
720
721 case APIC_TASKPRI:
b209749f 722 report_tpr_access(apic, true);
97222cc8
ED		 723 apic_set_tpr(apic, val & 0xff);
724 break;
725
726 case APIC_EOI:
727 apic_set_eoi(apic);
728 break;
729
730 case APIC_LDR:
0105d1a5
GN		 731 if (!apic_x2apic_mode(apic))
732 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
733 else
734 ret = 1;
97222cc8
ED		 735 break;
736
737 case APIC_DFR:
0105d1a5
GN		 738 if (!apic_x2apic_mode(apic))
739 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
740 else
741 ret = 1;
97222cc8
ED		 742 break;
743
fc61b800
GN		 744 case APIC_SPIV: {
745 u32 mask = 0x3ff;
746 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
747 mask |= APIC_SPIV_DIRECTED_EOI;
748 apic_set_reg(apic, APIC_SPIV, val & mask);
97222cc8
ED		 749 if (!(val & APIC_SPIV_APIC_ENABLED)) {
750 int i;
751 u32 lvt_val;
752
753 for (i = 0; i < APIC_LVT_NUM; i++) {
754 lvt_val = apic_get_reg(apic,
755 APIC_LVTT + 0x10 * i);
756 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
757 lvt_val | APIC_LVT_MASKED);
758 }
d3c7b77d 759 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 760
761 }
762 break;
fc61b800 763 }
97222cc8
ED		 764 case APIC_ICR:
765 /* No delay here, so we always clear the pending bit */
766 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
767 apic_send_ipi(apic);
768 break;
769
770 case APIC_ICR2:
0105d1a5
GN		 771 if (!apic_x2apic_mode(apic))
772 val &= 0xff000000;
773 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 774 break;
775
23930f95 776 case APIC_LVT0:
cc6e462c 777 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 778 case APIC_LVTT:
779 case APIC_LVTTHMR:
780 case APIC_LVTPC:
97222cc8
ED		 781 case APIC_LVT1:
782 case APIC_LVTERR:
783 /* TODO: Check vector */
784 if (!apic_sw_enabled(apic))
785 val |= APIC_LVT_MASKED;
786
0105d1a5
GN		 787 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
788 apic_set_reg(apic, reg, val);
97222cc8
ED		 789
790 break;
791
792 case APIC_TMICT:
d3c7b77d 793 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 794 apic_set_reg(apic, APIC_TMICT, val);
795 start_apic_timer(apic);
0105d1a5 796 break;
97222cc8
ED		 797
798 case APIC_TDCR:
799 if (val & 4)
800 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
801 apic_set_reg(apic, APIC_TDCR, val);
802 update_divide_count(apic);
803 break;
804
0105d1a5
GN		 805 case APIC_ESR:
806 if (apic_x2apic_mode(apic) && val != 0) {
807 printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
808 ret = 1;
809 }
810 break;
811
812 case APIC_SELF_IPI:
813 if (apic_x2apic_mode(apic)) {
814 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
815 } else
816 ret = 1;
817 break;
97222cc8 818 default:
0105d1a5 819 ret = 1;
97222cc8
ED		 820 break;
821 }
0105d1a5
GN		 822 if (ret)
823 apic_debug("Local APIC Write to read-only register %x\n", reg);
824 return ret;
825}
826
827static int apic_mmio_write(struct kvm_io_device *this,
828 gpa_t address, int len, const void *data)
829{
830 struct kvm_lapic *apic = to_lapic(this);
831 unsigned int offset = address - apic->base_address;
832 u32 val;
833
834 if (!apic_mmio_in_range(apic, address))
835 return -EOPNOTSUPP;
836
837 /*
838 * APIC register must be aligned on 128-bits boundary.
839 * 32/64/128 bits registers must be accessed thru 32 bits.
840 * Refer SDM 8.4.1
841 */
842 if (len != 4 || (offset & 0xf)) {
843 /* Don't shout loud, $infamous_os would cause only noise. */
844 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 845 return 0;
0105d1a5
GN		 846 }
847
848 val = *(u32*)data;
849
850 /* too common printing */
851 if (offset != APIC_EOI)
852 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
853 "0x%x\n", __func__, offset, len, val);
854
855 apic_reg_write(apic, offset & 0xff0, val);
856
bda9020e 857 return 0;
97222cc8
ED		 858}
859
d589444e 860void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 861{
ad312c7c 862 if (!vcpu->arch.apic)
97222cc8
ED		 863 return;
864
d3c7b77d 865 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 866
ad312c7c
ZX		 867 if (vcpu->arch.apic->regs_page)
868 __free_page(vcpu->arch.apic->regs_page);
97222cc8 869
ad312c7c 870 kfree(vcpu->arch.apic);
97222cc8
ED		 871}
872
873/*
874 *----------------------------------------------------------------------
875 * LAPIC interface
876 *----------------------------------------------------------------------
877 */
878
879void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
880{
ad312c7c 881 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 882
883 if (!apic)
884 return;
b93463aa
AK		 885 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
886 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 887}
888
889u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
890{
ad312c7c 891 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 892 u64 tpr;
893
894 if (!apic)
895 return 0;
896 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
897
898 return (tpr & 0xf0) >> 4;
899}
900
901void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
902{
ad312c7c 903 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 904
905 if (!apic) {
906 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 907 vcpu->arch.apic_base = value;
97222cc8
ED		 908 return;
909 }
c5af89b6
GN		 910
911 if (!kvm_vcpu_is_bsp(apic->vcpu))
97222cc8
ED		 912 value &= ~MSR_IA32_APICBASE_BSP;
913
ad312c7c 914 vcpu->arch.apic_base = value;
0105d1a5
GN		 915 if (apic_x2apic_mode(apic)) {
916 u32 id = kvm_apic_id(apic);
917 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
918 apic_set_reg(apic, APIC_LDR, ldr);
919 }
ad312c7c 920 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 921 MSR_IA32_APICBASE_BASE;
922
923 /* with FSB delivery interrupt, we can restart APIC functionality */
924 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 925 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 926
927}
928
c5ec1534 929void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 930{
931 struct kvm_lapic *apic;
932 int i;
933
b8688d51 934 apic_debug("%s\n", __func__);
97222cc8
ED		 935
936 ASSERT(vcpu);
ad312c7c 937 apic = vcpu->arch.apic;
97222cc8
ED		 938 ASSERT(apic != NULL);
939
940 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 941 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 942
943 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
fc61b800 944 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 945
946 for (i = 0; i < APIC_LVT_NUM; i++)
947 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 948 apic_set_reg(apic, APIC_LVT0,
949 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 950
951 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
952 apic_set_reg(apic, APIC_SPIV, 0xff);
953 apic_set_reg(apic, APIC_TASKPRI, 0);
954 apic_set_reg(apic, APIC_LDR, 0);
955 apic_set_reg(apic, APIC_ESR, 0);
956 apic_set_reg(apic, APIC_ICR, 0);
957 apic_set_reg(apic, APIC_ICR2, 0);
958 apic_set_reg(apic, APIC_TDCR, 0);
959 apic_set_reg(apic, APIC_TMICT, 0);
960 for (i = 0; i < 8; i++) {
961 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
962 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
963 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
964 }
33e4c686 965 apic->irr_pending = false;
b33ac88b 966 update_divide_count(apic);
d3c7b77d 967 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 968 if (kvm_vcpu_is_bsp(vcpu))
ad312c7c 969 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 970 apic_update_ppr(apic);
971
e1035715
GN		 972 vcpu->arch.apic_arb_prio = 0;
973
97222cc8 974 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 975 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 976 vcpu, kvm_apic_id(apic),
ad312c7c 977 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 978}
979
343f94fe 980bool kvm_apic_present(struct kvm_vcpu *vcpu)
97222cc8 981{
343f94fe
GN		 982 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
983}
97222cc8 984
343f94fe
GN		 985int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
986{
987 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
97222cc8
ED		 988}
989
990/*
991 *----------------------------------------------------------------------
992 * timer interface
993 *----------------------------------------------------------------------
994 */
1b9778da 995
d3c7b77d 996static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 997{
d3c7b77d
MT		 998 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
999 lapic_timer);
1000 return apic_lvtt_period(apic);
97222cc8
ED		 1001}
1002
3d80840d
MT		 1003int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1004{
1005 struct kvm_lapic *lapic = vcpu->arch.apic;
1006
54aaacee 1007 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 1008 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 1009
1010 return 0;
1011}
1012
8fdb2351 1013static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1014{
8fdb2351 1015 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 1016 int vector, mode, trig_mode;
23930f95 1017
8fdb2351 1018 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1019 vector = reg & APIC_VECTOR_MASK;
1020 mode = reg & APIC_MODE_MASK;
1021 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1022 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1023 }
1024 return 0;
1025}
1b9778da 1026
8fdb2351 1027void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1028{
8fdb2351
JK		 1029 struct kvm_lapic *apic = vcpu->arch.apic;
1030
1031 if (apic)
1032 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1033}
1034
386eb6e8 1035static struct kvm_timer_ops lapic_timer_ops = {
d3c7b77d
MT		 1036 .is_periodic = lapic_is_periodic,
1037};
97222cc8 1038
d76685c4
GH		 1039static const struct kvm_io_device_ops apic_mmio_ops = {
1040 .read = apic_mmio_read,
1041 .write = apic_mmio_write,
d76685c4
GH		 1042};
1043
97222cc8
ED		 1044int kvm_create_lapic(struct kvm_vcpu *vcpu)
1045{
1046 struct kvm_lapic *apic;
1047
1048 ASSERT(vcpu != NULL);
1049 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1050
1051 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1052 if (!apic)
1053 goto nomem;
1054
ad312c7c 1055 vcpu->arch.apic = apic;
97222cc8
ED		 1056
1057 apic->regs_page = alloc_page(GFP_KERNEL);
1058 if (apic->regs_page == NULL) {
1059 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1060 vcpu->vcpu_id);
d589444e 1061 goto nomem_free_apic;
97222cc8
ED		 1062 }
1063 apic->regs = page_address(apic->regs_page);
1064 memset(apic->regs, 0, PAGE_SIZE);
1065 apic->vcpu = vcpu;
1066
d3c7b77d
MT		 1067 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1068 HRTIMER_MODE_ABS);
1069 apic->lapic_timer.timer.function = kvm_timer_fn;
1070 apic->lapic_timer.t_ops = &lapic_timer_ops;
1071 apic->lapic_timer.kvm = vcpu->kvm;
1ed0ce00 1072 apic->lapic_timer.vcpu = vcpu;
d3c7b77d 1073
97222cc8 1074 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 1075 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 1076
c5ec1534 1077 kvm_lapic_reset(vcpu);
d76685c4 1078 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1079
1080 return 0;
d589444e
RR		 1081nomem_free_apic:
1082 kfree(apic);
97222cc8 1083nomem:
97222cc8
ED		 1084 return -ENOMEM;
1085}
97222cc8
ED		 1086
1087int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1088{
ad312c7c 1089 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1090 int highest_irr;
1091
1092 if (!apic || !apic_enabled(apic))
1093 return -1;
1094
6e5d865c 1095 apic_update_ppr(apic);
97222cc8
ED		 1096 highest_irr = apic_find_highest_irr(apic);
1097 if ((highest_irr == -1) ||
1098 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1099 return -1;
1100 return highest_irr;
1101}
1102
40487c68
QH		 1103int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1104{
ad312c7c 1105 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1106 int r = 0;
1107
c5af89b6 1108 if (kvm_vcpu_is_bsp(vcpu)) {
ad312c7c 1109 if (!apic_hw_enabled(vcpu->arch.apic))
40487c68
QH		 1110 r = 1;
1111 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1112 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1113 r = 1;
1114 }
1115 return r;
1116}
1117
1b9778da
ED		 1118void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1119{
ad312c7c 1120 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1121
d3c7b77d 1122 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1123 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1124 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1125 }
1126}
1127
97222cc8
ED		 1128int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1129{
1130 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1131 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1132
1133 if (vector == -1)
1134 return -1;
1135
1136 apic_set_vector(vector, apic->regs + APIC_ISR);
1137 apic_update_ppr(apic);
1138 apic_clear_irr(vector, apic);
1139 return vector;
1140}
96ad2cc6
ED		 1141
1142void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1143{
ad312c7c 1144 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1145
ad312c7c 1146 apic->base_address = vcpu->arch.apic_base &
96ad2cc6 1147 MSR_IA32_APICBASE_BASE;
fc61b800
GN		 1148 kvm_apic_set_version(vcpu);
1149
96ad2cc6 1150 apic_update_ppr(apic);
d3c7b77d 1151 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1152 update_divide_count(apic);
1153 start_apic_timer(apic);
6e24a6ef 1154 apic->irr_pending = true;
96ad2cc6 1155}
a3d7f85f 1156
2f52d58c 1157void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1158{
ad312c7c 1159 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1160 struct hrtimer *timer;
1161
1162 if (!apic)
1163 return;
1164
d3c7b77d 1165 timer = &apic->lapic_timer.timer;
a3d7f85f 1166 if (hrtimer_cancel(timer))
beb20d52 1167 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1168}
b93463aa
AK		 1169
1170void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1171{
1172 u32 data;
1173 void *vapic;
1174
1175 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1176 return;
1177
1178 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1179 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1180 kunmap_atomic(vapic, KM_USER0);
1181
1182 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1183}
1184
1185void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1186{
1187 u32 data, tpr;
1188 int max_irr, max_isr;
1189 struct kvm_lapic *apic;
1190 void *vapic;
1191
1192 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1193 return;
1194
1195 apic = vcpu->arch.apic;
1196 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1197 max_irr = apic_find_highest_irr(apic);
1198 if (max_irr < 0)
1199 max_irr = 0;
1200 max_isr = apic_find_highest_isr(apic);
1201 if (max_isr < 0)
1202 max_isr = 0;
1203 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1204
1205 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1206 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1207 kunmap_atomic(vapic, KM_USER0);
1208}
1209
1210void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1211{
1212 if (!irqchip_in_kernel(vcpu->kvm))
1213 return;
1214
1215 vcpu->arch.apic->vapic_addr = vapic_addr;
1216}
0105d1a5
GN		 1217
1218int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1219{
1220 struct kvm_lapic *apic = vcpu->arch.apic;
1221 u32 reg = (msr - APIC_BASE_MSR) << 4;
1222
1223 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1224 return 1;
1225
1226 /* if this is ICR write vector before command */
1227 if (msr == 0x830)
1228 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1229 return apic_reg_write(apic, reg, (u32)data);
1230}
1231
1232int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1233{
1234 struct kvm_lapic *apic = vcpu->arch.apic;
1235 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1236
1237 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1238 return 1;
1239
1240 if (apic_reg_read(apic, reg, 4, &low))
1241 return 1;
1242 if (msr == 0x830)
1243 apic_reg_read(apic, APIC_ICR2, 4, &high);
1244
1245 *data = (((u64)high) << 32) | low;
1246
1247 return 0;
1248}
Clone of davem's net-next-2.6 tree