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KVM: convert custom marker based tracing to event traces
[net-next-2.6.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
edf88417 20#include <linux/kvm_host.h>
97222cc8
ED		 21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
6f6d6a1a 28#include <linux/math64.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
34#include <asm/atomic.h>
5fdbf976 35#include "kvm_cache_regs.h"
97222cc8 36#include "irq.h"
229456fc 37#include "trace.h"
97222cc8 38
b682b814
MT		 39#ifndef CONFIG_X86_64
40#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
41#else
42#define mod_64(x, y) ((x) % (y))
43#endif
44
97222cc8
ED		 45#define PRId64 "d"
46#define PRIx64 "llx"
47#define PRIu64 "u"
48#define PRIo64 "o"
49
50#define APIC_BUS_CYCLE_NS 1
51
52/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
53#define apic_debug(fmt, arg...)
54
55#define APIC_LVT_NUM 6
56/* 14 is the version for Xeon and Pentium 8.4.8*/
57#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
58#define LAPIC_MMIO_LENGTH (1 << 12)
59/* followed define is not in apicdef.h */
60#define APIC_SHORT_MASK 0xc0000
61#define APIC_DEST_NOSHORT 0x0
62#define APIC_DEST_MASK 0x800
63#define MAX_APIC_VECTOR 256
64
65#define VEC_POS(v) ((v) & (32 - 1))
66#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 67
97222cc8
ED		 68static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
69{
70 return *((u32 *) (apic->regs + reg_off));
71}
72
73static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
74{
75 *((u32 *) (apic->regs + reg_off)) = val;
76}
77
78static inline int apic_test_and_set_vector(int vec, void *bitmap)
79{
80 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
81}
82
83static inline int apic_test_and_clear_vector(int vec, void *bitmap)
84{
85 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
88static inline void apic_set_vector(int vec, void *bitmap)
89{
90 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91}
92
93static inline void apic_clear_vector(int vec, void *bitmap)
94{
95 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96}
97
98static inline int apic_hw_enabled(struct kvm_lapic *apic)
99{
ad312c7c 100 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 101}
102
103static inline int apic_sw_enabled(struct kvm_lapic *apic)
104{
105 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
106}
107
108static inline int apic_enabled(struct kvm_lapic *apic)
109{
110 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
111}
112
113#define LVT_MASK \
114 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
115
116#define LINT_MASK \
117 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
118 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
119
120static inline int kvm_apic_id(struct kvm_lapic *apic)
121{
122 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
123}
124
125static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
126{
127 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
128}
129
130static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
131{
132 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
133}
134
135static inline int apic_lvtt_period(struct kvm_lapic *apic)
136{
137 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
138}
139
cc6e462c
JK		 140static inline int apic_lvt_nmi_mode(u32 lvt_val)
141{
142 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
143}
144
97222cc8
ED		 145static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
146 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
147 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
148 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
149 LINT_MASK, LINT_MASK, /* LVT0-1 */
150 LVT_MASK /* LVTERR */
151};
152
153static int find_highest_vector(void *bitmap)
154{
155 u32 *word = bitmap;
156 int word_offset = MAX_APIC_VECTOR >> 5;
157
158 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
159 continue;
160
161 if (likely(!word_offset && !word[0]))
162 return -1;
163 else
164 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
165}
166
167static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
168{
33e4c686 169 apic->irr_pending = true;
97222cc8
ED		 170 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
171}
172
33e4c686 173static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 174{
33e4c686 175 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 176}
177
178static inline int apic_find_highest_irr(struct kvm_lapic *apic)
179{
180 int result;
181
33e4c686
GN		 182 if (!apic->irr_pending)
183 return -1;
184
185 result = apic_search_irr(apic);
97222cc8
ED		 186 ASSERT(result == -1 || result >= 16);
187
188 return result;
189}
190
33e4c686
GN		 191static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
192{
193 apic->irr_pending = false;
194 apic_clear_vector(vec, apic->regs + APIC_IRR);
195 if (apic_search_irr(apic) != -1)
196 apic->irr_pending = true;
197}
198
6e5d865c
YS		 199int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
200{
ad312c7c 201 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 202 int highest_irr;
203
33e4c686
GN		 204 /* This may race with setting of irr in __apic_accept_irq() and
205 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
206 * will cause vmexit immediately and the value will be recalculated
207 * on the next vmentry.
208 */
6e5d865c
YS		 209 if (!apic)
210 return 0;
211 highest_irr = apic_find_highest_irr(apic);
212
213 return highest_irr;
214}
6e5d865c 215
6da7e3f6
GN		 216static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
217 int vector, int level, int trig_mode);
218
58c2dde1 219int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
97222cc8 220{
ad312c7c 221 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 222
58c2dde1
GN		 223 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
224 irq->level, irq->trig_mode);
97222cc8
ED		 225}
226
227static inline int apic_find_highest_isr(struct kvm_lapic *apic)
228{
229 int result;
230
231 result = find_highest_vector(apic->regs + APIC_ISR);
232 ASSERT(result == -1 || result >= 16);
233
234 return result;
235}
236
237static void apic_update_ppr(struct kvm_lapic *apic)
238{
239 u32 tpr, isrv, ppr;
240 int isr;
241
242 tpr = apic_get_reg(apic, APIC_TASKPRI);
243 isr = apic_find_highest_isr(apic);
244 isrv = (isr != -1) ? isr : 0;
245
246 if ((tpr & 0xf0) >= (isrv & 0xf0))
247 ppr = tpr & 0xff;
248 else
249 ppr = isrv & 0xf0;
250
251 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
252 apic, ppr, isr, isrv);
253
254 apic_set_reg(apic, APIC_PROCPRI, ppr);
255}
256
257static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
258{
259 apic_set_reg(apic, APIC_TASKPRI, tpr);
260 apic_update_ppr(apic);
261}
262
263int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
264{
343f94fe 265 return dest == 0xff || kvm_apic_id(apic) == dest;
97222cc8
ED		 266}
267
268int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
269{
270 int result = 0;
271 u8 logical_id;
272
273 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
274
275 switch (apic_get_reg(apic, APIC_DFR)) {
276 case APIC_DFR_FLAT:
277 if (logical_id & mda)
278 result = 1;
279 break;
280 case APIC_DFR_CLUSTER:
281 if (((logical_id >> 4) == (mda >> 0x4))
282 && (logical_id & mda & 0xf))
283 result = 1;
284 break;
285 default:
286 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
287 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
288 break;
289 }
290
291 return result;
292}
293
343f94fe 294int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
97222cc8
ED		 295 int short_hand, int dest, int dest_mode)
296{
297 int result = 0;
ad312c7c 298 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 299
300 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 301 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 302 target, source, dest, dest_mode, short_hand);
303
304 ASSERT(!target);
305 switch (short_hand) {
306 case APIC_DEST_NOSHORT:
343f94fe 307 if (dest_mode == 0)
97222cc8 308 /* Physical mode. */
343f94fe
GN		 309 result = kvm_apic_match_physical_addr(target, dest);
310 else
97222cc8
ED		 311 /* Logical mode. */
312 result = kvm_apic_match_logical_addr(target, dest);
313 break;
314 case APIC_DEST_SELF:
343f94fe 315 result = (target == source);
97222cc8
ED		 316 break;
317 case APIC_DEST_ALLINC:
318 result = 1;
319 break;
320 case APIC_DEST_ALLBUT:
343f94fe 321 result = (target != source);
97222cc8
ED		 322 break;
323 default:
324 printk(KERN_WARNING "Bad dest shorthand value %x\n",
325 short_hand);
326 break;
327 }
328
329 return result;
330}
331
332/*
333 * Add a pending IRQ into lapic.
334 * Return 1 if successfully added and 0 if discarded.
335 */
336static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
337 int vector, int level, int trig_mode)
338{
6da7e3f6 339 int result = 0;
c5ec1534 340 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 341
342 switch (delivery_mode) {
97222cc8 343 case APIC_DM_LOWEST:
e1035715
GN		 344 vcpu->arch.apic_arb_prio++;
345 case APIC_DM_FIXED:
97222cc8
ED		 346 /* FIXME add logic for vcpu on reset */
347 if (unlikely(!apic_enabled(apic)))
348 break;
349
6da7e3f6
GN		 350 result = !apic_test_and_set_irr(vector, apic);
351 if (!result) {
352 if (trig_mode)
353 apic_debug("level trig mode repeatedly for "
354 "vector %d", vector);
97222cc8
ED		 355 break;
356 }
357
358 if (trig_mode) {
359 apic_debug("level trig mode for vector %d", vector);
360 apic_set_vector(vector, apic->regs + APIC_TMR);
361 } else
362 apic_clear_vector(vector, apic->regs + APIC_TMR);
d7690175 363 kvm_vcpu_kick(vcpu);
97222cc8
ED		 364 break;
365
366 case APIC_DM_REMRD:
367 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
368 break;
369
370 case APIC_DM_SMI:
371 printk(KERN_DEBUG "Ignoring guest SMI\n");
372 break;
3419ffc8 373
97222cc8 374 case APIC_DM_NMI:
6da7e3f6 375 result = 1;
3419ffc8 376 kvm_inject_nmi(vcpu);
26df99c6 377 kvm_vcpu_kick(vcpu);
97222cc8
ED		 378 break;
379
380 case APIC_DM_INIT:
c5ec1534 381 if (level) {
6da7e3f6 382 result = 1;
a4535290 383 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534
HQ		 384 printk(KERN_DEBUG
385 "INIT on a runnable vcpu %d\n",
386 vcpu->vcpu_id);
a4535290 387 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
c5ec1534
HQ		 388 kvm_vcpu_kick(vcpu);
389 } else {
1b10bf31
JK		 390 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
391 vcpu->vcpu_id);
c5ec1534 392 }
97222cc8
ED		 393 break;
394
395 case APIC_DM_STARTUP:
1b10bf31
JK		 396 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
397 vcpu->vcpu_id, vector);
a4535290 398 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6da7e3f6 399 result = 1;
ad312c7c 400 vcpu->arch.sipi_vector = vector;
a4535290 401 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
d7690175 402 kvm_vcpu_kick(vcpu);
c5ec1534 403 }
97222cc8
ED		 404 break;
405
23930f95
JK		 406 case APIC_DM_EXTINT:
407 /*
408 * Should only be called by kvm_apic_local_deliver() with LVT0,
409 * before NMI watchdog was enabled. Already handled by
410 * kvm_apic_accept_pic_intr().
411 */
412 break;
413
97222cc8
ED		 414 default:
415 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
416 delivery_mode);
417 break;
418 }
419 return result;
420}
421
e1035715 422int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 423{
e1035715 424 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 425}
426
97222cc8
ED		 427static void apic_set_eoi(struct kvm_lapic *apic)
428{
429 int vector = apic_find_highest_isr(apic);
f5244726 430 int trigger_mode;
97222cc8
ED		 431 /*
432 * Not every write EOI will has corresponding ISR,
433 * one example is when Kernel check timer on setup_IO_APIC
434 */
435 if (vector == -1)
436 return;
437
438 apic_clear_vector(vector, apic->regs + APIC_ISR);
439 apic_update_ppr(apic);
440
441 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 442 trigger_mode = IOAPIC_LEVEL_TRIG;
443 else
444 trigger_mode = IOAPIC_EDGE_TRIG;
fa40a821 445 mutex_lock(&apic->vcpu->kvm->irq_lock);
f5244726 446 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
fa40a821 447 mutex_unlock(&apic->vcpu->kvm->irq_lock);
97222cc8
ED		 448}
449
450static void apic_send_ipi(struct kvm_lapic *apic)
451{
452 u32 icr_low = apic_get_reg(apic, APIC_ICR);
453 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
58c2dde1 454 struct kvm_lapic_irq irq;
97222cc8 455
58c2dde1
GN		 456 irq.vector = icr_low & APIC_VECTOR_MASK;
457 irq.delivery_mode = icr_low & APIC_MODE_MASK;
458 irq.dest_mode = icr_low & APIC_DEST_MASK;
459 irq.level = icr_low & APIC_INT_ASSERT;
460 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
461 irq.shorthand = icr_low & APIC_SHORT_MASK;
462 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8
ED		 463
464 apic_debug("icr_high 0x%x, icr_low 0x%x, "
465 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
466 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 467 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 468 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
469 irq.vector);
470
fa40a821 471 mutex_lock(&apic->vcpu->kvm->irq_lock);
58c2dde1 472 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
fa40a821 473 mutex_unlock(&apic->vcpu->kvm->irq_lock);
97222cc8
ED		 474}
475
476static u32 apic_get_tmcct(struct kvm_lapic *apic)
477{
b682b814
MT		 478 ktime_t remaining;
479 s64 ns;
9da8f4e8 480 u32 tmcct;
97222cc8
ED		 481
482 ASSERT(apic != NULL);
483
9da8f4e8 484 /* if initial count is 0, current count should also be 0 */
b682b814 485 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 486 return 0;
487
d3c7b77d 488 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
b682b814
MT		 489 if (ktime_to_ns(remaining) < 0)
490 remaining = ktime_set(0, 0);
491
d3c7b77d
MT		 492 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
493 tmcct = div64_u64(ns,
494 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 495
496 return tmcct;
497}
498
b209749f
AK		 499static void __report_tpr_access(struct kvm_lapic *apic, bool write)
500{
501 struct kvm_vcpu *vcpu = apic->vcpu;
502 struct kvm_run *run = vcpu->run;
503
504 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
5fdbf976 505 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 506 run->tpr_access.is_write = write;
507}
508
509static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
510{
511 if (apic->vcpu->arch.tpr_access_reporting)
512 __report_tpr_access(apic, write);
513}
514
97222cc8
ED		 515static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
516{
517 u32 val = 0;
518
519 if (offset >= LAPIC_MMIO_LENGTH)
520 return 0;
521
522 switch (offset) {
523 case APIC_ARBPRI:
524 printk(KERN_WARNING "Access APIC ARBPRI register "
525 "which is for P6\n");
526 break;
527
528 case APIC_TMCCT: /* Timer CCR */
529 val = apic_get_tmcct(apic);
530 break;
531
b209749f
AK		 532 case APIC_TASKPRI:
533 report_tpr_access(apic, false);
534 /* fall thru */
97222cc8 535 default:
6e5d865c 536 apic_update_ppr(apic);
97222cc8
ED		 537 val = apic_get_reg(apic, offset);
538 break;
539 }
540
541 return val;
542}
543
d76685c4
GH		 544static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
545{
546 return container_of(dev, struct kvm_lapic, dev);
547}
548
97222cc8
ED		 549static void apic_mmio_read(struct kvm_io_device *this,
550 gpa_t address, int len, void *data)
551{
d76685c4 552 struct kvm_lapic *apic = to_lapic(this);
97222cc8
ED		 553 unsigned int offset = address - apic->base_address;
554 unsigned char alignment = offset & 0xf;
555 u32 result;
556
557 if ((alignment + len) > 4) {
558 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
559 (unsigned long)address, len);
560 return;
561 }
562 result = __apic_read(apic, offset & ~0xf);
563
229456fc
MT		 564 trace_kvm_apic_read(offset, result);
565
97222cc8
ED		 566 switch (len) {
567 case 1:
568 case 2:
569 case 4:
570 memcpy(data, (char *)&result + alignment, len);
571 break;
572 default:
573 printk(KERN_ERR "Local APIC read with len = %x, "
574 "should be 1,2, or 4 instead\n", len);
575 break;
576 }
577}
578
579static void update_divide_count(struct kvm_lapic *apic)
580{
581 u32 tmp1, tmp2, tdcr;
582
583 tdcr = apic_get_reg(apic, APIC_TDCR);
584 tmp1 = tdcr & 0xf;
585 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 586 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 587
588 apic_debug("timer divide count is 0x%x\n",
9b5843dd 589 apic->divide_count);
97222cc8
ED		 590}
591
592static void start_apic_timer(struct kvm_lapic *apic)
593{
d3c7b77d 594 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 595
d3c7b77d
MT		 596 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
597 APIC_BUS_CYCLE_NS * apic->divide_count;
598 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 599
d3c7b77d 600 if (!apic->lapic_timer.period)
0b975a3c
AK		 601 return;
602
d3c7b77d
MT		 603 hrtimer_start(&apic->lapic_timer.timer,
604 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 605 HRTIMER_MODE_ABS);
606
607 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
608 PRIx64 ", "
609 "timer initial count 0x%x, period %lldns, "
b8688d51 610 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 611 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
612 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 613 apic->lapic_timer.period,
97222cc8 614 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 615 apic->lapic_timer.period)));
97222cc8
ED		 616}
617
cc6e462c
JK		 618static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
619{
620 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
621
622 if (apic_lvt_nmi_mode(lvt0_val)) {
623 if (!nmi_wd_enabled) {
624 apic_debug("Receive NMI setting on APIC_LVT0 "
625 "for cpu %d\n", apic->vcpu->vcpu_id);
626 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
627 }
628 } else if (nmi_wd_enabled)
629 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
630}
631
97222cc8
ED		 632static void apic_mmio_write(struct kvm_io_device *this,
633 gpa_t address, int len, const void *data)
634{
d76685c4 635 struct kvm_lapic *apic = to_lapic(this);
97222cc8
ED		 636 unsigned int offset = address - apic->base_address;
637 unsigned char alignment = offset & 0xf;
638 u32 val;
639
640 /*
641 * APIC register must be aligned on 128-bits boundary.
642 * 32/64/128 bits registers must be accessed thru 32 bits.
643 * Refer SDM 8.4.1
644 */
645 if (len != 4 || alignment) {
1b10bf31
JK		 646 /* Don't shout loud, $infamous_os would cause only noise. */
647 apic_debug("apic write: bad size=%d %lx\n",
648 len, (long)address);
97222cc8
ED		 649 return;
650 }
651
652 val = *(u32 *) data;
653
654 /* too common printing */
655 if (offset != APIC_EOI)
656 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
b8688d51 657 "0x%x\n", __func__, offset, len, val);
97222cc8
ED		 658
659 offset &= 0xff0;
660
229456fc 661 trace_kvm_apic_write(offset, val);
c7bf23ba 662
97222cc8
ED		 663 switch (offset) {
664 case APIC_ID: /* Local APIC ID */
665 apic_set_reg(apic, APIC_ID, val);
666 break;
667
668 case APIC_TASKPRI:
b209749f 669 report_tpr_access(apic, true);
97222cc8
ED		 670 apic_set_tpr(apic, val & 0xff);
671 break;
672
673 case APIC_EOI:
674 apic_set_eoi(apic);
675 break;
676
677 case APIC_LDR:
678 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
679 break;
680
681 case APIC_DFR:
682 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
683 break;
684
685 case APIC_SPIV:
686 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
687 if (!(val & APIC_SPIV_APIC_ENABLED)) {
688 int i;
689 u32 lvt_val;
690
691 for (i = 0; i < APIC_LVT_NUM; i++) {
692 lvt_val = apic_get_reg(apic,
693 APIC_LVTT + 0x10 * i);
694 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
695 lvt_val | APIC_LVT_MASKED);
696 }
d3c7b77d 697 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 698
699 }
700 break;
701
702 case APIC_ICR:
703 /* No delay here, so we always clear the pending bit */
704 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
705 apic_send_ipi(apic);
706 break;
707
708 case APIC_ICR2:
709 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
710 break;
711
23930f95 712 case APIC_LVT0:
cc6e462c 713 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 714 case APIC_LVTT:
715 case APIC_LVTTHMR:
716 case APIC_LVTPC:
97222cc8
ED		 717 case APIC_LVT1:
718 case APIC_LVTERR:
719 /* TODO: Check vector */
720 if (!apic_sw_enabled(apic))
721 val |= APIC_LVT_MASKED;
722
723 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
724 apic_set_reg(apic, offset, val);
725
726 break;
727
728 case APIC_TMICT:
d3c7b77d 729 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 730 apic_set_reg(apic, APIC_TMICT, val);
731 start_apic_timer(apic);
732 return;
733
734 case APIC_TDCR:
735 if (val & 4)
736 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
737 apic_set_reg(apic, APIC_TDCR, val);
738 update_divide_count(apic);
739 break;
740
741 default:
742 apic_debug("Local APIC Write to read-only register %x\n",
743 offset);
744 break;
745 }
746
747}
748
92760499
LV		 749static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
750 int len, int size)
97222cc8 751{
d76685c4 752 struct kvm_lapic *apic = to_lapic(this);
97222cc8
ED		 753 int ret = 0;
754
755
756 if (apic_hw_enabled(apic) &&
757 (addr >= apic->base_address) &&
758 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
759 ret = 1;
760
761 return ret;
762}
763
d589444e 764void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 765{
ad312c7c 766 if (!vcpu->arch.apic)
97222cc8
ED		 767 return;
768
d3c7b77d 769 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 770
ad312c7c
ZX		 771 if (vcpu->arch.apic->regs_page)
772 __free_page(vcpu->arch.apic->regs_page);
97222cc8 773
ad312c7c 774 kfree(vcpu->arch.apic);
97222cc8
ED		 775}
776
777/*
778 *----------------------------------------------------------------------
779 * LAPIC interface
780 *----------------------------------------------------------------------
781 */
782
783void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
784{
ad312c7c 785 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 786
787 if (!apic)
788 return;
b93463aa
AK		 789 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
790 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 791}
792
793u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
794{
ad312c7c 795 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 796 u64 tpr;
797
798 if (!apic)
799 return 0;
800 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
801
802 return (tpr & 0xf0) >> 4;
803}
804
805void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
806{
ad312c7c 807 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 808
809 if (!apic) {
810 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 811 vcpu->arch.apic_base = value;
97222cc8
ED		 812 return;
813 }
c5af89b6
GN		 814
815 if (!kvm_vcpu_is_bsp(apic->vcpu))
97222cc8
ED		 816 value &= ~MSR_IA32_APICBASE_BSP;
817
ad312c7c
ZX		 818 vcpu->arch.apic_base = value;
819 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 820 MSR_IA32_APICBASE_BASE;
821
822 /* with FSB delivery interrupt, we can restart APIC functionality */
823 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 824 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 825
826}
827
c5ec1534 828void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 829{
830 struct kvm_lapic *apic;
831 int i;
832
b8688d51 833 apic_debug("%s\n", __func__);
97222cc8
ED		 834
835 ASSERT(vcpu);
ad312c7c 836 apic = vcpu->arch.apic;
97222cc8
ED		 837 ASSERT(apic != NULL);
838
839 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 840 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 841
842 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
843 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
844
845 for (i = 0; i < APIC_LVT_NUM; i++)
846 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 847 apic_set_reg(apic, APIC_LVT0,
848 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 849
850 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
851 apic_set_reg(apic, APIC_SPIV, 0xff);
852 apic_set_reg(apic, APIC_TASKPRI, 0);
853 apic_set_reg(apic, APIC_LDR, 0);
854 apic_set_reg(apic, APIC_ESR, 0);
855 apic_set_reg(apic, APIC_ICR, 0);
856 apic_set_reg(apic, APIC_ICR2, 0);
857 apic_set_reg(apic, APIC_TDCR, 0);
858 apic_set_reg(apic, APIC_TMICT, 0);
859 for (i = 0; i < 8; i++) {
860 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
861 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
862 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
863 }
33e4c686 864 apic->irr_pending = false;
b33ac88b 865 update_divide_count(apic);
d3c7b77d 866 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 867 if (kvm_vcpu_is_bsp(vcpu))
ad312c7c 868 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 869 apic_update_ppr(apic);
870
e1035715
GN		 871 vcpu->arch.apic_arb_prio = 0;
872
97222cc8 873 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 874 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 875 vcpu, kvm_apic_id(apic),
ad312c7c 876 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 877}
878
343f94fe 879bool kvm_apic_present(struct kvm_vcpu *vcpu)
97222cc8 880{
343f94fe
GN		 881 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
882}
97222cc8 883
343f94fe
GN		 884int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
885{
886 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
97222cc8
ED		 887}
888
889/*
890 *----------------------------------------------------------------------
891 * timer interface
892 *----------------------------------------------------------------------
893 */
1b9778da 894
d3c7b77d 895static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 896{
d3c7b77d
MT		 897 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
898 lapic_timer);
899 return apic_lvtt_period(apic);
97222cc8
ED		 900}
901
3d80840d
MT		 902int apic_has_pending_timer(struct kvm_vcpu *vcpu)
903{
904 struct kvm_lapic *lapic = vcpu->arch.apic;
905
54aaacee 906 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 907 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 908
909 return 0;
910}
911
8fdb2351 912static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 913{
8fdb2351 914 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 915 int vector, mode, trig_mode;
23930f95 916
8fdb2351 917 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 918 vector = reg & APIC_VECTOR_MASK;
919 mode = reg & APIC_MODE_MASK;
920 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
921 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
922 }
923 return 0;
924}
1b9778da 925
8fdb2351 926void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 927{
8fdb2351
JK		 928 struct kvm_lapic *apic = vcpu->arch.apic;
929
930 if (apic)
931 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 932}
933
386eb6e8 934static struct kvm_timer_ops lapic_timer_ops = {
d3c7b77d
MT		 935 .is_periodic = lapic_is_periodic,
936};
97222cc8 937
d76685c4
GH		 938static const struct kvm_io_device_ops apic_mmio_ops = {
939 .read = apic_mmio_read,
940 .write = apic_mmio_write,
941 .in_range = apic_mmio_range,
942};
943
97222cc8
ED		 944int kvm_create_lapic(struct kvm_vcpu *vcpu)
945{
946 struct kvm_lapic *apic;
947
948 ASSERT(vcpu != NULL);
949 apic_debug("apic_init %d\n", vcpu->vcpu_id);
950
951 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
952 if (!apic)
953 goto nomem;
954
ad312c7c 955 vcpu->arch.apic = apic;
97222cc8
ED		 956
957 apic->regs_page = alloc_page(GFP_KERNEL);
958 if (apic->regs_page == NULL) {
959 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
960 vcpu->vcpu_id);
d589444e 961 goto nomem_free_apic;
97222cc8
ED		 962 }
963 apic->regs = page_address(apic->regs_page);
964 memset(apic->regs, 0, PAGE_SIZE);
965 apic->vcpu = vcpu;
966
d3c7b77d
MT		 967 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
968 HRTIMER_MODE_ABS);
969 apic->lapic_timer.timer.function = kvm_timer_fn;
970 apic->lapic_timer.t_ops = &lapic_timer_ops;
971 apic->lapic_timer.kvm = vcpu->kvm;
1ed0ce00 972 apic->lapic_timer.vcpu = vcpu;
d3c7b77d 973
97222cc8 974 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 975 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 976
c5ec1534 977 kvm_lapic_reset(vcpu);
d76685c4 978 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 979
980 return 0;
d589444e
RR		 981nomem_free_apic:
982 kfree(apic);
97222cc8 983nomem:
97222cc8
ED		 984 return -ENOMEM;
985}
97222cc8
ED		 986
987int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
988{
ad312c7c 989 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 990 int highest_irr;
991
992 if (!apic || !apic_enabled(apic))
993 return -1;
994
6e5d865c 995 apic_update_ppr(apic);
97222cc8
ED		 996 highest_irr = apic_find_highest_irr(apic);
997 if ((highest_irr == -1) ||
998 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
999 return -1;
1000 return highest_irr;
1001}
1002
40487c68
QH		 1003int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1004{
ad312c7c 1005 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1006 int r = 0;
1007
c5af89b6 1008 if (kvm_vcpu_is_bsp(vcpu)) {
ad312c7c 1009 if (!apic_hw_enabled(vcpu->arch.apic))
40487c68
QH		 1010 r = 1;
1011 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1012 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1013 r = 1;
1014 }
1015 return r;
1016}
1017
1b9778da
ED		 1018void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1019{
ad312c7c 1020 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1021
d3c7b77d 1022 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1023 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1024 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1025 }
1026}
1027
97222cc8
ED		 1028int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1029{
1030 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1031 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1032
1033 if (vector == -1)
1034 return -1;
1035
1036 apic_set_vector(vector, apic->regs + APIC_ISR);
1037 apic_update_ppr(apic);
1038 apic_clear_irr(vector, apic);
1039 return vector;
1040}
96ad2cc6
ED		 1041
1042void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1043{
ad312c7c 1044 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1045
ad312c7c 1046 apic->base_address = vcpu->arch.apic_base &
96ad2cc6
ED		 1047 MSR_IA32_APICBASE_BASE;
1048 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1049 apic_update_ppr(apic);
d3c7b77d 1050 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1051 update_divide_count(apic);
1052 start_apic_timer(apic);
1053}
a3d7f85f 1054
2f52d58c 1055void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1056{
ad312c7c 1057 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1058 struct hrtimer *timer;
1059
1060 if (!apic)
1061 return;
1062
d3c7b77d 1063 timer = &apic->lapic_timer.timer;
a3d7f85f 1064 if (hrtimer_cancel(timer))
beb20d52 1065 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1066}
b93463aa
AK		 1067
1068void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1069{
1070 u32 data;
1071 void *vapic;
1072
1073 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1074 return;
1075
1076 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1077 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1078 kunmap_atomic(vapic, KM_USER0);
1079
1080 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1081}
1082
1083void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1084{
1085 u32 data, tpr;
1086 int max_irr, max_isr;
1087 struct kvm_lapic *apic;
1088 void *vapic;
1089
1090 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1091 return;
1092
1093 apic = vcpu->arch.apic;
1094 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1095 max_irr = apic_find_highest_irr(apic);
1096 if (max_irr < 0)
1097 max_irr = 0;
1098 max_isr = apic_find_highest_isr(apic);
1099 if (max_isr < 0)
1100 max_isr = 0;
1101 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1102
1103 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1104 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1105 kunmap_atomic(vapic, KM_USER0);
1106}
1107
1108void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1109{
1110 if (!irqchip_in_kernel(vcpu->kvm))
1111 return;
1112
1113 vcpu->arch.apic->vapic_addr = vapic_addr;
1114}
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