[net-next-2.6.git] / arch / x86 / kernel / tsc.c

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/acpi_pmtmr.h>
#include <linux/cpufreq.h>
#include <linux/dmi.h>
#include <linux/delay.h>
#include <linux/clocksource.h>
#include <linux/percpu.h>

#include <asm/hpet.h>
#include <asm/timer.h>
#include <asm/vgtod.h>
#include <asm/time.h>
#include <asm/delay.h>

unsigned int cpu_khz;           /* TSC clocks / usec, not used here */
EXPORT_SYMBOL(cpu_khz);
unsigned int tsc_khz;
EXPORT_SYMBOL(tsc_khz);

/*
 * TSC can be unstable due to cpufreq or due to unsynced TSCs
 */
static int tsc_unstable;

/* native_sched_clock() is called before tsc_init(), so
   we must start with the TSC soft disabled to prevent
   erroneous rdtsc usage on !cpu_has_tsc processors */
static int tsc_disabled = -1;

/*
 * Scheduler clock - returns current time in nanosec units.
 */
u64 native_sched_clock(void)
{
	u64 this_offset;

	/*
	 * Fall back to jiffies if there's no TSC available:
	 * ( But note that we still use it if the TSC is marked
	 *   unstable. We do this because unlike Time Of Day,
	 *   the scheduler clock tolerates small errors and it's
	 *   very important for it to be as fast as the platform
	 *   can achive it. )
	 */
	if (unlikely(tsc_disabled)) {
		/* No locking but a rare wrong value is not a big deal: */
		return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
	}

	/* read the Time Stamp Counter: */
	rdtscll(this_offset);

	/* return the value in ns */
	return cycles_2_ns(this_offset);
}

/* We need to define a real function for sched_clock, to override the
   weak default version */
#ifdef CONFIG_PARAVIRT
unsigned long long sched_clock(void)
{
	return paravirt_sched_clock();
}
#else
unsigned long long
sched_clock(void) __attribute__((alias("native_sched_clock")));
#endif

int check_tsc_unstable(void)
{
	return tsc_unstable;
}
EXPORT_SYMBOL_GPL(check_tsc_unstable);

#ifdef CONFIG_X86_TSC
int __init notsc_setup(char *str)
{
	printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
			"cannot disable TSC completely.\n");
	tsc_disabled = 1;
	return 1;
}
#else
/*
 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
 * in cpu/common.c
 */
int __init notsc_setup(char *str)
{
	setup_clear_cpu_cap(X86_FEATURE_TSC);
	return 1;
}
#endif

__setup("notsc", notsc_setup);

#define MAX_RETRIES     5
#define SMI_TRESHOLD    50000

/*
 * Read TSC and the reference counters. Take care of SMI disturbance
 */
static u64 tsc_read_refs(u64 *pm, u64 *hpet)
{
	u64 t1, t2;
	int i;

	for (i = 0; i < MAX_RETRIES; i++) {
		t1 = get_cycles();
		if (hpet)
			*hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
		else
			*pm = acpi_pm_read_early();
		t2 = get_cycles();
		if ((t2 - t1) < SMI_TRESHOLD)
			return t2;
	}
	return ULLONG_MAX;
}

/**
 * native_calibrate_tsc - calibrate the tsc on boot
 */
unsigned long native_calibrate_tsc(void)
{
	unsigned long flags;
	u64 tsc1, tsc2, tr1, tr2, delta, pm1, pm2, hpet1, hpet2;
	int hpet = is_hpet_enabled();
	unsigned int tsc_khz_val = 0;

	local_irq_save(flags);

	tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);

	outb((inb(0x61) & ~0x02) | 0x01, 0x61);

	outb(0xb0, 0x43);
	outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
	outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
	tr1 = get_cycles();
	while ((inb(0x61) & 0x20) == 0);
	tr2 = get_cycles();

	tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);

	local_irq_restore(flags);

	/*
	 * Preset the result with the raw and inaccurate PIT
	 * calibration value
	 */
	delta = (tr2 - tr1);
	do_div(delta, 50);
	tsc_khz_val = delta;

	/* hpet or pmtimer available ? */
	if (!hpet && !pm1 && !pm2) {
		printk(KERN_INFO "TSC calibrated against PIT\n");
		goto out;
	}

	/* Check, whether the sampling was disturbed by an SMI */
	if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) {
		printk(KERN_WARNING "TSC calibration disturbed by SMI, "
				"using PIT calibration result\n");
		goto out;
	}

	tsc2 = (tsc2 - tsc1) * 1000000LL;

	if (hpet) {
		printk(KERN_INFO "TSC calibrated against HPET\n");
		if (hpet2 < hpet1)
			hpet2 += 0x100000000ULL;
		hpet2 -= hpet1;
		tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
		do_div(tsc1, 1000000);
	} else {
		printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
		if (pm2 < pm1)
			pm2 += (u64)ACPI_PM_OVRRUN;
		pm2 -= pm1;
		tsc1 = pm2 * 1000000000LL;
		do_div(tsc1, PMTMR_TICKS_PER_SEC);
	}

	do_div(tsc2, tsc1);
	tsc_khz_val = tsc2;

out:
	return tsc_khz_val;
}


#ifdef CONFIG_X86_32
/* Only called from the Powernow K7 cpu freq driver */
int recalibrate_cpu_khz(void)
{
#ifndef CONFIG_SMP
	unsigned long cpu_khz_old = cpu_khz;

	if (cpu_has_tsc) {
		tsc_khz = calibrate_tsc();
		cpu_khz = tsc_khz;
		cpu_data(0).loops_per_jiffy =
			cpufreq_scale(cpu_data(0).loops_per_jiffy,
					cpu_khz_old, cpu_khz);
		return 0;
	} else
		return -ENODEV;
#else
	return -ENODEV;
#endif
}

EXPORT_SYMBOL(recalibrate_cpu_khz);

#endif /* CONFIG_X86_32 */

/* Accelerators for sched_clock()
 * convert from cycles(64bits) => nanoseconds (64bits)
 *  basic equation:
 *              ns = cycles / (freq / ns_per_sec)
 *              ns = cycles * (ns_per_sec / freq)
 *              ns = cycles * (10^9 / (cpu_khz * 10^3))
 *              ns = cycles * (10^6 / cpu_khz)
 *
 *      Then we use scaling math (suggested by george@mvista.com) to get:
 *              ns = cycles * (10^6 * SC / cpu_khz) / SC
 *              ns = cycles * cyc2ns_scale / SC
 *
 *      And since SC is a constant power of two, we can convert the div
 *  into a shift.
 *
 *  We can use khz divisor instead of mhz to keep a better precision, since
 *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
 *  (mathieu.desnoyers@polymtl.ca)
 *
 *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
 */

DEFINE_PER_CPU(unsigned long, cyc2ns);

static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
{
	unsigned long long tsc_now, ns_now;
	unsigned long flags, *scale;

	local_irq_save(flags);
	sched_clock_idle_sleep_event();

	scale = &per_cpu(cyc2ns, cpu);

	rdtscll(tsc_now);
	ns_now = __cycles_2_ns(tsc_now);

	if (cpu_khz)
		*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;

	sched_clock_idle_wakeup_event(0);
	local_irq_restore(flags);
}

#ifdef CONFIG_CPU_FREQ

/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
 * changes.
 *
 * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
 * not that important because current Opteron setups do not support
 * scaling on SMP anyroads.
 *
 * Should fix up last_tsc too. Currently gettimeofday in the
 * first tick after the change will be slightly wrong.
 */

static unsigned int  ref_freq;
static unsigned long loops_per_jiffy_ref;
static unsigned long tsc_khz_ref;

static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
				void *data)
{
	struct cpufreq_freqs *freq = data;
	unsigned long *lpj, dummy;

	if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
		return 0;

	lpj = &dummy;
	if (!(freq->flags & CPUFREQ_CONST_LOOPS))
#ifdef CONFIG_SMP
		lpj = &cpu_data(freq->cpu).loops_per_jiffy;
#else
	lpj = &boot_cpu_data.loops_per_jiffy;
#endif

	if (!ref_freq) {
		ref_freq = freq->old;
		loops_per_jiffy_ref = *lpj;
		tsc_khz_ref = tsc_khz;
	}
	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
			(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
			(val == CPUFREQ_RESUMECHANGE)) {
		*lpj = 	cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);

		tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
		if (!(freq->flags & CPUFREQ_CONST_LOOPS))
			mark_tsc_unstable("cpufreq changes");
	}

	set_cyc2ns_scale(tsc_khz_ref, freq->cpu);

	return 0;
}

static struct notifier_block time_cpufreq_notifier_block = {
	.notifier_call  = time_cpufreq_notifier
};

static int __init cpufreq_tsc(void)
{
	cpufreq_register_notifier(&time_cpufreq_notifier_block,
				CPUFREQ_TRANSITION_NOTIFIER);
	return 0;
}

core_initcall(cpufreq_tsc);

#endif /* CONFIG_CPU_FREQ */

/* clocksource code */

static struct clocksource clocksource_tsc;

/*
 * We compare the TSC to the cycle_last value in the clocksource
 * structure to avoid a nasty time-warp. This can be observed in a
 * very small window right after one CPU updated cycle_last under
 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
 * is smaller than the cycle_last reference value due to a TSC which
 * is slighty behind. This delta is nowhere else observable, but in
 * that case it results in a forward time jump in the range of hours
 * due to the unsigned delta calculation of the time keeping core
 * code, which is necessary to support wrapping clocksources like pm
 * timer.
 */
static cycle_t read_tsc(void)
{
	cycle_t ret = (cycle_t)get_cycles();

	return ret >= clocksource_tsc.cycle_last ?
		ret : clocksource_tsc.cycle_last;
}

#ifdef CONFIG_X86_64
static cycle_t __vsyscall_fn vread_tsc(void)
{
	cycle_t ret = (cycle_t)vget_cycles();

	return ret >= __vsyscall_gtod_data.clock.cycle_last ?
		ret : __vsyscall_gtod_data.clock.cycle_last;
}
#endif

static struct clocksource clocksource_tsc = {
	.name                   = "tsc",
	.rating                 = 300,
	.read                   = read_tsc,
	.mask                   = CLOCKSOURCE_MASK(64),
	.shift                  = 22,
	.flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
				  CLOCK_SOURCE_MUST_VERIFY,
#ifdef CONFIG_X86_64
	.vread                  = vread_tsc,
#endif
};

void mark_tsc_unstable(char *reason)
{
	if (!tsc_unstable) {
		tsc_unstable = 1;
		printk("Marking TSC unstable due to %s\n", reason);
		/* Change only the rating, when not registered */
		if (clocksource_tsc.mult)
			clocksource_change_rating(&clocksource_tsc, 0);
		else
			clocksource_tsc.rating = 0;
	}
}

EXPORT_SYMBOL_GPL(mark_tsc_unstable);

static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
{
	printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
			d->ident);
	tsc_unstable = 1;
	return 0;
}

/* List of systems that have known TSC problems */
static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
	{
		.callback = dmi_mark_tsc_unstable,
		.ident = "IBM Thinkpad 380XD",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
			DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
		},
	},
	{}
};

/*
 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
 */
#ifdef CONFIG_MGEODE_LX
/* RTSC counts during suspend */
#define RTSC_SUSP 0x100

static void __init check_geode_tsc_reliable(void)
{
	unsigned long res_low, res_high;

	rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
	if (res_low & RTSC_SUSP)
		clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
}
#else
static inline void check_geode_tsc_reliable(void) { }
#endif

/*
 * Make an educated guess if the TSC is trustworthy and synchronized
 * over all CPUs.
 */
__cpuinit int unsynchronized_tsc(void)
{
	if (!cpu_has_tsc || tsc_unstable)
		return 1;

#ifdef CONFIG_SMP
	if (apic_is_clustered_box())
		return 1;
#endif

	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
		return 0;
	/*
	 * Intel systems are normally all synchronized.
	 * Exceptions must mark TSC as unstable:
	 */
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
		/* assume multi socket systems are not synchronized: */
		if (num_possible_cpus() > 1)
			tsc_unstable = 1;
	}

	return tsc_unstable;
}

static void __init init_tsc_clocksource(void)
{
	clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
			clocksource_tsc.shift);
	/* lower the rating if we already know its unstable: */
	if (check_tsc_unstable()) {
		clocksource_tsc.rating = 0;
		clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
	}
	clocksource_register(&clocksource_tsc);
}

void __init tsc_init(void)
{
	u64 lpj;
	int cpu;

	if (!cpu_has_tsc)
		return;

	tsc_khz = calibrate_tsc();
	cpu_khz = tsc_khz;

	if (!tsc_khz) {
		mark_tsc_unstable("could not calculate TSC khz");
		return;
	}

#ifdef CONFIG_X86_64
	if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
			(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
		cpu_khz = calibrate_cpu();
#endif

	lpj = ((u64)tsc_khz * 1000);
	do_div(lpj, HZ);
	lpj_fine = lpj;

	printk("Detected %lu.%03lu MHz processor.\n",
			(unsigned long)cpu_khz / 1000,
			(unsigned long)cpu_khz % 1000);

	/*
	 * Secondary CPUs do not run through tsc_init(), so set up
	 * all the scale factors for all CPUs, assuming the same
	 * speed as the bootup CPU. (cpufreq notifiers will fix this
	 * up if their speed diverges)
	 */
	for_each_possible_cpu(cpu)
		set_cyc2ns_scale(cpu_khz, cpu);

	if (tsc_disabled > 0)
		return;

	/* now allow native_sched_clock() to use rdtsc */
	tsc_disabled = 0;

	use_tsc_delay();
	/* Check and install the TSC clocksource */
	dmi_check_system(bad_tsc_dmi_table);

	if (unsynchronized_tsc())
		mark_tsc_unstable("TSCs unsynchronized");

	check_geode_tsc_reliable();
	init_tsc_clocksource();
}
Commit	Line	Data
bfc0f594	1	#include <linux/kernel.h>
0ef95533 AK	2	#include <linux/sched.h>
	3	#include <linux/init.h>
	4	#include <linux/module.h>
	5	#include <linux/timer.h>
bfc0f594	6	#include <linux/acpi_pmtmr.h>
2dbe06fa	7	#include <linux/cpufreq.h>
8fbbc4b4 AK	8	#include <linux/dmi.h>
	9	#include <linux/delay.h>
	10	#include <linux/clocksource.h>
	11	#include <linux/percpu.h>
bfc0f594 AK	12
bfc0f594 AK	13	#include <asm/hpet.h>
8fbbc4b4 AK	14	#include <asm/timer.h>
	15	#include <asm/vgtod.h>
	16	#include <asm/time.h>
	17	#include <asm/delay.h>
0ef95533 AK	18
	19	unsigned int cpu_khz; /* TSC clocks / usec, not used here */
	20	EXPORT_SYMBOL(cpu_khz);
	21	unsigned int tsc_khz;
	22	EXPORT_SYMBOL(tsc_khz);
	23
	24	/*
	25	* TSC can be unstable due to cpufreq or due to unsynced TSCs
	26	*/
8fbbc4b4	27	static int tsc_unstable;
0ef95533 AK	28
	29	/* native_sched_clock() is called before tsc_init(), so
	30	we must start with the TSC soft disabled to prevent
	31	erroneous rdtsc usage on !cpu_has_tsc processors */
8fbbc4b4	32	static int tsc_disabled = -1;
0ef95533 AK	33
	34	/*
	35	* Scheduler clock - returns current time in nanosec units.
	36	*/
	37	u64 native_sched_clock(void)
	38	{
	39	u64 this_offset;
	40
	41	/*
	42	* Fall back to jiffies if there's no TSC available:
	43	* ( But note that we still use it if the TSC is marked
	44	* unstable. We do this because unlike Time Of Day,
	45	* the scheduler clock tolerates small errors and it's
	46	* very important for it to be as fast as the platform
	47	* can achive it. )
	48	*/
	49	if (unlikely(tsc_disabled)) {
	50	/* No locking but a rare wrong value is not a big deal: */
	51	return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
	52	}
	53
	54	/* read the Time Stamp Counter: */
	55	rdtscll(this_offset);
	56
	57	/* return the value in ns */
	58	return cycles_2_ns(this_offset);
	59	}
	60
	61	/* We need to define a real function for sched_clock, to override the
	62	weak default version */
	63	#ifdef CONFIG_PARAVIRT
	64	unsigned long long sched_clock(void)
	65	{
	66	return paravirt_sched_clock();
	67	}
	68	#else
	69	unsigned long long
	70	sched_clock(void) __attribute__((alias("native_sched_clock")));
	71	#endif
	72
	73	int check_tsc_unstable(void)
	74	{
	75	return tsc_unstable;
	76	}
	77	EXPORT_SYMBOL_GPL(check_tsc_unstable);
	78
	79	#ifdef CONFIG_X86_TSC
	80	int __init notsc_setup(char *str)
	81	{
	82	printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
	83	"cannot disable TSC completely.\n");
	84	tsc_disabled = 1;
	85	return 1;
	86	}
	87	#else
	88	/*
	89	* disable flag for tsc. Takes effect by clearing the TSC cpu flag
	90	* in cpu/common.c
	91	*/
	92	int __init notsc_setup(char *str)
	93	{
	94	setup_clear_cpu_cap(X86_FEATURE_TSC);
	95	return 1;
	96	}
97	#endif
98
99	__setup("notsc", notsc_setup);
bfc0f594 AK	100
	101	#define MAX_RETRIES 5
	102	#define SMI_TRESHOLD 50000
	103
	104	/*
	105	* Read TSC and the reference counters. Take care of SMI disturbance
	106	*/
d554d9a4	107	static u64 tsc_read_refs(u64 pm, u64 hpet)
bfc0f594 AK	108	{
	109	u64 t1, t2;
	110	int i;
	111
	112	for (i = 0; i < MAX_RETRIES; i++) {
	113	t1 = get_cycles();
	114	if (hpet)
	115	*hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
	116	else
	117	*pm = acpi_pm_read_early();
	118	t2 = get_cycles();
	119	if ((t2 - t1) < SMI_TRESHOLD)
	120	return t2;
	121	}
	122	return ULLONG_MAX;
	123	}
	124
	125	/**
e93ef949	126	* native_calibrate_tsc - calibrate the tsc on boot
bfc0f594	127	*/
e93ef949	128	unsigned long native_calibrate_tsc(void)
bfc0f594 AK	129	{
	130	unsigned long flags;
	131	u64 tsc1, tsc2, tr1, tr2, delta, pm1, pm2, hpet1, hpet2;
	132	int hpet = is_hpet_enabled();
	133	unsigned int tsc_khz_val = 0;
	134
	135	local_irq_save(flags);
	136
	137	tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
	138
	139	outb((inb(0x61) & ~0x02) \| 0x01, 0x61);
	140
	141	outb(0xb0, 0x43);
	142	outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
	143	outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
	144	tr1 = get_cycles();
	145	while ((inb(0x61) & 0x20) == 0);
	146	tr2 = get_cycles();
	147
	148	tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
	149
	150	local_irq_restore(flags);
	151
	152	/*
	153	* Preset the result with the raw and inaccurate PIT
	154	* calibration value
	155	*/
	156	delta = (tr2 - tr1);
	157	do_div(delta, 50);
	158	tsc_khz_val = delta;
	159
	160	/* hpet or pmtimer available ? */
	161	if (!hpet && !pm1 && !pm2) {
	162	printk(KERN_INFO "TSC calibrated against PIT\n");
	163	goto out;
	164	}
	165
	166	/* Check, whether the sampling was disturbed by an SMI */
	167	if (tsc1 == ULLONG_MAX \|\| tsc2 == ULLONG_MAX) {
	168	printk(KERN_WARNING "TSC calibration disturbed by SMI, "
	169	"using PIT calibration result\n");
	170	goto out;
	171	}
	172
	173	tsc2 = (tsc2 - tsc1) * 1000000LL;
	174
	175	if (hpet) {
	176	printk(KERN_INFO "TSC calibrated against HPET\n");
	177	if (hpet2 < hpet1)
	178	hpet2 += 0x100000000ULL;
	179	hpet2 -= hpet1;
	180	tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
	181	do_div(tsc1, 1000000);
	182	} else {
	183	printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
	184	if (pm2 < pm1)
	185	pm2 += (u64)ACPI_PM_OVRRUN;
	186	pm2 -= pm1;
	187	tsc1 = pm2 * 1000000000LL;
	188	do_div(tsc1, PMTMR_TICKS_PER_SEC);
	189	}
	190
	191	do_div(tsc2, tsc1);
	192	tsc_khz_val = tsc2;
193
194	out:
195	return tsc_khz_val;
196	}
197
bfc0f594 AK	198
	199	#ifdef CONFIG_X86_32
	200	/* Only called from the Powernow K7 cpu freq driver */
	201	int recalibrate_cpu_khz(void)
	202	{
	203	#ifndef CONFIG_SMP
	204	unsigned long cpu_khz_old = cpu_khz;
	205
	206	if (cpu_has_tsc) {
e93ef949 AK	207	tsc_khz = calibrate_tsc();
e93ef949 AK	208	cpu_khz = tsc_khz;
bfc0f594 AK	209	cpu_data(0).loops_per_jiffy =
	210	cpufreq_scale(cpu_data(0).loops_per_jiffy,
	211	cpu_khz_old, cpu_khz);
	212	return 0;
	213	} else
	214	return -ENODEV;
	215	#else
	216	return -ENODEV;
	217	#endif
	218	}
	219
	220	EXPORT_SYMBOL(recalibrate_cpu_khz);
	221
	222	#endif /* CONFIG_X86_32 */
2dbe06fa AK	223
	224	/* Accelerators for sched_clock()
	225	* convert from cycles(64bits) => nanoseconds (64bits)
	226	* basic equation:
	227	* ns = cycles / (freq / ns_per_sec)
	228	* ns = cycles * (ns_per_sec / freq)
	229	* ns = cycles * (10^9 / (cpu_khz * 10^3))
	230	* ns = cycles * (10^6 / cpu_khz)
	231	*
	232	* Then we use scaling math (suggested by george@mvista.com) to get:
	233	* ns = cycles * (10^6 * SC / cpu_khz) / SC
	234	* ns = cycles * cyc2ns_scale / SC
	235	*
	236	* And since SC is a constant power of two, we can convert the div
	237	* into a shift.
	238	*
	239	* We can use khz divisor instead of mhz to keep a better precision, since
	240	* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
	241	* (mathieu.desnoyers@polymtl.ca)
	242	*
	243	* -johnstul@us.ibm.com "math is hard, lets go shopping!"
	244	*/
	245
	246	DEFINE_PER_CPU(unsigned long, cyc2ns);
	247
8fbbc4b4	248	static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
2dbe06fa AK	249	{
	250	unsigned long long tsc_now, ns_now;
	251	unsigned long flags, *scale;
	252
	253	local_irq_save(flags);
	254	sched_clock_idle_sleep_event();
	255
	256	scale = &per_cpu(cyc2ns, cpu);
	257
	258	rdtscll(tsc_now);
	259	ns_now = __cycles_2_ns(tsc_now);
	260
	261	if (cpu_khz)
	262	*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
	263
	264	sched_clock_idle_wakeup_event(0);
	265	local_irq_restore(flags);
	266	}
	267
	268	#ifdef CONFIG_CPU_FREQ
	269
	270	/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
	271	* changes.
	272	*
	273	* RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
	274	* not that important because current Opteron setups do not support
	275	* scaling on SMP anyroads.
	276	*
	277	* Should fix up last_tsc too. Currently gettimeofday in the
	278	* first tick after the change will be slightly wrong.
	279	*/
	280
	281	static unsigned int ref_freq;
	282	static unsigned long loops_per_jiffy_ref;
	283	static unsigned long tsc_khz_ref;
	284
	285	static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
	286	void *data)
	287	{
	288	struct cpufreq_freqs *freq = data;
	289	unsigned long *lpj, dummy;
	290
	291	if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
	292	return 0;
	293
	294	lpj = &dummy;
	295	if (!(freq->flags & CPUFREQ_CONST_LOOPS))
	296	#ifdef CONFIG_SMP
	297	lpj = &cpu_data(freq->cpu).loops_per_jiffy;
	298	#else
	299	lpj = &boot_cpu_data.loops_per_jiffy;
	300	#endif
	301
	302	if (!ref_freq) {
	303	ref_freq = freq->old;
	304	loops_per_jiffy_ref = *lpj;
	305	tsc_khz_ref = tsc_khz;
	306	}
	307	if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) \|\|
	308	(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) \|\|
	309	(val == CPUFREQ_RESUMECHANGE)) {
	310	*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
	311
	312	tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
313	if (!(freq->flags & CPUFREQ_CONST_LOOPS))
314	mark_tsc_unstable("cpufreq changes");
315	}
316
317	set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
318
319	return 0;
320	}
321
322	static struct notifier_block time_cpufreq_notifier_block = {
323	.notifier_call = time_cpufreq_notifier
324	};
325
326	static int __init cpufreq_tsc(void)
327	{
328	cpufreq_register_notifier(&time_cpufreq_notifier_block,
329	CPUFREQ_TRANSITION_NOTIFIER);
330	return 0;
331	}
332
333	core_initcall(cpufreq_tsc);
334
335	#endif /* CONFIG_CPU_FREQ */
8fbbc4b4 AK	336
	337	/* clocksource code */
	338
	339	static struct clocksource clocksource_tsc;
	340
	341	/*
	342	* We compare the TSC to the cycle_last value in the clocksource
	343	* structure to avoid a nasty time-warp. This can be observed in a
	344	* very small window right after one CPU updated cycle_last under
	345	* xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
	346	* is smaller than the cycle_last reference value due to a TSC which
	347	* is slighty behind. This delta is nowhere else observable, but in
	348	* that case it results in a forward time jump in the range of hours
	349	* due to the unsigned delta calculation of the time keeping core
	350	* code, which is necessary to support wrapping clocksources like pm
	351	* timer.
	352	*/
	353	static cycle_t read_tsc(void)
	354	{
	355	cycle_t ret = (cycle_t)get_cycles();
	356
	357	return ret >= clocksource_tsc.cycle_last ?
	358	ret : clocksource_tsc.cycle_last;
	359	}
	360
431ceb83	361	#ifdef CONFIG_X86_64
8fbbc4b4 AK	362	static cycle_t __vsyscall_fn vread_tsc(void)
	363	{
	364	cycle_t ret = (cycle_t)vget_cycles();
	365
	366	return ret >= __vsyscall_gtod_data.clock.cycle_last ?
	367	ret : __vsyscall_gtod_data.clock.cycle_last;
	368	}
431ceb83	369	#endif
8fbbc4b4 AK	370
	371	static struct clocksource clocksource_tsc = {
	372	.name = "tsc",
	373	.rating = 300,
	374	.read = read_tsc,
	375	.mask = CLOCKSOURCE_MASK(64),
	376	.shift = 22,
	377	.flags = CLOCK_SOURCE_IS_CONTINUOUS \|
	378	CLOCK_SOURCE_MUST_VERIFY,
	379	#ifdef CONFIG_X86_64
	380	.vread = vread_tsc,
	381	#endif
	382	};
	383
	384	void mark_tsc_unstable(char *reason)
	385	{
	386	if (!tsc_unstable) {
	387	tsc_unstable = 1;
	388	printk("Marking TSC unstable due to %s\n", reason);
	389	/* Change only the rating, when not registered */
	390	if (clocksource_tsc.mult)
	391	clocksource_change_rating(&clocksource_tsc, 0);
	392	else
	393	clocksource_tsc.rating = 0;
	394	}
	395	}
	396
	397	EXPORT_SYMBOL_GPL(mark_tsc_unstable);
	398
	399	static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
	400	{
	401	printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
	402	d->ident);
	403	tsc_unstable = 1;
	404	return 0;
	405	}
	406
	407	/* List of systems that have known TSC problems */
	408	static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
	409	{
	410	.callback = dmi_mark_tsc_unstable,
	411	.ident = "IBM Thinkpad 380XD",
	412	.matches = {
	413	DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
	414	DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
	415	},
	416	},
	417	{}
	418	};
	419
	420	/*
	421	* Geode_LX - the OLPC CPU has a possibly a very reliable TSC
	422	*/
	423	#ifdef CONFIG_MGEODE_LX
	424	/* RTSC counts during suspend */
	425	#define RTSC_SUSP 0x100
	426
	427	static void __init check_geode_tsc_reliable(void)
	428	{
	429	unsigned long res_low, res_high;
	430
	431	rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
	432	if (res_low & RTSC_SUSP)
	433	clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
434	}
435	#else
436	static inline void check_geode_tsc_reliable(void) { }
437	#endif
438
439	/*
440	* Make an educated guess if the TSC is trustworthy and synchronized
441	* over all CPUs.
442	*/
443	__cpuinit int unsynchronized_tsc(void)
444	{
445	if (!cpu_has_tsc \|\| tsc_unstable)
446	return 1;
447
448	#ifdef CONFIG_SMP
449	if (apic_is_clustered_box())
450	return 1;
451	#endif
452
453	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
454	return 0;
455	/*
456	* Intel systems are normally all synchronized.
457	* Exceptions must mark TSC as unstable:
458	*/
459	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
460	/* assume multi socket systems are not synchronized: */
461	if (num_possible_cpus() > 1)
462	tsc_unstable = 1;
463	}
464
465	return tsc_unstable;
466	}
467
468	static void __init init_tsc_clocksource(void)
469	{
470	clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
471	clocksource_tsc.shift);
472	/* lower the rating if we already know its unstable: */
473	if (check_tsc_unstable()) {
474	clocksource_tsc.rating = 0;
475	clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
476	}
477	clocksource_register(&clocksource_tsc);
478	}
479
480	void __init tsc_init(void)
481	{
482	u64 lpj;
483	int cpu;
484
485	if (!cpu_has_tsc)
486	return;
487
e93ef949 AK	488	tsc_khz = calibrate_tsc();
e93ef949 AK	489	cpu_khz = tsc_khz;
8fbbc4b4	490
e93ef949	491	if (!tsc_khz) {
8fbbc4b4 AK	492	mark_tsc_unstable("could not calculate TSC khz");
	493	return;
	494	}
	495
	496	#ifdef CONFIG_X86_64
	497	if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
	498	(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
	499	cpu_khz = calibrate_cpu();
	500	#endif
	501
	502	lpj = ((u64)tsc_khz * 1000);
	503	do_div(lpj, HZ);
	504	lpj_fine = lpj;
	505
	506	printk("Detected %lu.%03lu MHz processor.\n",
	507	(unsigned long)cpu_khz / 1000,
	508	(unsigned long)cpu_khz % 1000);
	509
	510	/*
	511	* Secondary CPUs do not run through tsc_init(), so set up
	512	* all the scale factors for all CPUs, assuming the same
	513	* speed as the bootup CPU. (cpufreq notifiers will fix this
	514	* up if their speed diverges)
	515	*/
	516	for_each_possible_cpu(cpu)
	517	set_cyc2ns_scale(cpu_khz, cpu);
	518
	519	if (tsc_disabled > 0)
	520	return;
	521
	522	/* now allow native_sched_clock() to use rdtsc */
	523	tsc_disabled = 0;
	524
	525	use_tsc_delay();
	526	/* Check and install the TSC clocksource */
	527	dmi_check_system(bad_tsc_dmi_table);
	528
	529	if (unsynchronized_tsc())
	530	mark_tsc_unstable("TSCs unsynchronized");
	531
	532	check_geode_tsc_reliable();
	533	init_tsc_clocksource();
	534	}
	535