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4cedb334
GOC
1/*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
68a1c3f8
GC
42#include <linux/init.h>
43#include <linux/smp.h>
a355352b 44#include <linux/module.h>
70708a18 45#include <linux/sched.h>
69c18c15 46#include <linux/percpu.h>
91718e8d 47#include <linux/bootmem.h>
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48#include <linux/err.h>
49#include <linux/nmi.h>
69c18c15 50
8aef135c 51#include <asm/acpi.h>
cb3c8b90 52#include <asm/desc.h>
69c18c15
GC
53#include <asm/nmi.h>
54#include <asm/irq.h>
55#include <asm/smp.h>
56#include <asm/cpu.h>
57#include <asm/numa.h>
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GOC
58#include <asm/pgtable.h>
59#include <asm/tlbflush.h>
60#include <asm/mtrr.h>
61#include <asm/nmi.h>
bbc2ff6a 62#include <asm/vmi.h>
cb3c8b90 63#include <linux/mc146818rtc.h>
68a1c3f8 64
f6bc4029 65#include <mach_apic.h>
cb3c8b90
GOC
66#include <mach_wakecpu.h>
67#include <smpboot_hooks.h>
68
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GOC
69/*
70 * FIXME: For x86_64, those are defined in other files. But moving them here,
71 * would make the setup areas dependent on smp, which is a loss. When we
72 * integrate apic between arches, we can probably do a better job, but
73 * right now, they'll stay here -- glommer
74 */
708650af 75
acbb6734
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76/* which logical CPU number maps to which CPU (physical APIC ID) */
77u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
78 { [0 ... NR_CPUS-1] = BAD_APICID };
79void *x86_cpu_to_apicid_early_ptr;
acbb6734
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80
81u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
82 = { [0 ... NR_CPUS-1] = BAD_APICID };
83void *x86_bios_cpu_apicid_early_ptr;
40014bac 84
16ecf7a4 85#ifdef CONFIG_X86_32
4cedb334 86u8 apicid_2_node[MAX_APICID];
acbb6734
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87#endif
88
a8db8453
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89/* State of each CPU */
90DEFINE_PER_CPU(int, cpu_state) = { 0 };
91
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92/* Store all idle threads, this can be reused instead of creating
93* a new thread. Also avoids complicated thread destroy functionality
94* for idle threads.
95*/
96#ifdef CONFIG_HOTPLUG_CPU
97/*
98 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
99 * removed after init for !CONFIG_HOTPLUG_CPU.
100 */
101static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
102#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
103#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
104#else
105struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
106#define get_idle_for_cpu(x) (idle_thread_array[(x)])
107#define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
108#endif
f6bc4029 109
a355352b
GC
110/* Number of siblings per CPU package */
111int smp_num_siblings = 1;
112EXPORT_SYMBOL(smp_num_siblings);
113
114/* Last level cache ID of each logical CPU */
115DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
116
117/* bitmap of online cpus */
118cpumask_t cpu_online_map __read_mostly;
119EXPORT_SYMBOL(cpu_online_map);
120
121cpumask_t cpu_callin_map;
122cpumask_t cpu_callout_map;
123cpumask_t cpu_possible_map;
124EXPORT_SYMBOL(cpu_possible_map);
125
126/* representing HT siblings of each logical CPU */
127DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
128EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
129
130/* representing HT and core siblings of each logical CPU */
131DEFINE_PER_CPU(cpumask_t, cpu_core_map);
132EXPORT_PER_CPU_SYMBOL(cpu_core_map);
133
134/* Per CPU bogomips and other parameters */
135DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
136EXPORT_PER_CPU_SYMBOL(cpu_info);
768d9505 137
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138static atomic_t init_deasserted;
139
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140static int boot_cpu_logical_apicid;
141
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GC
142/* ready for x86_64, no harm for x86, since it will overwrite after alloc */
143unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
144
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GC
145/* representing cpus for which sibling maps can be computed */
146static cpumask_t cpu_sibling_setup_map;
147
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148/* Set if we find a B stepping CPU */
149int __cpuinitdata smp_b_stepping;
1d89a7f0 150
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151#if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
152
153/* which logical CPUs are on which nodes */
154cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
155 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
156EXPORT_SYMBOL(node_to_cpumask_map);
157/* which node each logical CPU is on */
158int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
159EXPORT_SYMBOL(cpu_to_node_map);
160
161/* set up a mapping between cpu and node. */
162static void map_cpu_to_node(int cpu, int node)
163{
164 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
165 cpu_set(cpu, node_to_cpumask_map[node]);
166 cpu_to_node_map[cpu] = node;
167}
168
169/* undo a mapping between cpu and node. */
170static void unmap_cpu_to_node(int cpu)
171{
172 int node;
173
174 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
175 for (node = 0; node < MAX_NUMNODES; node++)
176 cpu_clear(cpu, node_to_cpumask_map[node]);
177 cpu_to_node_map[cpu] = 0;
178}
179#else /* !(CONFIG_NUMA && CONFIG_X86_32) */
180#define map_cpu_to_node(cpu, node) ({})
181#define unmap_cpu_to_node(cpu) ({})
182#endif
183
184#ifdef CONFIG_X86_32
185u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
186 { [0 ... NR_CPUS-1] = BAD_APICID };
187
188void map_cpu_to_logical_apicid(void)
189{
190 int cpu = smp_processor_id();
191 int apicid = logical_smp_processor_id();
192 int node = apicid_to_node(apicid);
193
194 if (!node_online(node))
195 node = first_online_node;
196
197 cpu_2_logical_apicid[cpu] = apicid;
198 map_cpu_to_node(cpu, node);
199}
200
201void unmap_cpu_to_logical_apicid(int cpu)
202{
203 cpu_2_logical_apicid[cpu] = BAD_APICID;
204 unmap_cpu_to_node(cpu);
205}
206#else
207#define unmap_cpu_to_logical_apicid(cpu) do {} while (0)
208#define map_cpu_to_logical_apicid() do {} while (0)
209#endif
210
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211/*
212 * Report back to the Boot Processor.
213 * Running on AP.
214 */
215void __cpuinit smp_callin(void)
216{
217 int cpuid, phys_id;
218 unsigned long timeout;
219
220 /*
221 * If waken up by an INIT in an 82489DX configuration
222 * we may get here before an INIT-deassert IPI reaches
223 * our local APIC. We have to wait for the IPI or we'll
224 * lock up on an APIC access.
225 */
226 wait_for_init_deassert(&init_deasserted);
227
228 /*
229 * (This works even if the APIC is not enabled.)
230 */
05f2d12c 231 phys_id = GET_APIC_ID(read_apic_id());
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GOC
232 cpuid = smp_processor_id();
233 if (cpu_isset(cpuid, cpu_callin_map)) {
234 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
235 phys_id, cpuid);
236 }
237 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
238
239 /*
240 * STARTUP IPIs are fragile beasts as they might sometimes
241 * trigger some glue motherboard logic. Complete APIC bus
242 * silence for 1 second, this overestimates the time the
243 * boot CPU is spending to send the up to 2 STARTUP IPIs
244 * by a factor of two. This should be enough.
245 */
246
247 /*
248 * Waiting 2s total for startup (udelay is not yet working)
249 */
250 timeout = jiffies + 2*HZ;
251 while (time_before(jiffies, timeout)) {
252 /*
253 * Has the boot CPU finished it's STARTUP sequence?
254 */
255 if (cpu_isset(cpuid, cpu_callout_map))
256 break;
257 cpu_relax();
258 }
259
260 if (!time_before(jiffies, timeout)) {
261 panic("%s: CPU%d started up but did not get a callout!\n",
262 __func__, cpuid);
263 }
264
265 /*
266 * the boot CPU has finished the init stage and is spinning
267 * on callin_map until we finish. We are free to set up this
268 * CPU, first the APIC. (this is probably redundant on most
269 * boards)
270 */
271
272 Dprintk("CALLIN, before setup_local_APIC().\n");
273 smp_callin_clear_local_apic();
274 setup_local_APIC();
275 end_local_APIC_setup();
276 map_cpu_to_logical_apicid();
277
278 /*
279 * Get our bogomips.
280 *
281 * Need to enable IRQs because it can take longer and then
282 * the NMI watchdog might kill us.
283 */
284 local_irq_enable();
285 calibrate_delay();
286 local_irq_disable();
287 Dprintk("Stack at about %p\n", &cpuid);
288
289 /*
290 * Save our processor parameters
291 */
292 smp_store_cpu_info(cpuid);
293
294 /*
295 * Allow the master to continue.
296 */
297 cpu_set(cpuid, cpu_callin_map);
298}
299
bbc2ff6a
GOC
300/*
301 * Activate a secondary processor.
302 */
303void __cpuinit start_secondary(void *unused)
304{
305 /*
306 * Don't put *anything* before cpu_init(), SMP booting is too
307 * fragile that we want to limit the things done here to the
308 * most necessary things.
309 */
310#ifdef CONFIG_VMI
311 vmi_bringup();
312#endif
313 cpu_init();
314 preempt_disable();
315 smp_callin();
316
317 /* otherwise gcc will move up smp_processor_id before the cpu_init */
318 barrier();
319 /*
320 * Check TSC synchronization with the BP:
321 */
322 check_tsc_sync_target();
323
324 if (nmi_watchdog == NMI_IO_APIC) {
325 disable_8259A_irq(0);
326 enable_NMI_through_LVT0();
327 enable_8259A_irq(0);
328 }
329
330 /* This must be done before setting cpu_online_map */
331 set_cpu_sibling_map(raw_smp_processor_id());
332 wmb();
333
334 /*
335 * We need to hold call_lock, so there is no inconsistency
336 * between the time smp_call_function() determines number of
337 * IPI recipients, and the time when the determination is made
338 * for which cpus receive the IPI. Holding this
339 * lock helps us to not include this cpu in a currently in progress
340 * smp_call_function().
341 */
342 lock_ipi_call_lock();
343#ifdef CONFIG_X86_64
344 spin_lock(&vector_lock);
345
346 /* Setup the per cpu irq handling data structures */
347 __setup_vector_irq(smp_processor_id());
348 /*
349 * Allow the master to continue.
350 */
351 spin_unlock(&vector_lock);
352#endif
353 cpu_set(smp_processor_id(), cpu_online_map);
354 unlock_ipi_call_lock();
355 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
356
357 setup_secondary_clock();
358
359 wmb();
360 cpu_idle();
361}
362
363#ifdef CONFIG_X86_32
364/*
365 * Everything has been set up for the secondary
366 * CPUs - they just need to reload everything
367 * from the task structure
368 * This function must not return.
369 */
370void __devinit initialize_secondary(void)
371{
372 /*
373 * We don't actually need to load the full TSS,
374 * basically just the stack pointer and the ip.
375 */
376
377 asm volatile(
378 "movl %0,%%esp\n\t"
379 "jmp *%1"
380 :
381 :"m" (current->thread.sp), "m" (current->thread.ip));
382}
383#endif
cb3c8b90 384
1d89a7f0
GOC
385static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
386{
387#ifdef CONFIG_X86_32
388 /*
389 * Mask B, Pentium, but not Pentium MMX
390 */
391 if (c->x86_vendor == X86_VENDOR_INTEL &&
392 c->x86 == 5 &&
393 c->x86_mask >= 1 && c->x86_mask <= 4 &&
394 c->x86_model <= 3)
395 /*
396 * Remember we have B step Pentia with bugs
397 */
398 smp_b_stepping = 1;
399
400 /*
401 * Certain Athlons might work (for various values of 'work') in SMP
402 * but they are not certified as MP capable.
403 */
404 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
405
406 if (num_possible_cpus() == 1)
407 goto valid_k7;
408
409 /* Athlon 660/661 is valid. */
410 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
411 (c->x86_mask == 1)))
412 goto valid_k7;
413
414 /* Duron 670 is valid */
415 if ((c->x86_model == 7) && (c->x86_mask == 0))
416 goto valid_k7;
417
418 /*
419 * Athlon 662, Duron 671, and Athlon >model 7 have capability
420 * bit. It's worth noting that the A5 stepping (662) of some
421 * Athlon XP's have the MP bit set.
422 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
423 * more.
424 */
425 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
426 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
427 (c->x86_model > 7))
428 if (cpu_has_mp)
429 goto valid_k7;
430
431 /* If we get here, not a certified SMP capable AMD system. */
432 add_taint(TAINT_UNSAFE_SMP);
433 }
434
435valid_k7:
436 ;
437#endif
438}
439
df96323d 440void __cpuinit smp_checks(void)
693d4b8a
GOC
441{
442 if (smp_b_stepping)
443 printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
444 "with B stepping processors.\n");
445
446 /*
447 * Don't taint if we are running SMP kernel on a single non-MP
448 * approved Athlon
449 */
450 if (tainted & TAINT_UNSAFE_SMP) {
f68e00a3 451 if (num_online_cpus())
693d4b8a
GOC
452 printk(KERN_INFO "WARNING: This combination of AMD"
453 "processors is not suitable for SMP.\n");
454 else
455 tainted &= ~TAINT_UNSAFE_SMP;
456 }
457}
458
1d89a7f0
GOC
459/*
460 * The bootstrap kernel entry code has set these up. Save them for
461 * a given CPU
462 */
463
464void __cpuinit smp_store_cpu_info(int id)
465{
466 struct cpuinfo_x86 *c = &cpu_data(id);
467
468 *c = boot_cpu_data;
469 c->cpu_index = id;
470 if (id != 0)
471 identify_secondary_cpu(c);
472 smp_apply_quirks(c);
473}
474
475
768d9505
GC
476void __cpuinit set_cpu_sibling_map(int cpu)
477{
478 int i;
479 struct cpuinfo_x86 *c = &cpu_data(cpu);
480
481 cpu_set(cpu, cpu_sibling_setup_map);
482
483 if (smp_num_siblings > 1) {
484 for_each_cpu_mask(i, cpu_sibling_setup_map) {
485 if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
486 c->cpu_core_id == cpu_data(i).cpu_core_id) {
487 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
488 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
489 cpu_set(i, per_cpu(cpu_core_map, cpu));
490 cpu_set(cpu, per_cpu(cpu_core_map, i));
491 cpu_set(i, c->llc_shared_map);
492 cpu_set(cpu, cpu_data(i).llc_shared_map);
493 }
494 }
495 } else {
496 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
497 }
498
499 cpu_set(cpu, c->llc_shared_map);
500
501 if (current_cpu_data.x86_max_cores == 1) {
502 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
503 c->booted_cores = 1;
504 return;
505 }
506
507 for_each_cpu_mask(i, cpu_sibling_setup_map) {
508 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
509 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
510 cpu_set(i, c->llc_shared_map);
511 cpu_set(cpu, cpu_data(i).llc_shared_map);
512 }
513 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
514 cpu_set(i, per_cpu(cpu_core_map, cpu));
515 cpu_set(cpu, per_cpu(cpu_core_map, i));
516 /*
517 * Does this new cpu bringup a new core?
518 */
519 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
520 /*
521 * for each core in package, increment
522 * the booted_cores for this new cpu
523 */
524 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
525 c->booted_cores++;
526 /*
527 * increment the core count for all
528 * the other cpus in this package
529 */
530 if (i != cpu)
531 cpu_data(i).booted_cores++;
532 } else if (i != cpu && !c->booted_cores)
533 c->booted_cores = cpu_data(i).booted_cores;
534 }
535 }
536}
537
70708a18
GC
538/* maps the cpu to the sched domain representing multi-core */
539cpumask_t cpu_coregroup_map(int cpu)
540{
541 struct cpuinfo_x86 *c = &cpu_data(cpu);
542 /*
543 * For perf, we return last level cache shared map.
544 * And for power savings, we return cpu_core_map
545 */
546 if (sched_mc_power_savings || sched_smt_power_savings)
547 return per_cpu(cpu_core_map, cpu);
548 else
549 return c->llc_shared_map;
550}
551
91718e8d
GC
552/*
553 * Currently trivial. Write the real->protected mode
554 * bootstrap into the page concerned. The caller
555 * has made sure it's suitably aligned.
556 */
557
558unsigned long __cpuinit setup_trampoline(void)
559{
560 memcpy(trampoline_base, trampoline_data,
561 trampoline_end - trampoline_data);
562 return virt_to_phys(trampoline_base);
563}
564
565#ifdef CONFIG_X86_32
566/*
567 * We are called very early to get the low memory for the
568 * SMP bootup trampoline page.
569 */
570void __init smp_alloc_memory(void)
571{
572 trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
573 /*
574 * Has to be in very low memory so we can execute
575 * real-mode AP code.
576 */
577 if (__pa(trampoline_base) >= 0x9F000)
578 BUG();
579}
580#endif
70708a18 581
904541e2
GOC
582void impress_friends(void)
583{
584 int cpu;
585 unsigned long bogosum = 0;
586 /*
587 * Allow the user to impress friends.
588 */
589 Dprintk("Before bogomips.\n");
590 for_each_possible_cpu(cpu)
591 if (cpu_isset(cpu, cpu_callout_map))
592 bogosum += cpu_data(cpu).loops_per_jiffy;
593 printk(KERN_INFO
594 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
f68e00a3 595 num_online_cpus(),
904541e2
GOC
596 bogosum/(500000/HZ),
597 (bogosum/(5000/HZ))%100);
598
599 Dprintk("Before bogocount - setting activated=1.\n");
600}
601
cb3c8b90
GOC
602static inline void __inquire_remote_apic(int apicid)
603{
604 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
605 char *names[] = { "ID", "VERSION", "SPIV" };
606 int timeout;
607 u32 status;
608
609 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
610
611 for (i = 0; i < ARRAY_SIZE(regs); i++) {
612 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
613
614 /*
615 * Wait for idle.
616 */
617 status = safe_apic_wait_icr_idle();
618 if (status)
619 printk(KERN_CONT
620 "a previous APIC delivery may have failed\n");
621
622 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
623 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
624
625 timeout = 0;
626 do {
627 udelay(100);
628 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
629 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
630
631 switch (status) {
632 case APIC_ICR_RR_VALID:
633 status = apic_read(APIC_RRR);
634 printk(KERN_CONT "%08x\n", status);
635 break;
636 default:
637 printk(KERN_CONT "failed\n");
638 }
639 }
640}
641
642#ifdef WAKE_SECONDARY_VIA_NMI
643/*
644 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
645 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
646 * won't ... remember to clear down the APIC, etc later.
647 */
648static int __devinit
649wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
650{
651 unsigned long send_status, accept_status = 0;
652 int maxlvt;
653
654 /* Target chip */
655 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
656
657 /* Boot on the stack */
658 /* Kick the second */
659 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
660
661 Dprintk("Waiting for send to finish...\n");
662 send_status = safe_apic_wait_icr_idle();
663
664 /*
665 * Give the other CPU some time to accept the IPI.
666 */
667 udelay(200);
668 /*
669 * Due to the Pentium erratum 3AP.
670 */
671 maxlvt = lapic_get_maxlvt();
672 if (maxlvt > 3) {
673 apic_read_around(APIC_SPIV);
674 apic_write(APIC_ESR, 0);
675 }
676 accept_status = (apic_read(APIC_ESR) & 0xEF);
677 Dprintk("NMI sent.\n");
678
679 if (send_status)
680 printk(KERN_ERR "APIC never delivered???\n");
681 if (accept_status)
682 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
683
684 return (send_status | accept_status);
685}
686#endif /* WAKE_SECONDARY_VIA_NMI */
687
cb3c8b90
GOC
688#ifdef WAKE_SECONDARY_VIA_INIT
689static int __devinit
690wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
691{
692 unsigned long send_status, accept_status = 0;
693 int maxlvt, num_starts, j;
694
695 /*
696 * Be paranoid about clearing APIC errors.
697 */
698 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
699 apic_read_around(APIC_SPIV);
700 apic_write(APIC_ESR, 0);
701 apic_read(APIC_ESR);
702 }
703
704 Dprintk("Asserting INIT.\n");
705
706 /*
707 * Turn INIT on target chip
708 */
709 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
710
711 /*
712 * Send IPI
713 */
714 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
715 | APIC_DM_INIT);
716
717 Dprintk("Waiting for send to finish...\n");
718 send_status = safe_apic_wait_icr_idle();
719
720 mdelay(10);
721
722 Dprintk("Deasserting INIT.\n");
723
724 /* Target chip */
725 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
726
727 /* Send IPI */
728 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
729
730 Dprintk("Waiting for send to finish...\n");
731 send_status = safe_apic_wait_icr_idle();
732
733 mb();
734 atomic_set(&init_deasserted, 1);
735
736 /*
737 * Should we send STARTUP IPIs ?
738 *
739 * Determine this based on the APIC version.
740 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
741 */
742 if (APIC_INTEGRATED(apic_version[phys_apicid]))
743 num_starts = 2;
744 else
745 num_starts = 0;
746
747 /*
748 * Paravirt / VMI wants a startup IPI hook here to set up the
749 * target processor state.
750 */
751 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
752#ifdef CONFIG_X86_64
753 (unsigned long)init_rsp);
754#else
755 (unsigned long)stack_start.sp);
756#endif
757
758 /*
759 * Run STARTUP IPI loop.
760 */
761 Dprintk("#startup loops: %d.\n", num_starts);
762
763 maxlvt = lapic_get_maxlvt();
764
765 for (j = 1; j <= num_starts; j++) {
766 Dprintk("Sending STARTUP #%d.\n", j);
767 apic_read_around(APIC_SPIV);
768 apic_write(APIC_ESR, 0);
769 apic_read(APIC_ESR);
770 Dprintk("After apic_write.\n");
771
772 /*
773 * STARTUP IPI
774 */
775
776 /* Target chip */
777 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
778
779 /* Boot on the stack */
780 /* Kick the second */
781 apic_write_around(APIC_ICR, APIC_DM_STARTUP
782 | (start_eip >> 12));
783
784 /*
785 * Give the other CPU some time to accept the IPI.
786 */
787 udelay(300);
788
789 Dprintk("Startup point 1.\n");
790
791 Dprintk("Waiting for send to finish...\n");
792 send_status = safe_apic_wait_icr_idle();
793
794 /*
795 * Give the other CPU some time to accept the IPI.
796 */
797 udelay(200);
798 /*
799 * Due to the Pentium erratum 3AP.
800 */
801 if (maxlvt > 3) {
802 apic_read_around(APIC_SPIV);
803 apic_write(APIC_ESR, 0);
804 }
805 accept_status = (apic_read(APIC_ESR) & 0xEF);
806 if (send_status || accept_status)
807 break;
808 }
809 Dprintk("After Startup.\n");
810
811 if (send_status)
812 printk(KERN_ERR "APIC never delivered???\n");
813 if (accept_status)
814 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
815
816 return (send_status | accept_status);
817}
818#endif /* WAKE_SECONDARY_VIA_INIT */
819
820struct create_idle {
821 struct work_struct work;
822 struct task_struct *idle;
823 struct completion done;
824 int cpu;
825};
826
827static void __cpuinit do_fork_idle(struct work_struct *work)
828{
829 struct create_idle *c_idle =
830 container_of(work, struct create_idle, work);
831
832 c_idle->idle = fork_idle(c_idle->cpu);
833 complete(&c_idle->done);
834}
835
836static int __cpuinit do_boot_cpu(int apicid, int cpu)
837/*
838 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
839 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
840 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
841 */
842{
843 unsigned long boot_error = 0;
844 int timeout;
845 unsigned long start_ip;
846 unsigned short nmi_high = 0, nmi_low = 0;
847 struct create_idle c_idle = {
848 .cpu = cpu,
849 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
850 };
851 INIT_WORK(&c_idle.work, do_fork_idle);
852#ifdef CONFIG_X86_64
853 /* allocate memory for gdts of secondary cpus. Hotplug is considered */
854 if (!cpu_gdt_descr[cpu].address &&
855 !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
856 printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
857 return -1;
858 }
859
860 /* Allocate node local memory for AP pdas */
861 if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
862 struct x8664_pda *newpda, *pda;
863 int node = cpu_to_node(cpu);
864 pda = cpu_pda(cpu);
865 newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC,
866 node);
867 if (newpda) {
868 memcpy(newpda, pda, sizeof(struct x8664_pda));
869 cpu_pda(cpu) = newpda;
870 } else
871 printk(KERN_ERR
872 "Could not allocate node local PDA for CPU %d on node %d\n",
873 cpu, node);
874 }
875#endif
876
877 alternatives_smp_switch(1);
878
879 c_idle.idle = get_idle_for_cpu(cpu);
880
881 /*
882 * We can't use kernel_thread since we must avoid to
883 * reschedule the child.
884 */
885 if (c_idle.idle) {
886 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
887 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
888 init_idle(c_idle.idle, cpu);
889 goto do_rest;
890 }
891
892 if (!keventd_up() || current_is_keventd())
893 c_idle.work.func(&c_idle.work);
894 else {
895 schedule_work(&c_idle.work);
896 wait_for_completion(&c_idle.done);
897 }
898
899 if (IS_ERR(c_idle.idle)) {
900 printk("failed fork for CPU %d\n", cpu);
901 return PTR_ERR(c_idle.idle);
902 }
903
904 set_idle_for_cpu(cpu, c_idle.idle);
905do_rest:
906#ifdef CONFIG_X86_32
907 per_cpu(current_task, cpu) = c_idle.idle;
908 init_gdt(cpu);
909 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
910 c_idle.idle->thread.ip = (unsigned long) start_secondary;
911 /* Stack for startup_32 can be just as for start_secondary onwards */
912 stack_start.sp = (void *) c_idle.idle->thread.sp;
913 irq_ctx_init(cpu);
914#else
915 cpu_pda(cpu)->pcurrent = c_idle.idle;
916 init_rsp = c_idle.idle->thread.sp;
917 load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
918 initial_code = (unsigned long)start_secondary;
919 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
920#endif
921
922 /* start_ip had better be page-aligned! */
923 start_ip = setup_trampoline();
924
925 /* So we see what's up */
926 printk(KERN_INFO "Booting processor %d/%d ip %lx\n",
927 cpu, apicid, start_ip);
928
929 /*
930 * This grunge runs the startup process for
931 * the targeted processor.
932 */
933
934 atomic_set(&init_deasserted, 0);
935
936 Dprintk("Setting warm reset code and vector.\n");
937
938 store_NMI_vector(&nmi_high, &nmi_low);
939
940 smpboot_setup_warm_reset_vector(start_ip);
941 /*
942 * Be paranoid about clearing APIC errors.
943 */
944 apic_write(APIC_ESR, 0);
945 apic_read(APIC_ESR);
946
cb3c8b90
GOC
947 /*
948 * Starting actual IPI sequence...
949 */
950 boot_error = wakeup_secondary_cpu(apicid, start_ip);
951
952 if (!boot_error) {
953 /*
954 * allow APs to start initializing.
955 */
956 Dprintk("Before Callout %d.\n", cpu);
957 cpu_set(cpu, cpu_callout_map);
958 Dprintk("After Callout %d.\n", cpu);
959
960 /*
961 * Wait 5s total for a response
962 */
963 for (timeout = 0; timeout < 50000; timeout++) {
964 if (cpu_isset(cpu, cpu_callin_map))
965 break; /* It has booted */
966 udelay(100);
967 }
968
969 if (cpu_isset(cpu, cpu_callin_map)) {
970 /* number CPUs logically, starting from 1 (BSP is 0) */
971 Dprintk("OK.\n");
972 printk(KERN_INFO "CPU%d: ", cpu);
973 print_cpu_info(&cpu_data(cpu));
974 Dprintk("CPU has booted.\n");
975 } else {
976 boot_error = 1;
977 if (*((volatile unsigned char *)trampoline_base)
978 == 0xA5)
979 /* trampoline started but...? */
980 printk(KERN_ERR "Stuck ??\n");
981 else
982 /* trampoline code not run */
983 printk(KERN_ERR "Not responding.\n");
984 inquire_remote_apic(apicid);
985 }
986 }
987
988 if (boot_error) {
989 /* Try to put things back the way they were before ... */
990 unmap_cpu_to_logical_apicid(cpu);
991#ifdef CONFIG_X86_64
992 clear_node_cpumask(cpu); /* was set by numa_add_cpu */
993#endif
994 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */
995 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
996 cpu_clear(cpu, cpu_possible_map);
997 cpu_clear(cpu, cpu_present_map);
998 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
999 }
1000
1001 /* mark "stuck" area as not stuck */
1002 *((volatile unsigned long *)trampoline_base) = 0;
1003
63d38198
AK
1004 /*
1005 * Cleanup possible dangling ends...
1006 */
1007 smpboot_restore_warm_reset_vector();
1008
cb3c8b90
GOC
1009 return boot_error;
1010}
1011
1012int __cpuinit native_cpu_up(unsigned int cpu)
1013{
1014 int apicid = cpu_present_to_apicid(cpu);
1015 unsigned long flags;
1016 int err;
1017
1018 WARN_ON(irqs_disabled());
1019
1020 Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1021
1022 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
1023 !physid_isset(apicid, phys_cpu_present_map)) {
1024 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
1025 return -EINVAL;
1026 }
1027
1028 /*
1029 * Already booted CPU?
1030 */
1031 if (cpu_isset(cpu, cpu_callin_map)) {
1032 Dprintk("do_boot_cpu %d Already started\n", cpu);
1033 return -ENOSYS;
1034 }
1035
1036 /*
1037 * Save current MTRR state in case it was changed since early boot
1038 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1039 */
1040 mtrr_save_state();
1041
1042 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1043
1044#ifdef CONFIG_X86_32
1045 /* init low mem mapping */
1046 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1047 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
1048 flush_tlb_all();
1049#endif
1050
1051 err = do_boot_cpu(apicid, cpu);
1052 if (err < 0) {
1053 Dprintk("do_boot_cpu failed %d\n", err);
1054 return err;
1055 }
1056
1057 /*
1058 * Check TSC synchronization with the AP (keep irqs disabled
1059 * while doing so):
1060 */
1061 local_irq_save(flags);
1062 check_tsc_sync_source(cpu);
1063 local_irq_restore(flags);
1064
1065 while (!cpu_isset(cpu, cpu_online_map)) {
1066 cpu_relax();
1067 touch_nmi_watchdog();
1068 }
1069
1070 return 0;
1071}
1072
8aef135c
GOC
1073/*
1074 * Fall back to non SMP mode after errors.
1075 *
1076 * RED-PEN audit/test this more. I bet there is more state messed up here.
1077 */
1078static __init void disable_smp(void)
1079{
1080 cpu_present_map = cpumask_of_cpu(0);
1081 cpu_possible_map = cpumask_of_cpu(0);
1082#ifdef CONFIG_X86_32
1083 smpboot_clear_io_apic_irqs();
1084#endif
1085 if (smp_found_config)
1086 phys_cpu_present_map =
1087 physid_mask_of_physid(boot_cpu_physical_apicid);
1088 else
1089 phys_cpu_present_map = physid_mask_of_physid(0);
1090 map_cpu_to_logical_apicid();
1091 cpu_set(0, per_cpu(cpu_sibling_map, 0));
1092 cpu_set(0, per_cpu(cpu_core_map, 0));
1093}
1094
1095/*
1096 * Various sanity checks.
1097 */
1098static int __init smp_sanity_check(unsigned max_cpus)
1099{
ac23d4ee 1100 preempt_disable();
8aef135c
GOC
1101 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1102 printk(KERN_WARNING "weird, boot CPU (#%d) not listed"
1103 "by the BIOS.\n", hard_smp_processor_id());
1104 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1105 }
1106
1107 /*
1108 * If we couldn't find an SMP configuration at boot time,
1109 * get out of here now!
1110 */
1111 if (!smp_found_config && !acpi_lapic) {
ac23d4ee 1112 preempt_enable();
8aef135c
GOC
1113 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1114 disable_smp();
1115 if (APIC_init_uniprocessor())
1116 printk(KERN_NOTICE "Local APIC not detected."
1117 " Using dummy APIC emulation.\n");
1118 return -1;
1119 }
1120
1121 /*
1122 * Should not be necessary because the MP table should list the boot
1123 * CPU too, but we do it for the sake of robustness anyway.
1124 */
1125 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1126 printk(KERN_NOTICE
1127 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1128 boot_cpu_physical_apicid);
1129 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1130 }
ac23d4ee 1131 preempt_enable();
8aef135c
GOC
1132
1133 /*
1134 * If we couldn't find a local APIC, then get out of here now!
1135 */
1136 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1137 !cpu_has_apic) {
1138 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1139 boot_cpu_physical_apicid);
1140 printk(KERN_ERR "... forcing use of dummy APIC emulation."
1141 "(tell your hw vendor)\n");
1142 smpboot_clear_io_apic();
1143 return -1;
1144 }
1145
1146 verify_local_APIC();
1147
1148 /*
1149 * If SMP should be disabled, then really disable it!
1150 */
1151 if (!max_cpus) {
1152 printk(KERN_INFO "SMP mode deactivated,"
1153 "forcing use of dummy APIC emulation.\n");
1154 smpboot_clear_io_apic();
1155#ifdef CONFIG_X86_32
1156 if (nmi_watchdog == NMI_LOCAL_APIC) {
1157 printk(KERN_INFO "activating minimal APIC for"
1158 "NMI watchdog use.\n");
1159 connect_bsp_APIC();
1160 setup_local_APIC();
1161 end_local_APIC_setup();
1162 }
1163#endif
1164 return -1;
1165 }
1166
1167 return 0;
1168}
1169
1170static void __init smp_cpu_index_default(void)
1171{
1172 int i;
1173 struct cpuinfo_x86 *c;
1174
1175 for_each_cpu_mask(i, cpu_possible_map) {
1176 c = &cpu_data(i);
1177 /* mark all to hotplug */
1178 c->cpu_index = NR_CPUS;
1179 }
1180}
1181
1182/*
1183 * Prepare for SMP bootup. The MP table or ACPI has been read
1184 * earlier. Just do some sanity checking here and enable APIC mode.
1185 */
1186void __init native_smp_prepare_cpus(unsigned int max_cpus)
1187{
1188 nmi_watchdog_default();
1189 smp_cpu_index_default();
1190 current_cpu_data = boot_cpu_data;
1191 cpu_callin_map = cpumask_of_cpu(0);
1192 mb();
1193 /*
1194 * Setup boot CPU information
1195 */
1196 smp_store_cpu_info(0); /* Final full version of the data */
1197 boot_cpu_logical_apicid = logical_smp_processor_id();
1198 current_thread_info()->cpu = 0; /* needed? */
1199 set_cpu_sibling_map(0);
1200
1201 if (smp_sanity_check(max_cpus) < 0) {
1202 printk(KERN_INFO "SMP disabled\n");
1203 disable_smp();
1204 return;
1205 }
1206
ac23d4ee 1207 preempt_disable();
05f2d12c 1208 if (GET_APIC_ID(read_apic_id()) != boot_cpu_physical_apicid) {
8aef135c 1209 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
05f2d12c 1210 GET_APIC_ID(read_apic_id()), boot_cpu_physical_apicid);
8aef135c
GOC
1211 /* Or can we switch back to PIC here? */
1212 }
ac23d4ee 1213 preempt_enable();
8aef135c
GOC
1214
1215#ifdef CONFIG_X86_32
1216 connect_bsp_APIC();
1217#endif
1218 /*
1219 * Switch from PIC to APIC mode.
1220 */
1221 setup_local_APIC();
1222
1223#ifdef CONFIG_X86_64
1224 /*
1225 * Enable IO APIC before setting up error vector
1226 */
1227 if (!skip_ioapic_setup && nr_ioapics)
1228 enable_IO_APIC();
1229#endif
1230 end_local_APIC_setup();
1231
1232 map_cpu_to_logical_apicid();
1233
1234 setup_portio_remap();
1235
1236 smpboot_setup_io_apic();
1237 /*
1238 * Set up local APIC timer on boot CPU.
1239 */
1240
1241 printk(KERN_INFO "CPU%d: ", 0);
1242 print_cpu_info(&cpu_data(0));
1243 setup_boot_clock();
1244}
a8db8453
GOC
1245/*
1246 * Early setup to make printk work.
1247 */
1248void __init native_smp_prepare_boot_cpu(void)
1249{
1250 int me = smp_processor_id();
1251#ifdef CONFIG_X86_32
1252 init_gdt(me);
1253 switch_to_new_gdt();
1254#endif
1255 /* already set me in cpu_online_map in boot_cpu_init() */
1256 cpu_set(me, cpu_callout_map);
1257 per_cpu(cpu_state, me) = CPU_ONLINE;
1258}
1259
83f7eb9c
GOC
1260void __init native_smp_cpus_done(unsigned int max_cpus)
1261{
83f7eb9c
GOC
1262 Dprintk("Boot done.\n");
1263
1264 impress_friends();
1265 smp_checks();
1266#ifdef CONFIG_X86_IO_APIC
1267 setup_ioapic_dest();
1268#endif
1269 check_nmi_watchdog();
1270#ifdef CONFIG_X86_32
1271 zap_low_mappings();
1272#endif
1273}
1274
68a1c3f8 1275#ifdef CONFIG_HOTPLUG_CPU
2cd9fb71
GOC
1276
1277# ifdef CONFIG_X86_32
1278void cpu_exit_clear(void)
1279{
1280 int cpu = raw_smp_processor_id();
1281
1282 idle_task_exit();
1283
1284 cpu_uninit();
1285 irq_ctx_exit(cpu);
1286
1287 cpu_clear(cpu, cpu_callout_map);
1288 cpu_clear(cpu, cpu_callin_map);
1289
1290 unmap_cpu_to_logical_apicid(cpu);
1291}
1292# endif /* CONFIG_X86_32 */
1293
768d9505
GC
1294void remove_siblinginfo(int cpu)
1295{
1296 int sibling;
1297 struct cpuinfo_x86 *c = &cpu_data(cpu);
1298
1299 for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
1300 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
1301 /*/
1302 * last thread sibling in this cpu core going down
1303 */
1304 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
1305 cpu_data(sibling).booted_cores--;
1306 }
1307
1308 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
1309 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
1310 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1311 cpus_clear(per_cpu(cpu_core_map, cpu));
1312 c->phys_proc_id = 0;
1313 c->cpu_core_id = 0;
1314 cpu_clear(cpu, cpu_sibling_setup_map);
1315}
68a1c3f8
GC
1316
1317int additional_cpus __initdata = -1;
1318
1319static __init int setup_additional_cpus(char *s)
1320{
1321 return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
1322}
1323early_param("additional_cpus", setup_additional_cpus);
1324
1325/*
1326 * cpu_possible_map should be static, it cannot change as cpu's
1327 * are onlined, or offlined. The reason is per-cpu data-structures
1328 * are allocated by some modules at init time, and dont expect to
1329 * do this dynamically on cpu arrival/departure.
1330 * cpu_present_map on the other hand can change dynamically.
1331 * In case when cpu_hotplug is not compiled, then we resort to current
1332 * behaviour, which is cpu_possible == cpu_present.
1333 * - Ashok Raj
1334 *
1335 * Three ways to find out the number of additional hotplug CPUs:
1336 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1337 * - The user can overwrite it with additional_cpus=NUM
1338 * - Otherwise don't reserve additional CPUs.
1339 * We do this because additional CPUs waste a lot of memory.
1340 * -AK
1341 */
1342__init void prefill_possible_map(void)
1343{
1344 int i;
1345 int possible;
1346
1347 if (additional_cpus == -1) {
1348 if (disabled_cpus > 0)
1349 additional_cpus = disabled_cpus;
1350 else
1351 additional_cpus = 0;
1352 }
1353 possible = num_processors + additional_cpus;
1354 if (possible > NR_CPUS)
1355 possible = NR_CPUS;
1356
1357 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1358 possible, max_t(int, possible - num_processors, 0));
1359
1360 for (i = 0; i < possible; i++)
1361 cpu_set(i, cpu_possible_map);
1362}
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1363
1364static void __ref remove_cpu_from_maps(int cpu)
1365{
1366 cpu_clear(cpu, cpu_online_map);
1367#ifdef CONFIG_X86_64
1368 cpu_clear(cpu, cpu_callout_map);
1369 cpu_clear(cpu, cpu_callin_map);
1370 /* was set by cpu_init() */
1371 clear_bit(cpu, (unsigned long *)&cpu_initialized);
1372 clear_node_cpumask(cpu);
1373#endif
1374}
1375
1376int __cpu_disable(void)
1377{
1378 int cpu = smp_processor_id();
1379
1380 /*
1381 * Perhaps use cpufreq to drop frequency, but that could go
1382 * into generic code.
1383 *
1384 * We won't take down the boot processor on i386 due to some
1385 * interrupts only being able to be serviced by the BSP.
1386 * Especially so if we're not using an IOAPIC -zwane
1387 */
1388 if (cpu == 0)
1389 return -EBUSY;
1390
1391 if (nmi_watchdog == NMI_LOCAL_APIC)
1392 stop_apic_nmi_watchdog(NULL);
1393 clear_local_APIC();
1394
1395 /*
1396 * HACK:
1397 * Allow any queued timer interrupts to get serviced
1398 * This is only a temporary solution until we cleanup
1399 * fixup_irqs as we do for IA64.
1400 */
1401 local_irq_enable();
1402 mdelay(1);
1403
1404 local_irq_disable();
1405 remove_siblinginfo(cpu);
1406
1407 /* It's now safe to remove this processor from the online map */
1408 remove_cpu_from_maps(cpu);
1409 fixup_irqs(cpu_online_map);
1410 return 0;
1411}
1412
1413void __cpu_die(unsigned int cpu)
1414{
1415 /* We don't do anything here: idle task is faking death itself. */
1416 unsigned int i;
1417
1418 for (i = 0; i < 10; i++) {
1419 /* They ack this in play_dead by setting CPU_DEAD */
1420 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1421 printk(KERN_INFO "CPU %d is now offline\n", cpu);
1422 if (1 == num_online_cpus())
1423 alternatives_smp_switch(0);
1424 return;
1425 }
1426 msleep(100);
1427 }
1428 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1429}
1430#else /* ... !CONFIG_HOTPLUG_CPU */
1431int __cpu_disable(void)
1432{
1433 return -ENOSYS;
1434}
1435
1436void __cpu_die(unsigned int cpu)
1437{
1438 /* We said "no" in __cpu_disable */
1439 BUG();
1440}
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1441#endif
1442
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1443/*
1444 * If the BIOS enumerates physical processors before logical,
1445 * maxcpus=N at enumeration-time can be used to disable HT.
1446 */
1447static int __init parse_maxcpus(char *arg)
1448{
1449 extern unsigned int maxcpus;
1450
1451 maxcpus = simple_strtoul(arg, NULL, 0);
1452 return 0;
1453}
1454early_param("maxcpus", parse_maxcpus);