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Merge branch 'ebt_config_compat_v4' of git://git.breakpoint.cc/fw/nf-next-2.6
[net-next-2.6.git] / arch / x86 / kernel / process_64.c
CommitLineData
1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6612538c 6 *
1da177e4
LT
7 * X86-64 port
8 * Andi Kleen.
76e4f660
AR
9 *
10 * CPU hotplug support - ashok.raj@intel.com
1da177e4
LT
11 */
12
13/*
14 * This file handles the architecture-dependent parts of process handling..
15 */
16
42059429 17#include <linux/stackprotector.h>
76e4f660 18#include <linux/cpu.h>
1da177e4
LT
19#include <linux/errno.h>
20#include <linux/sched.h>
6612538c 21#include <linux/fs.h>
1da177e4
LT
22#include <linux/kernel.h>
23#include <linux/mm.h>
24#include <linux/elfcore.h>
25#include <linux/smp.h>
26#include <linux/slab.h>
27#include <linux/user.h>
1da177e4
LT
28#include <linux/interrupt.h>
29#include <linux/delay.h>
6612538c 30#include <linux/module.h>
1da177e4 31#include <linux/ptrace.h>
95833c83 32#include <linux/notifier.h>
c6fd91f0 33#include <linux/kprobes.h>
1eeb66a1 34#include <linux/kdebug.h>
02290683 35#include <linux/tick.h>
529e25f6 36#include <linux/prctl.h>
7de08b4e
GP
37#include <linux/uaccess.h>
38#include <linux/io.h>
8b96f011 39#include <linux/ftrace.h>
1da177e4 40
1da177e4
LT
41#include <asm/pgtable.h>
42#include <asm/system.h>
1da177e4
LT
43#include <asm/processor.h>
44#include <asm/i387.h>
45#include <asm/mmu_context.h>
1da177e4 46#include <asm/prctl.h>
1da177e4
LT
47#include <asm/desc.h>
48#include <asm/proto.h>
49#include <asm/ia32.h>
95833c83 50#include <asm/idle.h>
bbc1f698 51#include <asm/syscalls.h>
bf53de90 52#include <asm/ds.h>
66cb5917 53#include <asm/debugreg.h>
1da177e4
LT
54
55asmlinkage extern void ret_from_fork(void);
56
3d1e42a7 57DEFINE_PER_CPU(unsigned long, old_rsp);
c2558e0e 58static DEFINE_PER_CPU(unsigned char, is_idle);
3d1e42a7 59
e041c683 60static ATOMIC_NOTIFIER_HEAD(idle_notifier);
95833c83
AK
61
62void idle_notifier_register(struct notifier_block *n)
63{
e041c683 64 atomic_notifier_chain_register(&idle_notifier, n);
95833c83 65}
c7d87d79
VP
66EXPORT_SYMBOL_GPL(idle_notifier_register);
67
68void idle_notifier_unregister(struct notifier_block *n)
69{
70 atomic_notifier_chain_unregister(&idle_notifier, n);
71}
72EXPORT_SYMBOL_GPL(idle_notifier_unregister);
95833c83 73
95833c83
AK
74void enter_idle(void)
75{
c2558e0e 76 percpu_write(is_idle, 1);
e041c683 77 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
95833c83
AK
78}
79
80static void __exit_idle(void)
81{
c2558e0e 82 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
a15da49d 83 return;
e041c683 84 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
95833c83
AK
85}
86
87/* Called from interrupts to signify idle end */
88void exit_idle(void)
89{
a15da49d
AK
90 /* idle loop has pid 0 */
91 if (current->pid)
95833c83
AK
92 return;
93 __exit_idle();
94}
95
913da64b 96#ifndef CONFIG_SMP
76e4f660
AR
97static inline void play_dead(void)
98{
99 BUG();
100}
913da64b 101#endif
76e4f660 102
1da177e4
LT
103/*
104 * The idle thread. There's no useful work to be
105 * done, so just try to conserve power and have a
106 * low exit latency (ie sit in a loop waiting for
107 * somebody to say that they'd like to reschedule)
108 */
b10db7f0 109void cpu_idle(void)
1da177e4 110{
495ab9c0 111 current_thread_info()->status |= TS_POLLING;
ce22bd92 112
ce22bd92 113 /*
5c79d2a5
TH
114 * If we're the non-boot CPU, nothing set the stack canary up
115 * for us. CPU0 already has it initialized but no harm in
116 * doing it again. This is a good place for updating it, as
117 * we wont ever return from this function (so the invalid
118 * canaries already on the stack wont ever trigger).
ce22bd92 119 */
18aa8bb1
IM
120 boot_init_stack_canary();
121
1da177e4
LT
122 /* endless idle loop with no priority at all */
123 while (1) {
b8f8c3cf 124 tick_nohz_stop_sched_tick(1);
1da177e4 125 while (!need_resched()) {
1da177e4 126
1da177e4 127 rmb();
6ddd2a27 128
76e4f660
AR
129 if (cpu_is_offline(smp_processor_id()))
130 play_dead();
d331e739
VP
131 /*
132 * Idle routines should keep interrupts disabled
133 * from here on, until they go to idle.
134 * Otherwise, idle callbacks can misfire.
135 */
136 local_irq_disable();
95833c83 137 enter_idle();
81d68a96
SR
138 /* Don't trace irqs off for idle */
139 stop_critical_timings();
6ddd2a27 140 pm_idle();
81d68a96 141 start_critical_timings();
a15da49d
AK
142 /* In many cases the interrupt that ended idle
143 has already called exit_idle. But some idle
144 loops can be woken up without interrupt. */
95833c83 145 __exit_idle();
1da177e4
LT
146 }
147
02290683 148 tick_nohz_restart_sched_tick();
5bfb5d69 149 preempt_enable_no_resched();
1da177e4 150 schedule();
5bfb5d69 151 preempt_disable();
1da177e4
LT
152 }
153}
154
6612538c 155/* Prints also some state that isn't saved in the pt_regs */
e2ce07c8 156void __show_regs(struct pt_regs *regs, int all)
1da177e4
LT
157{
158 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
bb1995d5 159 unsigned long d0, d1, d2, d3, d6, d7;
6612538c
HS
160 unsigned int fsindex, gsindex;
161 unsigned int ds, cs, es;
814e2c84
AI
162
163 show_regs_common();
d015a092 164 printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
aafbd7eb 165 printk_address(regs->ip, 1);
d015a092 166 printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss,
8092c654 167 regs->sp, regs->flags);
d015a092 168 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
65ea5b03 169 regs->ax, regs->bx, regs->cx);
d015a092 170 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
65ea5b03 171 regs->dx, regs->si, regs->di);
d015a092 172 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
65ea5b03 173 regs->bp, regs->r8, regs->r9);
d015a092 174 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
7de08b4e 175 regs->r10, regs->r11, regs->r12);
d015a092 176 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
7de08b4e 177 regs->r13, regs->r14, regs->r15);
1da177e4 178
7de08b4e
GP
179 asm("movl %%ds,%0" : "=r" (ds));
180 asm("movl %%cs,%0" : "=r" (cs));
181 asm("movl %%es,%0" : "=r" (es));
1da177e4
LT
182 asm("movl %%fs,%0" : "=r" (fsindex));
183 asm("movl %%gs,%0" : "=r" (gsindex));
184
185 rdmsrl(MSR_FS_BASE, fs);
7de08b4e
GP
186 rdmsrl(MSR_GS_BASE, gs);
187 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
1da177e4 188
e2ce07c8
PE
189 if (!all)
190 return;
1da177e4 191
f51c9452
GOC
192 cr0 = read_cr0();
193 cr2 = read_cr2();
194 cr3 = read_cr3();
195 cr4 = read_cr4();
1da177e4 196
d015a092 197 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
7de08b4e 198 fs, fsindex, gs, gsindex, shadowgs);
d015a092 199 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
8092c654 200 es, cr0);
d015a092 201 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
8092c654 202 cr4);
bb1995d5
AS
203
204 get_debugreg(d0, 0);
205 get_debugreg(d1, 1);
206 get_debugreg(d2, 2);
d015a092 207 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
bb1995d5
AS
208 get_debugreg(d3, 3);
209 get_debugreg(d6, 6);
210 get_debugreg(d7, 7);
d015a092 211 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
1da177e4
LT
212}
213
214void show_regs(struct pt_regs *regs)
215{
a489ca35 216 show_registers(regs);
bc850d6b 217 show_trace(NULL, regs, (void *)(regs + 1), regs->bp);
1da177e4
LT
218}
219
1da177e4
LT
220void release_thread(struct task_struct *dead_task)
221{
222 if (dead_task->mm) {
223 if (dead_task->mm->context.size) {
224 printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",
225 dead_task->comm,
226 dead_task->mm->context.ldt,
227 dead_task->mm->context.size);
228 BUG();
229 }
230 }
231}
232
233static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
234{
6612538c 235 struct user_desc ud = {
1da177e4
LT
236 .base_addr = addr,
237 .limit = 0xfffff,
238 .seg_32bit = 1,
239 .limit_in_pages = 1,
240 .useable = 1,
241 };
ade1af77 242 struct desc_struct *desc = t->thread.tls_array;
1da177e4 243 desc += tls;
80fbb69a 244 fill_ldt(desc, &ud);
1da177e4
LT
245}
246
247static inline u32 read_32bit_tls(struct task_struct *t, int tls)
248{
91394eb0 249 return get_desc_base(&t->thread.tls_array[tls]);
1da177e4
LT
250}
251
252/*
253 * This gets called before we allocate a new thread and copy
254 * the current task into it.
255 */
256void prepare_to_copy(struct task_struct *tsk)
257{
258 unlazy_fpu(tsk);
259}
260
6f2c55b8 261int copy_thread(unsigned long clone_flags, unsigned long sp,
1da177e4 262 unsigned long unused,
7de08b4e 263 struct task_struct *p, struct pt_regs *regs)
1da177e4
LT
264{
265 int err;
7de08b4e 266 struct pt_regs *childregs;
1da177e4
LT
267 struct task_struct *me = current;
268
a88cde13 269 childregs = ((struct pt_regs *)
57eafdc2 270 (THREAD_SIZE + task_stack_page(p))) - 1;
1da177e4
LT
271 *childregs = *regs;
272
65ea5b03 273 childregs->ax = 0;
fa4b8f84
BG
274 if (user_mode(regs))
275 childregs->sp = sp;
276 else
65ea5b03 277 childregs->sp = (unsigned long)childregs;
1da177e4 278
faca6227
PA
279 p->thread.sp = (unsigned long) childregs;
280 p->thread.sp0 = (unsigned long) (childregs+1);
281 p->thread.usersp = me->thread.usersp;
1da177e4 282
e4f17c43 283 set_tsk_thread_flag(p, TIF_FORK);
1da177e4
LT
284
285 p->thread.fs = me->thread.fs;
286 p->thread.gs = me->thread.gs;
66cb5917 287 p->thread.io_bitmap_ptr = NULL;
1da177e4 288
ada85708
JF
289 savesegment(gs, p->thread.gsindex);
290 savesegment(fs, p->thread.fsindex);
291 savesegment(es, p->thread.es);
292 savesegment(ds, p->thread.ds);
1da177e4 293
66cb5917 294 err = -ENOMEM;
24f1e32c 295 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
66cb5917 296
d3a4f48d 297 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
1da177e4
LT
298 p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
299 if (!p->thread.io_bitmap_ptr) {
300 p->thread.io_bitmap_max = 0;
301 return -ENOMEM;
302 }
a88cde13
AK
303 memcpy(p->thread.io_bitmap_ptr, me->thread.io_bitmap_ptr,
304 IO_BITMAP_BYTES);
d3a4f48d 305 set_tsk_thread_flag(p, TIF_IO_BITMAP);
6612538c 306 }
1da177e4
LT
307
308 /*
309 * Set a new TLS for the child thread?
310 */
311 if (clone_flags & CLONE_SETTLS) {
312#ifdef CONFIG_IA32_EMULATION
313 if (test_thread_flag(TIF_IA32))
efd1ca52 314 err = do_set_thread_area(p, -1,
65ea5b03 315 (struct user_desc __user *)childregs->si, 0);
7de08b4e
GP
316 else
317#endif
318 err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8);
319 if (err)
1da177e4
LT
320 goto out;
321 }
bf53de90 322
2311f0de
MM
323 clear_tsk_thread_flag(p, TIF_DS_AREA_MSR);
324 p->thread.ds_ctx = NULL;
bf53de90
MM
325
326 clear_tsk_thread_flag(p, TIF_DEBUGCTLMSR);
327 p->thread.debugctlmsr = 0;
328
1da177e4
LT
329 err = 0;
330out:
331 if (err && p->thread.io_bitmap_ptr) {
332 kfree(p->thread.io_bitmap_ptr);
333 p->thread.io_bitmap_max = 0;
334 }
66cb5917 335
1da177e4
LT
336 return err;
337}
338
e634d8fc
PA
339static void
340start_thread_common(struct pt_regs *regs, unsigned long new_ip,
341 unsigned long new_sp,
342 unsigned int _cs, unsigned int _ss, unsigned int _ds)
513ad84b 343{
ada85708 344 loadsegment(fs, 0);
e634d8fc
PA
345 loadsegment(es, _ds);
346 loadsegment(ds, _ds);
513ad84b
IM
347 load_gs_index(0);
348 regs->ip = new_ip;
349 regs->sp = new_sp;
3d1e42a7 350 percpu_write(old_rsp, new_sp);
e634d8fc
PA
351 regs->cs = _cs;
352 regs->ss = _ss;
a6f05a6a 353 regs->flags = X86_EFLAGS_IF;
513ad84b 354 set_fs(USER_DS);
aa283f49
SS
355 /*
356 * Free the old FP and other extended state
357 */
358 free_thread_xstate(current);
513ad84b 359}
e634d8fc
PA
360
361void
362start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
363{
364 start_thread_common(regs, new_ip, new_sp,
365 __USER_CS, __USER_DS, 0);
366}
513ad84b 367
a6f05a6a
PA
368#ifdef CONFIG_IA32_EMULATION
369void start_thread_ia32(struct pt_regs *regs, u32 new_ip, u32 new_sp)
370{
e634d8fc
PA
371 start_thread_common(regs, new_ip, new_sp,
372 __USER32_CS, __USER32_DS, __USER32_DS);
a6f05a6a
PA
373}
374#endif
513ad84b 375
1da177e4
LT
376/*
377 * switch_to(x,y) should switch tasks from x to y.
378 *
6612538c 379 * This could still be optimized:
1da177e4
LT
380 * - fold all the options into a flag word and test it with a single test.
381 * - could test fs/gs bitsliced
099f318b
AK
382 *
383 * Kprobes not supported here. Set the probe on schedule instead.
8b96f011 384 * Function graph tracer not supported too.
1da177e4 385 */
8b96f011 386__notrace_funcgraph struct task_struct *
a88cde13 387__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
1da177e4 388{
87b935a0
JF
389 struct thread_struct *prev = &prev_p->thread;
390 struct thread_struct *next = &next_p->thread;
6612538c 391 int cpu = smp_processor_id();
1da177e4 392 struct tss_struct *tss = &per_cpu(init_tss, cpu);
478de5a9 393 unsigned fsindex, gsindex;
17950c5b
JF
394 bool preload_fpu;
395
396 /*
397 * If the task has used fpu the last 5 timeslices, just do a full
398 * restore of the math state immediately to avoid the trap; the
399 * chances of needing FPU soon are obviously high now
400 */
401 preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5;
1da177e4 402
e07e23e1 403 /* we're going to use this soon, after a few expensive things */
17950c5b 404 if (preload_fpu)
61c4628b 405 prefetch(next->xstate);
e07e23e1 406
1da177e4
LT
407 /*
408 * Reload esp0, LDT and the page table pointer:
409 */
7818a1e0 410 load_sp0(tss, next);
1da177e4 411
7de08b4e 412 /*
1da177e4
LT
413 * Switch DS and ES.
414 * This won't pick up thread selector changes, but I guess that is ok.
415 */
ada85708 416 savesegment(es, prev->es);
1da177e4 417 if (unlikely(next->es | prev->es))
7de08b4e 418 loadsegment(es, next->es);
ada85708
JF
419
420 savesegment(ds, prev->ds);
1da177e4
LT
421 if (unlikely(next->ds | prev->ds))
422 loadsegment(ds, next->ds);
423
478de5a9
JF
424
425 /* We must save %fs and %gs before load_TLS() because
426 * %fs and %gs may be cleared by load_TLS().
427 *
428 * (e.g. xen_load_tls())
429 */
430 savesegment(fs, fsindex);
431 savesegment(gs, gsindex);
432
1da177e4
LT
433 load_TLS(next, cpu);
434
16d9dbf0
JF
435 /* Must be after DS reload */
436 unlazy_fpu(prev_p);
437
17950c5b
JF
438 /* Make sure cpu is ready for new context */
439 if (preload_fpu)
440 clts();
441
3fe0a63e
JF
442 /*
443 * Leave lazy mode, flushing any hypercalls made here.
444 * This must be done before restoring TLS segments so
445 * the GDT and LDT are properly updated, and must be
446 * done before math_state_restore, so the TS bit is up
447 * to date.
448 */
224101ed 449 arch_end_context_switch(next_p);
3fe0a63e 450
7de08b4e 451 /*
1da177e4 452 * Switch FS and GS.
87b935a0
JF
453 *
454 * Segment register != 0 always requires a reload. Also
455 * reload when it has changed. When prev process used 64bit
456 * base always reload to avoid an information leak.
1da177e4 457 */
87b935a0
JF
458 if (unlikely(fsindex | next->fsindex | prev->fs)) {
459 loadsegment(fs, next->fsindex);
7de08b4e 460 /*
87b935a0
JF
461 * Check if the user used a selector != 0; if yes
462 * clear 64bit base, since overloaded base is always
463 * mapped to the Null selector
464 */
465 if (fsindex)
7de08b4e 466 prev->fs = 0;
1da177e4 467 }
87b935a0
JF
468 /* when next process has a 64bit base use it */
469 if (next->fs)
470 wrmsrl(MSR_FS_BASE, next->fs);
471 prev->fsindex = fsindex;
472
473 if (unlikely(gsindex | next->gsindex | prev->gs)) {
474 load_gs_index(next->gsindex);
475 if (gsindex)
7de08b4e 476 prev->gs = 0;
1da177e4 477 }
87b935a0
JF
478 if (next->gs)
479 wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
480 prev->gsindex = gsindex;
1da177e4 481
7de08b4e 482 /*
45948d77 483 * Switch the PDA and FPU contexts.
1da177e4 484 */
3d1e42a7
BG
485 prev->usersp = percpu_read(old_rsp);
486 percpu_write(old_rsp, next->usersp);
c6f5e0ac 487 percpu_write(current_task, next_p);
18bd057b 488
9af45651 489 percpu_write(kernel_stack,
87b935a0 490 (unsigned long)task_stack_page(next_p) +
9af45651 491 THREAD_SIZE - KERNEL_STACK_OFFSET);
1da177e4
LT
492
493 /*
d3a4f48d 494 * Now maybe reload the debug registers and handle I/O bitmaps
1da177e4 495 */
eee3af4a
MM
496 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
497 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
d3a4f48d 498 __switch_to_xtra(prev_p, next_p, tss);
1da177e4 499
17950c5b
JF
500 /*
501 * Preload the FPU context, now that we've determined that the
502 * task is likely to be using it.
e07e23e1 503 */
17950c5b
JF
504 if (preload_fpu)
505 __math_state_restore();
66cb5917 506
1da177e4
LT
507 return prev_p;
508}
509
1da177e4
LT
510void set_personality_64bit(void)
511{
512 /* inherit personality from parent */
513
514 /* Make sure to be in 64bit mode */
6612538c 515 clear_thread_flag(TIF_IA32);
1da177e4
LT
516
517 /* TBD: overwrites user setup. Should have two bits.
518 But 64bit processes have always behaved this way,
519 so it's not too bad. The main problem is just that
6612538c 520 32bit childs are affected again. */
1da177e4
LT
521 current->personality &= ~READ_IMPLIES_EXEC;
522}
523
05d43ed8
PA
524void set_personality_ia32(void)
525{
526 /* inherit personality from parent */
527
528 /* Make sure to be in 32bit mode */
529 set_thread_flag(TIF_IA32);
1252f238 530 current->personality |= force_personality32;
05d43ed8
PA
531
532 /* Prepare the first "return" to user space */
533 current_thread_info()->status |= TS_COMPAT;
534}
535
1da177e4
LT
536unsigned long get_wchan(struct task_struct *p)
537{
538 unsigned long stack;
7de08b4e 539 u64 fp, ip;
1da177e4
LT
540 int count = 0;
541
7de08b4e
GP
542 if (!p || p == current || p->state == TASK_RUNNING)
543 return 0;
57eafdc2 544 stack = (unsigned long)task_stack_page(p);
e1e23bb0 545 if (p->thread.sp < stack || p->thread.sp >= stack+THREAD_SIZE)
1da177e4 546 return 0;
faca6227 547 fp = *(u64 *)(p->thread.sp);
7de08b4e 548 do {
a88cde13 549 if (fp < (unsigned long)stack ||
e1e23bb0 550 fp >= (unsigned long)stack+THREAD_SIZE)
7de08b4e 551 return 0;
65ea5b03
PA
552 ip = *(u64 *)(fp+8);
553 if (!in_sched_functions(ip))
554 return ip;
7de08b4e
GP
555 fp = *(u64 *)fp;
556 } while (count++ < 16);
1da177e4
LT
557 return 0;
558}
559
560long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
7de08b4e
GP
561{
562 int ret = 0;
1da177e4
LT
563 int doit = task == current;
564 int cpu;
565
7de08b4e 566 switch (code) {
1da177e4 567 case ARCH_SET_GS:
84929801 568 if (addr >= TASK_SIZE_OF(task))
7de08b4e 569 return -EPERM;
1da177e4 570 cpu = get_cpu();
7de08b4e 571 /* handle small bases via the GDT because that's faster to
1da177e4 572 switch. */
7de08b4e
GP
573 if (addr <= 0xffffffff) {
574 set_32bit_tls(task, GS_TLS, addr);
575 if (doit) {
1da177e4 576 load_TLS(&task->thread, cpu);
7de08b4e 577 load_gs_index(GS_TLS_SEL);
1da177e4 578 }
7de08b4e 579 task->thread.gsindex = GS_TLS_SEL;
1da177e4 580 task->thread.gs = 0;
7de08b4e 581 } else {
1da177e4
LT
582 task->thread.gsindex = 0;
583 task->thread.gs = addr;
584 if (doit) {
a88cde13
AK
585 load_gs_index(0);
586 ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr);
7de08b4e 587 }
1da177e4
LT
588 }
589 put_cpu();
590 break;
591 case ARCH_SET_FS:
592 /* Not strictly needed for fs, but do it for symmetry
593 with gs */
84929801 594 if (addr >= TASK_SIZE_OF(task))
6612538c 595 return -EPERM;
1da177e4 596 cpu = get_cpu();
6612538c 597 /* handle small bases via the GDT because that's faster to
1da177e4 598 switch. */
6612538c 599 if (addr <= 0xffffffff) {
1da177e4 600 set_32bit_tls(task, FS_TLS, addr);
6612538c
HS
601 if (doit) {
602 load_TLS(&task->thread, cpu);
ada85708 603 loadsegment(fs, FS_TLS_SEL);
1da177e4
LT
604 }
605 task->thread.fsindex = FS_TLS_SEL;
606 task->thread.fs = 0;
6612538c 607 } else {
1da177e4
LT
608 task->thread.fsindex = 0;
609 task->thread.fs = addr;
610 if (doit) {
611 /* set the selector to 0 to not confuse
612 __switch_to */
ada85708 613 loadsegment(fs, 0);
a88cde13 614 ret = checking_wrmsrl(MSR_FS_BASE, addr);
1da177e4
LT
615 }
616 }
617 put_cpu();
618 break;
6612538c
HS
619 case ARCH_GET_FS: {
620 unsigned long base;
1da177e4
LT
621 if (task->thread.fsindex == FS_TLS_SEL)
622 base = read_32bit_tls(task, FS_TLS);
a88cde13 623 else if (doit)
1da177e4 624 rdmsrl(MSR_FS_BASE, base);
a88cde13 625 else
1da177e4 626 base = task->thread.fs;
6612538c
HS
627 ret = put_user(base, (unsigned long __user *)addr);
628 break;
1da177e4 629 }
6612538c 630 case ARCH_GET_GS: {
1da177e4 631 unsigned long base;
97c2803c 632 unsigned gsindex;
1da177e4
LT
633 if (task->thread.gsindex == GS_TLS_SEL)
634 base = read_32bit_tls(task, GS_TLS);
97c2803c 635 else if (doit) {
ada85708 636 savesegment(gs, gsindex);
97c2803c
JB
637 if (gsindex)
638 rdmsrl(MSR_KERNEL_GS_BASE, base);
639 else
640 base = task->thread.gs;
7de08b4e 641 } else
1da177e4 642 base = task->thread.gs;
6612538c 643 ret = put_user(base, (unsigned long __user *)addr);
1da177e4
LT
644 break;
645 }
646
647 default:
648 ret = -EINVAL;
649 break;
6612538c 650 }
1da177e4 651
6612538c
HS
652 return ret;
653}
1da177e4
LT
654
655long sys_arch_prctl(int code, unsigned long addr)
656{
657 return do_arch_prctl(current, code, addr);
1da177e4
LT
658}
659
89240ba0
SS
660unsigned long KSTK_ESP(struct task_struct *task)
661{
662 return (test_tsk_thread_flag(task, TIF_IA32)) ?
663 (task_pt_regs(task)->sp) : ((task)->thread.usersp);
664}