[net-next-2.6.git] / arch / x86 / kernel / process.c

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/idle.h>
#include <linux/smp.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <trace/power.h>
#include <asm/system.h>
#include <asm/apic.h>

unsigned long idle_halt;
EXPORT_SYMBOL(idle_halt);
unsigned long idle_nomwait;
EXPORT_SYMBOL(idle_nomwait);

struct kmem_cache *task_xstate_cachep;

DEFINE_TRACE(power_start);
DEFINE_TRACE(power_end);

int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	*dst = *src;
	if (src->thread.xstate) {
		dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
						      GFP_KERNEL);
		if (!dst->thread.xstate)
			return -ENOMEM;
		WARN_ON((unsigned long)dst->thread.xstate & 15);
		memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	if (tsk->thread.xstate) {
		kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
		tsk->thread.xstate = NULL;
	}
}

void free_thread_info(struct thread_info *ti)
{
	free_thread_xstate(ti->task);
	free_pages((unsigned long)ti, get_order(THREAD_SIZE));
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC, NULL);
}

/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = 0;
EXPORT_SYMBOL(boot_option_idle_override);

/*
 * Powermanagement idle function, if any..
 */
void (*pm_idle)(void);
EXPORT_SYMBOL(pm_idle);

#ifdef CONFIG_X86_32
/*
 * This halt magic was a workaround for ancient floppy DMA
 * wreckage. It should be safe to remove.
 */
static int hlt_counter;
void disable_hlt(void)
{
	hlt_counter++;
}
EXPORT_SYMBOL(disable_hlt);

void enable_hlt(void)
{
	hlt_counter--;
}
EXPORT_SYMBOL(enable_hlt);

static inline int hlt_use_halt(void)
{
	return (!hlt_counter && boot_cpu_data.hlt_works_ok);
}
#else
static inline int hlt_use_halt(void)
{
	return 1;
}
#endif

/*
 * We use this if we don't have any better
 * idle routine..
 */
void default_idle(void)
{
	if (hlt_use_halt()) {
		struct power_trace it;

		trace_power_start(&it, POWER_CSTATE, 1);
		current_thread_info()->status &= ~TS_POLLING;
		/*
		 * TS_POLLING-cleared state must be visible before we
		 * test NEED_RESCHED:
		 */
		smp_mb();

		if (!need_resched())
			safe_halt();	/* enables interrupts racelessly */
		else
			local_irq_enable();
		current_thread_info()->status |= TS_POLLING;
		trace_power_end(&it);
	} else {
		local_irq_enable();
		/* loop is done by the caller */
		cpu_relax();
	}
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	cpu_clear(smp_processor_id(), cpu_online_map);
	disable_local_APIC();

	for (;;) {
		if (hlt_works(smp_processor_id()))
			halt();
	}
}

static void do_nothing(void *unused)
{
}

/*
 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 * pm_idle and update to new pm_idle value. Required while changing pm_idle
 * handler on SMP systems.
 *
 * Caller must have changed pm_idle to the new value before the call. Old
 * pm_idle value will not be used by any CPU after the return of this function.
 */
void cpu_idle_wait(void)
{
	smp_mb();
	/* kick all the CPUs so that they exit out of pm_idle */
	smp_call_function(do_nothing, NULL, 1);
}
EXPORT_SYMBOL_GPL(cpu_idle_wait);

/*
 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 * which can obviate IPI to trigger checking of need_resched.
 * We execute MONITOR against need_resched and enter optimized wait state
 * through MWAIT. Whenever someone changes need_resched, we would be woken
 * up from MWAIT (without an IPI).
 *
 * New with Core Duo processors, MWAIT can take some hints based on CPU
 * capability.
 */
void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
{
	struct power_trace it;

	trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
	if (!need_resched()) {
		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__mwait(ax, cx);
	}
	trace_power_end(&it);
}

/* Default MONITOR/MWAIT with no hints, used for default C1 state */
static void mwait_idle(void)
{
	struct power_trace it;
	if (!need_resched()) {
		trace_power_start(&it, POWER_CSTATE, 1);
		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__sti_mwait(0, 0);
		else
			local_irq_enable();
		trace_power_end(&it);
	} else
		local_irq_enable();
}

/*
 * On SMP it's slightly faster (but much more power-consuming!)
 * to poll the ->work.need_resched flag instead of waiting for the
 * cross-CPU IPI to arrive. Use this option with caution.
 */
static void poll_idle(void)
{
	struct power_trace it;

	trace_power_start(&it, POWER_CSTATE, 0);
	local_irq_enable();
	while (!need_resched())
		cpu_relax();
	trace_power_end(&it);
}

/*
 * mwait selection logic:
 *
 * It depends on the CPU. For AMD CPUs that support MWAIT this is
 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 * then depend on a clock divisor and current Pstate of the core. If
 * all cores of a processor are in halt state (C1) the processor can
 * enter the C1E (C1 enhanced) state. If mwait is used this will never
 * happen.
 *
 * idle=mwait overrides this decision and forces the usage of mwait.
 */
static int __cpuinitdata force_mwait;

#define MWAIT_INFO			0x05
#define MWAIT_ECX_EXTENDED_INFO		0x01
#define MWAIT_EDX_C1			0xf0

static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
{
	u32 eax, ebx, ecx, edx;

	if (force_mwait)
		return 1;

	if (c->cpuid_level < MWAIT_INFO)
		return 0;

	cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
	/* Check, whether EDX has extended info about MWAIT */
	if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
		return 1;

	/*
	 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
	 * C1  supports MWAIT
	 */
	return (edx & MWAIT_EDX_C1);
}

/*
 * Check for AMD CPUs, which have potentially C1E support
 */
static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
{
	if (c->x86_vendor != X86_VENDOR_AMD)
		return 0;

	if (c->x86 < 0x0F)
		return 0;

	/* Family 0x0f models < rev F do not have C1E */
	if (c->x86 == 0x0f && c->x86_model < 0x40)
		return 0;

	return 1;
}

static cpumask_t c1e_mask = CPU_MASK_NONE;
static int c1e_detected;

void c1e_remove_cpu(int cpu)
{
	cpu_clear(cpu, c1e_mask);
}

/*
 * C1E aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void c1e_idle(void)
{
	if (need_resched())
		return;

	if (!c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			c1e_detected = 1;
			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			printk(KERN_INFO "System has AMD C1E enabled\n");
			set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
		}
	}

	if (c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpu_isset(cpu, c1e_mask)) {
			cpu_set(cpu, c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere. Needs
			 * to run with interrupts enabled as it uses
			 * smp_function_call.
			 */
			local_irq_enable();
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
			       cpu);
			local_irq_disable();
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		 local_irq_disable();
		 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		 local_irq_enable();
	} else
		default_idle();
}

void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_SMP
	if (pm_idle == poll_idle && smp_num_siblings > 1) {
		printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
			" performance may degrade.\n");
	}
#endif
	if (pm_idle)
		return;

	if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
		/*
		 * One CPU supports mwait => All CPUs supports mwait
		 */
		printk(KERN_INFO "using mwait in idle threads.\n");
		pm_idle = mwait_idle;
	} else if (check_c1e_idle(c)) {
		printk(KERN_INFO "using C1E aware idle routine\n");
		pm_idle = c1e_idle;
	} else
		pm_idle = default_idle;
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		printk("using polling idle threads.\n");
		pm_idle = poll_idle;
	} else if (!strcmp(str, "mwait"))
		force_mwait = 1;
	else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		pm_idle = default_idle;
		idle_halt = 1;
		return 0;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		idle_nomwait = 1;
		return 0;
	} else
		return -1;

	boot_option_idle_override = 1;
	return 0;
}
early_param("idle", idle_setup);
Commit	Line	Data
61c4628b SS	1	#include <linux/errno.h>
	2	#include <linux/kernel.h>
	3	#include <linux/mm.h>
f0bc2202	4	#include <asm/idle.h>
61c4628b SS	5	#include <linux/smp.h>
	6	#include <linux/slab.h>
	7	#include <linux/sched.h>
7f424a8b PZ	8	#include <linux/module.h>
7f424a8b PZ	9	#include <linux/pm.h>
aa276e1c	10	#include <linux/clockchips.h>
12922110	11	#include <trace/power.h>
c1e3b377	12	#include <asm/system.h>
d3ec5cae	13	#include <asm/apic.h>
c1e3b377 ZY	14
	15	unsigned long idle_halt;
	16	EXPORT_SYMBOL(idle_halt);
da5e09a1 ZY	17	unsigned long idle_nomwait;
da5e09a1 ZY	18	EXPORT_SYMBOL(idle_nomwait);
61c4628b	19
aa283f49	20	struct kmem_cache *task_xstate_cachep;
61c4628b	21
b5f9fd0f JB	22	DEFINE_TRACE(power_start);
	23	DEFINE_TRACE(power_end);
	24
61c4628b SS	25	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	26	{
	27	dst = src;
aa283f49 SS	28	if (src->thread.xstate) {
	29	dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
	30	GFP_KERNEL);
	31	if (!dst->thread.xstate)
	32	return -ENOMEM;
	33	WARN_ON((unsigned long)dst->thread.xstate & 15);
	34	memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
	35	}
61c4628b SS	36	return 0;
	37	}
	38
aa283f49	39	void free_thread_xstate(struct task_struct *tsk)
61c4628b	40	{
aa283f49 SS	41	if (tsk->thread.xstate) {
	42	kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
	43	tsk->thread.xstate = NULL;
	44	}
	45	}
	46
aa283f49 SS	47	void free_thread_info(struct thread_info *ti)
	48	{
	49	free_thread_xstate(ti->task);
1679f271	50	free_pages((unsigned long)ti, get_order(THREAD_SIZE));
61c4628b SS	51	}
	52
	53	void arch_task_cache_init(void)
	54	{
	55	task_xstate_cachep =
	56	kmem_cache_create("task_xstate", xstate_size,
	57	__alignof__(union thread_xstate),
	58	SLAB_PANIC, NULL);
	59	}
7f424a8b	60
00dba564 TG	61	/*
	62	* Idle related variables and functions
	63	*/
	64	unsigned long boot_option_idle_override = 0;
	65	EXPORT_SYMBOL(boot_option_idle_override);
	66
	67	/*
	68	* Powermanagement idle function, if any..
	69	*/
	70	void (*pm_idle)(void);
	71	EXPORT_SYMBOL(pm_idle);
	72
	73	#ifdef CONFIG_X86_32
	74	/*
	75	* This halt magic was a workaround for ancient floppy DMA
	76	* wreckage. It should be safe to remove.
	77	*/
	78	static int hlt_counter;
	79	void disable_hlt(void)
	80	{
	81	hlt_counter++;
	82	}
	83	EXPORT_SYMBOL(disable_hlt);
	84
	85	void enable_hlt(void)
	86	{
	87	hlt_counter--;
	88	}
	89	EXPORT_SYMBOL(enable_hlt);
	90
	91	static inline int hlt_use_halt(void)
	92	{
	93	return (!hlt_counter && boot_cpu_data.hlt_works_ok);
	94	}
	95	#else
	96	static inline int hlt_use_halt(void)
	97	{
	98	return 1;
	99	}
	100	#endif
	101
	102	/*
	103	* We use this if we don't have any better
	104	* idle routine..
	105	*/
	106	void default_idle(void)
	107	{
	108	if (hlt_use_halt()) {
f3f47a67 AV	109	struct power_trace it;
	110
	111	trace_power_start(&it, POWER_CSTATE, 1);
00dba564 TG	112	current_thread_info()->status &= ~TS_POLLING;
	113	/*
	114	* TS_POLLING-cleared state must be visible before we
	115	* test NEED_RESCHED:
	116	*/
	117	smp_mb();
	118
	119	if (!need_resched())
	120	safe_halt(); /* enables interrupts racelessly */
	121	else
	122	local_irq_enable();
	123	current_thread_info()->status \|= TS_POLLING;
f3f47a67	124	trace_power_end(&it);
00dba564 TG	125	} else {
	126	local_irq_enable();
	127	/* loop is done by the caller */
	128	cpu_relax();
	129	}
	130	}
	131	#ifdef CONFIG_APM_MODULE
	132	EXPORT_SYMBOL(default_idle);
	133	#endif
	134
d3ec5cae IV	135	void stop_this_cpu(void *dummy)
	136	{
	137	local_irq_disable();
	138	/*
	139	* Remove this CPU:
	140	*/
	141	cpu_clear(smp_processor_id(), cpu_online_map);
	142	disable_local_APIC();
	143
	144	for (;;) {
	145	if (hlt_works(smp_processor_id()))
	146	halt();
	147	}
	148	}
	149
7f424a8b PZ	150	static void do_nothing(void *unused)
	151	{
	152	}
	153
	154	/*
	155	* cpu_idle_wait - Used to ensure that all the CPUs discard old value of
	156	* pm_idle and update to new pm_idle value. Required while changing pm_idle
	157	* handler on SMP systems.
	158	*
	159	* Caller must have changed pm_idle to the new value before the call. Old
	160	* pm_idle value will not be used by any CPU after the return of this function.
	161	*/
	162	void cpu_idle_wait(void)
	163	{
	164	smp_mb();
	165	/* kick all the CPUs so that they exit out of pm_idle */
127a237a	166	smp_call_function(do_nothing, NULL, 1);
7f424a8b PZ	167	}
	168	EXPORT_SYMBOL_GPL(cpu_idle_wait);
	169
	170	/*
	171	* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
	172	* which can obviate IPI to trigger checking of need_resched.
	173	* We execute MONITOR against need_resched and enter optimized wait state
	174	* through MWAIT. Whenever someone changes need_resched, we would be woken
	175	* up from MWAIT (without an IPI).
	176	*
	177	* New with Core Duo processors, MWAIT can take some hints based on CPU
	178	* capability.
	179	*/
	180	void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
	181	{
f3f47a67 AV	182	struct power_trace it;
	183
	184	trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
7f424a8b PZ	185	if (!need_resched()) {
	186	__monitor((void *)&current_thread_info()->flags, 0, 0);
	187	smp_mb();
	188	if (!need_resched())
	189	__mwait(ax, cx);
	190	}
f3f47a67	191	trace_power_end(&it);
7f424a8b PZ	192	}
	193
	194	/* Default MONITOR/MWAIT with no hints, used for default C1 state */
	195	static void mwait_idle(void)
	196	{
f3f47a67	197	struct power_trace it;
7f424a8b	198	if (!need_resched()) {
f3f47a67	199	trace_power_start(&it, POWER_CSTATE, 1);
7f424a8b PZ	200	__monitor((void *)&current_thread_info()->flags, 0, 0);
	201	smp_mb();
	202	if (!need_resched())
	203	__sti_mwait(0, 0);
	204	else
	205	local_irq_enable();
f3f47a67	206	trace_power_end(&it);
7f424a8b PZ	207	} else
	208	local_irq_enable();
	209	}
	210
7f424a8b PZ	211	/*
	212	* On SMP it's slightly faster (but much more power-consuming!)
	213	* to poll the ->work.need_resched flag instead of waiting for the
	214	* cross-CPU IPI to arrive. Use this option with caution.
	215	*/
	216	static void poll_idle(void)
	217	{
f3f47a67 AV	218	struct power_trace it;
	219
	220	trace_power_start(&it, POWER_CSTATE, 0);
7f424a8b	221	local_irq_enable();
2c7e9fd4 JK	222	while (!need_resched())
2c7e9fd4 JK	223	cpu_relax();
f3f47a67	224	trace_power_end(&it);
7f424a8b PZ	225	}
7f424a8b PZ	226
e9623b35 TG	227	/*
	228	* mwait selection logic:
	229	*
	230	* It depends on the CPU. For AMD CPUs that support MWAIT this is
	231	* wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
	232	* then depend on a clock divisor and current Pstate of the core. If
	233	* all cores of a processor are in halt state (C1) the processor can
	234	* enter the C1E (C1 enhanced) state. If mwait is used this will never
	235	* happen.
	236	*
	237	* idle=mwait overrides this decision and forces the usage of mwait.
	238	*/
08ad8afa	239	static int __cpuinitdata force_mwait;
09fd4b4e TG	240
	241	#define MWAIT_INFO 0x05
	242	#define MWAIT_ECX_EXTENDED_INFO 0x01
	243	#define MWAIT_EDX_C1 0xf0
	244
e9623b35 TG	245	static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
e9623b35 TG	246	{
09fd4b4e TG	247	u32 eax, ebx, ecx, edx;
09fd4b4e TG	248
e9623b35 TG	249	if (force_mwait)
	250	return 1;
	251
09fd4b4e TG	252	if (c->cpuid_level < MWAIT_INFO)
	253	return 0;
	254
	255	cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
	256	/* Check, whether EDX has extended info about MWAIT */
	257	if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
	258	return 1;
	259
	260	/*
	261	* edx enumeratios MONITOR/MWAIT extensions. Check, whether
	262	* C1 supports MWAIT
	263	*/
	264	return (edx & MWAIT_EDX_C1);
e9623b35 TG	265	}
e9623b35 TG	266
aa276e1c TG	267	/*
	268	* Check for AMD CPUs, which have potentially C1E support
	269	*/
	270	static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
	271	{
	272	if (c->x86_vendor != X86_VENDOR_AMD)
	273	return 0;
	274
	275	if (c->x86 < 0x0F)
	276	return 0;
	277
	278	/* Family 0x0f models < rev F do not have C1E */
	279	if (c->x86 == 0x0f && c->x86_model < 0x40)
	280	return 0;
	281
	282	return 1;
	283	}
	284
4faac97d TG	285	static cpumask_t c1e_mask = CPU_MASK_NONE;
	286	static int c1e_detected;
	287
	288	void c1e_remove_cpu(int cpu)
	289	{
	290	cpu_clear(cpu, c1e_mask);
	291	}
	292
aa276e1c TG	293	/*
	294	* C1E aware idle routine. We check for C1E active in the interrupt
	295	* pending message MSR. If we detect C1E, then we handle it the same
	296	* way as C3 power states (local apic timer and TSC stop)
	297	*/
	298	static void c1e_idle(void)
	299	{
aa276e1c TG	300	if (need_resched())
	301	return;
	302
	303	if (!c1e_detected) {
	304	u32 lo, hi;
	305
	306	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
	307	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
	308	c1e_detected = 1;
40fb1715	309	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
09bfeea1 AH	310	mark_tsc_unstable("TSC halt in AMD C1E");
09bfeea1 AH	311	printk(KERN_INFO "System has AMD C1E enabled\n");
a8d68290	312	set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
aa276e1c TG	313	}
	314	}
	315
	316	if (c1e_detected) {
	317	int cpu = smp_processor_id();
	318
	319	if (!cpu_isset(cpu, c1e_mask)) {
	320	cpu_set(cpu, c1e_mask);
0beefa20 TG	321	/*
	322	* Force broadcast so ACPI can not interfere. Needs
	323	* to run with interrupts enabled as it uses
	324	* smp_function_call.
	325	*/
	326	local_irq_enable();
aa276e1c TG	327	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
	328	&cpu);
	329	printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
	330	cpu);
0beefa20	331	local_irq_disable();
aa276e1c TG	332	}
aa276e1c TG	333	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
0beefa20	334
aa276e1c	335	default_idle();
0beefa20 TG	336
	337	/*
	338	* The switch back from broadcast mode needs to be
	339	* called with interrupts disabled.
	340	*/
	341	local_irq_disable();
	342	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	343	local_irq_enable();
aa276e1c TG	344	} else
	345	default_idle();
	346	}
	347
7f424a8b PZ	348	void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
7f424a8b PZ	349	{
7f424a8b PZ	350	#ifdef CONFIG_X86_SMP
	351	if (pm_idle == poll_idle && smp_num_siblings > 1) {
	352	printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
	353	" performance may degrade.\n");
	354	}
	355	#endif
6ddd2a27 TG	356	if (pm_idle)
	357	return;
	358
e9623b35	359	if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
7f424a8b	360	/*
7f424a8b PZ	361	* One CPU supports mwait => All CPUs supports mwait
7f424a8b PZ	362	*/
6ddd2a27 TG	363	printk(KERN_INFO "using mwait in idle threads.\n");
6ddd2a27 TG	364	pm_idle = mwait_idle;
aa276e1c TG	365	} else if (check_c1e_idle(c)) {
	366	printk(KERN_INFO "using C1E aware idle routine\n");
	367	pm_idle = c1e_idle;
6ddd2a27 TG	368	} else
6ddd2a27 TG	369	pm_idle = default_idle;
7f424a8b PZ	370	}
	371
	372	static int __init idle_setup(char *str)
	373	{
ab6bc3e3 CG	374	if (!str)
	375	return -EINVAL;
	376
7f424a8b PZ	377	if (!strcmp(str, "poll")) {
	378	printk("using polling idle threads.\n");
	379	pm_idle = poll_idle;
	380	} else if (!strcmp(str, "mwait"))
	381	force_mwait = 1;
c1e3b377 ZY	382	else if (!strcmp(str, "halt")) {
	383	/*
	384	* When the boot option of idle=halt is added, halt is
	385	* forced to be used for CPU idle. In such case CPU C2/C3
	386	* won't be used again.
	387	* To continue to load the CPU idle driver, don't touch
	388	* the boot_option_idle_override.
	389	*/
	390	pm_idle = default_idle;
	391	idle_halt = 1;
	392	return 0;
da5e09a1 ZY	393	} else if (!strcmp(str, "nomwait")) {
	394	/*
	395	* If the boot option of "idle=nomwait" is added,
	396	* it means that mwait will be disabled for CPU C2/C3
	397	* states. In such case it won't touch the variable
	398	* of boot_option_idle_override.
	399	*/
	400	idle_nomwait = 1;
	401	return 0;
c1e3b377	402	} else
7f424a8b PZ	403	return -1;
	404
	405	boot_option_idle_override = 1;
	406	return 0;
	407	}
	408	early_param("idle", idle_setup);
	409