[net-next-2.6.git] / arch / x86 / kernel / mrst.c

/*
 * mrst.c: Intel Moorestown platform specific setup code
 *
 * (C) Copyright 2008 Intel Corporation
 * Author: Jacob Pan (jacob.jun.pan@intel.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sfi.h>
#include <linux/irq.h>
#include <linux/module.h>

#include <asm/setup.h>
#include <asm/mpspec_def.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/io_apic.h>
#include <asm/mrst.h>
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/apb_timer.h>

static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
int sfi_mtimer_num;

struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
EXPORT_SYMBOL_GPL(sfi_mrtc_array);
int sfi_mrtc_num;

static inline void assign_to_mp_irq(struct mpc_intsrc *m,
				    struct mpc_intsrc *mp_irq)
{
	memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
}

static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
				struct mpc_intsrc *m)
{
	return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
}

static void save_mp_irq(struct mpc_intsrc *m)
{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
		if (!mp_irq_cmp(&mp_irqs[i], m))
			return;
	}

	assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
	if (++mp_irq_entries == MAX_IRQ_SOURCES)
		panic("Max # of irq sources exceeded!!\n");
}

/* parse all the mtimer info to a static mtimer array */
static int __init sfi_parse_mtmr(struct sfi_table_header *table)
{
	struct sfi_table_simple *sb;
	struct sfi_timer_table_entry *pentry;
	struct mpc_intsrc mp_irq;
	int totallen;

	sb = (struct sfi_table_simple *)table;
	if (!sfi_mtimer_num) {
		sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
					struct sfi_timer_table_entry);
		pentry = (struct sfi_timer_table_entry *) sb->pentry;
		totallen = sfi_mtimer_num * sizeof(*pentry);
		memcpy(sfi_mtimer_array, pentry, totallen);
	}

	printk(KERN_INFO "SFI: MTIMER info (num = %d):\n", sfi_mtimer_num);
	pentry = sfi_mtimer_array;
	for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
		printk(KERN_INFO "timer[%d]: paddr = 0x%08x, freq = %dHz,"
			" irq = %d\n", totallen, (u32)pentry->phys_addr,
			pentry->freq_hz, pentry->irq);
			if (!pentry->irq)
				continue;
			mp_irq.type = MP_IOAPIC;
			mp_irq.irqtype = mp_INT;
/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
			mp_irq.irqflag = 5;
			mp_irq.srcbus = 0;
			mp_irq.srcbusirq = pentry->irq;	/* IRQ */
			mp_irq.dstapic = MP_APIC_ALL;
			mp_irq.dstirq = pentry->irq;
			save_mp_irq(&mp_irq);
	}

	return 0;
}

struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
{
	int i;
	if (hint < sfi_mtimer_num) {
		if (!sfi_mtimer_usage[hint]) {
			pr_debug("hint taken for timer %d irq %d\n",\
				hint, sfi_mtimer_array[hint].irq);
			sfi_mtimer_usage[hint] = 1;
			return &sfi_mtimer_array[hint];
		}
	}
	/* take the first timer available */
	for (i = 0; i < sfi_mtimer_num;) {
		if (!sfi_mtimer_usage[i]) {
			sfi_mtimer_usage[i] = 1;
			return &sfi_mtimer_array[i];
		}
		i++;
	}
	return NULL;
}

void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
{
	int i;
	for (i = 0; i < sfi_mtimer_num;) {
		if (mtmr->irq == sfi_mtimer_array[i].irq) {
			sfi_mtimer_usage[i] = 0;
			return;
		}
		i++;
	}
}

/* parse all the mrtc info to a global mrtc array */
int __init sfi_parse_mrtc(struct sfi_table_header *table)
{
	struct sfi_table_simple *sb;
	struct sfi_rtc_table_entry *pentry;
	struct mpc_intsrc mp_irq;

	int totallen;

	sb = (struct sfi_table_simple *)table;
	if (!sfi_mrtc_num) {
		sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
						struct sfi_rtc_table_entry);
		pentry = (struct sfi_rtc_table_entry *)sb->pentry;
		totallen = sfi_mrtc_num * sizeof(*pentry);
		memcpy(sfi_mrtc_array, pentry, totallen);
	}

	printk(KERN_INFO "SFI: RTC info (num = %d):\n", sfi_mrtc_num);
	pentry = sfi_mrtc_array;
	for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
		printk(KERN_INFO "RTC[%d]: paddr = 0x%08x, irq = %d\n",
			totallen, (u32)pentry->phys_addr, pentry->irq);
		mp_irq.type = MP_IOAPIC;
		mp_irq.irqtype = mp_INT;
		mp_irq.irqflag = 0;
		mp_irq.srcbus = 0;
		mp_irq.srcbusirq = pentry->irq;	/* IRQ */
		mp_irq.dstapic = MP_APIC_ALL;
		mp_irq.dstirq = pentry->irq;
		save_mp_irq(&mp_irq);
	}
	return 0;
}

/*
 * the secondary clock in Moorestown can be APBT or LAPIC clock, default to
 * APBT but cmdline option can also override it.
 */
static void __cpuinit mrst_setup_secondary_clock(void)
{
	/* restore default lapic clock if disabled by cmdline */
	if (disable_apbt_percpu)
		return setup_secondary_APIC_clock();
	apbt_setup_secondary_clock();
}

static unsigned long __init mrst_calibrate_tsc(void)
{
	unsigned long flags, fast_calibrate;

	local_irq_save(flags);
	fast_calibrate = apbt_quick_calibrate();
	local_irq_restore(flags);

	if (fast_calibrate)
		return fast_calibrate;

	return 0;
}

void __init mrst_time_init(void)
{
	sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
	pre_init_apic_IRQ0();
	apbt_time_init();
}

void __init mrst_rtc_init(void)
{
	sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
}

/*
 * if we use per cpu apb timer, the bootclock already setup. if we use lapic
 * timer and one apbt timer for broadcast, we need to set up lapic boot clock.
 */
static void __init mrst_setup_boot_clock(void)
{
	pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
	if (disable_apbt_percpu)
		setup_boot_APIC_clock();
};

/* MID systems don't have i8042 controller */
static int mrst_i8042_detect(void)
{
	return 0;
}

/*
 * Moorestown specific x86_init function overrides and early setup
 * calls.
 */
void __init x86_mrst_early_setup(void)
{
	x86_init.resources.probe_roms = x86_init_noop;
	x86_init.resources.reserve_resources = x86_init_noop;

	x86_init.timers.timer_init = mrst_time_init;
	x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;

	x86_init.irqs.pre_vector_init = x86_init_noop;

	x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;

	x86_platform.calibrate_tsc = mrst_calibrate_tsc;
	x86_platform.i8042_detect = mrst_i8042_detect;
	x86_init.pci.init = pci_mrst_init;
	x86_init.pci.fixup_irqs = x86_init_noop;

	legacy_pic = &null_legacy_pic;

	/* Avoid searching for BIOS MP tables */
	x86_init.mpparse.find_smp_config = x86_init_noop;
	x86_init.mpparse.get_smp_config = x86_init_uint_noop;

}
Commit	Line	Data
3f4110a4 TG	1	/*
	2	* mrst.c: Intel Moorestown platform specific setup code
	3	*
	4	* (C) Copyright 2008 Intel Corporation
	5	* Author: Jacob Pan (jacob.jun.pan@intel.com)
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; version 2
	10	* of the License.
	11	*/
	12	#include <linux/init.h>
16ab5395 JP	13	#include <linux/kernel.h>
	14	#include <linux/sfi.h>
	15	#include <linux/irq.h>
cf089455	16	#include <linux/module.h>
3f4110a4 TG	17
3f4110a4 TG	18	#include <asm/setup.h>
16ab5395 JP	19	#include <asm/mpspec_def.h>
	20	#include <asm/hw_irq.h>
	21	#include <asm/apic.h>
	22	#include <asm/io_apic.h>
5b78b672 JP	23	#include <asm/mrst.h>
	24	#include <asm/io.h>
	25	#include <asm/i8259.h>
3746c6b6	26	#include <asm/apb_timer.h>
3f4110a4	27
16ab5395 JP	28	static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
	29	static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
	30	int sfi_mtimer_num;
	31
cf089455 FT	32	struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
	33	EXPORT_SYMBOL_GPL(sfi_mrtc_array);
	34	int sfi_mrtc_num;
	35
16ab5395 JP	36	static inline void assign_to_mp_irq(struct mpc_intsrc *m,
	37	struct mpc_intsrc *mp_irq)
	38	{
	39	memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
	40	}
	41
	42	static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
	43	struct mpc_intsrc *m)
	44	{
	45	return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
	46	}
	47
	48	static void save_mp_irq(struct mpc_intsrc *m)
	49	{
	50	int i;
	51
	52	for (i = 0; i < mp_irq_entries; i++) {
	53	if (!mp_irq_cmp(&mp_irqs[i], m))
	54	return;
	55	}
	56
	57	assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
	58	if (++mp_irq_entries == MAX_IRQ_SOURCES)
	59	panic("Max # of irq sources exceeded!!\n");
	60	}
	61
	62	/* parse all the mtimer info to a static mtimer array */
	63	static int __init sfi_parse_mtmr(struct sfi_table_header *table)
	64	{
	65	struct sfi_table_simple *sb;
	66	struct sfi_timer_table_entry *pentry;
	67	struct mpc_intsrc mp_irq;
	68	int totallen;
	69
	70	sb = (struct sfi_table_simple *)table;
	71	if (!sfi_mtimer_num) {
	72	sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
	73	struct sfi_timer_table_entry);
	74	pentry = (struct sfi_timer_table_entry *) sb->pentry;
	75	totallen = sfi_mtimer_num * sizeof(*pentry);
	76	memcpy(sfi_mtimer_array, pentry, totallen);
	77	}
	78
	79	printk(KERN_INFO "SFI: MTIMER info (num = %d):\n", sfi_mtimer_num);
	80	pentry = sfi_mtimer_array;
	81	for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
	82	printk(KERN_INFO "timer[%d]: paddr = 0x%08x, freq = %dHz,"
	83	" irq = %d\n", totallen, (u32)pentry->phys_addr,
	84	pentry->freq_hz, pentry->irq);
	85	if (!pentry->irq)
	86	continue;
	87	mp_irq.type = MP_IOAPIC;
	88	mp_irq.irqtype = mp_INT;
	89	/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
	90	mp_irq.irqflag = 5;
	91	mp_irq.srcbus = 0;
	92	mp_irq.srcbusirq = pentry->irq; /* IRQ */
	93	mp_irq.dstapic = MP_APIC_ALL;
	94	mp_irq.dstirq = pentry->irq;
	95	save_mp_irq(&mp_irq);
	96	}
	97
	98	return 0;
	99	}
100
101	struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
102	{
103	int i;
104	if (hint < sfi_mtimer_num) {
105	if (!sfi_mtimer_usage[hint]) {
106	pr_debug("hint taken for timer %d irq %d\n",\
107	hint, sfi_mtimer_array[hint].irq);
108	sfi_mtimer_usage[hint] = 1;
109	return &sfi_mtimer_array[hint];
110	}
111	}
112	/* take the first timer available */
113	for (i = 0; i < sfi_mtimer_num;) {
114	if (!sfi_mtimer_usage[i]) {
115	sfi_mtimer_usage[i] = 1;
116	return &sfi_mtimer_array[i];
117	}
118	i++;
119	}
120	return NULL;
121	}
122
123	void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
124	{
125	int i;
126	for (i = 0; i < sfi_mtimer_num;) {
127	if (mtmr->irq == sfi_mtimer_array[i].irq) {
128	sfi_mtimer_usage[i] = 0;
129	return;
130	}
131	i++;
132	}
133	}
134
cf089455 FT	135	/* parse all the mrtc info to a global mrtc array */
	136	int __init sfi_parse_mrtc(struct sfi_table_header *table)
	137	{
	138	struct sfi_table_simple *sb;
	139	struct sfi_rtc_table_entry *pentry;
	140	struct mpc_intsrc mp_irq;
	141
	142	int totallen;
	143
	144	sb = (struct sfi_table_simple *)table;
	145	if (!sfi_mrtc_num) {
	146	sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
	147	struct sfi_rtc_table_entry);
	148	pentry = (struct sfi_rtc_table_entry *)sb->pentry;
	149	totallen = sfi_mrtc_num * sizeof(*pentry);
	150	memcpy(sfi_mrtc_array, pentry, totallen);
	151	}
	152
	153	printk(KERN_INFO "SFI: RTC info (num = %d):\n", sfi_mrtc_num);
	154	pentry = sfi_mrtc_array;
	155	for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
	156	printk(KERN_INFO "RTC[%d]: paddr = 0x%08x, irq = %d\n",
	157	totallen, (u32)pentry->phys_addr, pentry->irq);
	158	mp_irq.type = MP_IOAPIC;
	159	mp_irq.irqtype = mp_INT;
	160	mp_irq.irqflag = 0;
	161	mp_irq.srcbus = 0;
	162	mp_irq.srcbusirq = pentry->irq; /* IRQ */
	163	mp_irq.dstapic = MP_APIC_ALL;
	164	mp_irq.dstirq = pentry->irq;
	165	save_mp_irq(&mp_irq);
	166	}
	167	return 0;
	168	}
	169
3746c6b6 JP	170	/*
	171	* the secondary clock in Moorestown can be APBT or LAPIC clock, default to
	172	* APBT but cmdline option can also override it.
	173	*/
	174	static void __cpuinit mrst_setup_secondary_clock(void)
	175	{
	176	/* restore default lapic clock if disabled by cmdline */
	177	if (disable_apbt_percpu)
	178	return setup_secondary_APIC_clock();
	179	apbt_setup_secondary_clock();
	180	}
	181
	182	static unsigned long __init mrst_calibrate_tsc(void)
	183	{
	184	unsigned long flags, fast_calibrate;
	185
	186	local_irq_save(flags);
	187	fast_calibrate = apbt_quick_calibrate();
	188	local_irq_restore(flags);
	189
	190	if (fast_calibrate)
	191	return fast_calibrate;
	192
	193	return 0;
	194	}
	195
	196	void __init mrst_time_init(void)
	197	{
	198	sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
	199	pre_init_apic_IRQ0();
	200	apbt_time_init();
	201	}
	202
cf089455 FT	203	void __init mrst_rtc_init(void)
	204	{
	205	sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
	206	}
	207
3746c6b6 JP	208	/*
	209	* if we use per cpu apb timer, the bootclock already setup. if we use lapic
	210	* timer and one apbt timer for broadcast, we need to set up lapic boot clock.
	211	*/
	212	static void __init mrst_setup_boot_clock(void)
	213	{
	214	pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
	215	if (disable_apbt_percpu)
	216	setup_boot_APIC_clock();
	217	};
	218
6d2cce62 FT	219	/* MID systems don't have i8042 controller */
	220	static int mrst_i8042_detect(void)
	221	{
	222	return 0;
	223	}
	224
3f4110a4 TG	225	/*
	226	* Moorestown specific x86_init function overrides and early setup
	227	* calls.
	228	*/
	229	void __init x86_mrst_early_setup(void)
	230	{
	231	x86_init.resources.probe_roms = x86_init_noop;
	232	x86_init.resources.reserve_resources = x86_init_noop;
5b78b672	233
3746c6b6 JP	234	x86_init.timers.timer_init = mrst_time_init;
	235	x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;
	236
	237	x86_init.irqs.pre_vector_init = x86_init_noop;
	238
	239	x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
	240
	241	x86_platform.calibrate_tsc = mrst_calibrate_tsc;
6d2cce62	242	x86_platform.i8042_detect = mrst_i8042_detect;
af2730f6 JP	243	x86_init.pci.init = pci_mrst_init;
	244	x86_init.pci.fixup_irqs = x86_init_noop;
	245
5b78b672	246	legacy_pic = &null_legacy_pic;
fea24e28 JP	247
	248	/* Avoid searching for BIOS MP tables */
	249	x86_init.mpparse.find_smp_config = x86_init_noop;
	250	x86_init.mpparse.get_smp_config = x86_init_uint_noop;
	251
3f4110a4	252	}