[net-next-2.6.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  This driver allows to upgrade microcode on AMD
 *  family 0x10 and 0x11 processors.
 *
 *  Licensed under the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/firmware.h>
#include <linux/pci_ids.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <asm/microcode.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

#define UCODE_MAGIC                0x00414d44
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
#define UCODE_UCODE_TYPE           0x00000001

struct equiv_cpu_entry {
	u32	installed_cpu;
	u32	fixed_errata_mask;
	u32	fixed_errata_compare;
	u16	equiv_cpu;
	u16	res;
} __attribute__((packed));

struct microcode_header_amd {
	u32	data_code;
	u32	patch_id;
	u16	mc_patch_data_id;
	u8	mc_patch_data_len;
	u8	init_flag;
	u32	mc_patch_data_checksum;
	u32	nb_dev_id;
	u32	sb_dev_id;
	u16	processor_rev_id;
	u8	nb_rev_id;
	u8	sb_rev_id;
	u8	bios_api_rev;
	u8	reserved1[3];
	u32	match_reg[8];
} __attribute__((packed));

struct microcode_amd {
	struct microcode_header_amd	hdr;
	unsigned int			mpb[0];
};

#define UCODE_MAX_SIZE			2048
#define UCODE_CONTAINER_SECTION_HDR	8
#define UCODE_CONTAINER_HEADER_SIZE	12

static struct equiv_cpu_entry *equiv_cpu_table;

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	u32 dummy;

	memset(csig, 0, sizeof(*csig));
	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		pr_warning("microcode: CPU%d: AMD CPU family 0x%x not "
			   "supported\n", cpu, c->x86);
		return -1;
	}
	rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
	pr_info("CPU%d: patch_level=0x%x\n", cpu, csig->rev);
	return 0;
}

static int get_matching_microcode(int cpu, void *mc, int rev)
{
	struct microcode_header_amd *mc_header = mc;
	unsigned int current_cpu_id;
	u16 equiv_cpu_id = 0;
	unsigned int i = 0;

	BUG_ON(equiv_cpu_table == NULL);
	current_cpu_id = cpuid_eax(0x00000001);

	while (equiv_cpu_table[i].installed_cpu != 0) {
		if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
			equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
			break;
		}
		i++;
	}

	if (!equiv_cpu_id)
		return 0;

	if (mc_header->processor_rev_id != equiv_cpu_id)
		return 0;

	/* ucode might be chipset specific -- currently we don't support this */
	if (mc_header->nb_dev_id || mc_header->sb_dev_id) {
		pr_err("CPU%d: loading of chipset specific code not yet supported\n",
		       cpu);
		return 0;
	}

	if (mc_header->patch_id <= rev)
		return 0;

	return 1;
}

static int apply_microcode_amd(int cpu)
{
	u32 rev, dummy;
	int cpu_num = raw_smp_processor_id();
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
	struct microcode_amd *mc_amd = uci->mc;

	/* We should bind the task to the CPU */
	BUG_ON(cpu_num != cpu);

	if (mc_amd == NULL)
		return 0;

	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
	/* get patch id after patching */
	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	/* check current patch id and patch's id for match */
	if (rev != mc_amd->hdr.patch_id) {
		pr_err("CPU%d: update failed (for patch_level=0x%x)\n",
		       cpu, mc_amd->hdr.patch_id);
		return -1;
	}

	pr_info("CPU%d: updated (new patch_level=0x%x)\n", cpu, rev);
	uci->cpu_sig.rev = rev;

	return 0;
}

static int get_ucode_data(void *to, const u8 *from, size_t n)
{
	memcpy(to, from, n);
	return 0;
}

static void *
get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size)
{
	unsigned int total_size;
	u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
	void *mc;

	if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
		return NULL;

	if (section_hdr[0] != UCODE_UCODE_TYPE) {
		pr_err("error: invalid type field in container file section header\n");
		return NULL;
	}

	total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8));

	if (total_size > size || total_size > UCODE_MAX_SIZE) {
		pr_err("error: size mismatch\n");
		return NULL;
	}

	mc = vmalloc(UCODE_MAX_SIZE);
	if (mc) {
		memset(mc, 0, UCODE_MAX_SIZE);
		if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR,
				   total_size)) {
			vfree(mc);
			mc = NULL;
		} else
			*mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
	}
	return mc;
}

static int install_equiv_cpu_table(const u8 *buf)
{
	u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE];
	unsigned int *buf_pos = (unsigned int *)container_hdr;
	unsigned long size;

	if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
		return 0;

	size = buf_pos[2];

	if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		pr_err("error: invalid type field in container file section header\n");
		return 0;
	}

	equiv_cpu_table = vmalloc(size);
	if (!equiv_cpu_table) {
		pr_err("failed to allocate equivalent CPU table\n");
		return 0;
	}

	buf += UCODE_CONTAINER_HEADER_SIZE;
	if (get_ucode_data(equiv_cpu_table, buf, size)) {
		vfree(equiv_cpu_table);
		return 0;
	}

	return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
}

static void free_equiv_cpu_table(void)
{
	vfree(equiv_cpu_table);
	equiv_cpu_table = NULL;
}

static enum ucode_state
generic_load_microcode(int cpu, const u8 *data, size_t size)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	const u8 *ucode_ptr = data;
	void *new_mc = NULL;
	void *mc;
	int new_rev = uci->cpu_sig.rev;
	unsigned int leftover;
	unsigned long offset;
	enum ucode_state state = UCODE_OK;

	offset = install_equiv_cpu_table(ucode_ptr);
	if (!offset) {
		pr_err("failed to create equivalent cpu table\n");
		return UCODE_ERROR;
	}

	ucode_ptr += offset;
	leftover = size - offset;

	while (leftover) {
		unsigned int uninitialized_var(mc_size);
		struct microcode_header_amd *mc_header;

		mc = get_next_ucode(ucode_ptr, leftover, &mc_size);
		if (!mc)
			break;

		mc_header = (struct microcode_header_amd *)mc;
		if (get_matching_microcode(cpu, mc, new_rev)) {
			vfree(new_mc);
			new_rev = mc_header->patch_id;
			new_mc  = mc;
		} else
			vfree(mc);

		ucode_ptr += mc_size;
		leftover  -= mc_size;
	}

	if (new_mc) {
		if (!leftover) {
			vfree(uci->mc);
			uci->mc = new_mc;
			pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
				 cpu, new_rev, uci->cpu_sig.rev);
		} else {
			vfree(new_mc);
			state = UCODE_ERROR;
		}
	} else
		state = UCODE_NFOUND;

	free_equiv_cpu_table();

	return state;
}

static enum ucode_state request_microcode_fw(int cpu, struct device *device)
{
	const char *fw_name = "amd-ucode/microcode_amd.bin";
	const struct firmware *firmware;
	enum ucode_state ret;

	if (request_firmware(&firmware, fw_name, device)) {
		printk(KERN_ERR "microcode: failed to load file %s\n", fw_name);
		return UCODE_NFOUND;
	}

	if (*(u32 *)firmware->data != UCODE_MAGIC) {
		pr_err("invalid UCODE_MAGIC (0x%08x)\n",
		       *(u32 *)firmware->data);
		return UCODE_ERROR;
	}

	ret = generic_load_microcode(cpu, firmware->data, firmware->size);

	release_firmware(firmware);

	return ret;
}

static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
	return UCODE_ERROR;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	vfree(uci->mc);
	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_fw,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	return &microcode_amd_ops;
}
Commit	Line	Data
80cc9f10 PO	1	/*
	2	* AMD CPU Microcode Update Driver for Linux
	3	* Copyright (C) 2008 Advanced Micro Devices Inc.
	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
	10	* This driver allows to upgrade microcode on AMD
	11	* family 0x10 and 0x11 processors.
	12	*
2a3282a7	13	* Licensed under the terms of the GNU General Public
80cc9f10	14	* License version 2. See file COPYING for details.
4bae1967	15	*/
f58e1f53 JP	16
	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	18
4bae1967	19	#include <linux/firmware.h>
4bae1967 IM	20	#include <linux/pci_ids.h>
	21	#include <linux/uaccess.h>
	22	#include <linux/vmalloc.h>
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
80cc9f10	25	#include <linux/pci.h>
80cc9f10	26
80cc9f10	27	#include <asm/microcode.h>
4bae1967 IM	28	#include <asm/processor.h>
4bae1967 IM	29	#include <asm/msr.h>
80cc9f10 PO	30
80cc9f10 PO	31	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	32	MODULE_AUTHOR("Peter Oruba");
5d7b6052	33	MODULE_LICENSE("GPL v2");
80cc9f10 PO	34
	35	#define UCODE_MAGIC 0x00414d44
	36	#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
	37	#define UCODE_UCODE_TYPE 0x00000001
	38
18dbc916	39	struct equiv_cpu_entry {
5549b94b AH	40	u32 installed_cpu;
	41	u32 fixed_errata_mask;
	42	u32 fixed_errata_compare;
	43	u16 equiv_cpu;
	44	u16 res;
	45	} __attribute__((packed));
18dbc916 DA	46
18dbc916 DA	47	struct microcode_header_amd {
5549b94b AH	48	u32 data_code;
	49	u32 patch_id;
	50	u16 mc_patch_data_id;
	51	u8 mc_patch_data_len;
	52	u8 init_flag;
	53	u32 mc_patch_data_checksum;
	54	u32 nb_dev_id;
	55	u32 sb_dev_id;
	56	u16 processor_rev_id;
	57	u8 nb_rev_id;
	58	u8 sb_rev_id;
	59	u8 bios_api_rev;
	60	u8 reserved1[3];
	61	u32 match_reg[8];
	62	} __attribute__((packed));
18dbc916 DA	63
18dbc916 DA	64	struct microcode_amd {
4bae1967 IM	65	struct microcode_header_amd hdr;
4bae1967 IM	66	unsigned int mpb[0];
18dbc916 DA	67	};
18dbc916 DA	68
6cc9b6d9 AH	69	#define UCODE_MAX_SIZE 2048
	70	#define UCODE_CONTAINER_SECTION_HDR 8
	71	#define UCODE_CONTAINER_HEADER_SIZE 12
80cc9f10	72
a0a29b62	73	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	74
d45de409	75	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10	76	{
3b2e3d85	77	struct cpuinfo_x86 *c = &cpu_data(cpu);
29d0887f	78	u32 dummy;
80cc9f10	79
8cc2361b	80	memset(csig, 0, sizeof(*csig));
3b2e3d85 AH	81	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
	82	pr_warning("microcode: CPU%d: AMD CPU family 0x%x not "
	83	"supported\n", cpu, c->x86);
	84	return -1;
	85	}
29d0887f	86	rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
f58e1f53	87	pr_info("CPU%d: patch_level=0x%x\n", cpu, csig->rev);
d45de409	88	return 0;
80cc9f10 PO	89	}
80cc9f10 PO	90
a0a29b62	91	static int get_matching_microcode(int cpu, void *mc, int rev)
80cc9f10	92	{
80cc9f10	93	struct microcode_header_amd *mc_header = mc;
80cc9f10	94	unsigned int current_cpu_id;
5549b94b	95	u16 equiv_cpu_id = 0;
80cc9f10 PO	96	unsigned int i = 0;
80cc9f10 PO	97
a0a29b62	98	BUG_ON(equiv_cpu_table == NULL);
80cc9f10 PO	99	current_cpu_id = cpuid_eax(0x00000001);
	100
	101	while (equiv_cpu_table[i].installed_cpu != 0) {
	102	if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
5549b94b	103	equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
80cc9f10 PO	104	break;
	105	}
	106	i++;
	107	}
	108
14c56942	109	if (!equiv_cpu_id)
80cc9f10	110	return 0;
80cc9f10	111
6e18da75	112	if (mc_header->processor_rev_id != equiv_cpu_id)
80cc9f10	113	return 0;
80cc9f10	114
98415301 AH	115	/* ucode might be chipset specific -- currently we don't support this */
98415301 AH	116	if (mc_header->nb_dev_id \|\| mc_header->sb_dev_id) {
f58e1f53 JP	117	pr_err("CPU%d: loading of chipset specific code not yet supported\n",
f58e1f53 JP	118	cpu);
98415301	119	return 0;
80cc9f10 PO	120	}
80cc9f10 PO	121
a0a29b62	122	if (mc_header->patch_id <= rev)
80cc9f10 PO	123	return 0;
80cc9f10 PO	124
80cc9f10 PO	125	return 1;
	126	}
	127
871b72dd	128	static int apply_microcode_amd(int cpu)
80cc9f10	129	{
29d0887f	130	u32 rev, dummy;
80cc9f10 PO	131	int cpu_num = raw_smp_processor_id();
80cc9f10 PO	132	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
18dbc916	133	struct microcode_amd *mc_amd = uci->mc;
80cc9f10 PO	134
	135	/* We should bind the task to the CPU */
	136	BUG_ON(cpu_num != cpu);
	137
18dbc916	138	if (mc_amd == NULL)
871b72dd	139	return 0;
80cc9f10	140
f34a10bd	141	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
80cc9f10	142	/* get patch id after patching */
29d0887f	143	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
80cc9f10 PO	144
80cc9f10 PO	145	/* check current patch id and patch's id for match */
18dbc916	146	if (rev != mc_amd->hdr.patch_id) {
f58e1f53 JP	147	pr_err("CPU%d: update failed (for patch_level=0x%x)\n",
f58e1f53 JP	148	cpu, mc_amd->hdr.patch_id);
871b72dd	149	return -1;
80cc9f10 PO	150	}
80cc9f10 PO	151
f58e1f53	152	pr_info("CPU%d: updated (new patch_level=0x%x)\n", cpu, rev);
d45de409	153	uci->cpu_sig.rev = rev;
871b72dd DA	154
871b72dd DA	155	return 0;
80cc9f10 PO	156	}
80cc9f10 PO	157
0657d9eb AH	158	static int get_ucode_data(void to, const u8 from, size_t n)
	159	{
	160	memcpy(to, from, n);
	161	return 0;
	162	}
	163
4bae1967 IM	164	static void *
4bae1967 IM	165	get_next_ucode(const u8 buf, unsigned int size, unsigned int mc_size)
80cc9f10	166	{
a0a29b62	167	unsigned int total_size;
d4738792	168	u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
a0a29b62	169	void *mc;
80cc9f10	170
d4738792	171	if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
a0a29b62	172	return NULL;
80cc9f10	173
d4738792	174	if (section_hdr[0] != UCODE_UCODE_TYPE) {
f58e1f53	175	pr_err("error: invalid type field in container file section header\n");
a0a29b62	176	return NULL;
80cc9f10 PO	177	}
80cc9f10 PO	178
d4738792	179	total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8));
80cc9f10	180
a0a29b62	181	if (total_size > size \|\| total_size > UCODE_MAX_SIZE) {
f58e1f53	182	pr_err("error: size mismatch\n");
a0a29b62	183	return NULL;
80cc9f10 PO	184	}
80cc9f10 PO	185
a0a29b62 DA	186	mc = vmalloc(UCODE_MAX_SIZE);
	187	if (mc) {
	188	memset(mc, 0, UCODE_MAX_SIZE);
be957763 AH	189	if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR,
be957763 AH	190	total_size)) {
a0a29b62 DA	191	vfree(mc);
	192	mc = NULL;
	193	} else
d4738792	194	*mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
80cc9f10	195	}
a0a29b62	196	return mc;
80cc9f10 PO	197	}
80cc9f10 PO	198
0657d9eb	199	static int install_equiv_cpu_table(const u8 *buf)
80cc9f10	200	{
b6cffde1 PO	201	u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE];
b6cffde1 PO	202	unsigned int buf_pos = (unsigned int )container_hdr;
a0a29b62	203	unsigned long size;
80cc9f10	204
b6cffde1	205	if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
80cc9f10 PO	206	return 0;
80cc9f10 PO	207
a0a29b62	208	size = buf_pos[2];
80cc9f10	209
a0a29b62	210	if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
f58e1f53	211	pr_err("error: invalid type field in container file section header\n");
80cc9f10 PO	212	return 0;
	213	}
	214
8e5e9521	215	equiv_cpu_table = vmalloc(size);
80cc9f10	216	if (!equiv_cpu_table) {
f58e1f53	217	pr_err("failed to allocate equivalent CPU table\n");
80cc9f10 PO	218	return 0;
	219	}
	220
b6cffde1	221	buf += UCODE_CONTAINER_HEADER_SIZE;
a0a29b62 DA	222	if (get_ucode_data(equiv_cpu_table, buf, size)) {
	223	vfree(equiv_cpu_table);
	224	return 0;
	225	}
80cc9f10	226
b6cffde1	227	return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
80cc9f10 PO	228	}
80cc9f10 PO	229
a0a29b62	230	static void free_equiv_cpu_table(void)
80cc9f10	231	{
aeef50bc F	232	vfree(equiv_cpu_table);
aeef50bc F	233	equiv_cpu_table = NULL;
a0a29b62	234	}
80cc9f10	235
871b72dd DA	236	static enum ucode_state
871b72dd DA	237	generic_load_microcode(int cpu, const u8 *data, size_t size)
a0a29b62 DA	238	{
a0a29b62 DA	239	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
8c135206 AH	240	const u8 *ucode_ptr = data;
	241	void *new_mc = NULL;
	242	void *mc;
a0a29b62 DA	243	int new_rev = uci->cpu_sig.rev;
	244	unsigned int leftover;
	245	unsigned long offset;
871b72dd	246	enum ucode_state state = UCODE_OK;
80cc9f10	247
0657d9eb	248	offset = install_equiv_cpu_table(ucode_ptr);
80cc9f10	249	if (!offset) {
f58e1f53	250	pr_err("failed to create equivalent cpu table\n");
871b72dd	251	return UCODE_ERROR;
80cc9f10 PO	252	}
80cc9f10 PO	253
a0a29b62 DA	254	ucode_ptr += offset;
	255	leftover = size - offset;
	256
	257	while (leftover) {
2f9284e4	258	unsigned int uninitialized_var(mc_size);
a0a29b62 DA	259	struct microcode_header_amd *mc_header;
a0a29b62 DA	260
0657d9eb	261	mc = get_next_ucode(ucode_ptr, leftover, &mc_size);
a0a29b62	262	if (!mc)
80cc9f10	263	break;
a0a29b62 DA	264
	265	mc_header = (struct microcode_header_amd *)mc;
	266	if (get_matching_microcode(cpu, mc, new_rev)) {
aeef50bc	267	vfree(new_mc);
a0a29b62 DA	268	new_rev = mc_header->patch_id;
a0a29b62 DA	269	new_mc = mc;
be957763	270	} else
a0a29b62 DA	271	vfree(mc);
	272
	273	ucode_ptr += mc_size;
	274	leftover -= mc_size;
80cc9f10	275	}
a0a29b62 DA	276
	277	if (new_mc) {
	278	if (!leftover) {
aeef50bc	279	vfree(uci->mc);
18dbc916	280	uci->mc = new_mc;
f58e1f53	281	pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
be957763	282	cpu, new_rev, uci->cpu_sig.rev);
871b72dd	283	} else {
a0a29b62	284	vfree(new_mc);
871b72dd DA	285	state = UCODE_ERROR;
	286	}
	287	} else
	288	state = UCODE_NFOUND;
a0a29b62 DA	289
	290	free_equiv_cpu_table();
	291
871b72dd	292	return state;
a0a29b62 DA	293	}
a0a29b62 DA	294
871b72dd	295	static enum ucode_state request_microcode_fw(int cpu, struct device *device)
a0a29b62	296	{
3b2e3d85 AH	297	const char *fw_name = "amd-ucode/microcode_amd.bin";
3b2e3d85 AH	298	const struct firmware *firmware;
871b72dd	299	enum ucode_state ret;
a0a29b62	300
3b2e3d85 AH	301	if (request_firmware(&firmware, fw_name, device)) {
3b2e3d85 AH	302	printk(KERN_ERR "microcode: failed to load file %s\n", fw_name);
871b72dd	303	return UCODE_NFOUND;
3b2e3d85	304	}
a0a29b62	305
506f90ee	306	if ((u32 )firmware->data != UCODE_MAGIC) {
f58e1f53	307	pr_err("invalid UCODE_MAGIC (0x%08x)\n",
506f90ee BP	308	(u32 )firmware->data);
	309	return UCODE_ERROR;
	310	}
	311
0657d9eb	312	ret = generic_load_microcode(cpu, firmware->data, firmware->size);
a0a29b62	313
3b2e3d85 AH	314	release_firmware(firmware);
3b2e3d85 AH	315
a0a29b62 DA	316	return ret;
	317	}
	318
871b72dd DA	319	static enum ucode_state
871b72dd DA	320	request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62	321	{
f58e1f53	322	pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
871b72dd	323	return UCODE_ERROR;
80cc9f10 PO	324	}
80cc9f10 PO	325
80cc9f10 PO	326	static void microcode_fini_cpu_amd(int cpu)
	327	{
	328	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	329
18dbc916 DA	330	vfree(uci->mc);
18dbc916 DA	331	uci->mc = NULL;
80cc9f10 PO	332	}
	333
	334	static struct microcode_ops microcode_amd_ops = {
a0a29b62 DA	335	.request_microcode_user = request_microcode_user,
a0a29b62 DA	336	.request_microcode_fw = request_microcode_fw,
80cc9f10 PO	337	.collect_cpu_info = collect_cpu_info_amd,
	338	.apply_microcode = apply_microcode_amd,
	339	.microcode_fini_cpu = microcode_fini_cpu_amd,
	340	};
	341
18dbc916	342	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	343	{
18dbc916	344	return &microcode_amd_ops;
80cc9f10	345	}