[net-next-2.6.git] / arch / x86 / kernel / i8259.c

#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/i8259.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 */

static int i8259A_auto_eoi;
DEFINE_RAW_SPINLOCK(i8259A_lock);
static void mask_and_ack_8259A(unsigned int);

struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.mask		= disable_8259A_irq,
	.disable	= disable_8259A_irq,
	.unmask		= enable_8259A_irq,
	.mask_ack	= mask_and_ack_8259A,
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

void disable_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

void enable_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
				      "XT");
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(unsigned int irq)
{
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		/* 'Specific EOI' to slave */
		outb(0x60+(irq&7), PIC_SLAVE_CMD);
		 /* 'Specific EOI' to master-IRQ2 */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG
			       "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static int i8259A_resume(struct sys_device *dev)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
	return 0;
}

static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
{
	save_ELCR(irq_trigger);
	return 0;
}

static int i8259A_shutdown(struct sys_device *dev)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-1 */
	return 0;
}

static struct sysdev_class i8259_sysdev_class = {
	.name = "i8259",
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static struct sys_device device_i8259A = {
	.id	= 0,
	.cls	= &i8259_sysdev_class,
};

static int __init i8259A_init_sysfs(void)
{
	int error = sysdev_class_register(&i8259_sysdev_class);
	if (!error)
		error = sysdev_register(&device_i8259A);
	return error;
}

device_initcall(i8259A_init_sysfs);

void mask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

void unmask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_pic - this has to work on a wide range of PC hardware.
	 */
	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
	   to 0x20-0x27 on i386 */
	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);

	/* 8259A-1 (the master) has a slave on IR2 */
	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);

	if (auto_eoi)	/* master does Auto EOI */
		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
	/* 8259A-2 is a slave on master's IR2 */
	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	/* (slave's support for AEOI in flat mode is to be investigated) */
	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);

	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.mask_ack = disable_8259A_irq;
	else
		i8259A_chip.mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}
Commit	Line	Data
21fd5132	1	#include <linux/linkage.h>
21fd5132 PM	2	#include <linux/errno.h>
	3	#include <linux/signal.h>
	4	#include <linux/sched.h>
	5	#include <linux/ioport.h>
	6	#include <linux/interrupt.h>
21fd5132	7	#include <linux/timex.h>
21fd5132 PM	8	#include <linux/slab.h>
	9	#include <linux/random.h>
	10	#include <linux/init.h>
	11	#include <linux/kernel_stat.h>
	12	#include <linux/sysdev.h>
	13	#include <linux/bitops.h>
7bafaf30 JSR	14	#include <linux/acpi.h>
	15	#include <linux/io.h>
	16	#include <linux/delay.h>
21fd5132	17
21fd5132 PM	18	#include <asm/atomic.h>
21fd5132 PM	19	#include <asm/system.h>
21fd5132	20	#include <asm/timer.h>
21fd5132	21	#include <asm/hw_irq.h>
21fd5132	22	#include <asm/pgtable.h>
21fd5132 PM	23	#include <asm/desc.h>
21fd5132 PM	24	#include <asm/apic.h>
21fd5132 PM	25	#include <asm/i8259.h>
	26
	27	/*
	28	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	29	* present in the majority of PC/AT boxes.
	30	* plus some generic x86 specific things if generic specifics makes
	31	* any sense at all.
	32	*/
	33
	34	static int i8259A_auto_eoi;
5619c280	35	DEFINE_RAW_SPINLOCK(i8259A_lock);
21fd5132 PM	36	static void mask_and_ack_8259A(unsigned int);
	37
	38	struct irq_chip i8259A_chip = {
	39	.name = "XT-PIC",
	40	.mask = disable_8259A_irq,
	41	.disable = disable_8259A_irq,
	42	.unmask = enable_8259A_irq,
	43	.mask_ack = mask_and_ack_8259A,
	44	};
	45
	46	/*
	47	* 8259A PIC functions to handle ISA devices:
	48	*/
	49
	50	/*
	51	* This contains the irq mask for both 8259A irq controllers,
	52	*/
	53	unsigned int cached_irq_mask = 0xffff;
	54
	55	/*
	56	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	57	* boards the timer interrupt is not really connected to any IO-APIC pin,
	58	* it's fed to the master 8259A's IR0 line only.
	59	*
	60	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	61	* this 'mixed mode' IRQ handling costs nothing because it's only used
	62	* at IRQ setup time.
	63	*/
	64	unsigned long io_apic_irqs;
	65
	66	void disable_8259A_irq(unsigned int irq)
	67	{
	68	unsigned int mask = 1 << irq;
	69	unsigned long flags;
	70
5619c280	71	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	72	cached_irq_mask \|= mask;
	73	if (irq & 8)
	74	outb(cached_slave_mask, PIC_SLAVE_IMR);
	75	else
	76	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	77	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	78	}
	79
	80	void enable_8259A_irq(unsigned int irq)
	81	{
	82	unsigned int mask = ~(1 << irq);
	83	unsigned long flags;
	84
5619c280	85	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	86	cached_irq_mask &= mask;
	87	if (irq & 8)
	88	outb(cached_slave_mask, PIC_SLAVE_IMR);
	89	else
	90	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	91	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	92	}
	93
	94	int i8259A_irq_pending(unsigned int irq)
	95	{
	96	unsigned int mask = 1<<irq;
	97	unsigned long flags;
	98	int ret;
	99
5619c280	100	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	101	if (irq < 8)
	102	ret = inb(PIC_MASTER_CMD) & mask;
	103	else
	104	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
5619c280	105	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	106
	107	return ret;
	108	}
	109
	110	void make_8259A_irq(unsigned int irq)
	111	{
	112	disable_irq_nosync(irq);
	113	io_apic_irqs &= ~(1<<irq);
	114	set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
	115	"XT");
	116	enable_irq(irq);
	117	}
	118
	119	/*
	120	* This function assumes to be called rarely. Switching between
	121	* 8259A registers is slow.
	122	* This has to be protected by the irq controller spinlock
	123	* before being called.
	124	*/
	125	static inline int i8259A_irq_real(unsigned int irq)
	126	{
	127	int value;
	128	int irqmask = 1<<irq;
	129
	130	if (irq < 8) {
680afbf9	131	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
21fd5132	132	value = inb(PIC_MASTER_CMD) & irqmask;
680afbf9	133	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
21fd5132 PM	134	return value;
21fd5132 PM	135	}
680afbf9	136	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
21fd5132	137	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
680afbf9	138	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
21fd5132 PM	139	return value;
	140	}
	141
	142	/*
	143	* Careful! The 8259A is a fragile beast, it pretty
	144	* much _has_ to be done exactly like this (mask it
	145	* first, _then_ send the EOI, and the order of EOI
	146	* to the two 8259s is important!
	147	*/
	148	static void mask_and_ack_8259A(unsigned int irq)
	149	{
	150	unsigned int irqmask = 1 << irq;
	151	unsigned long flags;
	152
5619c280	153	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	154	/*
	155	* Lightweight spurious IRQ detection. We do not want
	156	* to overdo spurious IRQ handling - it's usually a sign
	157	* of hardware problems, so we only do the checks we can
	158	* do without slowing down good hardware unnecessarily.
	159	*
	160	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	161	* usually resulting from the 8259A-1\|2 PICs) occur
	162	* even if the IRQ is masked in the 8259A. Thus we
	163	* can check spurious 8259A IRQs without doing the
	164	* quite slow i8259A_irq_real() call for every IRQ.
	165	* This does not cover 100% of spurious interrupts,
	166	* but should be enough to warn the user that there
	167	* is something bad going on ...
	168	*/
	169	if (cached_irq_mask & irqmask)
	170	goto spurious_8259A_irq;
	171	cached_irq_mask \|= irqmask;
	172
	173	handle_real_irq:
	174	if (irq & 8) {
	175	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	176	outb(cached_slave_mask, PIC_SLAVE_IMR);
21fd5132	177	/* 'Specific EOI' to slave */
3e8631d2	178	outb(0x60+(irq&7), PIC_SLAVE_CMD);
21fd5132	179	/* 'Specific EOI' to master-IRQ2 */
3e8631d2	180	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
21fd5132 PM	181	} else {
	182	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	183	outb(cached_master_mask, PIC_MASTER_IMR);
3e8631d2	184	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
21fd5132	185	}
5619c280	186	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	187	return;
	188
	189	spurious_8259A_irq:
	190	/*
	191	* this is the slow path - should happen rarely.
	192	*/
	193	if (i8259A_irq_real(irq))
	194	/*
	195	* oops, the IRQ _is_ in service according to the
	196	* 8259A - not spurious, go handle it.
	197	*/
	198	goto handle_real_irq;
	199
	200	{
	201	static int spurious_irq_mask;
	202	/*
	203	* At this point we can be sure the IRQ is spurious,
	204	* lets ACK and report it. [once per IRQ]
	205	*/
	206	if (!(spurious_irq_mask & irqmask)) {
21fd5132 PM	207	printk(KERN_DEBUG
21fd5132 PM	208	"spurious 8259A interrupt: IRQ%d.\n", irq);
21fd5132 PM	209	spurious_irq_mask \|= irqmask;
	210	}
	211	atomic_inc(&irq_err_count);
	212	/*
	213	* Theoretically we do not have to handle this IRQ,
	214	* but in Linux this does not cause problems and is
	215	* simpler for us.
	216	*/
	217	goto handle_real_irq;
	218	}
	219	}
	220
	221	static char irq_trigger[2];
	222	/**
	223	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	224	*/
	225	static void restore_ELCR(char *trigger)
	226	{
	227	outb(trigger[0], 0x4d0);
	228	outb(trigger[1], 0x4d1);
	229	}
	230
	231	static void save_ELCR(char *trigger)
	232	{
	233	/* IRQ 0,1,2,8,13 are marked as reserved */
	234	trigger[0] = inb(0x4d0) & 0xF8;
	235	trigger[1] = inb(0x4d1) & 0xDE;
	236	}
	237
	238	static int i8259A_resume(struct sys_device *dev)
	239	{
	240	init_8259A(i8259A_auto_eoi);
	241	restore_ELCR(irq_trigger);
	242	return 0;
	243	}
	244
	245	static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
	246	{
	247	save_ELCR(irq_trigger);
	248	return 0;
	249	}
	250
	251	static int i8259A_shutdown(struct sys_device *dev)
	252	{
	253	/* Put the i8259A into a quiescent state that
	254	* the kernel initialization code can get it
	255	* out of.
	256	*/
	257	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	258	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
	259	return 0;
	260	}
	261
	262	static struct sysdev_class i8259_sysdev_class = {
	263	.name = "i8259",
	264	.suspend = i8259A_suspend,
	265	.resume = i8259A_resume,
	266	.shutdown = i8259A_shutdown,
	267	};
	268
	269	static struct sys_device device_i8259A = {
	270	.id = 0,
	271	.cls = &i8259_sysdev_class,
	272	};
273
274	static int __init i8259A_init_sysfs(void)
275	{
276	int error = sysdev_class_register(&i8259_sysdev_class);
277	if (!error)
278	error = sysdev_register(&device_i8259A);
279	return error;
280	}
281
282	device_initcall(i8259A_init_sysfs);
283
d94d93ca SS	284	void mask_8259A(void)
	285	{
	286	unsigned long flags;
	287
5619c280	288	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	289
	290	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	291	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	292
5619c280	293	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	294	}
	295
	296	void unmask_8259A(void)
	297	{
	298	unsigned long flags;
	299
5619c280	300	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	301
	302	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	303	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	304
5619c280	305	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	306	}
d94d93ca SS	307
21fd5132 PM	308	void init_8259A(int auto_eoi)
	309	{
	310	unsigned long flags;
	311
	312	i8259A_auto_eoi = auto_eoi;
	313
5619c280	314	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	315
	316	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	317	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	318
	319	/*
	320	* outb_pic - this has to work on a wide range of PC hardware.
	321	*/
	322	outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
c46e62f7 PM	323
c46e62f7 PM	324	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
7bafaf30	325	to 0x20-0x27 on i386 */
21fd5132	326	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
c46e62f7	327
21fd5132	328	/* 8259A-1 (the master) has a slave on IR2 */
c46e62f7 PM	329	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
c46e62f7 PM	330
21fd5132 PM	331	if (auto_eoi) /* master does Auto EOI */
	332	outb_pic(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	333	else /* master expects normal EOI */
	334	outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	335
	336	outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
c46e62f7 PM	337
c46e62f7 PM	338	/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
21fd5132 PM	339	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
	340	/* 8259A-2 is a slave on master's IR2 */
	341	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	342	/* (slave's support for AEOI in flat mode is to be investigated) */
	343	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
	344
21fd5132 PM	345	if (auto_eoi)
	346	/*
	347	* In AEOI mode we just have to mask the interrupt
	348	* when acking.
	349	*/
	350	i8259A_chip.mask_ack = disable_8259A_irq;
	351	else
	352	i8259A_chip.mask_ack = mask_and_ack_8259A;
	353
	354	udelay(100); /* wait for 8259A to initialize */
	355
	356	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	357	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	358
5619c280	359	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132	360	}