[net-next-2.6.git] / arch / x86 / kernel / genx2apic_uv_x.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV APIC functions (note: not an Intel compatible APIC)
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <asm/smp.h>
#include <asm/ipi.h>
#include <asm/genapic.h>
#include <asm/pgtable.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/bios.h>

DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);

struct uv_blade_info *uv_blade_info;
EXPORT_SYMBOL_GPL(uv_blade_info);

short *uv_node_to_blade;
EXPORT_SYMBOL_GPL(uv_node_to_blade);

short *uv_cpu_to_blade;
EXPORT_SYMBOL_GPL(uv_cpu_to_blade);

short uv_possible_blades;
EXPORT_SYMBOL_GPL(uv_possible_blades);

unsigned long sn_rtc_cycles_per_second;
EXPORT_SYMBOL(sn_rtc_cycles_per_second);

/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */

static cpumask_t uv_target_cpus(void)
{
	return cpumask_of_cpu(0);
}

static cpumask_t uv_vector_allocation_domain(int cpu)
{
	cpumask_t domain = CPU_MASK_NONE;
	cpu_set(cpu, domain);
	return domain;
}

int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
{
	unsigned long val;
	int pnode;

	pnode = uv_apicid_to_pnode(phys_apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_INIT;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	mdelay(10);

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_STARTUP;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	return 0;
}

static void uv_send_IPI_one(int cpu, int vector)
{
	unsigned long val, apicid, lapicid;
	int pnode;

	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
	lapicid = apicid & 0x3f;		/* ZZZ macro needed */
	pnode = uv_apicid_to_pnode(apicid);
	val =
	    (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
					      UVH_IPI_INT_APIC_ID_SHFT) |
	    (vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

static void uv_send_IPI_mask(cpumask_t mask, int vector)
{
	unsigned int cpu;

	for_each_possible_cpu(cpu)
		if (cpu_isset(cpu, mask))
			uv_send_IPI_one(cpu, vector);
}

static void uv_send_IPI_allbutself(int vector)
{
	cpumask_t mask = cpu_online_map;

	cpu_clear(smp_processor_id(), mask);

	if (!cpus_empty(mask))
		uv_send_IPI_mask(mask, vector);
}

static void uv_send_IPI_all(int vector)
{
	uv_send_IPI_mask(cpu_online_map, vector);
}

static int uv_apic_id_registered(void)
{
	return 1;
}

static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;

	/*
	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
	 * May as well be the first.
	 */
	cpu = first_cpu(cpumask);
	if ((unsigned)cpu < nr_cpu_ids)
		return per_cpu(x86_cpu_to_apicid, cpu);
	else
		return BAD_APICID;
}

static unsigned int phys_pkg_id(int index_msb)
{
	return GET_APIC_ID(read_apic_id()) >> index_msb;
}

#ifdef ZZZ		/* Needs x2apic patch */
static void uv_send_IPI_self(int vector)
{
	apic_write(APIC_SELF_IPI, vector);
}
#endif

struct genapic apic_x2apic_uv_x = {
	.name = "UV large system",
	.int_delivery_mode = dest_Fixed,
	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	.target_cpus = uv_target_cpus,
	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	.apic_id_registered = uv_apic_id_registered,
	.send_IPI_all = uv_send_IPI_all,
	.send_IPI_allbutself = uv_send_IPI_allbutself,
	.send_IPI_mask = uv_send_IPI_mask,
	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	.phys_pkg_id = phys_pkg_id,	/* Fixme ZZZ */
};

static __cpuinit void set_x2apic_extra_bits(int pnode)
{
	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
}

/*
 * Called on boot cpu.
 */
static __init int boot_pnode_to_blade(int pnode)
{
	int blade;

	for (blade = 0; blade < uv_num_possible_blades(); blade++)
		if (pnode == uv_blade_info[blade].pnode)
			return blade;
	BUG();
}

struct redir_addr {
	unsigned long redirect;
	unsigned long alias;
};

#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT

static __initdata struct redir_addr redir_addrs[] = {
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
};

static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
{
	union uvh_si_alias0_overlay_config_u alias;
	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	int i;

	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
		alias.v = uv_read_local_mmr(redir_addrs[i].alias);
		if (alias.s.base == 0) {
			*size = (1UL << alias.s.m_alias);
			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
			return;
		}
	}
	BUG();
}

static __init void map_low_mmrs(void)
{
	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
}

enum map_type {map_wb, map_uc};

static __init void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
{
	unsigned long bytes, paddr;

	paddr = base << shift;
	bytes = (1UL << shift);
	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	       					paddr + bytes);
	if (map_type == map_uc)
		init_extra_mapping_uc(paddr, bytes);
	else
		init_extra_mapping_wb(paddr, bytes);

}
static __init void map_gru_high(int max_pnode)
{
	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;

	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	if (gru.s.enable)
		map_high("GRU", gru.s.base, shift, map_wb);
}

static __init void map_config_high(int max_pnode)
{
	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;

	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	if (cfg.s.enable)
		map_high("CONFIG", cfg.s.base, shift, map_uc);
}

static __init void map_mmr_high(int max_pnode)
{
	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	if (mmr.s.enable)
		map_high("MMR", mmr.s.base, shift, map_uc);
}

static __init void map_mmioh_high(int max_pnode)
{
	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	if (mmioh.s.enable)
		map_high("MMIOH", mmioh.s.base, shift, map_uc);
}

static __init void uv_rtc_init(void)
{
	long status, ticks_per_sec, drift;

	status =
	    x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
					&drift);
	if (status != 0 || ticks_per_sec < 100000) {
		printk(KERN_WARNING
			"unable to determine platform RTC clock frequency, "
			"guessing.\n");
		/* BIOS gives wrong value for clock freq. so guess */
		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
	} else
		sn_rtc_cycles_per_second = ticks_per_sec;
}

static bool uv_system_inited;

void __init uv_system_init(void)
{
	union uvh_si_addr_map_config_u m_n_config;
	union uvh_node_id_u node_id;
	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
	int max_pnode = 0;
	unsigned long mmr_base, present;

	map_low_mmrs();

	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
	m_val = m_n_config.s.m_skt;
	n_val = m_n_config.s.n_skt;
	mmr_base =
	    uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	    ~UV_MMR_ENABLE;
	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);

	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
		uv_possible_blades +=
		  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());

	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	uv_blade_info = alloc_bootmem_pages(bytes);

	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);

	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	uv_node_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_node_to_blade, 255, bytes);

	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_cpu_to_blade, 255, bytes);

	blade = 0;
	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
		present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
		for (j = 0; j < 64; j++) {
			if (!test_bit(j, &present))
				continue;
			uv_blade_info[blade].pnode = (i * 64 + j);
			uv_blade_info[blade].nr_possible_cpus = 0;
			uv_blade_info[blade].nr_online_cpus = 0;
			blade++;
		}
	}

	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	gnode_upper = (((unsigned long)node_id.s.node_id) &
		       ~((1 << n_val) - 1)) << m_val;

	uv_rtc_init();

	for_each_present_cpu(cpu) {
		nid = cpu_to_node(cpu);
		pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
		blade = boot_pnode_to_blade(pnode);
		lcpu = uv_blade_info[blade].nr_possible_cpus;
		uv_blade_info[blade].nr_possible_cpus++;

		uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
		uv_cpu_hub_info(cpu)->lowmem_remap_top =
					lowmem_redir_base + lowmem_redir_size;
		uv_cpu_hub_info(cpu)->m_val = m_val;
		uv_cpu_hub_info(cpu)->n_val = m_val;
		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
		uv_cpu_hub_info(cpu)->pnode = pnode;
		uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
		uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
		uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
		uv_node_to_blade[nid] = blade;
		uv_cpu_to_blade[cpu] = blade;
		max_pnode = max(pnode, max_pnode);

		printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
			"lcpu %d, blade %d\n",
			cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
			lcpu, blade);
	}

	map_gru_high(max_pnode);
	map_mmr_high(max_pnode);
	map_config_high(max_pnode);
	map_mmioh_high(max_pnode);
	uv_system_inited = true;
}

/*
 * Called on each cpu to initialize the per_cpu UV data area.
 * 	ZZZ hotplug not supported yet
 */
void __cpuinit uv_cpu_init(void)
{
	BUG_ON(!uv_system_inited);

	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;

	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
		set_x2apic_extra_bits(uv_hub_info->pnode);
}
Commit	Line	Data
ac23d4ee JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV APIC functions (note: not an Intel compatible APIC)
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
ac23d4ee JS	9	*/
ac23d4ee JS	10
83f5d894	11	#include <linux/kernel.h>
ac23d4ee JS	12	#include <linux/threads.h>
	13	#include <linux/cpumask.h>
	14	#include <linux/string.h>
	15	#include <linux/kernel.h>
	16	#include <linux/ctype.h>
	17	#include <linux/init.h>
	18	#include <linux/sched.h>
	19	#include <linux/bootmem.h>
	20	#include <linux/module.h>
	21	#include <asm/smp.h>
	22	#include <asm/ipi.h>
	23	#include <asm/genapic.h>
83f5d894	24	#include <asm/pgtable.h>
ac23d4ee JS	25	#include <asm/uv/uv_mmrs.h>
ac23d4ee JS	26	#include <asm/uv/uv_hub.h>
7019cc2d	27	#include <asm/uv/bios.h>
ac23d4ee JS	28
	29	DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	30	EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
	31
	32	struct uv_blade_info *uv_blade_info;
	33	EXPORT_SYMBOL_GPL(uv_blade_info);
	34
	35	short *uv_node_to_blade;
	36	EXPORT_SYMBOL_GPL(uv_node_to_blade);
	37
	38	short *uv_cpu_to_blade;
	39	EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
	40
	41	short uv_possible_blades;
	42	EXPORT_SYMBOL_GPL(uv_possible_blades);
	43
7019cc2d RA	44	unsigned long sn_rtc_cycles_per_second;
	45	EXPORT_SYMBOL(sn_rtc_cycles_per_second);
	46
ac23d4ee JS	47	/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
	48
	49	static cpumask_t uv_target_cpus(void)
	50	{
	51	return cpumask_of_cpu(0);
	52	}
	53
	54	static cpumask_t uv_vector_allocation_domain(int cpu)
	55	{
	56	cpumask_t domain = CPU_MASK_NONE;
	57	cpu_set(cpu, domain);
	58	return domain;
	59	}
	60
	61	int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
	62	{
	63	unsigned long val;
9f5314fb	64	int pnode;
ac23d4ee	65
9f5314fb	66	pnode = uv_apicid_to_pnode(phys_apicid);
ac23d4ee JS	67	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	68	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	69	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
34d05591	70	APIC_DM_INIT;
9f5314fb	71	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
34d05591 JS	72	mdelay(10);
	73
	74	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	75	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	76	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	77	APIC_DM_STARTUP;
9f5314fb	78	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	79	return 0;
	80	}
	81
	82	static void uv_send_IPI_one(int cpu, int vector)
	83	{
34d05591	84	unsigned long val, apicid, lapicid;
9f5314fb	85	int pnode;
ac23d4ee JS	86
ac23d4ee JS	87	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
34d05591	88	lapicid = apicid & 0x3f; /* ZZZ macro needed */
9f5314fb	89	pnode = uv_apicid_to_pnode(apicid);
ac23d4ee	90	val =
34d05591	91	(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<
ac23d4ee JS	92	UVH_IPI_INT_APIC_ID_SHFT) \|
ac23d4ee JS	93	(vector << UVH_IPI_INT_VECTOR_SHFT);
9f5314fb	94	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	95	}
	96
	97	static void uv_send_IPI_mask(cpumask_t mask, int vector)
	98	{
	99	unsigned int cpu;
	100
247bc6ca	101	for_each_possible_cpu(cpu)
ac23d4ee JS	102	if (cpu_isset(cpu, mask))
	103	uv_send_IPI_one(cpu, vector);
	104	}
	105
	106	static void uv_send_IPI_allbutself(int vector)
	107	{
	108	cpumask_t mask = cpu_online_map;
	109
	110	cpu_clear(smp_processor_id(), mask);
	111
	112	if (!cpus_empty(mask))
	113	uv_send_IPI_mask(mask, vector);
	114	}
	115
	116	static void uv_send_IPI_all(int vector)
	117	{
	118	uv_send_IPI_mask(cpu_online_map, vector);
	119	}
	120
	121	static int uv_apic_id_registered(void)
	122	{
	123	return 1;
	124	}
	125
	126	static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
	127	{
	128	int cpu;
	129
	130	/*
	131	* We're using fixed IRQ delivery, can only return one phys APIC ID.
	132	* May as well be the first.
	133	*/
	134	cpu = first_cpu(cpumask);
247bc6ca	135	if ((unsigned)cpu < nr_cpu_ids)
ac23d4ee JS	136	return per_cpu(x86_cpu_to_apicid, cpu);
	137	else
	138	return BAD_APICID;
	139	}
	140
	141	static unsigned int phys_pkg_id(int index_msb)
	142	{
	143	return GET_APIC_ID(read_apic_id()) >> index_msb;
	144	}
	145
	146	#ifdef ZZZ /* Needs x2apic patch */
	147	static void uv_send_IPI_self(int vector)
	148	{
	149	apic_write(APIC_SELF_IPI, vector);
	150	}
	151	#endif
	152
	153	struct genapic apic_x2apic_uv_x = {
	154	.name = "UV large system",
	155	.int_delivery_mode = dest_Fixed,
	156	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	157	.target_cpus = uv_target_cpus,
	158	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	159	.apic_id_registered = uv_apic_id_registered,
	160	.send_IPI_all = uv_send_IPI_all,
	161	.send_IPI_allbutself = uv_send_IPI_allbutself,
	162	.send_IPI_mask = uv_send_IPI_mask,
	163	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	164	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	165	.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
	166	};
	167
9f5314fb	168	static __cpuinit void set_x2apic_extra_bits(int pnode)
ac23d4ee	169	{
9f5314fb	170	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
ac23d4ee JS	171	}
	172
	173	/*
	174	* Called on boot cpu.
	175	*/
9f5314fb JS	176	static __init int boot_pnode_to_blade(int pnode)
	177	{
	178	int blade;
	179
	180	for (blade = 0; blade < uv_num_possible_blades(); blade++)
	181	if (pnode == uv_blade_info[blade].pnode)
	182	return blade;
	183	BUG();
	184	}
	185
	186	struct redir_addr {
	187	unsigned long redirect;
	188	unsigned long alias;
	189	};
	190
	191	#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
	192
	193	static __initdata struct redir_addr redir_addrs[] = {
	194	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	195	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	196	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
	197	};
	198
	199	static __init void get_lowmem_redirect(unsigned long base, unsigned long size)
	200	{
	201	union uvh_si_alias0_overlay_config_u alias;
	202	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	203	int i;
	204
	205	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
	206	alias.v = uv_read_local_mmr(redir_addrs[i].alias);
	207	if (alias.s.base == 0) {
	208	*size = (1UL << alias.s.m_alias);
	209	redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
	210	*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
	211	return;
	212	}
	213	}
	214	BUG();
	215	}
	216
83f5d894 JS	217	static __init void map_low_mmrs(void)
	218	{
	219	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	220	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
	221	}
	222
	223	enum map_type {map_wb, map_uc};
	224
c9d08f08	225	static __init void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
83f5d894 JS	226	{
	227	unsigned long bytes, paddr;
	228
	229	paddr = base << shift;
	230	bytes = (1UL << shift);
	231	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	232	paddr + bytes);
	233	if (map_type == map_uc)
	234	init_extra_mapping_uc(paddr, bytes);
	235	else
	236	init_extra_mapping_wb(paddr, bytes);
	237
	238	}
	239	static __init void map_gru_high(int max_pnode)
	240	{
	241	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	242	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
	243
	244	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	245	if (gru.s.enable)
	246	map_high("GRU", gru.s.base, shift, map_wb);
	247	}
	248
	249	static __init void map_config_high(int max_pnode)
	250	{
	251	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	252	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
	253
	254	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	255	if (cfg.s.enable)
	256	map_high("CONFIG", cfg.s.base, shift, map_uc);
	257	}
	258
	259	static __init void map_mmr_high(int max_pnode)
	260	{
	261	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	262	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
	263
	264	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	265	if (mmr.s.enable)
	266	map_high("MMR", mmr.s.base, shift, map_uc);
	267	}
	268
	269	static __init void map_mmioh_high(int max_pnode)
	270	{
	271	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	272	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
	273
	274	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	275	if (mmioh.s.enable)
	276	map_high("MMIOH", mmioh.s.base, shift, map_uc);
	277	}
	278
7019cc2d RA	279	static __init void uv_rtc_init(void)
	280	{
	281	long status, ticks_per_sec, drift;
	282
	283	status =
	284	x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
	285	&drift);
	286	if (status != 0 \|\| ticks_per_sec < 100000) {
	287	printk(KERN_WARNING
	288	"unable to determine platform RTC clock frequency, "
	289	"guessing.\n");
	290	/* BIOS gives wrong value for clock freq. so guess */
	291	sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
	292	} else
	293	sn_rtc_cycles_per_second = ticks_per_sec;
	294	}
	295
c4bd1fda MS	296	static bool uv_system_inited;
	297
	298	void __init uv_system_init(void)
ac23d4ee JS	299	{
ac23d4ee JS	300	union uvh_si_addr_map_config_u m_n_config;
9f5314fb JS	301	union uvh_node_id_u node_id;
	302	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	303	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
83f5d894	304	int max_pnode = 0;
9f5314fb	305	unsigned long mmr_base, present;
ac23d4ee	306
83f5d894 JS	307	map_low_mmrs();
83f5d894 JS	308
ac23d4ee	309	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
9f5314fb JS	310	m_val = m_n_config.s.m_skt;
9f5314fb JS	311	n_val = m_n_config.s.n_skt;
ac23d4ee JS	312	mmr_base =
	313	uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	314	~UV_MMR_ENABLE;
	315	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
	316
9f5314fb JS	317	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
	318	uv_possible_blades +=
	319	hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
ac23d4ee JS	320	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
	321
	322	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	323	uv_blade_info = alloc_bootmem_pages(bytes);
	324
9f5314fb JS	325	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
9f5314fb JS	326
ac23d4ee JS	327	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	328	uv_node_to_blade = alloc_bootmem_pages(bytes);
	329	memset(uv_node_to_blade, 255, bytes);
	330
	331	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	332	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	333	memset(uv_cpu_to_blade, 255, bytes);
	334
9f5314fb JS	335	blade = 0;
	336	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
	337	present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
	338	for (j = 0; j < 64; j++) {
	339	if (!test_bit(j, &present))
	340	continue;
	341	uv_blade_info[blade].pnode = (i * 64 + j);
	342	uv_blade_info[blade].nr_possible_cpus = 0;
ac23d4ee	343	uv_blade_info[blade].nr_online_cpus = 0;
9f5314fb	344	blade++;
ac23d4ee	345	}
9f5314fb	346	}
ac23d4ee	347
9f5314fb JS	348	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	349	gnode_upper = (((unsigned long)node_id.s.node_id) &
	350	~((1 << n_val) - 1)) << m_val;
	351
7019cc2d RA	352	uv_rtc_init();
7019cc2d RA	353
9f5314fb JS	354	for_each_present_cpu(cpu) {
	355	nid = cpu_to_node(cpu);
	356	pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
	357	blade = boot_pnode_to_blade(pnode);
	358	lcpu = uv_blade_info[blade].nr_possible_cpus;
	359	uv_blade_info[blade].nr_possible_cpus++;
	360
	361	uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
	362	uv_cpu_hub_info(cpu)->lowmem_remap_top =
	363	lowmem_redir_base + lowmem_redir_size;
	364	uv_cpu_hub_info(cpu)->m_val = m_val;
	365	uv_cpu_hub_info(cpu)->n_val = m_val;
ac23d4ee JS	366	uv_cpu_hub_info(cpu)->numa_blade_id = blade;
ac23d4ee JS	367	uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
9f5314fb JS	368	uv_cpu_hub_info(cpu)->pnode = pnode;
	369	uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
	370	uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
	371	uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
ac23d4ee JS	372	uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
ac23d4ee JS	373	uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
ac23d4ee JS	374	uv_node_to_blade[nid] = blade;
ac23d4ee JS	375	uv_cpu_to_blade[cpu] = blade;
83f5d894	376	max_pnode = max(pnode, max_pnode);
ac23d4ee	377
83f5d894	378	printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
9f5314fb JS	379	"lcpu %d, blade %d\n",
	380	cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
	381	lcpu, blade);
ac23d4ee	382	}
83f5d894 JS	383
	384	map_gru_high(max_pnode);
	385	map_mmr_high(max_pnode);
	386	map_config_high(max_pnode);
	387	map_mmioh_high(max_pnode);
c4bd1fda	388	uv_system_inited = true;
ac23d4ee JS	389	}
	390
	391	/*
	392	* Called on each cpu to initialize the per_cpu UV data area.
9f5314fb	393	* ZZZ hotplug not supported yet
ac23d4ee JS	394	*/
	395	void __cpuinit uv_cpu_init(void)
	396	{
c4bd1fda	397	BUG_ON(!uv_system_inited);
ac23d4ee JS	398
	399	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
	400
	401	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
9f5314fb	402	set_x2apic_extra_bits(uv_hub_info->pnode);
ac23d4ee	403	}