[net-next-2.6.git] / arch / x86 / kernel / genx2apic_uv_x.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV APIC functions (note: not an Intel compatible APIC)
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/hardirq.h>
#include <asm/smp.h>
#include <asm/ipi.h>
#include <asm/genapic.h>
#include <asm/pgtable.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/bios.h>

DEFINE_PER_CPU(int, x2apic_extra_bits);

static enum uv_system_type uv_system_type;

static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
	if (!strcmp(oem_id, "SGI")) {
		if (!strcmp(oem_table_id, "UVL"))
			uv_system_type = UV_LEGACY_APIC;
		else if (!strcmp(oem_table_id, "UVX"))
			uv_system_type = UV_X2APIC;
		else if (!strcmp(oem_table_id, "UVH")) {
			uv_system_type = UV_NON_UNIQUE_APIC;
			return 1;
		}
	}
	return 0;
}

enum uv_system_type get_uv_system_type(void)
{
	return uv_system_type;
}

int is_uv_system(void)
{
	return uv_system_type != UV_NONE;
}

DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);

struct uv_blade_info *uv_blade_info;
EXPORT_SYMBOL_GPL(uv_blade_info);

short *uv_node_to_blade;
EXPORT_SYMBOL_GPL(uv_node_to_blade);

short *uv_cpu_to_blade;
EXPORT_SYMBOL_GPL(uv_cpu_to_blade);

short uv_possible_blades;
EXPORT_SYMBOL_GPL(uv_possible_blades);

unsigned long sn_rtc_cycles_per_second;
EXPORT_SYMBOL(sn_rtc_cycles_per_second);

/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */

static cpumask_t uv_target_cpus(void)
{
	return cpumask_of_cpu(0);
}

static cpumask_t uv_vector_allocation_domain(int cpu)
{
	cpumask_t domain = CPU_MASK_NONE;
	cpu_set(cpu, domain);
	return domain;
}

int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
{
	unsigned long val;
	int pnode;

	pnode = uv_apicid_to_pnode(phys_apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_INIT;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	mdelay(10);

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_STARTUP;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	return 0;
}

static void uv_send_IPI_one(int cpu, int vector)
{
	unsigned long val, apicid, lapicid;
	int pnode;

	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
	lapicid = apicid & 0x3f;		/* ZZZ macro needed */
	pnode = uv_apicid_to_pnode(apicid);
	val =
	    (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
					      UVH_IPI_INT_APIC_ID_SHFT) |
	    (vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

static void uv_send_IPI_mask(cpumask_t mask, int vector)
{
	unsigned int cpu;

	for_each_possible_cpu(cpu)
		if (cpu_isset(cpu, mask))
			uv_send_IPI_one(cpu, vector);
}

static void uv_send_IPI_allbutself(int vector)
{
	cpumask_t mask = cpu_online_map;

	cpu_clear(smp_processor_id(), mask);

	if (!cpus_empty(mask))
		uv_send_IPI_mask(mask, vector);
}

static void uv_send_IPI_all(int vector)
{
	uv_send_IPI_mask(cpu_online_map, vector);
}

static int uv_apic_id_registered(void)
{
	return 1;
}

static void uv_init_apic_ldr(void)
{
}

static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;

	/*
	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
	 * May as well be the first.
	 */
	cpu = first_cpu(cpumask);
	if ((unsigned)cpu < nr_cpu_ids)
		return per_cpu(x86_cpu_to_apicid, cpu);
	else
		return BAD_APICID;
}

static unsigned int get_apic_id(unsigned long x)
{
	unsigned int id;

	WARN_ON(preemptible() && num_online_cpus() > 1);
	id = x | __get_cpu_var(x2apic_extra_bits);

	return id;
}

static unsigned long set_apic_id(unsigned int id)
{
	unsigned long x;

	/* maskout x2apic_extra_bits ? */
	x = id;
	return x;
}

static unsigned int uv_read_apic_id(void)
{

	return get_apic_id(apic_read(APIC_ID));
}

static unsigned int phys_pkg_id(int index_msb)
{
	return uv_read_apic_id() >> index_msb;
}

#ifdef ZZZ		/* Needs x2apic patch */
static void uv_send_IPI_self(int vector)
{
	apic_write(APIC_SELF_IPI, vector);
}
#endif

struct genapic apic_x2apic_uv_x = {
	.name = "UV large system",
	.acpi_madt_oem_check = uv_acpi_madt_oem_check,
	.int_delivery_mode = dest_Fixed,
	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	.target_cpus = uv_target_cpus,
	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	.apic_id_registered = uv_apic_id_registered,
	.init_apic_ldr = uv_init_apic_ldr,
	.send_IPI_all = uv_send_IPI_all,
	.send_IPI_allbutself = uv_send_IPI_allbutself,
	.send_IPI_mask = uv_send_IPI_mask,
	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	.phys_pkg_id = phys_pkg_id,	/* Fixme ZZZ */
	.get_apic_id = get_apic_id,
	.set_apic_id = set_apic_id,
	.apic_id_mask = (0xFFFFFFFFu),
};

static __cpuinit void set_x2apic_extra_bits(int pnode)
{
	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
}

/*
 * Called on boot cpu.
 */
static __init int boot_pnode_to_blade(int pnode)
{
	int blade;

	for (blade = 0; blade < uv_num_possible_blades(); blade++)
		if (pnode == uv_blade_info[blade].pnode)
			return blade;
	BUG();
}

struct redir_addr {
	unsigned long redirect;
	unsigned long alias;
};

#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT

static __initdata struct redir_addr redir_addrs[] = {
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
};

static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
{
	union uvh_si_alias0_overlay_config_u alias;
	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	int i;

	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
		alias.v = uv_read_local_mmr(redir_addrs[i].alias);
		if (alias.s.base == 0) {
			*size = (1UL << alias.s.m_alias);
			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
			return;
		}
	}
	BUG();
}

static __init void map_low_mmrs(void)
{
	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
}

enum map_type {map_wb, map_uc};

static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
{
	unsigned long bytes, paddr;

	paddr = base << shift;
	bytes = (1UL << shift);
	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	       					paddr + bytes);
	if (map_type == map_uc)
		init_extra_mapping_uc(paddr, bytes);
	else
		init_extra_mapping_wb(paddr, bytes);

}
static __init void map_gru_high(int max_pnode)
{
	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;

	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	if (gru.s.enable)
		map_high("GRU", gru.s.base, shift, map_wb);
}

static __init void map_config_high(int max_pnode)
{
	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;

	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	if (cfg.s.enable)
		map_high("CONFIG", cfg.s.base, shift, map_uc);
}

static __init void map_mmr_high(int max_pnode)
{
	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	if (mmr.s.enable)
		map_high("MMR", mmr.s.base, shift, map_uc);
}

static __init void map_mmioh_high(int max_pnode)
{
	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	if (mmioh.s.enable)
		map_high("MMIOH", mmioh.s.base, shift, map_uc);
}

static __init void uv_rtc_init(void)
{
	long status, ticks_per_sec, drift;

	status =
	    x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
					&drift);
	if (status != 0 || ticks_per_sec < 100000) {
		printk(KERN_WARNING
			"unable to determine platform RTC clock frequency, "
			"guessing.\n");
		/* BIOS gives wrong value for clock freq. so guess */
		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
	} else
		sn_rtc_cycles_per_second = ticks_per_sec;
}

static __init void uv_system_init(void)
{
	union uvh_si_addr_map_config_u m_n_config;
	union uvh_node_id_u node_id;
	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
	int max_pnode = 0;
	unsigned long mmr_base, present;

	map_low_mmrs();

	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
	m_val = m_n_config.s.m_skt;
	n_val = m_n_config.s.n_skt;
	mmr_base =
	    uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	    ~UV_MMR_ENABLE;
	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);

	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
		uv_possible_blades +=
		  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());

	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	uv_blade_info = alloc_bootmem_pages(bytes);

	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);

	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	uv_node_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_node_to_blade, 255, bytes);

	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_cpu_to_blade, 255, bytes);

	blade = 0;
	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
		present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
		for (j = 0; j < 64; j++) {
			if (!test_bit(j, &present))
				continue;
			uv_blade_info[blade].pnode = (i * 64 + j);
			uv_blade_info[blade].nr_possible_cpus = 0;
			uv_blade_info[blade].nr_online_cpus = 0;
			blade++;
		}
	}

	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	gnode_upper = (((unsigned long)node_id.s.node_id) &
		       ~((1 << n_val) - 1)) << m_val;

	uv_rtc_init();

	for_each_present_cpu(cpu) {
		nid = cpu_to_node(cpu);
		pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
		blade = boot_pnode_to_blade(pnode);
		lcpu = uv_blade_info[blade].nr_possible_cpus;
		uv_blade_info[blade].nr_possible_cpus++;

		uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
		uv_cpu_hub_info(cpu)->lowmem_remap_top =
					lowmem_redir_base + lowmem_redir_size;
		uv_cpu_hub_info(cpu)->m_val = m_val;
		uv_cpu_hub_info(cpu)->n_val = m_val;
		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
		uv_cpu_hub_info(cpu)->pnode = pnode;
		uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
		uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
		uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
		uv_node_to_blade[nid] = blade;
		uv_cpu_to_blade[cpu] = blade;
		max_pnode = max(pnode, max_pnode);

		printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
			"lcpu %d, blade %d\n",
			cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
			lcpu, blade);
	}

	map_gru_high(max_pnode);
	map_mmr_high(max_pnode);
	map_config_high(max_pnode);
	map_mmioh_high(max_pnode);
}

/*
 * Called on each cpu to initialize the per_cpu UV data area.
 * 	ZZZ hotplug not supported yet
 */
void __cpuinit uv_cpu_init(void)
{
	if (!uv_node_to_blade)
		uv_system_init();

	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;

	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
		set_x2apic_extra_bits(uv_hub_info->pnode);
}
Commit	Line	Data
ac23d4ee JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV APIC functions (note: not an Intel compatible APIC)
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
ac23d4ee JS	9	*/
ac23d4ee JS	10
83f5d894	11	#include <linux/kernel.h>
ac23d4ee JS	12	#include <linux/threads.h>
	13	#include <linux/cpumask.h>
	14	#include <linux/string.h>
ac23d4ee JS	15	#include <linux/ctype.h>
	16	#include <linux/init.h>
	17	#include <linux/sched.h>
	18	#include <linux/bootmem.h>
	19	#include <linux/module.h>
0c81c746	20	#include <linux/hardirq.h>
ac23d4ee JS	21	#include <asm/smp.h>
	22	#include <asm/ipi.h>
	23	#include <asm/genapic.h>
83f5d894	24	#include <asm/pgtable.h>
ac23d4ee JS	25	#include <asm/uv/uv_mmrs.h>
ac23d4ee JS	26	#include <asm/uv/uv_hub.h>
7019cc2d	27	#include <asm/uv/bios.h>
ac23d4ee	28
510b3725 YL	29	DEFINE_PER_CPU(int, x2apic_extra_bits);
510b3725 YL	30
1b9b89e7 YL	31	static enum uv_system_type uv_system_type;
	32
	33	static int __init uv_acpi_madt_oem_check(char oem_id, char oem_table_id)
	34	{
	35	if (!strcmp(oem_id, "SGI")) {
	36	if (!strcmp(oem_table_id, "UVL"))
	37	uv_system_type = UV_LEGACY_APIC;
	38	else if (!strcmp(oem_table_id, "UVX"))
	39	uv_system_type = UV_X2APIC;
	40	else if (!strcmp(oem_table_id, "UVH")) {
	41	uv_system_type = UV_NON_UNIQUE_APIC;
	42	return 1;
	43	}
	44	}
	45	return 0;
	46	}
	47
	48	enum uv_system_type get_uv_system_type(void)
	49	{
	50	return uv_system_type;
	51	}
	52
	53	int is_uv_system(void)
	54	{
	55	return uv_system_type != UV_NONE;
	56	}
	57
ac23d4ee JS	58	DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	59	EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
	60
	61	struct uv_blade_info *uv_blade_info;
	62	EXPORT_SYMBOL_GPL(uv_blade_info);
	63
	64	short *uv_node_to_blade;
	65	EXPORT_SYMBOL_GPL(uv_node_to_blade);
	66
	67	short *uv_cpu_to_blade;
	68	EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
	69
	70	short uv_possible_blades;
	71	EXPORT_SYMBOL_GPL(uv_possible_blades);
	72
7019cc2d RA	73	unsigned long sn_rtc_cycles_per_second;
	74	EXPORT_SYMBOL(sn_rtc_cycles_per_second);
	75
ac23d4ee JS	76	/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
	77
	78	static cpumask_t uv_target_cpus(void)
	79	{
	80	return cpumask_of_cpu(0);
	81	}
	82
	83	static cpumask_t uv_vector_allocation_domain(int cpu)
	84	{
	85	cpumask_t domain = CPU_MASK_NONE;
	86	cpu_set(cpu, domain);
	87	return domain;
	88	}
	89
	90	int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
	91	{
	92	unsigned long val;
9f5314fb	93	int pnode;
ac23d4ee	94
9f5314fb	95	pnode = uv_apicid_to_pnode(phys_apicid);
ac23d4ee JS	96	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	97	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	98	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
34d05591	99	APIC_DM_INIT;
9f5314fb	100	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
34d05591 JS	101	mdelay(10);
	102
	103	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	104	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	105	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	106	APIC_DM_STARTUP;
9f5314fb	107	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	108	return 0;
	109	}
	110
	111	static void uv_send_IPI_one(int cpu, int vector)
	112	{
34d05591	113	unsigned long val, apicid, lapicid;
9f5314fb	114	int pnode;
ac23d4ee JS	115
ac23d4ee JS	116	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
34d05591	117	lapicid = apicid & 0x3f; /* ZZZ macro needed */
9f5314fb	118	pnode = uv_apicid_to_pnode(apicid);
ac23d4ee	119	val =
34d05591	120	(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<
ac23d4ee JS	121	UVH_IPI_INT_APIC_ID_SHFT) \|
ac23d4ee JS	122	(vector << UVH_IPI_INT_VECTOR_SHFT);
9f5314fb	123	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	124	}
	125
	126	static void uv_send_IPI_mask(cpumask_t mask, int vector)
	127	{
	128	unsigned int cpu;
	129
247bc6ca	130	for_each_possible_cpu(cpu)
ac23d4ee JS	131	if (cpu_isset(cpu, mask))
	132	uv_send_IPI_one(cpu, vector);
	133	}
	134
	135	static void uv_send_IPI_allbutself(int vector)
	136	{
	137	cpumask_t mask = cpu_online_map;
	138
	139	cpu_clear(smp_processor_id(), mask);
	140
	141	if (!cpus_empty(mask))
	142	uv_send_IPI_mask(mask, vector);
	143	}
	144
	145	static void uv_send_IPI_all(int vector)
	146	{
	147	uv_send_IPI_mask(cpu_online_map, vector);
	148	}
	149
	150	static int uv_apic_id_registered(void)
	151	{
	152	return 1;
	153	}
	154
277d1f58	155	static void uv_init_apic_ldr(void)
5c520a67 SS	156	{
	157	}
	158
ac23d4ee JS	159	static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
	160	{
	161	int cpu;
	162
	163	/*
	164	* We're using fixed IRQ delivery, can only return one phys APIC ID.
	165	* May as well be the first.
	166	*/
	167	cpu = first_cpu(cpumask);
247bc6ca	168	if ((unsigned)cpu < nr_cpu_ids)
ac23d4ee JS	169	return per_cpu(x86_cpu_to_apicid, cpu);
	170	else
	171	return BAD_APICID;
	172	}
	173
f910a9dc	174	static unsigned int get_apic_id(unsigned long x)
0c81c746 SS	175	{
	176	unsigned int id;
	177
	178	WARN_ON(preemptible() && num_online_cpus() > 1);
f910a9dc	179	id = x \| __get_cpu_var(x2apic_extra_bits);
0c81c746 SS	180
	181	return id;
	182	}
	183
1b9b89e7	184	static unsigned long set_apic_id(unsigned int id)
f910a9dc YL	185	{
	186	unsigned long x;
	187
	188	/* maskout x2apic_extra_bits ? */
	189	x = id;
	190	return x;
	191	}
	192
	193	static unsigned int uv_read_apic_id(void)
	194	{
	195
	196	return get_apic_id(apic_read(APIC_ID));
	197	}
	198
ac23d4ee JS	199	static unsigned int phys_pkg_id(int index_msb)
ac23d4ee JS	200	{
0c81c746	201	return uv_read_apic_id() >> index_msb;
ac23d4ee JS	202	}
	203
	204	#ifdef ZZZ /* Needs x2apic patch */
	205	static void uv_send_IPI_self(int vector)
	206	{
	207	apic_write(APIC_SELF_IPI, vector);
	208	}
	209	#endif
	210
	211	struct genapic apic_x2apic_uv_x = {
	212	.name = "UV large system",
1b9b89e7	213	.acpi_madt_oem_check = uv_acpi_madt_oem_check,
ac23d4ee JS	214	.int_delivery_mode = dest_Fixed,
	215	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	216	.target_cpus = uv_target_cpus,
	217	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	218	.apic_id_registered = uv_apic_id_registered,
5c520a67	219	.init_apic_ldr = uv_init_apic_ldr,
ac23d4ee JS	220	.send_IPI_all = uv_send_IPI_all,
	221	.send_IPI_allbutself = uv_send_IPI_allbutself,
	222	.send_IPI_mask = uv_send_IPI_mask,
	223	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	224	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	225	.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
f910a9dc YL	226	.get_apic_id = get_apic_id,
	227	.set_apic_id = set_apic_id,
	228	.apic_id_mask = (0xFFFFFFFFu),
ac23d4ee JS	229	};
ac23d4ee JS	230
9f5314fb	231	static __cpuinit void set_x2apic_extra_bits(int pnode)
ac23d4ee	232	{
9f5314fb	233	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
ac23d4ee JS	234	}
	235
	236	/*
	237	* Called on boot cpu.
	238	*/
9f5314fb JS	239	static __init int boot_pnode_to_blade(int pnode)
	240	{
	241	int blade;
	242
	243	for (blade = 0; blade < uv_num_possible_blades(); blade++)
	244	if (pnode == uv_blade_info[blade].pnode)
	245	return blade;
	246	BUG();
	247	}
	248
	249	struct redir_addr {
	250	unsigned long redirect;
	251	unsigned long alias;
	252	};
	253
	254	#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
	255
	256	static __initdata struct redir_addr redir_addrs[] = {
	257	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	258	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	259	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
	260	};
	261
	262	static __init void get_lowmem_redirect(unsigned long base, unsigned long size)
	263	{
	264	union uvh_si_alias0_overlay_config_u alias;
	265	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	266	int i;
	267
	268	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
	269	alias.v = uv_read_local_mmr(redir_addrs[i].alias);
	270	if (alias.s.base == 0) {
	271	*size = (1UL << alias.s.m_alias);
	272	redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
	273	*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
	274	return;
	275	}
	276	}
	277	BUG();
	278	}
	279
83f5d894 JS	280	static __init void map_low_mmrs(void)
	281	{
	282	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	283	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
	284	}
	285
	286	enum map_type {map_wb, map_uc};
	287
	288	static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
	289	{
	290	unsigned long bytes, paddr;
	291
	292	paddr = base << shift;
	293	bytes = (1UL << shift);
	294	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	295	paddr + bytes);
	296	if (map_type == map_uc)
	297	init_extra_mapping_uc(paddr, bytes);
	298	else
	299	init_extra_mapping_wb(paddr, bytes);
	300
	301	}
	302	static __init void map_gru_high(int max_pnode)
	303	{
	304	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	305	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
	306
	307	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	308	if (gru.s.enable)
	309	map_high("GRU", gru.s.base, shift, map_wb);
	310	}
	311
	312	static __init void map_config_high(int max_pnode)
	313	{
	314	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	315	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
	316
	317	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	318	if (cfg.s.enable)
	319	map_high("CONFIG", cfg.s.base, shift, map_uc);
	320	}
	321
	322	static __init void map_mmr_high(int max_pnode)
	323	{
	324	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	325	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
	326
	327	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	328	if (mmr.s.enable)
	329	map_high("MMR", mmr.s.base, shift, map_uc);
	330	}
	331
	332	static __init void map_mmioh_high(int max_pnode)
	333	{
	334	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	335	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
	336
	337	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	338	if (mmioh.s.enable)
	339	map_high("MMIOH", mmioh.s.base, shift, map_uc);
	340	}
	341
7019cc2d RA	342	static __init void uv_rtc_init(void)
	343	{
	344	long status, ticks_per_sec, drift;
	345
	346	status =
	347	x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
	348	&drift);
	349	if (status != 0 \|\| ticks_per_sec < 100000) {
	350	printk(KERN_WARNING
	351	"unable to determine platform RTC clock frequency, "
	352	"guessing.\n");
	353	/* BIOS gives wrong value for clock freq. so guess */
	354	sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
	355	} else
	356	sn_rtc_cycles_per_second = ticks_per_sec;
	357	}
	358
ac23d4ee JS	359	static __init void uv_system_init(void)
	360	{
	361	union uvh_si_addr_map_config_u m_n_config;
9f5314fb JS	362	union uvh_node_id_u node_id;
	363	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	364	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
83f5d894	365	int max_pnode = 0;
9f5314fb	366	unsigned long mmr_base, present;
ac23d4ee	367
83f5d894 JS	368	map_low_mmrs();
83f5d894 JS	369
ac23d4ee	370	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
9f5314fb JS	371	m_val = m_n_config.s.m_skt;
9f5314fb JS	372	n_val = m_n_config.s.n_skt;
ac23d4ee JS	373	mmr_base =
	374	uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	375	~UV_MMR_ENABLE;
	376	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
	377
9f5314fb JS	378	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
	379	uv_possible_blades +=
	380	hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
ac23d4ee JS	381	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
	382
	383	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	384	uv_blade_info = alloc_bootmem_pages(bytes);
	385
9f5314fb JS	386	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
9f5314fb JS	387
ac23d4ee JS	388	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	389	uv_node_to_blade = alloc_bootmem_pages(bytes);
	390	memset(uv_node_to_blade, 255, bytes);
	391
	392	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	393	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	394	memset(uv_cpu_to_blade, 255, bytes);
	395
9f5314fb JS	396	blade = 0;
	397	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
	398	present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
	399	for (j = 0; j < 64; j++) {
	400	if (!test_bit(j, &present))
	401	continue;
	402	uv_blade_info[blade].pnode = (i * 64 + j);
	403	uv_blade_info[blade].nr_possible_cpus = 0;
ac23d4ee	404	uv_blade_info[blade].nr_online_cpus = 0;
9f5314fb	405	blade++;
ac23d4ee	406	}
9f5314fb	407	}
ac23d4ee	408
9f5314fb JS	409	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	410	gnode_upper = (((unsigned long)node_id.s.node_id) &
	411	~((1 << n_val) - 1)) << m_val;
	412
7019cc2d RA	413	uv_rtc_init();
7019cc2d RA	414
9f5314fb JS	415	for_each_present_cpu(cpu) {
	416	nid = cpu_to_node(cpu);
	417	pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
	418	blade = boot_pnode_to_blade(pnode);
	419	lcpu = uv_blade_info[blade].nr_possible_cpus;
	420	uv_blade_info[blade].nr_possible_cpus++;
	421
	422	uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
	423	uv_cpu_hub_info(cpu)->lowmem_remap_top =
	424	lowmem_redir_base + lowmem_redir_size;
	425	uv_cpu_hub_info(cpu)->m_val = m_val;
	426	uv_cpu_hub_info(cpu)->n_val = m_val;
ac23d4ee JS	427	uv_cpu_hub_info(cpu)->numa_blade_id = blade;
ac23d4ee JS	428	uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
9f5314fb JS	429	uv_cpu_hub_info(cpu)->pnode = pnode;
	430	uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
	431	uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
	432	uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
ac23d4ee JS	433	uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
ac23d4ee JS	434	uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
ac23d4ee JS	435	uv_node_to_blade[nid] = blade;
ac23d4ee JS	436	uv_cpu_to_blade[cpu] = blade;
83f5d894	437	max_pnode = max(pnode, max_pnode);
ac23d4ee	438
83f5d894	439	printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
9f5314fb JS	440	"lcpu %d, blade %d\n",
	441	cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
	442	lcpu, blade);
ac23d4ee	443	}
83f5d894 JS	444
	445	map_gru_high(max_pnode);
	446	map_mmr_high(max_pnode);
	447	map_config_high(max_pnode);
	448	map_mmioh_high(max_pnode);
ac23d4ee JS	449	}
	450
	451	/*
	452	* Called on each cpu to initialize the per_cpu UV data area.
9f5314fb	453	* ZZZ hotplug not supported yet
ac23d4ee JS	454	*/
	455	void __cpuinit uv_cpu_init(void)
	456	{
	457	if (!uv_node_to_blade)
	458	uv_system_init();
	459
	460	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
	461
	462	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
9f5314fb	463	set_x2apic_extra_bits(uv_hub_info->pnode);
ac23d4ee	464	}
1b9b89e7 YL	465
1b9b89e7 YL	466