[net-next-2.6.git] / arch / x86 / kernel / genx2apic_uv_x.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV APIC functions (note: not an Intel compatible APIC)
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/hardirq.h>
#include <asm/smp.h>
#include <asm/ipi.h>
#include <asm/genapic.h>
#include <asm/pgtable.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/bios.h>

DEFINE_PER_CPU(int, x2apic_extra_bits);

static enum uv_system_type uv_system_type;

static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
	if (!strcmp(oem_id, "SGI")) {
		if (!strcmp(oem_table_id, "UVL"))
			uv_system_type = UV_LEGACY_APIC;
		else if (!strcmp(oem_table_id, "UVX"))
			uv_system_type = UV_X2APIC;
		else if (!strcmp(oem_table_id, "UVH")) {
			uv_system_type = UV_NON_UNIQUE_APIC;
			return 1;
		}
	}
	return 0;
}

enum uv_system_type get_uv_system_type(void)
{
	return uv_system_type;
}

int is_uv_system(void)
{
	return uv_system_type != UV_NONE;
}
EXPORT_SYMBOL_GPL(is_uv_system);

DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);

struct uv_blade_info *uv_blade_info;
EXPORT_SYMBOL_GPL(uv_blade_info);

short *uv_node_to_blade;
EXPORT_SYMBOL_GPL(uv_node_to_blade);

short *uv_cpu_to_blade;
EXPORT_SYMBOL_GPL(uv_cpu_to_blade);

short uv_possible_blades;
EXPORT_SYMBOL_GPL(uv_possible_blades);

unsigned long sn_rtc_cycles_per_second;
EXPORT_SYMBOL(sn_rtc_cycles_per_second);

/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */

static cpumask_t uv_target_cpus(void)
{
	return cpumask_of_cpu(0);
}

static cpumask_t uv_vector_allocation_domain(int cpu)
{
	cpumask_t domain = CPU_MASK_NONE;
	cpu_set(cpu, domain);
	return domain;
}

int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
{
	unsigned long val;
	int pnode;

	pnode = uv_apicid_to_pnode(phys_apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_INIT;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	mdelay(10);

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_STARTUP;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	return 0;
}

static void uv_send_IPI_one(int cpu, int vector)
{
	unsigned long val, apicid, lapicid;
	int pnode;

	apicid = per_cpu(x86_cpu_to_apicid, cpu);
	lapicid = apicid & 0x3f;		/* ZZZ macro needed */
	pnode = uv_apicid_to_pnode(apicid);
	val =
	    (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
					      UVH_IPI_INT_APIC_ID_SHFT) |
	    (vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

static void uv_send_IPI_mask(cpumask_t mask, int vector)
{
	unsigned int cpu;

	for_each_possible_cpu(cpu)
		if (cpu_isset(cpu, mask))
			uv_send_IPI_one(cpu, vector);
}

static void uv_send_IPI_allbutself(int vector)
{
	cpumask_t mask = cpu_online_map;

	cpu_clear(smp_processor_id(), mask);

	if (!cpus_empty(mask))
		uv_send_IPI_mask(mask, vector);
}

static void uv_send_IPI_all(int vector)
{
	uv_send_IPI_mask(cpu_online_map, vector);
}

static int uv_apic_id_registered(void)
{
	return 1;
}

static void uv_init_apic_ldr(void)
{
}

static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;

	/*
	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
	 * May as well be the first.
	 */
	cpu = first_cpu(cpumask);
	if ((unsigned)cpu < nr_cpu_ids)
		return per_cpu(x86_cpu_to_apicid, cpu);
	else
		return BAD_APICID;
}

static unsigned int get_apic_id(unsigned long x)
{
	unsigned int id;

	WARN_ON(preemptible() && num_online_cpus() > 1);
	id = x | __get_cpu_var(x2apic_extra_bits);

	return id;
}

static unsigned long set_apic_id(unsigned int id)
{
	unsigned long x;

	/* maskout x2apic_extra_bits ? */
	x = id;
	return x;
}

static unsigned int uv_read_apic_id(void)
{

	return get_apic_id(apic_read(APIC_ID));
}

static unsigned int phys_pkg_id(int index_msb)
{
	return uv_read_apic_id() >> index_msb;
}

static void uv_send_IPI_self(int vector)
{
	apic_write(APIC_SELF_IPI, vector);
}

struct genapic apic_x2apic_uv_x = {
	.name = "UV large system",
	.acpi_madt_oem_check = uv_acpi_madt_oem_check,
	.int_delivery_mode = dest_Fixed,
	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	.target_cpus = uv_target_cpus,
	.vector_allocation_domain = uv_vector_allocation_domain,
	.apic_id_registered = uv_apic_id_registered,
	.init_apic_ldr = uv_init_apic_ldr,
	.send_IPI_all = uv_send_IPI_all,
	.send_IPI_allbutself = uv_send_IPI_allbutself,
	.send_IPI_mask = uv_send_IPI_mask,
	.send_IPI_self = uv_send_IPI_self,
	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	.phys_pkg_id = phys_pkg_id,
	.get_apic_id = get_apic_id,
	.set_apic_id = set_apic_id,
	.apic_id_mask = (0xFFFFFFFFu),
};

static __cpuinit void set_x2apic_extra_bits(int pnode)
{
	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
}

/*
 * Called on boot cpu.
 */
static __init int boot_pnode_to_blade(int pnode)
{
	int blade;

	for (blade = 0; blade < uv_num_possible_blades(); blade++)
		if (pnode == uv_blade_info[blade].pnode)
			return blade;
	BUG();
}

struct redir_addr {
	unsigned long redirect;
	unsigned long alias;
};

#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT

static __initdata struct redir_addr redir_addrs[] = {
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
};

static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
{
	union uvh_si_alias0_overlay_config_u alias;
	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	int i;

	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
		alias.v = uv_read_local_mmr(redir_addrs[i].alias);
		if (alias.s.base == 0) {
			*size = (1UL << alias.s.m_alias);
			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
			return;
		}
	}
	BUG();
}

static __init void map_low_mmrs(void)
{
	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
}

enum map_type {map_wb, map_uc};

static __init void map_high(char *id, unsigned long base, int shift,
			    int max_pnode, enum map_type map_type)
{
	unsigned long bytes, paddr;

	paddr = base << shift;
	bytes = (1UL << shift) * (max_pnode + 1);
	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	       					paddr + bytes);
	if (map_type == map_uc)
		init_extra_mapping_uc(paddr, bytes);
	else
		init_extra_mapping_wb(paddr, bytes);

}
static __init void map_gru_high(int max_pnode)
{
	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;

	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	if (gru.s.enable)
		map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
}

static __init void map_config_high(int max_pnode)
{
	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;

	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	if (cfg.s.enable)
		map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
}

static __init void map_mmr_high(int max_pnode)
{
	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	if (mmr.s.enable)
		map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
}

static __init void map_mmioh_high(int max_pnode)
{
	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	if (mmioh.s.enable)
		map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
}

static __init void uv_rtc_init(void)
{
	long status;
	u64 ticks_per_sec;

	status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
					&ticks_per_sec);
	if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
		printk(KERN_WARNING
			"unable to determine platform RTC clock frequency, "
			"guessing.\n");
		/* BIOS gives wrong value for clock freq. so guess */
		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
	} else
		sn_rtc_cycles_per_second = ticks_per_sec;
}

/*
 * Called on each cpu to initialize the per_cpu UV data area.
 * 	ZZZ hotplug not supported yet
 */
void __cpuinit uv_cpu_init(void)
{
	/* CPU 0 initilization will be done via uv_system_init. */
	if (!uv_blade_info)
		return;

	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;

	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
		set_x2apic_extra_bits(uv_hub_info->pnode);
}


void __init uv_system_init(void)
{
	union uvh_si_addr_map_config_u m_n_config;
	union uvh_node_id_u node_id;
	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
	int max_pnode = 0;
	unsigned long mmr_base, present;

	map_low_mmrs();

	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
	m_val = m_n_config.s.m_skt;
	n_val = m_n_config.s.n_skt;
	mmr_base =
	    uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	    ~UV_MMR_ENABLE;
	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);

	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
		uv_possible_blades +=
		  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());

	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	uv_blade_info = kmalloc(bytes, GFP_KERNEL);

	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);

	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
	memset(uv_node_to_blade, 255, bytes);

	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
	memset(uv_cpu_to_blade, 255, bytes);

	blade = 0;
	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
		present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
		for (j = 0; j < 64; j++) {
			if (!test_bit(j, &present))
				continue;
			uv_blade_info[blade].pnode = (i * 64 + j);
			uv_blade_info[blade].nr_possible_cpus = 0;
			uv_blade_info[blade].nr_online_cpus = 0;
			blade++;
		}
	}

	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	gnode_upper = (((unsigned long)node_id.s.node_id) &
		       ~((1 << n_val) - 1)) << m_val;

	uv_bios_init();
	uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
			    &uv_coherency_id, &uv_region_size);
	uv_rtc_init();

	for_each_present_cpu(cpu) {
		nid = cpu_to_node(cpu);
		pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
		blade = boot_pnode_to_blade(pnode);
		lcpu = uv_blade_info[blade].nr_possible_cpus;
		uv_blade_info[blade].nr_possible_cpus++;

		uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
		uv_cpu_hub_info(cpu)->lowmem_remap_top =
					lowmem_redir_base + lowmem_redir_size;
		uv_cpu_hub_info(cpu)->m_val = m_val;
		uv_cpu_hub_info(cpu)->n_val = m_val;
		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
		uv_cpu_hub_info(cpu)->pnode = pnode;
		uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
		uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
		uv_cpu_hub_info(cpu)->coherency_domain_number = uv_coherency_id;
		uv_node_to_blade[nid] = blade;
		uv_cpu_to_blade[cpu] = blade;
		max_pnode = max(pnode, max_pnode);

		printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
			"lcpu %d, blade %d\n",
			cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
			lcpu, blade);
	}

	map_gru_high(max_pnode);
	map_mmr_high(max_pnode);
	map_config_high(max_pnode);
	map_mmioh_high(max_pnode);

	uv_cpu_init();
}
Commit	Line	Data
ac23d4ee JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV APIC functions (note: not an Intel compatible APIC)
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
ac23d4ee JS	9	*/
ac23d4ee JS	10
83f5d894	11	#include <linux/kernel.h>
ac23d4ee JS	12	#include <linux/threads.h>
	13	#include <linux/cpumask.h>
	14	#include <linux/string.h>
ac23d4ee JS	15	#include <linux/ctype.h>
	16	#include <linux/init.h>
	17	#include <linux/sched.h>
ac23d4ee	18	#include <linux/module.h>
0c81c746	19	#include <linux/hardirq.h>
ac23d4ee JS	20	#include <asm/smp.h>
	21	#include <asm/ipi.h>
	22	#include <asm/genapic.h>
83f5d894	23	#include <asm/pgtable.h>
ac23d4ee JS	24	#include <asm/uv/uv_mmrs.h>
ac23d4ee JS	25	#include <asm/uv/uv_hub.h>
7019cc2d	26	#include <asm/uv/bios.h>
ac23d4ee	27
510b3725 YL	28	DEFINE_PER_CPU(int, x2apic_extra_bits);
510b3725 YL	29
1b9b89e7 YL	30	static enum uv_system_type uv_system_type;
1b9b89e7 YL	31
f8827c01	32	static int uv_acpi_madt_oem_check(char oem_id, char oem_table_id)
1b9b89e7 YL	33	{
	34	if (!strcmp(oem_id, "SGI")) {
	35	if (!strcmp(oem_table_id, "UVL"))
	36	uv_system_type = UV_LEGACY_APIC;
	37	else if (!strcmp(oem_table_id, "UVX"))
	38	uv_system_type = UV_X2APIC;
	39	else if (!strcmp(oem_table_id, "UVH")) {
	40	uv_system_type = UV_NON_UNIQUE_APIC;
	41	return 1;
	42	}
	43	}
	44	return 0;
	45	}
	46
	47	enum uv_system_type get_uv_system_type(void)
	48	{
	49	return uv_system_type;
	50	}
	51
	52	int is_uv_system(void)
	53	{
	54	return uv_system_type != UV_NONE;
	55	}
8067794b	56	EXPORT_SYMBOL_GPL(is_uv_system);
1b9b89e7	57
ac23d4ee JS	58	DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	59	EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
	60
	61	struct uv_blade_info *uv_blade_info;
	62	EXPORT_SYMBOL_GPL(uv_blade_info);
	63
	64	short *uv_node_to_blade;
	65	EXPORT_SYMBOL_GPL(uv_node_to_blade);
	66
	67	short *uv_cpu_to_blade;
	68	EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
	69
	70	short uv_possible_blades;
	71	EXPORT_SYMBOL_GPL(uv_possible_blades);
	72
7019cc2d RA	73	unsigned long sn_rtc_cycles_per_second;
	74	EXPORT_SYMBOL(sn_rtc_cycles_per_second);
	75
ac23d4ee JS	76	/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
	77
	78	static cpumask_t uv_target_cpus(void)
	79	{
	80	return cpumask_of_cpu(0);
	81	}
	82
	83	static cpumask_t uv_vector_allocation_domain(int cpu)
	84	{
	85	cpumask_t domain = CPU_MASK_NONE;
	86	cpu_set(cpu, domain);
	87	return domain;
	88	}
	89
	90	int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
	91	{
	92	unsigned long val;
9f5314fb	93	int pnode;
ac23d4ee	94
9f5314fb	95	pnode = uv_apicid_to_pnode(phys_apicid);
ac23d4ee JS	96	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	97	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	98	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
34d05591	99	APIC_DM_INIT;
9f5314fb	100	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
34d05591 JS	101	mdelay(10);
	102
	103	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	104	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	105	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	106	APIC_DM_STARTUP;
9f5314fb	107	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	108	return 0;
	109	}
	110
	111	static void uv_send_IPI_one(int cpu, int vector)
	112	{
34d05591	113	unsigned long val, apicid, lapicid;
9f5314fb	114	int pnode;
ac23d4ee	115
1e0b5d00	116	apicid = per_cpu(x86_cpu_to_apicid, cpu);
34d05591	117	lapicid = apicid & 0x3f; /* ZZZ macro needed */
9f5314fb	118	pnode = uv_apicid_to_pnode(apicid);
ac23d4ee	119	val =
34d05591	120	(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<
ac23d4ee JS	121	UVH_IPI_INT_APIC_ID_SHFT) \|
ac23d4ee JS	122	(vector << UVH_IPI_INT_VECTOR_SHFT);
9f5314fb	123	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	124	}
	125
	126	static void uv_send_IPI_mask(cpumask_t mask, int vector)
	127	{
	128	unsigned int cpu;
	129
247bc6ca	130	for_each_possible_cpu(cpu)
ac23d4ee JS	131	if (cpu_isset(cpu, mask))
	132	uv_send_IPI_one(cpu, vector);
	133	}
	134
	135	static void uv_send_IPI_allbutself(int vector)
	136	{
	137	cpumask_t mask = cpu_online_map;
	138
	139	cpu_clear(smp_processor_id(), mask);
	140
	141	if (!cpus_empty(mask))
	142	uv_send_IPI_mask(mask, vector);
	143	}
	144
	145	static void uv_send_IPI_all(int vector)
	146	{
	147	uv_send_IPI_mask(cpu_online_map, vector);
	148	}
	149
	150	static int uv_apic_id_registered(void)
	151	{
	152	return 1;
	153	}
	154
277d1f58	155	static void uv_init_apic_ldr(void)
5c520a67 SS	156	{
	157	}
	158
ac23d4ee JS	159	static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
	160	{
	161	int cpu;
	162
	163	/*
	164	* We're using fixed IRQ delivery, can only return one phys APIC ID.
	165	* May as well be the first.
	166	*/
	167	cpu = first_cpu(cpumask);
247bc6ca	168	if ((unsigned)cpu < nr_cpu_ids)
ac23d4ee JS	169	return per_cpu(x86_cpu_to_apicid, cpu);
	170	else
	171	return BAD_APICID;
	172	}
	173
f910a9dc	174	static unsigned int get_apic_id(unsigned long x)
0c81c746 SS	175	{
	176	unsigned int id;
	177
	178	WARN_ON(preemptible() && num_online_cpus() > 1);
f910a9dc	179	id = x \| __get_cpu_var(x2apic_extra_bits);
0c81c746 SS	180
	181	return id;
	182	}
	183
1b9b89e7	184	static unsigned long set_apic_id(unsigned int id)
f910a9dc YL	185	{
	186	unsigned long x;
	187
	188	/* maskout x2apic_extra_bits ? */
	189	x = id;
	190	return x;
	191	}
	192
	193	static unsigned int uv_read_apic_id(void)
	194	{
	195
	196	return get_apic_id(apic_read(APIC_ID));
	197	}
	198
ac23d4ee JS	199	static unsigned int phys_pkg_id(int index_msb)
ac23d4ee JS	200	{
0c81c746	201	return uv_read_apic_id() >> index_msb;
ac23d4ee JS	202	}
ac23d4ee JS	203
ac23d4ee JS	204	static void uv_send_IPI_self(int vector)
	205	{
	206	apic_write(APIC_SELF_IPI, vector);
	207	}
ac23d4ee JS	208
	209	struct genapic apic_x2apic_uv_x = {
	210	.name = "UV large system",
1b9b89e7	211	.acpi_madt_oem_check = uv_acpi_madt_oem_check,
ac23d4ee JS	212	.int_delivery_mode = dest_Fixed,
	213	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	214	.target_cpus = uv_target_cpus,
1e0b5d00	215	.vector_allocation_domain = uv_vector_allocation_domain,
ac23d4ee	216	.apic_id_registered = uv_apic_id_registered,
5c520a67	217	.init_apic_ldr = uv_init_apic_ldr,
ac23d4ee JS	218	.send_IPI_all = uv_send_IPI_all,
	219	.send_IPI_allbutself = uv_send_IPI_allbutself,
	220	.send_IPI_mask = uv_send_IPI_mask,
1e0b5d00	221	.send_IPI_self = uv_send_IPI_self,
ac23d4ee	222	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
1e0b5d00	223	.phys_pkg_id = phys_pkg_id,
f910a9dc YL	224	.get_apic_id = get_apic_id,
	225	.set_apic_id = set_apic_id,
	226	.apic_id_mask = (0xFFFFFFFFu),
ac23d4ee JS	227	};
ac23d4ee JS	228
9f5314fb	229	static __cpuinit void set_x2apic_extra_bits(int pnode)
ac23d4ee	230	{
9f5314fb	231	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
ac23d4ee JS	232	}
	233
	234	/*
	235	* Called on boot cpu.
	236	*/
9f5314fb JS	237	static __init int boot_pnode_to_blade(int pnode)
	238	{
	239	int blade;
	240
	241	for (blade = 0; blade < uv_num_possible_blades(); blade++)
	242	if (pnode == uv_blade_info[blade].pnode)
	243	return blade;
	244	BUG();
	245	}
	246
	247	struct redir_addr {
	248	unsigned long redirect;
	249	unsigned long alias;
	250	};
	251
	252	#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
	253
	254	static __initdata struct redir_addr redir_addrs[] = {
	255	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	256	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	257	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
	258	};
	259
	260	static __init void get_lowmem_redirect(unsigned long base, unsigned long size)
	261	{
	262	union uvh_si_alias0_overlay_config_u alias;
	263	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	264	int i;
	265
	266	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
	267	alias.v = uv_read_local_mmr(redir_addrs[i].alias);
	268	if (alias.s.base == 0) {
	269	*size = (1UL << alias.s.m_alias);
	270	redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
	271	*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
	272	return;
	273	}
	274	}
	275	BUG();
	276	}
	277
83f5d894 JS	278	static __init void map_low_mmrs(void)
	279	{
	280	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	281	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
	282	}
	283
	284	enum map_type {map_wb, map_uc};
	285
d2f904bb JS	286	static __init void map_high(char *id, unsigned long base, int shift,
d2f904bb JS	287	int max_pnode, enum map_type map_type)
83f5d894 JS	288	{
	289	unsigned long bytes, paddr;
	290
	291	paddr = base << shift;
d2f904bb	292	bytes = (1UL << shift) * (max_pnode + 1);
83f5d894 JS	293	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	294	paddr + bytes);
	295	if (map_type == map_uc)
	296	init_extra_mapping_uc(paddr, bytes);
	297	else
	298	init_extra_mapping_wb(paddr, bytes);
	299
	300	}
	301	static __init void map_gru_high(int max_pnode)
	302	{
	303	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	304	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
	305
	306	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	307	if (gru.s.enable)
d2f904bb	308	map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
83f5d894 JS	309	}
	310
	311	static __init void map_config_high(int max_pnode)
	312	{
	313	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	314	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
	315
	316	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	317	if (cfg.s.enable)
d2f904bb	318	map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
83f5d894 JS	319	}
	320
	321	static __init void map_mmr_high(int max_pnode)
	322	{
	323	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	324	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
	325
	326	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	327	if (mmr.s.enable)
d2f904bb	328	map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
83f5d894 JS	329	}
	330
	331	static __init void map_mmioh_high(int max_pnode)
	332	{
	333	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	334	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
	335
	336	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	337	if (mmioh.s.enable)
d2f904bb	338	map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
83f5d894 JS	339	}
83f5d894 JS	340
7019cc2d RA	341	static __init void uv_rtc_init(void)
7019cc2d RA	342	{
922402f1 RA	343	long status;
922402f1 RA	344	u64 ticks_per_sec;
7019cc2d	345
922402f1 RA	346	status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
	347	&ticks_per_sec);
	348	if (status != BIOS_STATUS_SUCCESS \|\| ticks_per_sec < 100000) {
7019cc2d RA	349	printk(KERN_WARNING
	350	"unable to determine platform RTC clock frequency, "
	351	"guessing.\n");
	352	/* BIOS gives wrong value for clock freq. so guess */
	353	sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
	354	} else
	355	sn_rtc_cycles_per_second = ticks_per_sec;
	356	}
	357
8da077d6 JS	358	/*
	359	* Called on each cpu to initialize the per_cpu UV data area.
	360	* ZZZ hotplug not supported yet
	361	*/
	362	void __cpuinit uv_cpu_init(void)
	363	{
	364	/* CPU 0 initilization will be done via uv_system_init. */
	365	if (!uv_blade_info)
	366	return;
	367
	368	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
	369
	370	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
	371	set_x2apic_extra_bits(uv_hub_info->pnode);
	372	}
	373
c4bd1fda MS	374
c4bd1fda MS	375	void __init uv_system_init(void)
ac23d4ee JS	376	{
ac23d4ee JS	377	union uvh_si_addr_map_config_u m_n_config;
9f5314fb JS	378	union uvh_node_id_u node_id;
	379	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	380	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
83f5d894	381	int max_pnode = 0;
9f5314fb	382	unsigned long mmr_base, present;
ac23d4ee	383
83f5d894 JS	384	map_low_mmrs();
83f5d894 JS	385
ac23d4ee	386	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
9f5314fb JS	387	m_val = m_n_config.s.m_skt;
9f5314fb JS	388	n_val = m_n_config.s.n_skt;
ac23d4ee JS	389	mmr_base =
	390	uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	391	~UV_MMR_ENABLE;
	392	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
	393
9f5314fb JS	394	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
	395	uv_possible_blades +=
	396	hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
ac23d4ee JS	397	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
	398
	399	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
ef020ab0	400	uv_blade_info = kmalloc(bytes, GFP_KERNEL);
ac23d4ee	401
9f5314fb JS	402	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
9f5314fb JS	403
ac23d4ee	404	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
ef020ab0	405	uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
ac23d4ee JS	406	memset(uv_node_to_blade, 255, bytes);
	407
	408	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
ef020ab0	409	uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
ac23d4ee JS	410	memset(uv_cpu_to_blade, 255, bytes);
ac23d4ee JS	411
9f5314fb JS	412	blade = 0;
	413	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
	414	present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
	415	for (j = 0; j < 64; j++) {
	416	if (!test_bit(j, &present))
	417	continue;
	418	uv_blade_info[blade].pnode = (i * 64 + j);
	419	uv_blade_info[blade].nr_possible_cpus = 0;
ac23d4ee	420	uv_blade_info[blade].nr_online_cpus = 0;
9f5314fb	421	blade++;
ac23d4ee	422	}
9f5314fb	423	}
ac23d4ee	424
9f5314fb JS	425	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	426	gnode_upper = (((unsigned long)node_id.s.node_id) &
	427	~((1 << n_val) - 1)) << m_val;
	428
7f594232	429	uv_bios_init();
922402f1 RA	430	uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
922402f1 RA	431	&uv_coherency_id, &uv_region_size);
7019cc2d RA	432	uv_rtc_init();
7019cc2d RA	433
9f5314fb JS	434	for_each_present_cpu(cpu) {
	435	nid = cpu_to_node(cpu);
	436	pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
	437	blade = boot_pnode_to_blade(pnode);
	438	lcpu = uv_blade_info[blade].nr_possible_cpus;
	439	uv_blade_info[blade].nr_possible_cpus++;
	440
	441	uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
	442	uv_cpu_hub_info(cpu)->lowmem_remap_top =
	443	lowmem_redir_base + lowmem_redir_size;
	444	uv_cpu_hub_info(cpu)->m_val = m_val;
	445	uv_cpu_hub_info(cpu)->n_val = m_val;
ac23d4ee JS	446	uv_cpu_hub_info(cpu)->numa_blade_id = blade;
ac23d4ee JS	447	uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
9f5314fb JS	448	uv_cpu_hub_info(cpu)->pnode = pnode;
	449	uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
	450	uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
	451	uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
ac23d4ee	452	uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
922402f1	453	uv_cpu_hub_info(cpu)->coherency_domain_number = uv_coherency_id;
ac23d4ee JS	454	uv_node_to_blade[nid] = blade;
ac23d4ee JS	455	uv_cpu_to_blade[cpu] = blade;
83f5d894	456	max_pnode = max(pnode, max_pnode);
ac23d4ee	457
83f5d894	458	printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
9f5314fb JS	459	"lcpu %d, blade %d\n",
	460	cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
	461	lcpu, blade);
ac23d4ee	462	}
83f5d894 JS	463
	464	map_gru_high(max_pnode);
	465	map_mmr_high(max_pnode);
	466	map_config_high(max_pnode);
	467	map_mmioh_high(max_pnode);
ac23d4ee	468
8da077d6	469	uv_cpu_init();
ac23d4ee	470	}