[net-next-2.6.git] / arch / x86 / kernel / cpu / perf_event_intel_ds.c

#ifdef CONFIG_CPU_SUP_INTEL

/* The maximal number of PEBS events: */
#define MAX_PEBS_EVENTS		4

/* The size of a BTS record in bytes: */
#define BTS_RECORD_SIZE		24

#define BTS_BUFFER_SIZE		(PAGE_SIZE << 4)
#define PEBS_BUFFER_SIZE	PAGE_SIZE

/*
 * pebs_record_32 for p4 and core not supported

struct pebs_record_32 {
	u32 flags, ip;
	u32 ax, bc, cx, dx;
	u32 si, di, bp, sp;
};

 */

struct pebs_record_core {
	u64 flags, ip;
	u64 ax, bx, cx, dx;
	u64 si, di, bp, sp;
	u64 r8,  r9,  r10, r11;
	u64 r12, r13, r14, r15;
};

struct pebs_record_nhm {
	u64 flags, ip;
	u64 ax, bx, cx, dx;
	u64 si, di, bp, sp;
	u64 r8,  r9,  r10, r11;
	u64 r12, r13, r14, r15;
	u64 status, dla, dse, lat;
};

/*
 * Bits in the debugctlmsr controlling branch tracing.
 */
#define X86_DEBUGCTL_TR			(1 << 6)
#define X86_DEBUGCTL_BTS		(1 << 7)
#define X86_DEBUGCTL_BTINT		(1 << 8)
#define X86_DEBUGCTL_BTS_OFF_OS		(1 << 9)
#define X86_DEBUGCTL_BTS_OFF_USR	(1 << 10)

/*
 * A debug store configuration.
 *
 * We only support architectures that use 64bit fields.
 */
struct debug_store {
	u64	bts_buffer_base;
	u64	bts_index;
	u64	bts_absolute_maximum;
	u64	bts_interrupt_threshold;
	u64	pebs_buffer_base;
	u64	pebs_index;
	u64	pebs_absolute_maximum;
	u64	pebs_interrupt_threshold;
	u64	pebs_event_reset[MAX_PEBS_EVENTS];
};

static void init_debug_store_on_cpu(int cpu)
{
	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;

	if (!ds)
		return;

	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
		     (u32)((u64)(unsigned long)ds),
		     (u32)((u64)(unsigned long)ds >> 32));
}

static void fini_debug_store_on_cpu(int cpu)
{
	if (!per_cpu(cpu_hw_events, cpu).ds)
		return;

	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
}

static void release_ds_buffers(void)
{
	int cpu;

	if (!x86_pmu.bts && !x86_pmu.pebs)
		return;

	get_online_cpus();

	for_each_online_cpu(cpu)
		fini_debug_store_on_cpu(cpu);

	for_each_possible_cpu(cpu) {
		struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;

		if (!ds)
			continue;

		per_cpu(cpu_hw_events, cpu).ds = NULL;

		kfree((void *)(unsigned long)ds->pebs_buffer_base);
		kfree((void *)(unsigned long)ds->bts_buffer_base);
		kfree(ds);
	}

	put_online_cpus();
}

static int reserve_ds_buffers(void)
{
	int cpu, err = 0;

	if (!x86_pmu.bts && !x86_pmu.pebs)
		return 0;

	get_online_cpus();

	for_each_possible_cpu(cpu) {
		struct debug_store *ds;
		void *buffer;
		int max, thresh;

		err = -ENOMEM;
		ds = kzalloc(sizeof(*ds), GFP_KERNEL);
		if (unlikely(!ds))
			break;
		per_cpu(cpu_hw_events, cpu).ds = ds;

		if (x86_pmu.bts) {
			buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
			if (unlikely(!buffer))
				break;

			max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
			thresh = max / 16;

			ds->bts_buffer_base = (u64)(unsigned long)buffer;
			ds->bts_index = ds->bts_buffer_base;
			ds->bts_absolute_maximum = ds->bts_buffer_base +
				max * BTS_RECORD_SIZE;
			ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
				thresh * BTS_RECORD_SIZE;
		}

		if (x86_pmu.pebs) {
			buffer = kzalloc(PEBS_BUFFER_SIZE, GFP_KERNEL);
			if (unlikely(!buffer))
				break;

			max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;

			ds->pebs_buffer_base = (u64)(unsigned long)buffer;
			ds->pebs_index = ds->pebs_buffer_base;
			ds->pebs_absolute_maximum = ds->pebs_buffer_base +
				max * x86_pmu.pebs_record_size;
			/*
			 * Always use single record PEBS
			 */
			ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
				x86_pmu.pebs_record_size;
		}

		err = 0;
	}

	if (err)
		release_ds_buffers();
	else {
		for_each_online_cpu(cpu)
			init_debug_store_on_cpu(cpu);
	}

	put_online_cpus();

	return err;
}

/*
 * BTS
 */

static struct event_constraint bts_constraint =
	EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);

static void intel_pmu_enable_bts(u64 config)
{
	unsigned long debugctlmsr;

	debugctlmsr = get_debugctlmsr();

	debugctlmsr |= X86_DEBUGCTL_TR;
	debugctlmsr |= X86_DEBUGCTL_BTS;
	debugctlmsr |= X86_DEBUGCTL_BTINT;

	if (!(config & ARCH_PERFMON_EVENTSEL_OS))
		debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;

	if (!(config & ARCH_PERFMON_EVENTSEL_USR))
		debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;

	update_debugctlmsr(debugctlmsr);
}

static void intel_pmu_disable_bts(void)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	unsigned long debugctlmsr;

	if (!cpuc->ds)
		return;

	debugctlmsr = get_debugctlmsr();

	debugctlmsr &=
		~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
		  X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);

	update_debugctlmsr(debugctlmsr);
}

static void intel_pmu_drain_bts_buffer(void)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct debug_store *ds = cpuc->ds;
	struct bts_record {
		u64	from;
		u64	to;
		u64	flags;
	};
	struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
	struct bts_record *at, *top;
	struct perf_output_handle handle;
	struct perf_event_header header;
	struct perf_sample_data data;
	struct pt_regs regs;

	if (!event)
		return;

	if (!ds)
		return;

	at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
	top = (struct bts_record *)(unsigned long)ds->bts_index;

	if (top <= at)
		return;

	ds->bts_index = ds->bts_buffer_base;

	perf_sample_data_init(&data, 0);
	data.period = event->hw.last_period;
	regs.ip     = 0;

	/*
	 * Prepare a generic sample, i.e. fill in the invariant fields.
	 * We will overwrite the from and to address before we output
	 * the sample.
	 */
	perf_prepare_sample(&header, &data, event, &regs);

	if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1))
		return;

	for (; at < top; at++) {
		data.ip		= at->from;
		data.addr	= at->to;

		perf_output_sample(&handle, &header, &data, event);
	}

	perf_output_end(&handle);

	/* There's new data available. */
	event->hw.interrupts++;
	event->pending_kill = POLL_IN;
}

/*
 * PEBS
 */

static struct event_constraint intel_core_pebs_events[] = {
	PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
	PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
	PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
	PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
	PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
	PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
	PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
	PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
	PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
	EVENT_CONSTRAINT_END
};

static struct event_constraint intel_nehalem_pebs_events[] = {
	PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
	PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
	PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
	PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
	PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
	PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
	PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
	PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
	PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
	EVENT_CONSTRAINT_END
};

static struct event_constraint *
intel_pebs_constraints(struct perf_event *event)
{
	struct event_constraint *c;

	if (!event->attr.precise)
		return NULL;

	if (x86_pmu.pebs_constraints) {
		for_each_event_constraint(c, x86_pmu.pebs_constraints) {
			if ((event->hw.config & c->cmask) == c->code)
				return c;
		}
	}

	return &emptyconstraint;
}

static void intel_pmu_pebs_enable(struct perf_event *event)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;
	u64 val = cpuc->pebs_enabled;

	hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;

	val |= 1ULL << hwc->idx;
	wrmsrl(MSR_IA32_PEBS_ENABLE, val);

	if (x86_pmu.intel_cap.pebs_trap)
		intel_pmu_lbr_enable(event);
}

static void intel_pmu_pebs_disable(struct perf_event *event)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;
	u64 val = cpuc->pebs_enabled;

	val &= ~(1ULL << hwc->idx);
	wrmsrl(MSR_IA32_PEBS_ENABLE, val);

	hwc->config |= ARCH_PERFMON_EVENTSEL_INT;

	if (x86_pmu.intel_cap.pebs_trap)
		intel_pmu_lbr_disable(event);
}

static void intel_pmu_pebs_enable_all(void)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);

	if (cpuc->pebs_enabled)
		wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
}

static void intel_pmu_pebs_disable_all(void)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);

	if (cpuc->pebs_enabled)
		wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
}

#include <asm/insn.h>

static inline bool kernel_ip(unsigned long ip)
{
#ifdef CONFIG_X86_32
	return ip > PAGE_OFFSET;
#else
	return (long)ip < 0;
#endif
}

static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	unsigned long from = cpuc->lbr_entries[0].from;
	unsigned long old_to, to = cpuc->lbr_entries[0].to;
	unsigned long ip = regs->ip;

	/*
	 * We don't need to fixup if the PEBS assist is fault like
	 */
	if (!x86_pmu.intel_cap.pebs_trap)
		return 1;

	if (!cpuc->lbr_stack.nr || !from || !to)
		return 0;

	if (ip < to)
		return 0;

	/*
	 * We sampled a branch insn, rewind using the LBR stack
	 */
	if (ip == to) {
		regs->ip = from;
		return 1;
	}

	do {
		struct insn insn;
		u8 buf[MAX_INSN_SIZE];
		void *kaddr;

		old_to = to;
		if (!kernel_ip(ip)) {
			int bytes, size = min_t(int, MAX_INSN_SIZE, ip - to);

			bytes = copy_from_user_nmi(buf, (void __user *)to, size);
			if (bytes != size)
				return 0;

			kaddr = buf;
		} else
			kaddr = (void *)to;

		kernel_insn_init(&insn, kaddr);
		insn_get_length(&insn);
		to += insn.length;
	} while (to < ip);

	if (to == ip) {
		regs->ip = old_to;
		return 1;
	}

	return 0;
}

static int intel_pmu_save_and_restart(struct perf_event *event);
static void intel_pmu_disable_event(struct perf_event *event);

static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct debug_store *ds = cpuc->ds;
	struct perf_event *event = cpuc->events[0]; /* PMC0 only */
	struct pebs_record_core *at, *top;
	struct perf_sample_data data;
	struct perf_raw_record raw;
	struct pt_regs regs;
	int n;

	if (!event || !ds || !x86_pmu.pebs)
		return;

	intel_pmu_pebs_disable_all();

	at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
	top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;

	if (top <= at)
		goto out;

	ds->pebs_index = ds->pebs_buffer_base;

	if (!intel_pmu_save_and_restart(event))
		goto out;

	perf_sample_data_init(&data, 0);
	data.period = event->hw.last_period;

	if (event->attr.sample_type & PERF_SAMPLE_RAW) {
		raw.size = x86_pmu.pebs_record_size;
		raw.data = at;
		data.raw = &raw;
	}

	n = top - at;

	/*
	 * Should not happen, we program the threshold at 1 and do not
	 * set a reset value.
	 */
	WARN_ON_ONCE(n > 1);

	/*
	 * We use the interrupt regs as a base because the PEBS record
	 * does not contain a full regs set, specifically it seems to
	 * lack segment descriptors, which get used by things like
	 * user_mode().
	 *
	 * In the simple case fix up only the IP and BP,SP regs, for
	 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
	 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
	 */
	regs = *iregs;
	regs.ip = at->ip;
	regs.bp = at->bp;
	regs.sp = at->sp;

	if (intel_pmu_pebs_fixup_ip(&regs))
		regs.flags |= PERF_EFLAGS_EXACT;
	else
		regs.flags &= ~PERF_EFLAGS_EXACT;

	if (perf_event_overflow(event, 1, &data, &regs))
		intel_pmu_disable_event(event);

out:
	intel_pmu_pebs_enable_all();
}

static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
{
	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	struct debug_store *ds = cpuc->ds;
	struct pebs_record_nhm *at, *top;
	struct perf_sample_data data;
	struct perf_event *event = NULL;
	struct perf_raw_record raw;
	struct pt_regs regs;
	int bit, n;

	if (!ds || !x86_pmu.pebs)
		return;

	intel_pmu_pebs_disable_all();

	at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
	top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;

	if (top <= at)
		goto out;

	ds->pebs_index = ds->pebs_buffer_base;

	n = top - at;

	/*
	 * Should not happen, we program the threshold at 1 and do not
	 * set a reset value.
	 */
	WARN_ON_ONCE(n > MAX_PEBS_EVENTS);

	for ( ; at < top; at++) {
		for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
			if (!cpuc->events[bit]->attr.precise)
				continue;

			event = cpuc->events[bit];
		}

		if (!event)
			continue;

		if (!intel_pmu_save_and_restart(event))
			continue;

		perf_sample_data_init(&data, 0);
		data.period = event->hw.last_period;

		if (event->attr.sample_type & PERF_SAMPLE_RAW) {
			raw.size = x86_pmu.pebs_record_size;
			raw.data = at;
			data.raw = &raw;
		}

		/*
		 * See the comment in intel_pmu_drain_pebs_core()
		 */
		regs = *iregs;
		regs.ip = at->ip;
		regs.bp = at->bp;
		regs.sp = at->sp;

		if (intel_pmu_pebs_fixup_ip(&regs))
			regs.flags |= PERF_EFLAGS_EXACT;
		else
			regs.flags &= ~PERF_EFLAGS_EXACT;

		if (perf_event_overflow(event, 1, &data, &regs))
			intel_pmu_disable_event(event);
	}
out:
	intel_pmu_pebs_enable_all();
}

/*
 * BTS, PEBS probe and setup
 */

static void intel_ds_init(void)
{
	/*
	 * No support for 32bit formats
	 */
	if (!boot_cpu_has(X86_FEATURE_DTES64))
		return;

	x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
	if (x86_pmu.pebs) {
		char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
		int format = x86_pmu.intel_cap.pebs_format;

		switch (format) {
		case 0:
			printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
			x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
			x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
			x86_pmu.pebs_constraints = intel_core_pebs_events;
			break;

		case 1:
			printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
			x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
			x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
			x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
			break;

		default:
			printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
			x86_pmu.pebs = 0;
			break;
		}
	}
}

#else /* CONFIG_CPU_SUP_INTEL */

static int reseve_ds_buffers(void)
{
	return 0;
}

static void release_ds_buffers(void)
{
}

#endif /* CONFIG_CPU_SUP_INTEL */
Commit	Line	Data
ca037701 PZ	1	#ifdef CONFIG_CPU_SUP_INTEL
	2
	3	/* The maximal number of PEBS events: */
	4	#define MAX_PEBS_EVENTS 4
	5
	6	/* The size of a BTS record in bytes: */
	7	#define BTS_RECORD_SIZE 24
	8
	9	#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
	10	#define PEBS_BUFFER_SIZE PAGE_SIZE
	11
	12	/*
	13	* pebs_record_32 for p4 and core not supported
	14
	15	struct pebs_record_32 {
	16	u32 flags, ip;
	17	u32 ax, bc, cx, dx;
	18	u32 si, di, bp, sp;
	19	};
	20
	21	*/
	22
	23	struct pebs_record_core {
	24	u64 flags, ip;
	25	u64 ax, bx, cx, dx;
	26	u64 si, di, bp, sp;
	27	u64 r8, r9, r10, r11;
	28	u64 r12, r13, r14, r15;
	29	};
	30
	31	struct pebs_record_nhm {
	32	u64 flags, ip;
	33	u64 ax, bx, cx, dx;
	34	u64 si, di, bp, sp;
	35	u64 r8, r9, r10, r11;
	36	u64 r12, r13, r14, r15;
	37	u64 status, dla, dse, lat;
	38	};
	39
	40	/*
	41	* Bits in the debugctlmsr controlling branch tracing.
	42	*/
	43	#define X86_DEBUGCTL_TR (1 << 6)
	44	#define X86_DEBUGCTL_BTS (1 << 7)
	45	#define X86_DEBUGCTL_BTINT (1 << 8)
	46	#define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
	47	#define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
	48
	49	/*
	50	* A debug store configuration.
	51	*
	52	* We only support architectures that use 64bit fields.
	53	*/
	54	struct debug_store {
	55	u64 bts_buffer_base;
	56	u64 bts_index;
	57	u64 bts_absolute_maximum;
	58	u64 bts_interrupt_threshold;
	59	u64 pebs_buffer_base;
	60	u64 pebs_index;
	61	u64 pebs_absolute_maximum;
	62	u64 pebs_interrupt_threshold;
	63	u64 pebs_event_reset[MAX_PEBS_EVENTS];
	64	};
65
66	static void init_debug_store_on_cpu(int cpu)
67	{
68	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
69
70	if (!ds)
71	return;
72
73	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
74	(u32)((u64)(unsigned long)ds),
75	(u32)((u64)(unsigned long)ds >> 32));
76	}
77
78	static void fini_debug_store_on_cpu(int cpu)
79	{
80	if (!per_cpu(cpu_hw_events, cpu).ds)
81	return;
82
83	wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
84	}
85
86	static void release_ds_buffers(void)
87	{
88	int cpu;
89
90	if (!x86_pmu.bts && !x86_pmu.pebs)
91	return;
92
93	get_online_cpus();
94
95	for_each_online_cpu(cpu)
96	fini_debug_store_on_cpu(cpu);
97
98	for_each_possible_cpu(cpu) {
99	struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
100
101	if (!ds)
102	continue;
103
104	per_cpu(cpu_hw_events, cpu).ds = NULL;
105
106	kfree((void *)(unsigned long)ds->pebs_buffer_base);
107	kfree((void *)(unsigned long)ds->bts_buffer_base);
108	kfree(ds);
109	}
110
111	put_online_cpus();
112	}
113
114	static int reserve_ds_buffers(void)
115	{
116	int cpu, err = 0;
117
118	if (!x86_pmu.bts && !x86_pmu.pebs)
119	return 0;
120
121	get_online_cpus();
122
123	for_each_possible_cpu(cpu) {
124	struct debug_store *ds;
125	void *buffer;
126	int max, thresh;
127
128	err = -ENOMEM;
129	ds = kzalloc(sizeof(*ds), GFP_KERNEL);
3adaebd6	130	if (unlikely(!ds))
ca037701	131	break;
ca037701 PZ	132	per_cpu(cpu_hw_events, cpu).ds = ds;
	133
	134	if (x86_pmu.bts) {
	135	buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
	136	if (unlikely(!buffer))
	137	break;
	138
	139	max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
	140	thresh = max / 16;
	141
	142	ds->bts_buffer_base = (u64)(unsigned long)buffer;
	143	ds->bts_index = ds->bts_buffer_base;
	144	ds->bts_absolute_maximum = ds->bts_buffer_base +
	145	max * BTS_RECORD_SIZE;
	146	ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
	147	thresh * BTS_RECORD_SIZE;
	148	}
	149
	150	if (x86_pmu.pebs) {
	151	buffer = kzalloc(PEBS_BUFFER_SIZE, GFP_KERNEL);
	152	if (unlikely(!buffer))
	153	break;
	154
	155	max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
	156
	157	ds->pebs_buffer_base = (u64)(unsigned long)buffer;
	158	ds->pebs_index = ds->pebs_buffer_base;
	159	ds->pebs_absolute_maximum = ds->pebs_buffer_base +
	160	max * x86_pmu.pebs_record_size;
	161	/*
	162	* Always use single record PEBS
	163	*/
	164	ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
	165	x86_pmu.pebs_record_size;
	166	}
	167
	168	err = 0;
	169	}
	170
	171	if (err)
	172	release_ds_buffers();
	173	else {
	174	for_each_online_cpu(cpu)
	175	init_debug_store_on_cpu(cpu);
	176	}
	177
	178	put_online_cpus();
	179
	180	return err;
	181	}
	182
	183	/*
	184	* BTS
	185	*/
	186
	187	static struct event_constraint bts_constraint =
	188	EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
	189
	190	static void intel_pmu_enable_bts(u64 config)
	191	{
	192	unsigned long debugctlmsr;
	193
	194	debugctlmsr = get_debugctlmsr();
	195
196	debugctlmsr \|= X86_DEBUGCTL_TR;
197	debugctlmsr \|= X86_DEBUGCTL_BTS;
198	debugctlmsr \|= X86_DEBUGCTL_BTINT;
199
200	if (!(config & ARCH_PERFMON_EVENTSEL_OS))
201	debugctlmsr \|= X86_DEBUGCTL_BTS_OFF_OS;
202
203	if (!(config & ARCH_PERFMON_EVENTSEL_USR))
204	debugctlmsr \|= X86_DEBUGCTL_BTS_OFF_USR;
205
206	update_debugctlmsr(debugctlmsr);
207	}
208
209	static void intel_pmu_disable_bts(void)
210	{
211	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
212	unsigned long debugctlmsr;
213
214	if (!cpuc->ds)
215	return;
216
217	debugctlmsr = get_debugctlmsr();
218
219	debugctlmsr &=
220	~(X86_DEBUGCTL_TR \| X86_DEBUGCTL_BTS \| X86_DEBUGCTL_BTINT \|
221	X86_DEBUGCTL_BTS_OFF_OS \| X86_DEBUGCTL_BTS_OFF_USR);
222
223	update_debugctlmsr(debugctlmsr);
224	}
225
226	static void intel_pmu_drain_bts_buffer(void)
227	{
228	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
229	struct debug_store *ds = cpuc->ds;
230	struct bts_record {
231	u64 from;
232	u64 to;
233	u64 flags;
234	};
235	struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
236	struct bts_record at, top;
237	struct perf_output_handle handle;
238	struct perf_event_header header;
239	struct perf_sample_data data;
240	struct pt_regs regs;
241
242	if (!event)
243	return;
244
245	if (!ds)
246	return;
247
248	at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
249	top = (struct bts_record *)(unsigned long)ds->bts_index;
250
251	if (top <= at)
252	return;
253
254	ds->bts_index = ds->bts_buffer_base;
255
256	perf_sample_data_init(&data, 0);
257	data.period = event->hw.last_period;
258	regs.ip = 0;
259
260	/*
261	* Prepare a generic sample, i.e. fill in the invariant fields.
262	* We will overwrite the from and to address before we output
263	* the sample.
264	*/
265	perf_prepare_sample(&header, &data, event, &regs);
266
267	if (perf_output_begin(&handle, event, header.size * (top - at), 1, 1))
268	return;
269
270	for (; at < top; at++) {
271	data.ip = at->from;
272	data.addr = at->to;
273
274	perf_output_sample(&handle, &header, &data, event);
275	}
276
277	perf_output_end(&handle);
278
279	/* There's new data available. */
280	event->hw.interrupts++;
281	event->pending_kill = POLL_IN;
282	}
283
284	/*
285	* PEBS
286	*/
287
288	static struct event_constraint intel_core_pebs_events[] = {
289	PEBS_EVENT_CONSTRAINT(0x00c0, 0x1), /* INSTR_RETIRED.ANY */
290	PEBS_EVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
291	PEBS_EVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
292	PEBS_EVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
293	PEBS_EVENT_CONSTRAINT(0x01cb, 0x1), /* MEM_LOAD_RETIRED.L1D_MISS */
294	PEBS_EVENT_CONSTRAINT(0x02cb, 0x1), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
295	PEBS_EVENT_CONSTRAINT(0x04cb, 0x1), /* MEM_LOAD_RETIRED.L2_MISS */
296	PEBS_EVENT_CONSTRAINT(0x08cb, 0x1), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
297	PEBS_EVENT_CONSTRAINT(0x10cb, 0x1), /* MEM_LOAD_RETIRED.DTLB_MISS */
298	EVENT_CONSTRAINT_END
299	};
300
301	static struct event_constraint intel_nehalem_pebs_events[] = {
302	PEBS_EVENT_CONSTRAINT(0x00c0, 0xf), /* INSTR_RETIRED.ANY */
303	PEBS_EVENT_CONSTRAINT(0xfec1, 0xf), /* X87_OPS_RETIRED.ANY */
304	PEBS_EVENT_CONSTRAINT(0x00c5, 0xf), /* BR_INST_RETIRED.MISPRED */
305	PEBS_EVENT_CONSTRAINT(0x1fc7, 0xf), /* SIMD_INST_RETURED.ANY */
306	PEBS_EVENT_CONSTRAINT(0x01cb, 0xf), /* MEM_LOAD_RETIRED.L1D_MISS */
307	PEBS_EVENT_CONSTRAINT(0x02cb, 0xf), /* MEM_LOAD_RETIRED.L1D_LINE_MISS */
308	PEBS_EVENT_CONSTRAINT(0x04cb, 0xf), /* MEM_LOAD_RETIRED.L2_MISS */
309	PEBS_EVENT_CONSTRAINT(0x08cb, 0xf), /* MEM_LOAD_RETIRED.L2_LINE_MISS */
310	PEBS_EVENT_CONSTRAINT(0x10cb, 0xf), /* MEM_LOAD_RETIRED.DTLB_MISS */
311	EVENT_CONSTRAINT_END
312	};
313
314	static struct event_constraint *
315	intel_pebs_constraints(struct perf_event *event)
316	{
317	struct event_constraint *c;
318
319	if (!event->attr.precise)
320	return NULL;
321
322	if (x86_pmu.pebs_constraints) {
323	for_each_event_constraint(c, x86_pmu.pebs_constraints) {
324	if ((event->hw.config & c->cmask) == c->code)
325	return c;
326	}
327	}
328
329	return &emptyconstraint;
330	}
331
ef21f683	332	static void intel_pmu_pebs_enable(struct perf_event *event)
ca037701 PZ	333	{
ca037701 PZ	334	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
ef21f683	335	struct hw_perf_event *hwc = &event->hw;
ca037701 PZ	336	u64 val = cpuc->pebs_enabled;
	337
	338	hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
	339
	340	val \|= 1ULL << hwc->idx;
	341	wrmsrl(MSR_IA32_PEBS_ENABLE, val);
ef21f683	342
8db909a7 PZ	343	if (x86_pmu.intel_cap.pebs_trap)
8db909a7 PZ	344	intel_pmu_lbr_enable(event);
ca037701 PZ	345	}
ca037701 PZ	346
ef21f683	347	static void intel_pmu_pebs_disable(struct perf_event *event)
ca037701 PZ	348	{
ca037701 PZ	349	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
ef21f683	350	struct hw_perf_event *hwc = &event->hw;
ca037701 PZ	351	u64 val = cpuc->pebs_enabled;
	352
	353	val &= ~(1ULL << hwc->idx);
	354	wrmsrl(MSR_IA32_PEBS_ENABLE, val);
	355
	356	hwc->config \|= ARCH_PERFMON_EVENTSEL_INT;
ef21f683	357
8db909a7 PZ	358	if (x86_pmu.intel_cap.pebs_trap)
8db909a7 PZ	359	intel_pmu_lbr_disable(event);
ca037701 PZ	360	}
	361
	362	static void intel_pmu_pebs_enable_all(void)
	363	{
	364	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	365
	366	if (cpuc->pebs_enabled)
	367	wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
	368	}
	369
	370	static void intel_pmu_pebs_disable_all(void)
	371	{
	372	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	373
	374	if (cpuc->pebs_enabled)
	375	wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
	376	}
	377
ef21f683 PZ	378	#include <asm/insn.h>
ef21f683 PZ	379
ef21f683 PZ	380	static inline bool kernel_ip(unsigned long ip)
	381	{
	382	#ifdef CONFIG_X86_32
	383	return ip > PAGE_OFFSET;
	384	#else
	385	return (long)ip < 0;
	386	#endif
	387	}
	388
	389	static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
	390	{
	391	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	392	unsigned long from = cpuc->lbr_entries[0].from;
	393	unsigned long old_to, to = cpuc->lbr_entries[0].to;
	394	unsigned long ip = regs->ip;
	395
8db909a7 PZ	396	/*
	397	* We don't need to fixup if the PEBS assist is fault like
	398	*/
	399	if (!x86_pmu.intel_cap.pebs_trap)
	400	return 1;
	401
ef21f683 PZ	402	if (!cpuc->lbr_stack.nr \|\| !from \|\| !to)
	403	return 0;
	404
	405	if (ip < to)
	406	return 0;
	407
	408	/*
	409	* We sampled a branch insn, rewind using the LBR stack
	410	*/
	411	if (ip == to) {
	412	regs->ip = from;
	413	return 1;
	414	}
	415
	416	do {
	417	struct insn insn;
	418	u8 buf[MAX_INSN_SIZE];
	419	void *kaddr;
	420
	421	old_to = to;
	422	if (!kernel_ip(ip)) {
	423	int bytes, size = min_t(int, MAX_INSN_SIZE, ip - to);
	424
	425	bytes = copy_from_user_nmi(buf, (void __user *)to, size);
	426	if (bytes != size)
	427	return 0;
	428
	429	kaddr = buf;
	430	} else
	431	kaddr = (void *)to;
	432
	433	kernel_insn_init(&insn, kaddr);
	434	insn_get_length(&insn);
	435	to += insn.length;
	436	} while (to < ip);
	437
	438	if (to == ip) {
	439	regs->ip = old_to;
	440	return 1;
	441	}
	442
	443	return 0;
	444	}
	445
ca037701 PZ	446	static int intel_pmu_save_and_restart(struct perf_event *event);
	447	static void intel_pmu_disable_event(struct perf_event *event);
	448
	449	static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
	450	{
	451	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	452	struct debug_store *ds = cpuc->ds;
	453	struct perf_event event = cpuc->events[0]; / PMC0 only */
	454	struct pebs_record_core at, top;
	455	struct perf_sample_data data;
7e1a40dd	456	struct perf_raw_record raw;
ca037701 PZ	457	struct pt_regs regs;
	458	int n;
	459
	460	if (!event \|\| !ds \|\| !x86_pmu.pebs)
	461	return;
	462
	463	intel_pmu_pebs_disable_all();
	464
	465	at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
	466	top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
	467
	468	if (top <= at)
	469	goto out;
	470
	471	ds->pebs_index = ds->pebs_buffer_base;
	472
	473	if (!intel_pmu_save_and_restart(event))
	474	goto out;
	475
	476	perf_sample_data_init(&data, 0);
	477	data.period = event->hw.last_period;
	478
7e1a40dd PZ	479	if (event->attr.sample_type & PERF_SAMPLE_RAW) {
	480	raw.size = x86_pmu.pebs_record_size;
	481	raw.data = at;
	482	data.raw = &raw;
	483	}
	484
ca037701 PZ	485	n = top - at;
	486
	487	/*
	488	* Should not happen, we program the threshold at 1 and do not
	489	* set a reset value.
	490	*/
	491	WARN_ON_ONCE(n > 1);
	492
	493	/*
	494	* We use the interrupt regs as a base because the PEBS record
	495	* does not contain a full regs set, specifically it seems to
	496	* lack segment descriptors, which get used by things like
	497	* user_mode().
	498	*
	499	* In the simple case fix up only the IP and BP,SP regs, for
	500	* PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
	501	* A possible PERF_SAMPLE_REGS will have to transfer all regs.
	502	*/
	503	regs = *iregs;
	504	regs.ip = at->ip;
	505	regs.bp = at->bp;
	506	regs.sp = at->sp;
	507
ef21f683 PZ	508	if (intel_pmu_pebs_fixup_ip(&regs))
	509	regs.flags \|= PERF_EFLAGS_EXACT;
	510	else
	511	regs.flags &= ~PERF_EFLAGS_EXACT;
	512
ca037701 PZ	513	if (perf_event_overflow(event, 1, &data, &regs))
	514	intel_pmu_disable_event(event);
	515
	516	out:
	517	intel_pmu_pebs_enable_all();
	518	}
	519
	520	static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
	521	{
	522	struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
	523	struct debug_store *ds = cpuc->ds;
	524	struct pebs_record_nhm at, top;
	525	struct perf_sample_data data;
	526	struct perf_event *event = NULL;
7e1a40dd	527	struct perf_raw_record raw;
ca037701 PZ	528	struct pt_regs regs;
	529	int bit, n;
	530
	531	if (!ds \|\| !x86_pmu.pebs)
	532	return;
	533
	534	intel_pmu_pebs_disable_all();
	535
	536	at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
	537	top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
	538
	539	if (top <= at)
	540	goto out;
	541
	542	ds->pebs_index = ds->pebs_buffer_base;
	543
	544	n = top - at;
	545
	546	/*
	547	* Should not happen, we program the threshold at 1 and do not
	548	* set a reset value.
	549	*/
	550	WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
	551
	552	for ( ; at < top; at++) {
	553	for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
	554	if (!cpuc->events[bit]->attr.precise)
	555	continue;
	556
	557	event = cpuc->events[bit];
	558	}
	559
	560	if (!event)
	561	continue;
	562
	563	if (!intel_pmu_save_and_restart(event))
	564	continue;
	565
	566	perf_sample_data_init(&data, 0);
	567	data.period = event->hw.last_period;
	568
7e1a40dd PZ	569	if (event->attr.sample_type & PERF_SAMPLE_RAW) {
	570	raw.size = x86_pmu.pebs_record_size;
	571	raw.data = at;
	572	data.raw = &raw;
	573	}
	574
ca037701 PZ	575	/*
	576	* See the comment in intel_pmu_drain_pebs_core()
	577	*/
	578	regs = *iregs;
	579	regs.ip = at->ip;
	580	regs.bp = at->bp;
	581	regs.sp = at->sp;
	582
ef21f683 PZ	583	if (intel_pmu_pebs_fixup_ip(&regs))
	584	regs.flags \|= PERF_EFLAGS_EXACT;
	585	else
	586	regs.flags &= ~PERF_EFLAGS_EXACT;
	587
ca037701 PZ	588	if (perf_event_overflow(event, 1, &data, &regs))
	589	intel_pmu_disable_event(event);
	590	}
	591	out:
	592	intel_pmu_pebs_enable_all();
	593	}
	594
	595	/*
	596	* BTS, PEBS probe and setup
	597	*/
	598
	599	static void intel_ds_init(void)
	600	{
	601	/*
	602	* No support for 32bit formats
	603	*/
	604	if (!boot_cpu_has(X86_FEATURE_DTES64))
	605	return;
	606
	607	x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
	608	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
	609	if (x86_pmu.pebs) {
8db909a7 PZ	610	char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
8db909a7 PZ	611	int format = x86_pmu.intel_cap.pebs_format;
ca037701 PZ	612
	613	switch (format) {
	614	case 0:
8db909a7	615	printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
ca037701 PZ	616	x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
	617	x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
	618	x86_pmu.pebs_constraints = intel_core_pebs_events;
	619	break;
	620
	621	case 1:
8db909a7	622	printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
ca037701 PZ	623	x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
	624	x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
	625	x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
	626	break;
	627
	628	default:
8db909a7	629	printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
ca037701 PZ	630	x86_pmu.pebs = 0;
	631	break;
	632	}
	633	}
	634	}
	635
	636	#else /* CONFIG_CPU_SUP_INTEL */
	637
	638	static int reseve_ds_buffers(void)
	639	{
	640	return 0;
	641	}
	642
	643	static void release_ds_buffers(void)
	644	{
	645	}
	646
	647	#endif /* CONFIG_CPU_SUP_INTEL */