]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
dbd51be0 JSR |
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
1da177e4 LT |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). |
32 | */ | |
33 | ||
dbd51be0 JSR |
34 | #define DEBUG |
35 | ||
36 | #include <linux/types.h> /* FIXME: kvm_para.h needs this */ | |
37 | ||
38 | #include <linux/kvm_para.h> | |
39 | #include <linux/uaccess.h> | |
1da177e4 | 40 | #include <linux/module.h> |
dbd51be0 | 41 | #include <linux/mutex.h> |
1da177e4 | 42 | #include <linux/init.h> |
dbd51be0 JSR |
43 | #include <linux/sort.h> |
44 | #include <linux/cpu.h> | |
1da177e4 LT |
45 | #include <linux/pci.h> |
46 | #include <linux/smp.h> | |
1da177e4 | 47 | |
dbd51be0 | 48 | #include <asm/processor.h> |
99fc8d42 | 49 | #include <asm/e820.h> |
1da177e4 | 50 | #include <asm/mtrr.h> |
1da177e4 | 51 | #include <asm/msr.h> |
dbd51be0 | 52 | |
1da177e4 LT |
53 | #include "mtrr.h" |
54 | ||
dbd51be0 | 55 | u32 num_var_ranges; |
1da177e4 | 56 | |
b558bc0a | 57 | unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; |
14cc3e2b | 58 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 59 | |
6c5806ca | 60 | u64 size_or_mask, size_and_mask; |
5400743d | 61 | static bool mtrr_aps_delayed_init; |
1da177e4 | 62 | |
3b9cfc0a | 63 | static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM]; |
1da177e4 | 64 | |
3b9cfc0a | 65 | const struct mtrr_ops *mtrr_if; |
1da177e4 LT |
66 | |
67 | static void set_mtrr(unsigned int reg, unsigned long base, | |
68 | unsigned long size, mtrr_type type); | |
69 | ||
3b9cfc0a | 70 | void set_mtrr_ops(const struct mtrr_ops *ops) |
1da177e4 LT |
71 | { |
72 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
73 | mtrr_ops[ops->vendor] = ops; | |
74 | } | |
75 | ||
76 | /* Returns non-zero if we have the write-combining memory type */ | |
77 | static int have_wrcomb(void) | |
78 | { | |
79 | struct pci_dev *dev; | |
a6954ba2 | 80 | u8 rev; |
dbd51be0 JSR |
81 | |
82 | dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL); | |
83 | if (dev != NULL) { | |
84 | /* | |
85 | * ServerWorks LE chipsets < rev 6 have problems with | |
86 | * write-combining. Don't allow it and leave room for other | |
87 | * chipsets to be tagged | |
88 | */ | |
1da177e4 LT |
89 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && |
90 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
91 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
92 | if (rev <= 5) { | |
dbd51be0 | 93 | pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); |
a6954ba2 LR |
94 | pci_dev_put(dev); |
95 | return 0; | |
96 | } | |
1da177e4 | 97 | } |
dbd51be0 JSR |
98 | /* |
99 | * Intel 450NX errata # 23. Non ascending cacheline evictions to | |
100 | * write combining memory may resulting in data corruption | |
101 | */ | |
1da177e4 LT |
102 | if (dev->vendor == PCI_VENDOR_ID_INTEL && |
103 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
dbd51be0 | 104 | pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); |
1da177e4 LT |
105 | pci_dev_put(dev); |
106 | return 0; | |
107 | } | |
108 | pci_dev_put(dev); | |
dbd51be0 JSR |
109 | } |
110 | return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0; | |
1da177e4 LT |
111 | } |
112 | ||
113 | /* This function returns the number of variable MTRRs */ | |
114 | static void __init set_num_var_ranges(void) | |
115 | { | |
116 | unsigned long config = 0, dummy; | |
117 | ||
dbd51be0 | 118 | if (use_intel()) |
d9bcc01d | 119 | rdmsr(MSR_MTRRcap, config, dummy); |
dbd51be0 | 120 | else if (is_cpu(AMD)) |
1da177e4 LT |
121 | config = 2; |
122 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
123 | config = 8; | |
dbd51be0 | 124 | |
1da177e4 LT |
125 | num_var_ranges = config & 0xff; |
126 | } | |
127 | ||
128 | static void __init init_table(void) | |
129 | { | |
130 | int i, max; | |
131 | ||
132 | max = num_var_ranges; | |
1da177e4 | 133 | for (i = 0; i < max; i++) |
99fc8d42 | 134 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
135 | } |
136 | ||
137 | struct set_mtrr_data { | |
138 | atomic_t count; | |
139 | atomic_t gate; | |
140 | unsigned long smp_base; | |
141 | unsigned long smp_size; | |
142 | unsigned int smp_reg; | |
143 | mtrr_type smp_type; | |
144 | }; | |
145 | ||
dbd51be0 JSR |
146 | /** |
147 | * ipi_handler - Synchronisation handler. Executed by "other" CPUs. | |
6c550ee4 | 148 | * @info: pointer to mtrr configuration data |
dbd51be0 JSR |
149 | * |
150 | * Returns nothing. | |
151 | */ | |
1da177e4 | 152 | static void ipi_handler(void *info) |
1da177e4 | 153 | { |
4e2947f1 | 154 | #ifdef CONFIG_SMP |
1da177e4 LT |
155 | struct set_mtrr_data *data = info; |
156 | unsigned long flags; | |
157 | ||
158 | local_irq_save(flags); | |
159 | ||
160 | atomic_dec(&data->count); | |
dbd51be0 | 161 | while (!atomic_read(&data->gate)) |
1da177e4 LT |
162 | cpu_relax(); |
163 | ||
164 | /* The master has cleared me to execute */ | |
dbd51be0 JSR |
165 | if (data->smp_reg != ~0U) { |
166 | mtrr_if->set(data->smp_reg, data->smp_base, | |
1da177e4 | 167 | data->smp_size, data->smp_type); |
d0af9eed SS |
168 | } else if (mtrr_aps_delayed_init) { |
169 | /* | |
170 | * Initialize the MTRRs inaddition to the synchronisation. | |
171 | */ | |
1da177e4 | 172 | mtrr_if->set_all(); |
dbd51be0 | 173 | } |
1da177e4 LT |
174 | |
175 | atomic_dec(&data->count); | |
dbd51be0 | 176 | while (atomic_read(&data->gate)) |
1da177e4 LT |
177 | cpu_relax(); |
178 | ||
179 | atomic_dec(&data->count); | |
180 | local_irq_restore(flags); | |
1da177e4 | 181 | #endif |
4e2947f1 | 182 | } |
1da177e4 | 183 | |
dbd51be0 JSR |
184 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) |
185 | { | |
365bff80 JB |
186 | return type1 == MTRR_TYPE_UNCACHABLE || |
187 | type2 == MTRR_TYPE_UNCACHABLE || | |
188 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
189 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
190 | } | |
191 | ||
1da177e4 LT |
192 | /** |
193 | * set_mtrr - update mtrrs on all processors | |
194 | * @reg: mtrr in question | |
195 | * @base: mtrr base | |
196 | * @size: mtrr size | |
197 | * @type: mtrr type | |
198 | * | |
199 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
dbd51be0 | 200 | * |
1da177e4 LT |
201 | * 1. Send IPI to do the following: |
202 | * 2. Disable Interrupts | |
dbd51be0 | 203 | * 3. Wait for all procs to do so |
1da177e4 LT |
204 | * 4. Enter no-fill cache mode |
205 | * 5. Flush caches | |
206 | * 6. Clear PGE bit | |
207 | * 7. Flush all TLBs | |
208 | * 8. Disable all range registers | |
209 | * 9. Update the MTRRs | |
210 | * 10. Enable all range registers | |
211 | * 11. Flush all TLBs and caches again | |
212 | * 12. Enter normal cache mode and reenable caching | |
dbd51be0 | 213 | * 13. Set PGE |
1da177e4 LT |
214 | * 14. Wait for buddies to catch up |
215 | * 15. Enable interrupts. | |
dbd51be0 | 216 | * |
1da177e4 LT |
217 | * What does that mean for us? Well, first we set data.count to the number |
218 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
219 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
dbd51be0 JSR |
220 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each |
221 | * CPU goes through the transition of updating MTRRs. | |
222 | * The CPU vendors may each do it differently, | |
223 | * so we call mtrr_if->set() callback and let them take care of it. | |
224 | * When they're done, they again decrement data->count and wait for data.gate | |
225 | * to be reset. | |
226 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag | |
1da177e4 LT |
227 | * Everyone then enables interrupts and we all continue on. |
228 | * | |
229 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
230 | * becomes nops. | |
231 | */ | |
dbd51be0 JSR |
232 | static void |
233 | set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) | |
1da177e4 LT |
234 | { |
235 | struct set_mtrr_data data; | |
236 | unsigned long flags; | |
237 | ||
238 | data.smp_reg = reg; | |
239 | data.smp_base = base; | |
240 | data.smp_size = size; | |
241 | data.smp_type = type; | |
242 | atomic_set(&data.count, num_booting_cpus() - 1); | |
dbd51be0 JSR |
243 | |
244 | /* Make sure data.count is visible before unleashing other CPUs */ | |
d25c1ba2 | 245 | smp_wmb(); |
dbd51be0 | 246 | atomic_set(&data.gate, 0); |
1da177e4 | 247 | |
dbd51be0 | 248 | /* Start the ball rolling on other CPUs */ |
8691e5a8 | 249 | if (smp_call_function(ipi_handler, &data, 0) != 0) |
1da177e4 LT |
250 | panic("mtrr: timed out waiting for other CPUs\n"); |
251 | ||
252 | local_irq_save(flags); | |
253 | ||
dbd51be0 | 254 | while (atomic_read(&data.count)) |
1da177e4 LT |
255 | cpu_relax(); |
256 | ||
dbd51be0 | 257 | /* Ok, reset count and toggle gate */ |
1da177e4 | 258 | atomic_set(&data.count, num_booting_cpus() - 1); |
d25c1ba2 | 259 | smp_wmb(); |
dbd51be0 | 260 | atomic_set(&data.gate, 1); |
1da177e4 | 261 | |
dbd51be0 | 262 | /* Do our MTRR business */ |
1da177e4 | 263 | |
dbd51be0 JSR |
264 | /* |
265 | * HACK! | |
1da177e4 LT |
266 | * We use this same function to initialize the mtrrs on boot. |
267 | * The state of the boot cpu's mtrrs has been saved, and we want | |
dbd51be0 | 268 | * to replicate across all the APs. |
1da177e4 LT |
269 | * If we're doing that @reg is set to something special... |
270 | */ | |
dbd51be0 JSR |
271 | if (reg != ~0U) |
272 | mtrr_if->set(reg, base, size, type); | |
d0af9eed SS |
273 | else if (!mtrr_aps_delayed_init) |
274 | mtrr_if->set_all(); | |
1da177e4 | 275 | |
dbd51be0 JSR |
276 | /* Wait for the others */ |
277 | while (atomic_read(&data.count)) | |
1da177e4 LT |
278 | cpu_relax(); |
279 | ||
280 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 281 | smp_wmb(); |
dbd51be0 | 282 | atomic_set(&data.gate, 0); |
1da177e4 LT |
283 | |
284 | /* | |
285 | * Wait here for everyone to have seen the gate change | |
286 | * So we're the last ones to touch 'data' | |
287 | */ | |
dbd51be0 | 288 | while (atomic_read(&data.count)) |
1da177e4 LT |
289 | cpu_relax(); |
290 | ||
291 | local_irq_restore(flags); | |
292 | } | |
293 | ||
294 | /** | |
dbd51be0 JSR |
295 | * mtrr_add_page - Add a memory type region |
296 | * @base: Physical base address of region in pages (in units of 4 kB!) | |
297 | * @size: Physical size of region in pages (4 kB) | |
298 | * @type: Type of MTRR desired | |
299 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 300 | * |
dbd51be0 JSR |
301 | * Memory type region registers control the caching on newer Intel and |
302 | * non Intel processors. This function allows drivers to request an | |
303 | * MTRR is added. The details and hardware specifics of each processor's | |
304 | * implementation are hidden from the caller, but nevertheless the | |
305 | * caller should expect to need to provide a power of two size on an | |
306 | * equivalent power of two boundary. | |
1da177e4 | 307 | * |
dbd51be0 JSR |
308 | * If the region cannot be added either because all regions are in use |
309 | * or the CPU cannot support it a negative value is returned. On success | |
310 | * the register number for this entry is returned, but should be treated | |
311 | * as a cookie only. | |
1da177e4 | 312 | * |
dbd51be0 JSR |
313 | * On a multiprocessor machine the changes are made to all processors. |
314 | * This is required on x86 by the Intel processors. | |
1da177e4 | 315 | * |
dbd51be0 | 316 | * The available types are |
1da177e4 | 317 | * |
dbd51be0 | 318 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 319 | * |
dbd51be0 | 320 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 321 | * |
dbd51be0 | 322 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 323 | * |
dbd51be0 | 324 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 325 | * |
dbd51be0 JSR |
326 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
327 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 328 | */ |
dbd51be0 | 329 | int mtrr_add_page(unsigned long base, unsigned long size, |
2d2ee8de | 330 | unsigned int type, bool increment) |
1da177e4 | 331 | { |
dbd51be0 | 332 | unsigned long lbase, lsize; |
365bff80 | 333 | int i, replace, error; |
1da177e4 | 334 | mtrr_type ltype; |
1da177e4 LT |
335 | |
336 | if (!mtrr_if) | |
337 | return -ENXIO; | |
dbd51be0 JSR |
338 | |
339 | error = mtrr_if->validate_add_page(base, size, type); | |
340 | if (error) | |
1da177e4 LT |
341 | return error; |
342 | ||
343 | if (type >= MTRR_NUM_TYPES) { | |
dbd51be0 | 344 | pr_warning("mtrr: type: %u invalid\n", type); |
1da177e4 LT |
345 | return -EINVAL; |
346 | } | |
347 | ||
dbd51be0 | 348 | /* If the type is WC, check that this processor supports it */ |
1da177e4 | 349 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { |
dbd51be0 | 350 | pr_warning("mtrr: your processor doesn't support write-combining\n"); |
1da177e4 LT |
351 | return -ENOSYS; |
352 | } | |
353 | ||
365bff80 | 354 | if (!size) { |
dbd51be0 | 355 | pr_warning("mtrr: zero sized request\n"); |
365bff80 JB |
356 | return -EINVAL; |
357 | } | |
358 | ||
1da177e4 | 359 | if (base & size_or_mask || size & size_or_mask) { |
dbd51be0 | 360 | pr_warning("mtrr: base or size exceeds the MTRR width\n"); |
1da177e4 LT |
361 | return -EINVAL; |
362 | } | |
363 | ||
364 | error = -EINVAL; | |
365bff80 | 365 | replace = -1; |
1da177e4 | 366 | |
3b520b23 | 367 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 368 | get_online_cpus(); |
dbd51be0 JSR |
369 | |
370 | /* Search for existing MTRR */ | |
14cc3e2b | 371 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
372 | for (i = 0; i < num_var_ranges; ++i) { |
373 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
dbd51be0 JSR |
374 | if (!lsize || base > lbase + lsize - 1 || |
375 | base + size - 1 < lbase) | |
1da177e4 | 376 | continue; |
dbd51be0 JSR |
377 | /* |
378 | * At this point we know there is some kind of | |
379 | * overlap/enclosure | |
380 | */ | |
365bff80 | 381 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
dbd51be0 JSR |
382 | if (base <= lbase && |
383 | base + size - 1 >= lbase + lsize - 1) { | |
365bff80 JB |
384 | /* New region encloses an existing region */ |
385 | if (type == ltype) { | |
386 | replace = replace == -1 ? i : -2; | |
387 | continue; | |
dbd51be0 | 388 | } else if (types_compatible(type, ltype)) |
365bff80 JB |
389 | continue; |
390 | } | |
dbd51be0 JSR |
391 | pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing" |
392 | " 0x%lx000,0x%lx000\n", base, size, lbase, | |
393 | lsize); | |
1da177e4 LT |
394 | goto out; |
395 | } | |
dbd51be0 | 396 | /* New region is enclosed by an existing region */ |
1da177e4 | 397 | if (ltype != type) { |
365bff80 | 398 | if (types_compatible(type, ltype)) |
1da177e4 | 399 | continue; |
dbd51be0 JSR |
400 | pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", |
401 | base, size, mtrr_attrib_to_str(ltype), | |
402 | mtrr_attrib_to_str(type)); | |
1da177e4 LT |
403 | goto out; |
404 | } | |
405 | if (increment) | |
99fc8d42 | 406 | ++mtrr_usage_table[i]; |
1da177e4 LT |
407 | error = i; |
408 | goto out; | |
409 | } | |
dbd51be0 | 410 | /* Search for an empty MTRR */ |
365bff80 | 411 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
412 | if (i >= 0) { |
413 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
414 | if (likely(replace < 0)) { |
415 | mtrr_usage_table[i] = 1; | |
416 | } else { | |
417 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 418 | if (increment) |
99fc8d42 | 419 | mtrr_usage_table[i]++; |
365bff80 JB |
420 | if (unlikely(replace != i)) { |
421 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 422 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
423 | } |
424 | } | |
dbd51be0 JSR |
425 | } else { |
426 | pr_info("mtrr: no more MTRRs available\n"); | |
427 | } | |
1da177e4 LT |
428 | error = i; |
429 | out: | |
14cc3e2b | 430 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 431 | put_online_cpus(); |
1da177e4 LT |
432 | return error; |
433 | } | |
434 | ||
c92c6ffd AM |
435 | static int mtrr_check(unsigned long base, unsigned long size) |
436 | { | |
437 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
dbd51be0 JSR |
438 | pr_warning("mtrr: size and base must be multiples of 4 kiB\n"); |
439 | pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
c92c6ffd AM |
440 | dump_stack(); |
441 | return -1; | |
442 | } | |
443 | return 0; | |
444 | } | |
445 | ||
1da177e4 | 446 | /** |
dbd51be0 JSR |
447 | * mtrr_add - Add a memory type region |
448 | * @base: Physical base address of region | |
449 | * @size: Physical size of region | |
450 | * @type: Type of MTRR desired | |
451 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 452 | * |
dbd51be0 JSR |
453 | * Memory type region registers control the caching on newer Intel and |
454 | * non Intel processors. This function allows drivers to request an | |
455 | * MTRR is added. The details and hardware specifics of each processor's | |
456 | * implementation are hidden from the caller, but nevertheless the | |
457 | * caller should expect to need to provide a power of two size on an | |
458 | * equivalent power of two boundary. | |
1da177e4 | 459 | * |
dbd51be0 JSR |
460 | * If the region cannot be added either because all regions are in use |
461 | * or the CPU cannot support it a negative value is returned. On success | |
462 | * the register number for this entry is returned, but should be treated | |
463 | * as a cookie only. | |
1da177e4 | 464 | * |
dbd51be0 JSR |
465 | * On a multiprocessor machine the changes are made to all processors. |
466 | * This is required on x86 by the Intel processors. | |
1da177e4 | 467 | * |
dbd51be0 | 468 | * The available types are |
1da177e4 | 469 | * |
dbd51be0 | 470 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 471 | * |
dbd51be0 | 472 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 473 | * |
dbd51be0 | 474 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 475 | * |
dbd51be0 | 476 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 477 | * |
dbd51be0 JSR |
478 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
479 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 480 | */ |
dbd51be0 JSR |
481 | int mtrr_add(unsigned long base, unsigned long size, unsigned int type, |
482 | bool increment) | |
1da177e4 | 483 | { |
c92c6ffd | 484 | if (mtrr_check(base, size)) |
1da177e4 | 485 | return -EINVAL; |
1da177e4 LT |
486 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
487 | increment); | |
488 | } | |
dbd51be0 | 489 | EXPORT_SYMBOL(mtrr_add); |
1da177e4 LT |
490 | |
491 | /** | |
dbd51be0 JSR |
492 | * mtrr_del_page - delete a memory type region |
493 | * @reg: Register returned by mtrr_add | |
494 | * @base: Physical base address | |
495 | * @size: Size of region | |
1da177e4 | 496 | * |
dbd51be0 JSR |
497 | * If register is supplied then base and size are ignored. This is |
498 | * how drivers should call it. | |
1da177e4 | 499 | * |
dbd51be0 JSR |
500 | * Releases an MTRR region. If the usage count drops to zero the |
501 | * register is freed and the region returns to default state. | |
502 | * On success the register is returned, on failure a negative error | |
503 | * code. | |
1da177e4 | 504 | */ |
1da177e4 LT |
505 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) |
506 | { | |
507 | int i, max; | |
508 | mtrr_type ltype; | |
365bff80 | 509 | unsigned long lbase, lsize; |
1da177e4 LT |
510 | int error = -EINVAL; |
511 | ||
512 | if (!mtrr_if) | |
513 | return -ENXIO; | |
514 | ||
515 | max = num_var_ranges; | |
3b520b23 | 516 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 517 | get_online_cpus(); |
14cc3e2b | 518 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
519 | if (reg < 0) { |
520 | /* Search for existing MTRR */ | |
521 | for (i = 0; i < max; ++i) { | |
522 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
523 | if (lbase == base && lsize == size) { | |
524 | reg = i; | |
525 | break; | |
526 | } | |
527 | } | |
528 | if (reg < 0) { | |
dbd51be0 JSR |
529 | pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n", |
530 | base, size); | |
1da177e4 LT |
531 | goto out; |
532 | } | |
533 | } | |
534 | if (reg >= max) { | |
dbd51be0 | 535 | pr_warning("mtrr: register: %d too big\n", reg); |
1da177e4 LT |
536 | goto out; |
537 | } | |
1da177e4 LT |
538 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
539 | if (lsize < 1) { | |
dbd51be0 | 540 | pr_warning("mtrr: MTRR %d not used\n", reg); |
1da177e4 LT |
541 | goto out; |
542 | } | |
99fc8d42 | 543 | if (mtrr_usage_table[reg] < 1) { |
dbd51be0 | 544 | pr_warning("mtrr: reg: %d has count=0\n", reg); |
1da177e4 LT |
545 | goto out; |
546 | } | |
99fc8d42 | 547 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
548 | set_mtrr(reg, 0, 0, 0); |
549 | error = reg; | |
550 | out: | |
14cc3e2b | 551 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 552 | put_online_cpus(); |
1da177e4 LT |
553 | return error; |
554 | } | |
dbd51be0 | 555 | |
1da177e4 | 556 | /** |
dbd51be0 JSR |
557 | * mtrr_del - delete a memory type region |
558 | * @reg: Register returned by mtrr_add | |
559 | * @base: Physical base address | |
560 | * @size: Size of region | |
1da177e4 | 561 | * |
dbd51be0 JSR |
562 | * If register is supplied then base and size are ignored. This is |
563 | * how drivers should call it. | |
1da177e4 | 564 | * |
dbd51be0 JSR |
565 | * Releases an MTRR region. If the usage count drops to zero the |
566 | * register is freed and the region returns to default state. | |
567 | * On success the register is returned, on failure a negative error | |
568 | * code. | |
1da177e4 | 569 | */ |
dbd51be0 | 570 | int mtrr_del(int reg, unsigned long base, unsigned long size) |
1da177e4 | 571 | { |
c92c6ffd | 572 | if (mtrr_check(base, size)) |
1da177e4 | 573 | return -EINVAL; |
1da177e4 LT |
574 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
575 | } | |
1da177e4 LT |
576 | EXPORT_SYMBOL(mtrr_del); |
577 | ||
dbd51be0 JSR |
578 | /* |
579 | * HACK ALERT! | |
1da177e4 LT |
580 | * These should be called implicitly, but we can't yet until all the initcall |
581 | * stuff is done... | |
582 | */ | |
1da177e4 LT |
583 | static void __init init_ifs(void) |
584 | { | |
475850c8 | 585 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
586 | amd_init_mtrr(); |
587 | cyrix_init_mtrr(); | |
588 | centaur_init_mtrr(); | |
475850c8 | 589 | #endif |
1da177e4 LT |
590 | } |
591 | ||
3b520b23 SL |
592 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
593 | * MTRR driver doesn't require this | |
594 | */ | |
1da177e4 LT |
595 | struct mtrr_value { |
596 | mtrr_type ltype; | |
597 | unsigned long lbase; | |
365bff80 | 598 | unsigned long lsize; |
1da177e4 LT |
599 | }; |
600 | ||
f0348c43 | 601 | static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; |
1da177e4 | 602 | |
dbd51be0 | 603 | static int mtrr_save(struct sys_device *sysdev, pm_message_t state) |
1da177e4 LT |
604 | { |
605 | int i; | |
1da177e4 LT |
606 | |
607 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
608 | mtrr_if->get(i, &mtrr_value[i].lbase, |
609 | &mtrr_value[i].lsize, | |
610 | &mtrr_value[i].ltype); | |
1da177e4 LT |
611 | } |
612 | return 0; | |
613 | } | |
614 | ||
dbd51be0 | 615 | static int mtrr_restore(struct sys_device *sysdev) |
1da177e4 LT |
616 | { |
617 | int i; | |
618 | ||
619 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
620 | if (mtrr_value[i].lsize) { |
621 | set_mtrr(i, mtrr_value[i].lbase, | |
622 | mtrr_value[i].lsize, | |
623 | mtrr_value[i].ltype); | |
624 | } | |
1da177e4 | 625 | } |
1da177e4 LT |
626 | return 0; |
627 | } | |
628 | ||
629 | ||
630 | ||
631 | static struct sysdev_driver mtrr_sysdev_driver = { | |
632 | .suspend = mtrr_save, | |
633 | .resume = mtrr_restore, | |
634 | }; | |
635 | ||
0d890355 | 636 | int __initdata changed_by_mtrr_cleanup; |
1da177e4 LT |
637 | |
638 | /** | |
3b520b23 | 639 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 | 640 | * |
dbd51be0 | 641 | * This needs to be called early; before any of the other CPUs are |
1da177e4 | 642 | * initialized (i.e. before smp_init()). |
dbd51be0 | 643 | * |
1da177e4 | 644 | */ |
9ef231a4 | 645 | void __init mtrr_bp_init(void) |
1da177e4 | 646 | { |
95ffa243 | 647 | u32 phys_addr; |
dbd51be0 | 648 | |
1da177e4 LT |
649 | init_ifs(); |
650 | ||
95ffa243 YL |
651 | phys_addr = 32; |
652 | ||
1da177e4 LT |
653 | if (cpu_has_mtrr) { |
654 | mtrr_if = &generic_mtrr_ops; | |
dbd51be0 | 655 | size_or_mask = 0xff000000; /* 36 bits */ |
1da177e4 | 656 | size_and_mask = 0x00f00000; |
95ffa243 | 657 | phys_addr = 36; |
1f2c958a | 658 | |
dbd51be0 JSR |
659 | /* |
660 | * This is an AMD specific MSR, but we assume(hope?) that | |
661 | * Intel will implement it to when they extend the address | |
662 | * bus of the Xeon. | |
663 | */ | |
1f2c958a | 664 | if (cpuid_eax(0x80000000) >= 0x80000008) { |
1f2c958a | 665 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
af9c142d SL |
666 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
667 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
668 | boot_cpu_data.x86 == 0xF && | |
669 | boot_cpu_data.x86_model == 0x3 && | |
670 | (boot_cpu_data.x86_mask == 0x3 || | |
671 | boot_cpu_data.x86_mask == 0x4)) | |
672 | phys_addr = 36; | |
673 | ||
6c5806ca AH |
674 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
675 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
676 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
677 | boot_cpu_data.x86 == 6) { | |
dbd51be0 JSR |
678 | /* |
679 | * VIA C* family have Intel style MTRRs, | |
680 | * but don't support PAE | |
681 | */ | |
682 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1f2c958a | 683 | size_and_mask = 0; |
95ffa243 | 684 | phys_addr = 32; |
1da177e4 LT |
685 | } |
686 | } else { | |
687 | switch (boot_cpu_data.x86_vendor) { | |
688 | case X86_VENDOR_AMD: | |
689 | if (cpu_has_k6_mtrr) { | |
690 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
691 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
692 | size_or_mask = 0xfff00000; /* 32 bits */ | |
693 | size_and_mask = 0; | |
694 | } | |
695 | break; | |
696 | case X86_VENDOR_CENTAUR: | |
697 | if (cpu_has_centaur_mcr) { | |
698 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
699 | size_or_mask = 0xfff00000; /* 32 bits */ | |
700 | size_and_mask = 0; | |
701 | } | |
702 | break; | |
703 | case X86_VENDOR_CYRIX: | |
704 | if (cpu_has_cyrix_arr) { | |
705 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
706 | size_or_mask = 0xfff00000; /* 32 bits */ | |
707 | size_and_mask = 0; | |
708 | } | |
709 | break; | |
710 | default: | |
711 | break; | |
712 | } | |
713 | } | |
1da177e4 LT |
714 | |
715 | if (mtrr_if) { | |
716 | set_num_var_ranges(); | |
717 | init_table(); | |
95ffa243 | 718 | if (use_intel()) { |
3b520b23 | 719 | get_mtrr_state(); |
95ffa243 | 720 | |
12031a62 YL |
721 | if (mtrr_cleanup(phys_addr)) { |
722 | changed_by_mtrr_cleanup = 1; | |
95ffa243 | 723 | mtrr_if->set_all(); |
12031a62 | 724 | } |
95ffa243 | 725 | } |
1da177e4 | 726 | } |
1da177e4 LT |
727 | } |
728 | ||
3b520b23 SL |
729 | void mtrr_ap_init(void) |
730 | { | |
d0af9eed | 731 | if (!use_intel() || mtrr_aps_delayed_init) |
3b520b23 SL |
732 | return; |
733 | /* | |
dbd51be0 JSR |
734 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries |
735 | * changed, but this routine will be called in cpu boot time, | |
736 | * holding the lock breaks it. | |
737 | * | |
738 | * This routine is called in two cases: | |
739 | * | |
740 | * 1. very earily time of software resume, when there absolutely | |
741 | * isn't mtrr entry changes; | |
742 | * | |
743 | * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug | |
744 | * lock to prevent mtrr entry changes | |
3b520b23 | 745 | */ |
d0af9eed | 746 | set_mtrr(~0U, 0, 0, 0); |
3b520b23 SL |
747 | } |
748 | ||
2b1f6278 BK |
749 | /** |
750 | * Save current fixed-range MTRR state of the BSP | |
751 | */ | |
752 | void mtrr_save_state(void) | |
753 | { | |
8691e5a8 | 754 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1); |
2b1f6278 BK |
755 | } |
756 | ||
d0af9eed SS |
757 | void set_mtrr_aps_delayed_init(void) |
758 | { | |
759 | if (!use_intel()) | |
760 | return; | |
761 | ||
5400743d | 762 | mtrr_aps_delayed_init = true; |
d0af9eed SS |
763 | } |
764 | ||
765 | /* | |
766 | * MTRR initialization for all AP's | |
767 | */ | |
768 | void mtrr_aps_init(void) | |
769 | { | |
770 | if (!use_intel()) | |
771 | return; | |
772 | ||
773 | set_mtrr(~0U, 0, 0, 0); | |
5400743d | 774 | mtrr_aps_delayed_init = false; |
d0af9eed SS |
775 | } |
776 | ||
777 | void mtrr_bp_restore(void) | |
778 | { | |
779 | if (!use_intel()) | |
780 | return; | |
781 | ||
782 | mtrr_if->set_all(); | |
783 | } | |
784 | ||
3b520b23 SL |
785 | static int __init mtrr_init_finialize(void) |
786 | { | |
787 | if (!mtrr_if) | |
788 | return 0; | |
dbd51be0 | 789 | |
95ffa243 | 790 | if (use_intel()) { |
12031a62 | 791 | if (!changed_by_mtrr_cleanup) |
95ffa243 | 792 | mtrr_state_warn(); |
dbd51be0 | 793 | return 0; |
3b520b23 | 794 | } |
dbd51be0 JSR |
795 | |
796 | /* | |
797 | * The CPU has no MTRR and seems to not support SMP. They have | |
798 | * specific drivers, we use a tricky method to support | |
799 | * suspend/resume for them. | |
800 | * | |
801 | * TBD: is there any system with such CPU which supports | |
802 | * suspend/resume? If no, we should remove the code. | |
803 | */ | |
804 | sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver); | |
805 | ||
3b520b23 SL |
806 | return 0; |
807 | } | |
808 | subsys_initcall(mtrr_init_finialize); |