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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e | 35 | #include <linux/fs.h> |
9b1beaf2 | 36 | #include <linux/mm.h> |
e9eee03e | 37 | |
d88203d1 | 38 | #include <asm/processor.h> |
ccc3c319 AK |
39 | #include <asm/hw_irq.h> |
40 | #include <asm/apic.h> | |
e02e68d3 | 41 | #include <asm/idle.h> |
ccc3c319 | 42 | #include <asm/ipi.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
5d727926 AK |
48 | /* Handle unconfigured int18 (should never happen) */ |
49 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
50 | { | |
51 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
52 | smp_processor_id()); | |
53 | } | |
54 | ||
55 | /* Call the installed machine check handler for this CPU setup. */ | |
56 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
57 | unexpected_machine_check; | |
04b2b1a4 | 58 | |
4e5b3e69 | 59 | int mce_disabled __read_mostly; |
04b2b1a4 | 60 | |
4efc0670 | 61 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 62 | |
e9eee03e | 63 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 64 | |
3c079792 AK |
65 | #define SPINUNIT 100 /* 100ns */ |
66 | ||
553f265f AK |
67 | atomic_t mce_entry; |
68 | ||
01ca79f1 AK |
69 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
70 | ||
bd78432c TH |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
4e5b3e69 HS |
78 | static int tolerant __read_mostly = 1; |
79 | static int banks __read_mostly; | |
80 | static u64 *bank __read_mostly; | |
81 | static int rip_msr __read_mostly; | |
82 | static int mce_bootlog __read_mostly = -1; | |
83 | static int monarch_timeout __read_mostly = -1; | |
84 | static int mce_panic_timeout __read_mostly; | |
85 | static int mce_dont_log_ce __read_mostly; | |
86 | int mce_cmci_disabled __read_mostly; | |
87 | int mce_ignore_ce __read_mostly; | |
88 | int mce_ser __read_mostly; | |
a98f0dd3 | 89 | |
1020bcbc HS |
90 | /* User mode helper program triggered by machine check event */ |
91 | static unsigned long mce_need_notify; | |
92 | static char mce_helper[128]; | |
93 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 94 | |
06b7a7a5 AK |
95 | static unsigned long dont_init_banks; |
96 | ||
e02e68d3 | 97 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
98 | static DEFINE_PER_CPU(struct mce, mces_seen); |
99 | static int cpu_missing; | |
100 | ||
e02e68d3 | 101 | |
ee031c31 AK |
102 | /* MCA banks polled by the period polling timer for corrected events */ |
103 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
104 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
105 | }; | |
106 | ||
06b7a7a5 AK |
107 | static inline int skip_bank_init(int i) |
108 | { | |
109 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
110 | } | |
111 | ||
9b1beaf2 AK |
112 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
113 | ||
b5f2fa4e AK |
114 | /* Do initial initialization of a struct mce */ |
115 | void mce_setup(struct mce *m) | |
116 | { | |
117 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 118 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 119 | rdtscll(m->tsc); |
8ee08347 AK |
120 | /* We hope get_seconds stays lockless */ |
121 | m->time = get_seconds(); | |
122 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
123 | m->cpuid = cpuid_eax(1); | |
124 | #ifdef CONFIG_SMP | |
125 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
126 | #endif | |
127 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
128 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
129 | } |
130 | ||
ea149b36 AK |
131 | DEFINE_PER_CPU(struct mce, injectm); |
132 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
133 | ||
1da177e4 LT |
134 | /* |
135 | * Lockless MCE logging infrastructure. | |
136 | * This avoids deadlocks on printk locks without having to break locks. Also | |
137 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
138 | */ | |
139 | ||
231fd906 | 140 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
141 | .signature = MCE_LOG_SIGNATURE, |
142 | .len = MCE_LOG_LEN, | |
143 | .recordlen = sizeof(struct mce), | |
d88203d1 | 144 | }; |
1da177e4 LT |
145 | |
146 | void mce_log(struct mce *mce) | |
147 | { | |
148 | unsigned next, entry; | |
e9eee03e | 149 | |
1da177e4 | 150 | mce->finished = 0; |
7644143c | 151 | wmb(); |
1da177e4 LT |
152 | for (;;) { |
153 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 154 | for (;;) { |
e9eee03e IM |
155 | /* |
156 | * When the buffer fills up discard new entries. | |
157 | * Assume that the earlier errors are the more | |
158 | * interesting ones: | |
159 | */ | |
673242c1 | 160 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
161 | set_bit(MCE_OVERFLOW, |
162 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
163 | return; |
164 | } | |
e9eee03e | 165 | /* Old left over entry. Skip: */ |
673242c1 AK |
166 | if (mcelog.entry[entry].finished) { |
167 | entry++; | |
168 | continue; | |
169 | } | |
7644143c | 170 | break; |
1da177e4 | 171 | } |
1da177e4 LT |
172 | smp_rmb(); |
173 | next = entry + 1; | |
174 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
175 | break; | |
176 | } | |
177 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 178 | wmb(); |
1da177e4 | 179 | mcelog.entry[entry].finished = 1; |
7644143c | 180 | wmb(); |
1da177e4 | 181 | |
a0189c70 | 182 | mce->finished = 1; |
1020bcbc | 183 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
184 | } |
185 | ||
549d042d BP |
186 | void __weak decode_mce(struct mce *m) |
187 | { | |
188 | return; | |
189 | } | |
190 | ||
77e26cca | 191 | static void print_mce(struct mce *m) |
1da177e4 | 192 | { |
86503560 | 193 | printk(KERN_EMERG |
1da177e4 | 194 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 195 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 196 | if (m->ip) { |
d88203d1 | 197 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 198 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 199 | m->cs, m->ip); |
1da177e4 | 200 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 201 | print_symbol("{%s}", m->ip); |
ad361c98 | 202 | printk(KERN_CONT "\n"); |
1da177e4 | 203 | } |
f6d1826d | 204 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 205 | if (m->addr) |
ad361c98 | 206 | printk(KERN_CONT "ADDR %llx ", m->addr); |
1da177e4 | 207 | if (m->misc) |
ad361c98 JP |
208 | printk(KERN_CONT "MISC %llx ", m->misc); |
209 | printk(KERN_CONT "\n"); | |
8ee08347 AK |
210 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
211 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
212 | m->apicid); | |
549d042d BP |
213 | |
214 | decode_mce(m); | |
86503560 AK |
215 | } |
216 | ||
77e26cca HS |
217 | static void print_mce_head(void) |
218 | { | |
ad361c98 | 219 | printk(KERN_EMERG "\nHARDWARE ERROR\n"); |
77e26cca HS |
220 | } |
221 | ||
86503560 AK |
222 | static void print_mce_tail(void) |
223 | { | |
224 | printk(KERN_EMERG "This is not a software problem!\n" | |
ad361c98 | 225 | "Run through mcelog --ascii to decode and contact your hardware vendor\n"); |
1da177e4 LT |
226 | } |
227 | ||
f94b61c2 AK |
228 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
229 | ||
230 | static atomic_t mce_paniced; | |
231 | ||
232 | /* Panic in progress. Enable interrupts and wait for final IPI */ | |
233 | static void wait_for_panic(void) | |
234 | { | |
235 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
236 | preempt_disable(); | |
237 | local_irq_enable(); | |
238 | while (timeout-- > 0) | |
239 | udelay(1); | |
29b0f591 AK |
240 | if (panic_timeout == 0) |
241 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
242 | panic("Panicing machine check CPU died"); |
243 | } | |
244 | ||
bd19a5e6 | 245 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 246 | { |
1da177e4 | 247 | int i; |
e02e68d3 | 248 | |
f94b61c2 AK |
249 | /* |
250 | * Make sure only one CPU runs in machine check panic | |
251 | */ | |
252 | if (atomic_add_return(1, &mce_paniced) > 1) | |
253 | wait_for_panic(); | |
254 | barrier(); | |
255 | ||
d896a940 AK |
256 | bust_spinlocks(1); |
257 | console_verbose(); | |
77e26cca | 258 | print_mce_head(); |
a0189c70 | 259 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 260 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 261 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
262 | if (!(m->status & MCI_STATUS_VAL)) |
263 | continue; | |
264 | if (!(m->status & MCI_STATUS_UC)) | |
265 | print_mce(m); | |
a0189c70 AK |
266 | } |
267 | /* Now print uncorrected but with the final one last */ | |
268 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
269 | struct mce *m = &mcelog.entry[i]; | |
270 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 271 | continue; |
77e26cca HS |
272 | if (!(m->status & MCI_STATUS_UC)) |
273 | continue; | |
a0189c70 | 274 | if (!final || memcmp(m, final, sizeof(struct mce))) |
77e26cca | 275 | print_mce(m); |
1da177e4 | 276 | } |
a0189c70 | 277 | if (final) |
77e26cca | 278 | print_mce(final); |
3c079792 AK |
279 | if (cpu_missing) |
280 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 281 | print_mce_tail(); |
bd19a5e6 AK |
282 | if (exp) |
283 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
29b0f591 AK |
284 | if (panic_timeout == 0) |
285 | panic_timeout = mce_panic_timeout; | |
e02e68d3 | 286 | panic(msg); |
d88203d1 | 287 | } |
1da177e4 | 288 | |
ea149b36 AK |
289 | /* Support code for software error injection */ |
290 | ||
291 | static int msr_to_offset(u32 msr) | |
292 | { | |
293 | unsigned bank = __get_cpu_var(injectm.bank); | |
294 | if (msr == rip_msr) | |
295 | return offsetof(struct mce, ip); | |
296 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
297 | return offsetof(struct mce, status); | |
298 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
299 | return offsetof(struct mce, addr); | |
300 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
301 | return offsetof(struct mce, misc); | |
302 | if (msr == MSR_IA32_MCG_STATUS) | |
303 | return offsetof(struct mce, mcgstatus); | |
304 | return -1; | |
305 | } | |
306 | ||
5f8c1a54 AK |
307 | /* MSR access wrappers used for error injection */ |
308 | static u64 mce_rdmsrl(u32 msr) | |
309 | { | |
310 | u64 v; | |
ea149b36 AK |
311 | if (__get_cpu_var(injectm).finished) { |
312 | int offset = msr_to_offset(msr); | |
313 | if (offset < 0) | |
314 | return 0; | |
315 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
316 | } | |
5f8c1a54 AK |
317 | rdmsrl(msr, v); |
318 | return v; | |
319 | } | |
320 | ||
321 | static void mce_wrmsrl(u32 msr, u64 v) | |
322 | { | |
ea149b36 AK |
323 | if (__get_cpu_var(injectm).finished) { |
324 | int offset = msr_to_offset(msr); | |
325 | if (offset >= 0) | |
326 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
327 | return; | |
328 | } | |
5f8c1a54 AK |
329 | wrmsrl(msr, v); |
330 | } | |
331 | ||
9b1beaf2 AK |
332 | /* |
333 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
334 | * process context work function. This is vastly simplified because there's | |
335 | * only a single reader and a single writer. | |
336 | */ | |
337 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
338 | ||
339 | struct mce_ring { | |
340 | unsigned short start; | |
341 | unsigned short end; | |
342 | unsigned long ring[MCE_RING_SIZE]; | |
343 | }; | |
344 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
345 | ||
346 | /* Runs with CPU affinity in workqueue */ | |
347 | static int mce_ring_empty(void) | |
348 | { | |
349 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
350 | ||
351 | return r->start == r->end; | |
352 | } | |
353 | ||
354 | static int mce_ring_get(unsigned long *pfn) | |
355 | { | |
356 | struct mce_ring *r; | |
357 | int ret = 0; | |
358 | ||
359 | *pfn = 0; | |
360 | get_cpu(); | |
361 | r = &__get_cpu_var(mce_ring); | |
362 | if (r->start == r->end) | |
363 | goto out; | |
364 | *pfn = r->ring[r->start]; | |
365 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
366 | ret = 1; | |
367 | out: | |
368 | put_cpu(); | |
369 | return ret; | |
370 | } | |
371 | ||
372 | /* Always runs in MCE context with preempt off */ | |
373 | static int mce_ring_add(unsigned long pfn) | |
374 | { | |
375 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
376 | unsigned next; | |
377 | ||
378 | next = (r->end + 1) % MCE_RING_SIZE; | |
379 | if (next == r->start) | |
380 | return -1; | |
381 | r->ring[r->end] = pfn; | |
382 | wmb(); | |
383 | r->end = next; | |
384 | return 0; | |
385 | } | |
386 | ||
88ccbedd | 387 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 388 | { |
04b2b1a4 | 389 | if (mce_disabled) |
5b4408fd | 390 | return 0; |
3d1712c9 | 391 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
392 | } |
393 | ||
9b1beaf2 AK |
394 | static void mce_schedule_work(void) |
395 | { | |
396 | if (!mce_ring_empty()) { | |
397 | struct work_struct *work = &__get_cpu_var(mce_work); | |
398 | if (!work_pending(work)) | |
399 | schedule_work(work); | |
400 | } | |
401 | } | |
402 | ||
1b2797dc HY |
403 | /* |
404 | * Get the address of the instruction at the time of the machine check | |
405 | * error. | |
406 | */ | |
94ad8474 AK |
407 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
408 | { | |
1b2797dc HY |
409 | |
410 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 411 | m->ip = regs->ip; |
94ad8474 AK |
412 | m->cs = regs->cs; |
413 | } else { | |
65ea5b03 | 414 | m->ip = 0; |
94ad8474 AK |
415 | m->cs = 0; |
416 | } | |
1b2797dc | 417 | if (rip_msr) |
5f8c1a54 | 418 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
419 | } |
420 | ||
ccc3c319 AK |
421 | #ifdef CONFIG_X86_LOCAL_APIC |
422 | /* | |
423 | * Called after interrupts have been reenabled again | |
424 | * when a MCE happened during an interrupts off region | |
425 | * in the kernel. | |
426 | */ | |
427 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
428 | { | |
429 | ack_APIC_irq(); | |
430 | exit_idle(); | |
431 | irq_enter(); | |
9ff36ee9 | 432 | mce_notify_irq(); |
9b1beaf2 | 433 | mce_schedule_work(); |
ccc3c319 AK |
434 | irq_exit(); |
435 | } | |
436 | #endif | |
437 | ||
438 | static void mce_report_event(struct pt_regs *regs) | |
439 | { | |
440 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 441 | mce_notify_irq(); |
9b1beaf2 AK |
442 | /* |
443 | * Triggering the work queue here is just an insurance | |
444 | * policy in case the syscall exit notify handler | |
445 | * doesn't run soon enough or ends up running on the | |
446 | * wrong CPU (can happen when audit sleeps) | |
447 | */ | |
448 | mce_schedule_work(); | |
ccc3c319 AK |
449 | return; |
450 | } | |
451 | ||
452 | #ifdef CONFIG_X86_LOCAL_APIC | |
453 | /* | |
454 | * Without APIC do not notify. The event will be picked | |
455 | * up eventually. | |
456 | */ | |
457 | if (!cpu_has_apic) | |
458 | return; | |
459 | ||
460 | /* | |
461 | * When interrupts are disabled we cannot use | |
462 | * kernel services safely. Trigger an self interrupt | |
463 | * through the APIC to instead do the notification | |
464 | * after interrupts are reenabled again. | |
465 | */ | |
466 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
467 | ||
468 | /* | |
469 | * Wait for idle afterwards again so that we don't leave the | |
470 | * APIC in a non idle state because the normal APIC writes | |
471 | * cannot exclude us. | |
472 | */ | |
473 | apic_wait_icr_idle(); | |
474 | #endif | |
475 | } | |
476 | ||
ca84f696 AK |
477 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
478 | ||
d88203d1 | 479 | /* |
b79109c3 AK |
480 | * Poll for corrected events or events that happened before reset. |
481 | * Those are just logged through /dev/mcelog. | |
482 | * | |
483 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
484 | * |
485 | * Note: spec recommends to panic for fatal unsignalled | |
486 | * errors here. However this would be quite problematic -- | |
487 | * we would need to reimplement the Monarch handling and | |
488 | * it would mess up the exclusion between exception handler | |
489 | * and poll hander -- * so we skip this for now. | |
490 | * These cases should not happen anyways, or only when the CPU | |
491 | * is already totally * confused. In this case it's likely it will | |
492 | * not fully execute the machine check handler either. | |
b79109c3 | 493 | */ |
ee031c31 | 494 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
495 | { |
496 | struct mce m; | |
497 | int i; | |
498 | ||
ca84f696 AK |
499 | __get_cpu_var(mce_poll_count)++; |
500 | ||
b79109c3 AK |
501 | mce_setup(&m); |
502 | ||
5f8c1a54 | 503 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 504 | for (i = 0; i < banks; i++) { |
ee031c31 | 505 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
506 | continue; |
507 | ||
508 | m.misc = 0; | |
509 | m.addr = 0; | |
510 | m.bank = i; | |
511 | m.tsc = 0; | |
512 | ||
513 | barrier(); | |
5f8c1a54 | 514 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
515 | if (!(m.status & MCI_STATUS_VAL)) |
516 | continue; | |
517 | ||
518 | /* | |
ed7290d0 AK |
519 | * Uncorrected or signalled events are handled by the exception |
520 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
521 | * |
522 | * TBD do the same check for MCI_STATUS_EN here? | |
523 | */ | |
ed7290d0 AK |
524 | if (!(flags & MCP_UC) && |
525 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
526 | continue; |
527 | ||
528 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 529 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 530 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 531 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
532 | |
533 | if (!(flags & MCP_TIMESTAMP)) | |
534 | m.tsc = 0; | |
535 | /* | |
536 | * Don't get the IP here because it's unlikely to | |
537 | * have anything to do with the actual error location. | |
538 | */ | |
62fdac59 | 539 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
540 | mce_log(&m); |
541 | add_taint(TAINT_MACHINE_CHECK); | |
542 | } | |
b79109c3 AK |
543 | |
544 | /* | |
545 | * Clear state for this bank. | |
546 | */ | |
5f8c1a54 | 547 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
548 | } |
549 | ||
550 | /* | |
551 | * Don't clear MCG_STATUS here because it's only defined for | |
552 | * exceptions. | |
553 | */ | |
88921be3 AK |
554 | |
555 | sync_core(); | |
b79109c3 | 556 | } |
ea149b36 | 557 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 558 | |
bd19a5e6 AK |
559 | /* |
560 | * Do a quick check if any of the events requires a panic. | |
561 | * This decides if we keep the events around or clear them. | |
562 | */ | |
563 | static int mce_no_way_out(struct mce *m, char **msg) | |
564 | { | |
565 | int i; | |
566 | ||
567 | for (i = 0; i < banks; i++) { | |
568 | m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | |
569 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) | |
570 | return 1; | |
571 | } | |
572 | return 0; | |
573 | } | |
574 | ||
3c079792 AK |
575 | /* |
576 | * Variable to establish order between CPUs while scanning. | |
577 | * Each CPU spins initially until executing is equal its number. | |
578 | */ | |
579 | static atomic_t mce_executing; | |
580 | ||
581 | /* | |
582 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
583 | */ | |
584 | static atomic_t mce_callin; | |
585 | ||
586 | /* | |
587 | * Check if a timeout waiting for other CPUs happened. | |
588 | */ | |
589 | static int mce_timed_out(u64 *t) | |
590 | { | |
591 | /* | |
592 | * The others already did panic for some reason. | |
593 | * Bail out like in a timeout. | |
594 | * rmb() to tell the compiler that system_state | |
595 | * might have been modified by someone else. | |
596 | */ | |
597 | rmb(); | |
598 | if (atomic_read(&mce_paniced)) | |
599 | wait_for_panic(); | |
600 | if (!monarch_timeout) | |
601 | goto out; | |
602 | if ((s64)*t < SPINUNIT) { | |
603 | /* CHECKME: Make panic default for 1 too? */ | |
604 | if (tolerant < 1) | |
605 | mce_panic("Timeout synchronizing machine check over CPUs", | |
606 | NULL, NULL); | |
607 | cpu_missing = 1; | |
608 | return 1; | |
609 | } | |
610 | *t -= SPINUNIT; | |
611 | out: | |
612 | touch_nmi_watchdog(); | |
613 | return 0; | |
614 | } | |
615 | ||
616 | /* | |
617 | * The Monarch's reign. The Monarch is the CPU who entered | |
618 | * the machine check handler first. It waits for the others to | |
619 | * raise the exception too and then grades them. When any | |
620 | * error is fatal panic. Only then let the others continue. | |
621 | * | |
622 | * The other CPUs entering the MCE handler will be controlled by the | |
623 | * Monarch. They are called Subjects. | |
624 | * | |
625 | * This way we prevent any potential data corruption in a unrecoverable case | |
626 | * and also makes sure always all CPU's errors are examined. | |
627 | * | |
628 | * Also this detects the case of an machine check event coming from outer | |
629 | * space (not detected by any CPUs) In this case some external agent wants | |
630 | * us to shut down, so panic too. | |
631 | * | |
632 | * The other CPUs might still decide to panic if the handler happens | |
633 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
634 | * state and won't corrupt anything by itself. It's ok to let the others | |
635 | * continue for a bit first. | |
636 | * | |
637 | * All the spin loops have timeouts; when a timeout happens a CPU | |
638 | * typically elects itself to be Monarch. | |
639 | */ | |
640 | static void mce_reign(void) | |
641 | { | |
642 | int cpu; | |
643 | struct mce *m = NULL; | |
644 | int global_worst = 0; | |
645 | char *msg = NULL; | |
646 | char *nmsg = NULL; | |
647 | ||
648 | /* | |
649 | * This CPU is the Monarch and the other CPUs have run | |
650 | * through their handlers. | |
651 | * Grade the severity of the errors of all the CPUs. | |
652 | */ | |
653 | for_each_possible_cpu(cpu) { | |
654 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
655 | &nmsg); | |
656 | if (severity > global_worst) { | |
657 | msg = nmsg; | |
658 | global_worst = severity; | |
659 | m = &per_cpu(mces_seen, cpu); | |
660 | } | |
661 | } | |
662 | ||
663 | /* | |
664 | * Cannot recover? Panic here then. | |
665 | * This dumps all the mces in the log buffer and stops the | |
666 | * other CPUs. | |
667 | */ | |
668 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 669 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
670 | |
671 | /* | |
672 | * For UC somewhere we let the CPU who detects it handle it. | |
673 | * Also must let continue the others, otherwise the handling | |
674 | * CPU could deadlock on a lock. | |
675 | */ | |
676 | ||
677 | /* | |
678 | * No machine check event found. Must be some external | |
679 | * source or one CPU is hung. Panic. | |
680 | */ | |
681 | if (!m && tolerant < 3) | |
682 | mce_panic("Machine check from unknown source", NULL, NULL); | |
683 | ||
684 | /* | |
685 | * Now clear all the mces_seen so that they don't reappear on | |
686 | * the next mce. | |
687 | */ | |
688 | for_each_possible_cpu(cpu) | |
689 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
690 | } | |
691 | ||
692 | static atomic_t global_nwo; | |
693 | ||
694 | /* | |
695 | * Start of Monarch synchronization. This waits until all CPUs have | |
696 | * entered the exception handler and then determines if any of them | |
697 | * saw a fatal event that requires panic. Then it executes them | |
698 | * in the entry order. | |
699 | * TBD double check parallel CPU hotunplug | |
700 | */ | |
7fb06fc9 | 701 | static int mce_start(int *no_way_out) |
3c079792 | 702 | { |
7fb06fc9 | 703 | int order; |
3c079792 AK |
704 | int cpus = num_online_cpus(); |
705 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
706 | ||
7fb06fc9 HS |
707 | if (!timeout) |
708 | return -1; | |
3c079792 | 709 | |
7fb06fc9 | 710 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
711 | /* |
712 | * global_nwo should be updated before mce_callin | |
713 | */ | |
714 | smp_wmb(); | |
7fb06fc9 | 715 | order = atomic_add_return(1, &mce_callin); |
3c079792 AK |
716 | |
717 | /* | |
718 | * Wait for everyone. | |
719 | */ | |
720 | while (atomic_read(&mce_callin) != cpus) { | |
721 | if (mce_timed_out(&timeout)) { | |
722 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 723 | return -1; |
3c079792 AK |
724 | } |
725 | ndelay(SPINUNIT); | |
726 | } | |
727 | ||
184e1fdf HY |
728 | /* |
729 | * mce_callin should be read before global_nwo | |
730 | */ | |
731 | smp_rmb(); | |
3c079792 | 732 | |
7fb06fc9 HS |
733 | if (order == 1) { |
734 | /* | |
735 | * Monarch: Starts executing now, the others wait. | |
736 | */ | |
3c079792 | 737 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
738 | } else { |
739 | /* | |
740 | * Subject: Now start the scanning loop one by one in | |
741 | * the original callin order. | |
742 | * This way when there are any shared banks it will be | |
743 | * only seen by one CPU before cleared, avoiding duplicates. | |
744 | */ | |
745 | while (atomic_read(&mce_executing) < order) { | |
746 | if (mce_timed_out(&timeout)) { | |
747 | atomic_set(&global_nwo, 0); | |
748 | return -1; | |
749 | } | |
750 | ndelay(SPINUNIT); | |
751 | } | |
3c079792 AK |
752 | } |
753 | ||
754 | /* | |
7fb06fc9 | 755 | * Cache the global no_way_out state. |
3c079792 | 756 | */ |
7fb06fc9 HS |
757 | *no_way_out = atomic_read(&global_nwo); |
758 | ||
759 | return order; | |
3c079792 AK |
760 | } |
761 | ||
762 | /* | |
763 | * Synchronize between CPUs after main scanning loop. | |
764 | * This invokes the bulk of the Monarch processing. | |
765 | */ | |
766 | static int mce_end(int order) | |
767 | { | |
768 | int ret = -1; | |
769 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
770 | ||
771 | if (!timeout) | |
772 | goto reset; | |
773 | if (order < 0) | |
774 | goto reset; | |
775 | ||
776 | /* | |
777 | * Allow others to run. | |
778 | */ | |
779 | atomic_inc(&mce_executing); | |
780 | ||
781 | if (order == 1) { | |
782 | /* CHECKME: Can this race with a parallel hotplug? */ | |
783 | int cpus = num_online_cpus(); | |
784 | ||
785 | /* | |
786 | * Monarch: Wait for everyone to go through their scanning | |
787 | * loops. | |
788 | */ | |
789 | while (atomic_read(&mce_executing) <= cpus) { | |
790 | if (mce_timed_out(&timeout)) | |
791 | goto reset; | |
792 | ndelay(SPINUNIT); | |
793 | } | |
794 | ||
795 | mce_reign(); | |
796 | barrier(); | |
797 | ret = 0; | |
798 | } else { | |
799 | /* | |
800 | * Subject: Wait for Monarch to finish. | |
801 | */ | |
802 | while (atomic_read(&mce_executing) != 0) { | |
803 | if (mce_timed_out(&timeout)) | |
804 | goto reset; | |
805 | ndelay(SPINUNIT); | |
806 | } | |
807 | ||
808 | /* | |
809 | * Don't reset anything. That's done by the Monarch. | |
810 | */ | |
811 | return 0; | |
812 | } | |
813 | ||
814 | /* | |
815 | * Reset all global state. | |
816 | */ | |
817 | reset: | |
818 | atomic_set(&global_nwo, 0); | |
819 | atomic_set(&mce_callin, 0); | |
820 | barrier(); | |
821 | ||
822 | /* | |
823 | * Let others run again. | |
824 | */ | |
825 | atomic_set(&mce_executing, 0); | |
826 | return ret; | |
827 | } | |
828 | ||
9b1beaf2 AK |
829 | /* |
830 | * Check if the address reported by the CPU is in a format we can parse. | |
831 | * It would be possible to add code for most other cases, but all would | |
832 | * be somewhat complicated (e.g. segment offset would require an instruction | |
833 | * parser). So only support physical addresses upto page granuality for now. | |
834 | */ | |
835 | static int mce_usable_address(struct mce *m) | |
836 | { | |
837 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
838 | return 0; | |
839 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
840 | return 0; | |
841 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
842 | return 0; | |
843 | return 1; | |
844 | } | |
845 | ||
3c079792 AK |
846 | static void mce_clear_state(unsigned long *toclear) |
847 | { | |
848 | int i; | |
849 | ||
850 | for (i = 0; i < banks; i++) { | |
851 | if (test_bit(i, toclear)) | |
852 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
853 | } | |
854 | } | |
855 | ||
b79109c3 AK |
856 | /* |
857 | * The actual machine check handler. This only handles real | |
858 | * exceptions when something got corrupted coming in through int 18. | |
859 | * | |
860 | * This is executed in NMI context not subject to normal locking rules. This | |
861 | * implies that most kernel services cannot be safely used. Don't even | |
862 | * think about putting a printk in there! | |
3c079792 AK |
863 | * |
864 | * On Intel systems this is entered on all CPUs in parallel through | |
865 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
866 | * so be always careful when synchronizing with others. | |
1da177e4 | 867 | */ |
e9eee03e | 868 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 869 | { |
3c079792 | 870 | struct mce m, *final; |
1da177e4 | 871 | int i; |
3c079792 AK |
872 | int worst = 0; |
873 | int severity; | |
874 | /* | |
875 | * Establish sequential order between the CPUs entering the machine | |
876 | * check handler. | |
877 | */ | |
7fb06fc9 | 878 | int order; |
bd78432c TH |
879 | /* |
880 | * If no_way_out gets set, there is no safe way to recover from this | |
881 | * MCE. If tolerant is cranked up, we'll try anyway. | |
882 | */ | |
883 | int no_way_out = 0; | |
884 | /* | |
885 | * If kill_it gets set, there might be a way to recover from this | |
886 | * error. | |
887 | */ | |
888 | int kill_it = 0; | |
b79109c3 | 889 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 890 | char *msg = "Unknown"; |
1da177e4 | 891 | |
553f265f AK |
892 | atomic_inc(&mce_entry); |
893 | ||
01ca79f1 AK |
894 | __get_cpu_var(mce_exception_count)++; |
895 | ||
b79109c3 | 896 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 897 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 898 | goto out; |
b79109c3 | 899 | if (!banks) |
32561696 | 900 | goto out; |
1da177e4 | 901 | |
b5f2fa4e AK |
902 | mce_setup(&m); |
903 | ||
5f8c1a54 | 904 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
bd19a5e6 | 905 | no_way_out = mce_no_way_out(&m, &msg); |
d88203d1 | 906 | |
3c079792 AK |
907 | final = &__get_cpu_var(mces_seen); |
908 | *final = m; | |
909 | ||
1da177e4 LT |
910 | barrier(); |
911 | ||
ed7290d0 AK |
912 | /* |
913 | * When no restart IP must always kill or panic. | |
914 | */ | |
915 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
916 | kill_it = 1; | |
917 | ||
3c079792 AK |
918 | /* |
919 | * Go through all the banks in exclusion of the other CPUs. | |
920 | * This way we don't report duplicated events on shared banks | |
921 | * because the first one to see it will clear it. | |
922 | */ | |
7fb06fc9 | 923 | order = mce_start(&no_way_out); |
1da177e4 | 924 | for (i = 0; i < banks; i++) { |
b79109c3 | 925 | __clear_bit(i, toclear); |
0d7482e3 | 926 | if (!bank[i]) |
1da177e4 | 927 | continue; |
d88203d1 TG |
928 | |
929 | m.misc = 0; | |
1da177e4 LT |
930 | m.addr = 0; |
931 | m.bank = i; | |
1da177e4 | 932 | |
5f8c1a54 | 933 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
934 | if ((m.status & MCI_STATUS_VAL) == 0) |
935 | continue; | |
936 | ||
b79109c3 | 937 | /* |
ed7290d0 AK |
938 | * Non uncorrected or non signaled errors are handled by |
939 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 940 | */ |
ed7290d0 AK |
941 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
942 | !no_way_out) | |
b79109c3 AK |
943 | continue; |
944 | ||
945 | /* | |
946 | * Set taint even when machine check was not enabled. | |
947 | */ | |
948 | add_taint(TAINT_MACHINE_CHECK); | |
949 | ||
ed7290d0 | 950 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 951 | |
ed7290d0 AK |
952 | /* |
953 | * When machine check was for corrected handler don't touch, | |
954 | * unless we're panicing. | |
955 | */ | |
956 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
957 | continue; | |
958 | __set_bit(i, toclear); | |
959 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
960 | /* |
961 | * Machine check event was not enabled. Clear, but | |
962 | * ignore. | |
963 | */ | |
964 | continue; | |
1da177e4 LT |
965 | } |
966 | ||
ed7290d0 AK |
967 | /* |
968 | * Kill on action required. | |
969 | */ | |
970 | if (severity == MCE_AR_SEVERITY) | |
971 | kill_it = 1; | |
972 | ||
1da177e4 | 973 | if (m.status & MCI_STATUS_MISCV) |
5f8c1a54 | 974 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 975 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 976 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 977 | |
9b1beaf2 AK |
978 | /* |
979 | * Action optional error. Queue address for later processing. | |
980 | * When the ring overflows we just ignore the AO error. | |
981 | * RED-PEN add some logging mechanism when | |
982 | * usable_address or mce_add_ring fails. | |
983 | * RED-PEN don't ignore overflow for tolerant == 0 | |
984 | */ | |
985 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
986 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
987 | ||
94ad8474 | 988 | mce_get_rip(&m, regs); |
b79109c3 | 989 | mce_log(&m); |
1da177e4 | 990 | |
3c079792 AK |
991 | if (severity > worst) { |
992 | *final = m; | |
993 | worst = severity; | |
1da177e4 | 994 | } |
1da177e4 LT |
995 | } |
996 | ||
3c079792 AK |
997 | if (!no_way_out) |
998 | mce_clear_state(toclear); | |
999 | ||
e9eee03e | 1000 | /* |
3c079792 AK |
1001 | * Do most of the synchronization with other CPUs. |
1002 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1003 | */ |
3c079792 AK |
1004 | if (mce_end(order) < 0) |
1005 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1006 | |
1007 | /* | |
1008 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1009 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1010 | * |
1011 | * This is mainly used in the case when the system doesn't | |
1012 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1013 | */ |
1014 | if (no_way_out && tolerant < 3) | |
ac960375 | 1015 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1016 | |
1017 | /* | |
1018 | * If the error seems to be unrecoverable, something should be | |
1019 | * done. Try to kill as little as possible. If we can kill just | |
1020 | * one task, do that. If the user has set the tolerance very | |
1021 | * high, don't try to do anything at all. | |
1022 | */ | |
bd78432c | 1023 | |
ed7290d0 AK |
1024 | if (kill_it && tolerant < 3) |
1025 | force_sig(SIGBUS, current); | |
1da177e4 | 1026 | |
e02e68d3 TH |
1027 | /* notify userspace ASAP */ |
1028 | set_thread_flag(TIF_MCE_NOTIFY); | |
1029 | ||
3c079792 AK |
1030 | if (worst > 0) |
1031 | mce_report_event(regs); | |
5f8c1a54 | 1032 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1033 | out: |
553f265f | 1034 | atomic_dec(&mce_entry); |
88921be3 | 1035 | sync_core(); |
1da177e4 | 1036 | } |
ea149b36 | 1037 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1038 | |
9b1beaf2 AK |
1039 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1040 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1041 | { | |
1042 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1043 | } | |
1044 | ||
1045 | /* | |
1046 | * Called after mce notification in process context. This code | |
1047 | * is allowed to sleep. Call the high level VM handler to process | |
1048 | * any corrupted pages. | |
1049 | * Assume that the work queue code only calls this one at a time | |
1050 | * per CPU. | |
1051 | * Note we don't disable preemption, so this code might run on the wrong | |
1052 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1053 | * This is merely a fast path to expedite processing in some common | |
1054 | * cases. | |
1055 | */ | |
1056 | void mce_notify_process(void) | |
1057 | { | |
1058 | unsigned long pfn; | |
1059 | mce_notify_irq(); | |
1060 | while (mce_ring_get(&pfn)) | |
1061 | memory_failure(pfn, MCE_VECTOR); | |
1062 | } | |
1063 | ||
1064 | static void mce_process_work(struct work_struct *dummy) | |
1065 | { | |
1066 | mce_notify_process(); | |
1067 | } | |
1068 | ||
15d5f839 DZ |
1069 | #ifdef CONFIG_X86_MCE_INTEL |
1070 | /*** | |
1071 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1072 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1073 | * @status: Event status information |
1074 | * | |
1075 | * This function should be called by the thermal interrupt after the | |
1076 | * event has been processed and the decision was made to log the event | |
1077 | * further. | |
1078 | * | |
1079 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1080 | * and historically has been the register value of the | |
1081 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1082 | */ | |
b5f2fa4e | 1083 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1084 | { |
1085 | struct mce m; | |
1086 | ||
b5f2fa4e | 1087 | mce_setup(&m); |
15d5f839 DZ |
1088 | m.bank = MCE_THERMAL_BANK; |
1089 | m.status = status; | |
15d5f839 DZ |
1090 | mce_log(&m); |
1091 | } | |
1092 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1093 | ||
1da177e4 | 1094 | /* |
8a336b0a TH |
1095 | * Periodic polling timer for "silent" machine check errors. If the |
1096 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1097 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1098 | */ |
1da177e4 | 1099 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1100 | |
6298c512 | 1101 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 1102 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1103 | |
52d168e2 | 1104 | static void mcheck_timer(unsigned long data) |
1da177e4 | 1105 | { |
52d168e2 | 1106 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1107 | int *n; |
52d168e2 AK |
1108 | |
1109 | WARN_ON(smp_processor_id() != data); | |
1110 | ||
e9eee03e | 1111 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1112 | machine_check_poll(MCP_TIMESTAMP, |
1113 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1114 | } |
1da177e4 LT |
1115 | |
1116 | /* | |
e02e68d3 TH |
1117 | * Alert userspace if needed. If we logged an MCE, reduce the |
1118 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1119 | */ |
6298c512 | 1120 | n = &__get_cpu_var(next_interval); |
9ff36ee9 | 1121 | if (mce_notify_irq()) |
6298c512 | 1122 | *n = max(*n/2, HZ/100); |
14a02530 | 1123 | else |
6298c512 | 1124 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1125 | |
6298c512 | 1126 | t->expires = jiffies + *n; |
5be6066a | 1127 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1128 | } |
1129 | ||
9bd98405 AK |
1130 | static void mce_do_trigger(struct work_struct *work) |
1131 | { | |
1020bcbc | 1132 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1133 | } |
1134 | ||
1135 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1136 | ||
e02e68d3 | 1137 | /* |
9bd98405 AK |
1138 | * Notify the user(s) about new machine check events. |
1139 | * Can be called from interrupt context, but not from machine check/NMI | |
1140 | * context. | |
e02e68d3 | 1141 | */ |
9ff36ee9 | 1142 | int mce_notify_irq(void) |
e02e68d3 | 1143 | { |
8457c84d AK |
1144 | /* Not more than two messages every minute */ |
1145 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1146 | ||
e02e68d3 | 1147 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1148 | |
1020bcbc | 1149 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1150 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1151 | |
1152 | /* | |
1153 | * There is no risk of missing notifications because | |
1154 | * work_pending is always cleared before the function is | |
1155 | * executed. | |
1156 | */ | |
1020bcbc | 1157 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1158 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1159 | |
8457c84d | 1160 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1161 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1162 | |
1163 | return 1; | |
1da177e4 | 1164 | } |
e02e68d3 TH |
1165 | return 0; |
1166 | } | |
9ff36ee9 | 1167 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1168 | |
d88203d1 | 1169 | /* |
1da177e4 LT |
1170 | * Initialize Machine Checks for a CPU. |
1171 | */ | |
0d7482e3 | 1172 | static int mce_cap_init(void) |
1da177e4 | 1173 | { |
0d7482e3 | 1174 | unsigned b; |
e9eee03e | 1175 | u64 cap; |
1da177e4 LT |
1176 | |
1177 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1178 | |
1179 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
1180 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
1181 | ||
0d7482e3 AK |
1182 | if (b > MAX_NR_BANKS) { |
1183 | printk(KERN_WARNING | |
1184 | "MCE: Using only %u machine check banks out of %u\n", | |
1185 | MAX_NR_BANKS, b); | |
1186 | b = MAX_NR_BANKS; | |
1187 | } | |
1188 | ||
1189 | /* Don't support asymmetric configurations today */ | |
1190 | WARN_ON(banks != 0 && b != banks); | |
1191 | banks = b; | |
1192 | if (!bank) { | |
1193 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
1194 | if (!bank) | |
1195 | return -ENOMEM; | |
1196 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 1197 | } |
0d7482e3 | 1198 | |
94ad8474 | 1199 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1200 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1201 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1202 | |
ed7290d0 AK |
1203 | if (cap & MCG_SER_P) |
1204 | mce_ser = 1; | |
1205 | ||
0d7482e3 AK |
1206 | return 0; |
1207 | } | |
1208 | ||
8be91105 | 1209 | static void mce_init(void) |
0d7482e3 | 1210 | { |
e9eee03e | 1211 | mce_banks_t all_banks; |
0d7482e3 AK |
1212 | u64 cap; |
1213 | int i; | |
1214 | ||
b79109c3 AK |
1215 | /* |
1216 | * Log the machine checks left over from the previous reset. | |
1217 | */ | |
ee031c31 | 1218 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1219 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1220 | |
1221 | set_in_cr4(X86_CR4_MCE); | |
1222 | ||
0d7482e3 | 1223 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1224 | if (cap & MCG_CTL_P) |
1225 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1226 | ||
1227 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
1228 | if (skip_bank_init(i)) |
1229 | continue; | |
0d7482e3 | 1230 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 1231 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 1232 | } |
1da177e4 LT |
1233 | } |
1234 | ||
1235 | /* Add per CPU specific workarounds here */ | |
e412cd25 | 1236 | static int mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1237 | { |
e412cd25 IM |
1238 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1239 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1240 | return -EOPNOTSUPP; | |
1241 | } | |
1242 | ||
1da177e4 | 1243 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1244 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1245 | if (c->x86 == 15 && banks > 4) { |
1246 | /* | |
1247 | * disable GART TBL walk error reporting, which | |
1248 | * trips off incorrectly with the IOMMU & 3ware | |
1249 | * & Cerberus: | |
1250 | */ | |
0d7482e3 | 1251 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
1252 | } |
1253 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1254 | /* | |
1255 | * Lots of broken BIOS around that don't clear them | |
1256 | * by default and leave crap in there. Don't log: | |
1257 | */ | |
911f6a7b | 1258 | mce_bootlog = 0; |
e9eee03e | 1259 | } |
2e6f694f AK |
1260 | /* |
1261 | * Various K7s with broken bank 0 around. Always disable | |
1262 | * by default. | |
1263 | */ | |
203abd67 | 1264 | if (c->x86 == 6 && banks > 0) |
2e6f694f | 1265 | bank[0] = 0; |
1da177e4 | 1266 | } |
e583538f | 1267 | |
06b7a7a5 AK |
1268 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1269 | /* | |
1270 | * SDM documents that on family 6 bank 0 should not be written | |
1271 | * because it aliases to another special BIOS controlled | |
1272 | * register. | |
1273 | * But it's not aliased anymore on model 0x1a+ | |
1274 | * Don't ignore bank 0 completely because there could be a | |
1275 | * valid event later, merely don't write CTL0. | |
1276 | */ | |
1277 | ||
1278 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
1279 | __set_bit(0, &dont_init_banks); | |
3c079792 AK |
1280 | |
1281 | /* | |
1282 | * All newer Intel systems support MCE broadcasting. Enable | |
1283 | * synchronization with a one second timeout. | |
1284 | */ | |
1285 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1286 | monarch_timeout < 0) | |
1287 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1288 | |
e412cd25 IM |
1289 | /* |
1290 | * There are also broken BIOSes on some Pentium M and | |
1291 | * earlier systems: | |
1292 | */ | |
1293 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1294 | mce_bootlog = 0; |
06b7a7a5 | 1295 | } |
3c079792 AK |
1296 | if (monarch_timeout < 0) |
1297 | monarch_timeout = 0; | |
29b0f591 AK |
1298 | if (mce_bootlog != 0) |
1299 | mce_panic_timeout = 30; | |
e412cd25 IM |
1300 | |
1301 | return 0; | |
d88203d1 | 1302 | } |
1da177e4 | 1303 | |
4efc0670 AK |
1304 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
1305 | { | |
1306 | if (c->x86 != 5) | |
1307 | return; | |
1308 | switch (c->x86_vendor) { | |
1309 | case X86_VENDOR_INTEL: | |
c6978369 | 1310 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1311 | break; |
1312 | case X86_VENDOR_CENTAUR: | |
1313 | winchip_mcheck_init(c); | |
1314 | break; | |
1315 | } | |
1316 | } | |
1317 | ||
cc3ca220 | 1318 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
1319 | { |
1320 | switch (c->x86_vendor) { | |
1321 | case X86_VENDOR_INTEL: | |
1322 | mce_intel_feature_init(c); | |
1323 | break; | |
89b831ef JS |
1324 | case X86_VENDOR_AMD: |
1325 | mce_amd_feature_init(c); | |
1326 | break; | |
1da177e4 LT |
1327 | default: |
1328 | break; | |
1329 | } | |
1330 | } | |
1331 | ||
52d168e2 AK |
1332 | static void mce_init_timer(void) |
1333 | { | |
1334 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 1335 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 1336 | |
62fdac59 HS |
1337 | if (mce_ignore_ce) |
1338 | return; | |
1339 | ||
6298c512 AK |
1340 | *n = check_interval * HZ; |
1341 | if (!*n) | |
52d168e2 AK |
1342 | return; |
1343 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 1344 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1345 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1346 | } |
1347 | ||
d88203d1 | 1348 | /* |
1da177e4 | 1349 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1350 | * Must be called with preempt off: |
1da177e4 | 1351 | */ |
e6982c67 | 1352 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 1353 | { |
4efc0670 AK |
1354 | if (mce_disabled) |
1355 | return; | |
1356 | ||
1357 | mce_ancient_init(c); | |
1358 | ||
5b4408fd | 1359 | if (!mce_available(c)) |
1da177e4 LT |
1360 | return; |
1361 | ||
e412cd25 | 1362 | if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) { |
04b2b1a4 | 1363 | mce_disabled = 1; |
0d7482e3 AK |
1364 | return; |
1365 | } | |
0d7482e3 | 1366 | |
5d727926 AK |
1367 | machine_check_vector = do_machine_check; |
1368 | ||
8be91105 | 1369 | mce_init(); |
1da177e4 | 1370 | mce_cpu_features(c); |
52d168e2 | 1371 | mce_init_timer(); |
9b1beaf2 | 1372 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
1da177e4 LT |
1373 | } |
1374 | ||
1375 | /* | |
1376 | * Character device to read and clear the MCE log. | |
1377 | */ | |
1378 | ||
f528e7ba | 1379 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1380 | static int open_count; /* #times opened */ |
1381 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1382 | |
1383 | static int mce_open(struct inode *inode, struct file *file) | |
1384 | { | |
1385 | spin_lock(&mce_state_lock); | |
1386 | ||
1387 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1388 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1389 | |
f528e7ba TH |
1390 | return -EBUSY; |
1391 | } | |
1392 | ||
1393 | if (file->f_flags & O_EXCL) | |
1394 | open_exclu = 1; | |
1395 | open_count++; | |
1396 | ||
1397 | spin_unlock(&mce_state_lock); | |
1398 | ||
bd78432c | 1399 | return nonseekable_open(inode, file); |
f528e7ba TH |
1400 | } |
1401 | ||
1402 | static int mce_release(struct inode *inode, struct file *file) | |
1403 | { | |
1404 | spin_lock(&mce_state_lock); | |
1405 | ||
1406 | open_count--; | |
1407 | open_exclu = 0; | |
1408 | ||
1409 | spin_unlock(&mce_state_lock); | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
d88203d1 TG |
1414 | static void collect_tscs(void *data) |
1415 | { | |
1da177e4 | 1416 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1417 | |
1da177e4 | 1418 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1419 | } |
1da177e4 | 1420 | |
e9eee03e IM |
1421 | static DEFINE_MUTEX(mce_read_mutex); |
1422 | ||
d88203d1 TG |
1423 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1424 | loff_t *off) | |
1da177e4 | 1425 | { |
e9eee03e | 1426 | char __user *buf = ubuf; |
f0de53bb | 1427 | unsigned long *cpu_tsc; |
ef41df43 | 1428 | unsigned prev, next; |
1da177e4 LT |
1429 | int i, err; |
1430 | ||
6bca67f9 | 1431 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1432 | if (!cpu_tsc) |
1433 | return -ENOMEM; | |
1434 | ||
8c8b8859 | 1435 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
1436 | next = rcu_dereference(mcelog.next); |
1437 | ||
1438 | /* Only supports full reads right now */ | |
d88203d1 | 1439 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1440 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1441 | kfree(cpu_tsc); |
e9eee03e | 1442 | |
1da177e4 LT |
1443 | return -EINVAL; |
1444 | } | |
1445 | ||
1446 | err = 0; | |
ef41df43 HY |
1447 | prev = 0; |
1448 | do { | |
1449 | for (i = prev; i < next; i++) { | |
1450 | unsigned long start = jiffies; | |
1451 | ||
1452 | while (!mcelog.entry[i].finished) { | |
1453 | if (time_after_eq(jiffies, start + 2)) { | |
1454 | memset(mcelog.entry + i, 0, | |
1455 | sizeof(struct mce)); | |
1456 | goto timeout; | |
1457 | } | |
1458 | cpu_relax(); | |
673242c1 | 1459 | } |
ef41df43 HY |
1460 | smp_rmb(); |
1461 | err |= copy_to_user(buf, mcelog.entry + i, | |
1462 | sizeof(struct mce)); | |
1463 | buf += sizeof(struct mce); | |
1464 | timeout: | |
1465 | ; | |
673242c1 | 1466 | } |
1da177e4 | 1467 | |
ef41df43 HY |
1468 | memset(mcelog.entry + prev, 0, |
1469 | (next - prev) * sizeof(struct mce)); | |
1470 | prev = next; | |
1471 | next = cmpxchg(&mcelog.next, prev, 0); | |
1472 | } while (next != prev); | |
1da177e4 | 1473 | |
b2b18660 | 1474 | synchronize_sched(); |
1da177e4 | 1475 | |
d88203d1 TG |
1476 | /* |
1477 | * Collect entries that were still getting written before the | |
1478 | * synchronize. | |
1479 | */ | |
15c8b6c1 | 1480 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1481 | |
d88203d1 TG |
1482 | for (i = next; i < MCE_LOG_LEN; i++) { |
1483 | if (mcelog.entry[i].finished && | |
1484 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1485 | err |= copy_to_user(buf, mcelog.entry+i, | |
1486 | sizeof(struct mce)); | |
1da177e4 LT |
1487 | smp_rmb(); |
1488 | buf += sizeof(struct mce); | |
1489 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1490 | } | |
d88203d1 | 1491 | } |
8c8b8859 | 1492 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1493 | kfree(cpu_tsc); |
e9eee03e | 1494 | |
d88203d1 | 1495 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1496 | } |
1497 | ||
e02e68d3 TH |
1498 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1499 | { | |
1500 | poll_wait(file, &mce_wait, wait); | |
1501 | if (rcu_dereference(mcelog.next)) | |
1502 | return POLLIN | POLLRDNORM; | |
1503 | return 0; | |
1504 | } | |
1505 | ||
c68461b6 | 1506 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1507 | { |
1508 | int __user *p = (int __user *)arg; | |
d88203d1 | 1509 | |
1da177e4 | 1510 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1511 | return -EPERM; |
e9eee03e | 1512 | |
1da177e4 | 1513 | switch (cmd) { |
d88203d1 | 1514 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1515 | return put_user(sizeof(struct mce), p); |
1516 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1517 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1518 | case MCE_GETCLEAR_FLAGS: { |
1519 | unsigned flags; | |
d88203d1 TG |
1520 | |
1521 | do { | |
1da177e4 | 1522 | flags = mcelog.flags; |
d88203d1 | 1523 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1524 | |
d88203d1 | 1525 | return put_user(flags, p); |
1da177e4 LT |
1526 | } |
1527 | default: | |
d88203d1 TG |
1528 | return -ENOTTY; |
1529 | } | |
1da177e4 LT |
1530 | } |
1531 | ||
a1ff41bf | 1532 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1533 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1534 | .open = mce_open, |
1535 | .release = mce_release, | |
1536 | .read = mce_read, | |
1537 | .poll = mce_poll, | |
1538 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1539 | }; |
ea149b36 | 1540 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1541 | |
1542 | static struct miscdevice mce_log_device = { | |
1543 | MISC_MCELOG_MINOR, | |
1544 | "mcelog", | |
1545 | &mce_chrdev_ops, | |
1546 | }; | |
1547 | ||
13503fa9 | 1548 | /* |
62fdac59 HS |
1549 | * mce=off Disables machine check |
1550 | * mce=no_cmci Disables CMCI | |
1551 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1552 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1553 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1554 | * monarchtimeout is how long to wait for other CPUs on machine | |
1555 | * check, or 0 to not wait | |
13503fa9 HS |
1556 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1557 | * mce=nobootlog Don't log MCEs from before booting. | |
1558 | */ | |
1da177e4 LT |
1559 | static int __init mcheck_enable(char *str) |
1560 | { | |
4efc0670 AK |
1561 | if (*str == 0) |
1562 | enable_p5_mce(); | |
1563 | if (*str == '=') | |
1564 | str++; | |
1da177e4 | 1565 | if (!strcmp(str, "off")) |
04b2b1a4 | 1566 | mce_disabled = 1; |
62fdac59 HS |
1567 | else if (!strcmp(str, "no_cmci")) |
1568 | mce_cmci_disabled = 1; | |
1569 | else if (!strcmp(str, "dont_log_ce")) | |
1570 | mce_dont_log_ce = 1; | |
1571 | else if (!strcmp(str, "ignore_ce")) | |
1572 | mce_ignore_ce = 1; | |
13503fa9 HS |
1573 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1574 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1575 | else if (isdigit(str[0])) { |
8c566ef5 | 1576 | get_option(&str, &tolerant); |
3c079792 AK |
1577 | if (*str == ',') { |
1578 | ++str; | |
1579 | get_option(&str, &monarch_timeout); | |
1580 | } | |
1581 | } else { | |
4efc0670 | 1582 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1583 | str); |
1584 | return 0; | |
1585 | } | |
9b41046c | 1586 | return 1; |
1da177e4 | 1587 | } |
4efc0670 | 1588 | __setup("mce", mcheck_enable); |
1da177e4 | 1589 | |
d88203d1 | 1590 | /* |
1da177e4 | 1591 | * Sysfs support |
d88203d1 | 1592 | */ |
1da177e4 | 1593 | |
973a2dd1 AK |
1594 | /* |
1595 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1596 | * them later. | |
1597 | */ | |
1598 | static int mce_disable(void) | |
1599 | { | |
1600 | int i; | |
1601 | ||
06b7a7a5 AK |
1602 | for (i = 0; i < banks; i++) { |
1603 | if (!skip_bank_init(i)) | |
1604 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1605 | } | |
973a2dd1 AK |
1606 | return 0; |
1607 | } | |
1608 | ||
1609 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1610 | { | |
1611 | return mce_disable(); | |
1612 | } | |
1613 | ||
1614 | static int mce_shutdown(struct sys_device *dev) | |
1615 | { | |
1616 | return mce_disable(); | |
1617 | } | |
1618 | ||
e9eee03e IM |
1619 | /* |
1620 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1621 | * Only one CPU is active at this time, the others get re-added later using | |
1622 | * CPU hotplug: | |
1623 | */ | |
1da177e4 LT |
1624 | static int mce_resume(struct sys_device *dev) |
1625 | { | |
8be91105 | 1626 | mce_init(); |
6ec68bff | 1627 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1628 | |
1da177e4 LT |
1629 | return 0; |
1630 | } | |
1631 | ||
52d168e2 AK |
1632 | static void mce_cpu_restart(void *data) |
1633 | { | |
1634 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1635 | if (!mce_available(¤t_cpu_data)) |
1636 | return; | |
1637 | mce_init(); | |
52d168e2 AK |
1638 | mce_init_timer(); |
1639 | } | |
1640 | ||
1da177e4 | 1641 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1642 | static void mce_restart(void) |
1643 | { | |
52d168e2 | 1644 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1645 | } |
1646 | ||
9af43b54 HS |
1647 | /* Toggle features for corrected errors */ |
1648 | static void mce_disable_ce(void *all) | |
1649 | { | |
1650 | if (!mce_available(¤t_cpu_data)) | |
1651 | return; | |
1652 | if (all) | |
1653 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1654 | cmci_clear(); | |
1655 | } | |
1656 | ||
1657 | static void mce_enable_ce(void *all) | |
1658 | { | |
1659 | if (!mce_available(¤t_cpu_data)) | |
1660 | return; | |
1661 | cmci_reenable(); | |
1662 | cmci_recheck(); | |
1663 | if (all) | |
1664 | mce_init_timer(); | |
1665 | } | |
1666 | ||
1da177e4 | 1667 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1668 | .suspend = mce_suspend, |
1669 | .shutdown = mce_shutdown, | |
1670 | .resume = mce_resume, | |
1671 | .name = "machinecheck", | |
1da177e4 LT |
1672 | }; |
1673 | ||
cb491fca | 1674 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1675 | |
1676 | __cpuinitdata | |
1677 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1678 | |
0d7482e3 AK |
1679 | static struct sysdev_attribute *bank_attrs; |
1680 | ||
1681 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1682 | char *buf) | |
1683 | { | |
1684 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1685 | |
f6d1826d | 1686 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1687 | } |
1688 | ||
1689 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1690 | const char *buf, size_t size) |
0d7482e3 | 1691 | { |
9319cec8 | 1692 | u64 new; |
e9eee03e | 1693 | |
9319cec8 | 1694 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1695 | return -EINVAL; |
e9eee03e | 1696 | |
0d7482e3 AK |
1697 | bank[attr - bank_attrs] = new; |
1698 | mce_restart(); | |
e9eee03e | 1699 | |
9319cec8 | 1700 | return size; |
0d7482e3 | 1701 | } |
a98f0dd3 | 1702 | |
e9eee03e IM |
1703 | static ssize_t |
1704 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1705 | { |
1020bcbc | 1706 | strcpy(buf, mce_helper); |
a98f0dd3 | 1707 | strcat(buf, "\n"); |
1020bcbc | 1708 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1709 | } |
1710 | ||
4a0b2b4d | 1711 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1712 | const char *buf, size_t siz) |
a98f0dd3 AK |
1713 | { |
1714 | char *p; | |
e9eee03e | 1715 | |
1020bcbc HS |
1716 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1717 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1718 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1719 | |
e9084ec9 | 1720 | if (p) |
e9eee03e IM |
1721 | *p = 0; |
1722 | ||
e9084ec9 | 1723 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1724 | } |
1725 | ||
9af43b54 HS |
1726 | static ssize_t set_ignore_ce(struct sys_device *s, |
1727 | struct sysdev_attribute *attr, | |
1728 | const char *buf, size_t size) | |
1729 | { | |
1730 | u64 new; | |
1731 | ||
1732 | if (strict_strtoull(buf, 0, &new) < 0) | |
1733 | return -EINVAL; | |
1734 | ||
1735 | if (mce_ignore_ce ^ !!new) { | |
1736 | if (new) { | |
1737 | /* disable ce features */ | |
1738 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1739 | mce_ignore_ce = 1; | |
1740 | } else { | |
1741 | /* enable ce features */ | |
1742 | mce_ignore_ce = 0; | |
1743 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1744 | } | |
1745 | } | |
1746 | return size; | |
1747 | } | |
1748 | ||
1749 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1750 | struct sysdev_attribute *attr, | |
1751 | const char *buf, size_t size) | |
1752 | { | |
1753 | u64 new; | |
1754 | ||
1755 | if (strict_strtoull(buf, 0, &new) < 0) | |
1756 | return -EINVAL; | |
1757 | ||
1758 | if (mce_cmci_disabled ^ !!new) { | |
1759 | if (new) { | |
1760 | /* disable cmci */ | |
1761 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1762 | mce_cmci_disabled = 1; | |
1763 | } else { | |
1764 | /* enable cmci */ | |
1765 | mce_cmci_disabled = 0; | |
1766 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1767 | } | |
1768 | } | |
1769 | return size; | |
1770 | } | |
1771 | ||
b56f642d AK |
1772 | static ssize_t store_int_with_restart(struct sys_device *s, |
1773 | struct sysdev_attribute *attr, | |
1774 | const char *buf, size_t size) | |
1775 | { | |
1776 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1777 | mce_restart(); | |
1778 | return ret; | |
1779 | } | |
1780 | ||
a98f0dd3 | 1781 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1782 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1783 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1784 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1785 | |
b56f642d AK |
1786 | static struct sysdev_ext_attribute attr_check_interval = { |
1787 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1788 | store_int_with_restart), | |
1789 | &check_interval | |
1790 | }; | |
e9eee03e | 1791 | |
9af43b54 HS |
1792 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1793 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1794 | &mce_ignore_ce | |
1795 | }; | |
1796 | ||
1797 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1798 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1799 | &mce_cmci_disabled |
1800 | }; | |
1801 | ||
cb491fca | 1802 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1803 | &attr_tolerant.attr, |
1804 | &attr_check_interval.attr, | |
1805 | &attr_trigger, | |
3c079792 | 1806 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1807 | &attr_dont_log_ce.attr, |
1808 | &attr_ignore_ce.attr, | |
1809 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1810 | NULL |
1811 | }; | |
1da177e4 | 1812 | |
cb491fca | 1813 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1814 | |
e9eee03e | 1815 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1816 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1817 | { |
1818 | int err; | |
b1f49f95 | 1819 | int i, j; |
92cb7612 | 1820 | |
90367556 | 1821 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1822 | return -EIO; |
1823 | ||
cb491fca IM |
1824 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1825 | per_cpu(mce_dev, cpu).id = cpu; | |
1826 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1827 | |
cb491fca | 1828 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1829 | if (err) |
1830 | return err; | |
1831 | ||
cb491fca IM |
1832 | for (i = 0; mce_attrs[i]; i++) { |
1833 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1834 | if (err) |
1835 | goto error; | |
1836 | } | |
b1f49f95 | 1837 | for (j = 0; j < banks; j++) { |
cb491fca | 1838 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
b1f49f95 | 1839 | &bank_attrs[j]); |
0d7482e3 AK |
1840 | if (err) |
1841 | goto error2; | |
1842 | } | |
cb491fca | 1843 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1844 | |
d435d862 | 1845 | return 0; |
0d7482e3 | 1846 | error2: |
b1f49f95 HS |
1847 | while (--j >= 0) |
1848 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[j]); | |
d435d862 | 1849 | error: |
cb491fca IM |
1850 | while (--i >= 0) |
1851 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1852 | ||
1853 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1854 | |
91c6d400 AK |
1855 | return err; |
1856 | } | |
1857 | ||
2d9cd6c2 | 1858 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1859 | { |
73ca5358 SL |
1860 | int i; |
1861 | ||
cb491fca | 1862 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1863 | return; |
1864 | ||
cb491fca IM |
1865 | for (i = 0; mce_attrs[i]; i++) |
1866 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1867 | ||
0d7482e3 | 1868 | for (i = 0; i < banks; i++) |
cb491fca IM |
1869 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1870 | ||
1871 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1872 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1873 | } |
91c6d400 | 1874 | |
d6b75584 | 1875 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1876 | static void mce_disable_cpu(void *h) |
d6b75584 | 1877 | { |
88ccbedd | 1878 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1879 | int i; |
d6b75584 AK |
1880 | |
1881 | if (!mce_available(¤t_cpu_data)) | |
1882 | return; | |
88ccbedd AK |
1883 | if (!(action & CPU_TASKS_FROZEN)) |
1884 | cmci_clear(); | |
06b7a7a5 AK |
1885 | for (i = 0; i < banks; i++) { |
1886 | if (!skip_bank_init(i)) | |
1887 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1888 | } | |
d6b75584 AK |
1889 | } |
1890 | ||
ec5b3d32 | 1891 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1892 | { |
88ccbedd | 1893 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1894 | int i; |
d6b75584 AK |
1895 | |
1896 | if (!mce_available(¤t_cpu_data)) | |
1897 | return; | |
e9eee03e | 1898 | |
88ccbedd AK |
1899 | if (!(action & CPU_TASKS_FROZEN)) |
1900 | cmci_reenable(); | |
06b7a7a5 AK |
1901 | for (i = 0; i < banks; i++) { |
1902 | if (!skip_bank_init(i)) | |
1903 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1904 | } | |
d6b75584 AK |
1905 | } |
1906 | ||
91c6d400 | 1907 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1908 | static int __cpuinit |
1909 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1910 | { |
1911 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1912 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1913 | |
1914 | switch (action) { | |
bae19fe0 AH |
1915 | case CPU_ONLINE: |
1916 | case CPU_ONLINE_FROZEN: | |
1917 | mce_create_device(cpu); | |
8735728e RW |
1918 | if (threshold_cpu_callback) |
1919 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1920 | break; |
91c6d400 | 1921 | case CPU_DEAD: |
8bb78442 | 1922 | case CPU_DEAD_FROZEN: |
8735728e RW |
1923 | if (threshold_cpu_callback) |
1924 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1925 | mce_remove_device(cpu); |
1926 | break; | |
52d168e2 AK |
1927 | case CPU_DOWN_PREPARE: |
1928 | case CPU_DOWN_PREPARE_FROZEN: | |
1929 | del_timer_sync(t); | |
88ccbedd | 1930 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1931 | break; |
1932 | case CPU_DOWN_FAILED: | |
1933 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1934 | t->expires = round_jiffies(jiffies + |
1935 | __get_cpu_var(next_interval)); | |
52d168e2 | 1936 | add_timer_on(t, cpu); |
88ccbedd AK |
1937 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1938 | break; | |
1939 | case CPU_POST_DEAD: | |
1940 | /* intentionally ignoring frozen here */ | |
1941 | cmci_rediscover(cpu); | |
52d168e2 | 1942 | break; |
91c6d400 | 1943 | } |
bae19fe0 | 1944 | return NOTIFY_OK; |
91c6d400 AK |
1945 | } |
1946 | ||
1e35669d | 1947 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1948 | .notifier_call = mce_cpu_callback, |
1949 | }; | |
1950 | ||
0d7482e3 AK |
1951 | static __init int mce_init_banks(void) |
1952 | { | |
1953 | int i; | |
1954 | ||
1955 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1956 | GFP_KERNEL); | |
1957 | if (!bank_attrs) | |
1958 | return -ENOMEM; | |
1959 | ||
1960 | for (i = 0; i < banks; i++) { | |
1961 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1962 | |
1963 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1964 | if (!a->attr.name) |
1965 | goto nomem; | |
e9eee03e IM |
1966 | |
1967 | a->attr.mode = 0644; | |
1968 | a->show = show_bank; | |
1969 | a->store = set_bank; | |
0d7482e3 AK |
1970 | } |
1971 | return 0; | |
1972 | ||
1973 | nomem: | |
1974 | while (--i >= 0) | |
1975 | kfree(bank_attrs[i].attr.name); | |
1976 | kfree(bank_attrs); | |
1977 | bank_attrs = NULL; | |
e9eee03e | 1978 | |
0d7482e3 AK |
1979 | return -ENOMEM; |
1980 | } | |
1981 | ||
91c6d400 AK |
1982 | static __init int mce_init_device(void) |
1983 | { | |
1984 | int err; | |
1985 | int i = 0; | |
1986 | ||
1da177e4 LT |
1987 | if (!mce_available(&boot_cpu_data)) |
1988 | return -EIO; | |
0d7482e3 | 1989 | |
e92fae06 | 1990 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1991 | |
0d7482e3 AK |
1992 | err = mce_init_banks(); |
1993 | if (err) | |
1994 | return err; | |
1995 | ||
1da177e4 | 1996 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1997 | if (err) |
1998 | return err; | |
91c6d400 AK |
1999 | |
2000 | for_each_online_cpu(i) { | |
d435d862 AM |
2001 | err = mce_create_device(i); |
2002 | if (err) | |
2003 | return err; | |
91c6d400 AK |
2004 | } |
2005 | ||
be6b5a35 | 2006 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2007 | misc_register(&mce_log_device); |
e9eee03e | 2008 | |
1da177e4 | 2009 | return err; |
1da177e4 | 2010 | } |
91c6d400 | 2011 | |
1da177e4 | 2012 | device_initcall(mce_init_device); |
a988d334 | 2013 | |
4efc0670 | 2014 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 2015 | |
a988d334 IM |
2016 | int nr_mce_banks; |
2017 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
2018 | ||
a988d334 IM |
2019 | /* This has to be run for each processor */ |
2020 | void mcheck_init(struct cpuinfo_x86 *c) | |
2021 | { | |
c6978369 | 2022 | if (mce_disabled) |
a988d334 IM |
2023 | return; |
2024 | ||
2025 | switch (c->x86_vendor) { | |
2026 | case X86_VENDOR_AMD: | |
2027 | amd_mcheck_init(c); | |
2028 | break; | |
2029 | ||
2030 | case X86_VENDOR_INTEL: | |
2031 | if (c->x86 == 5) | |
2032 | intel_p5_mcheck_init(c); | |
2033 | if (c->x86 == 6) | |
2034 | intel_p6_mcheck_init(c); | |
2035 | if (c->x86 == 15) | |
2036 | intel_p4_mcheck_init(c); | |
2037 | break; | |
2038 | ||
2039 | case X86_VENDOR_CENTAUR: | |
2040 | if (c->x86 == 5) | |
2041 | winchip_mcheck_init(c); | |
2042 | break; | |
2043 | ||
2044 | default: | |
2045 | break; | |
2046 | } | |
b659294b | 2047 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
2048 | } |
2049 | ||
a988d334 IM |
2050 | static int __init mcheck_enable(char *str) |
2051 | { | |
c6978369 | 2052 | mce_p5_enabled = 1; |
a988d334 IM |
2053 | return 1; |
2054 | } | |
a988d334 IM |
2055 | __setup("mce", mcheck_enable); |
2056 | ||
d7c3c9a6 AK |
2057 | #endif /* CONFIG_X86_OLD_MCE */ |
2058 | ||
2059 | /* | |
2060 | * Old style boot options parsing. Only for compatibility. | |
2061 | */ | |
2062 | static int __init mcheck_disable(char *str) | |
2063 | { | |
2064 | mce_disabled = 1; | |
2065 | return 1; | |
2066 | } | |
2067 | __setup("nomce", mcheck_disable); |