[net-next-2.6.git] / arch / x86 / kernel / cpu / cyrix.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/processor-cyrix.h>
#include <asm/timer.h>
#include <asm/pci-direct.h>
#include <asm/tsc.h>

#include "cpu.h"

/*
 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
 */
static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
	unsigned char ccr2, ccr3;
	unsigned long flags;
	
	/* we test for DEVID by checking whether CCR3 is writable */
	local_irq_save(flags);
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	getCx86(0xc0);   /* dummy to change bus */

	if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
		ccr2 = getCx86(CX86_CCR2);
		setCx86(CX86_CCR2, ccr2 ^ 0x04);
		getCx86(0xc0);  /* dummy */

		if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
			*dir0 = 0xfd;
		else {                          /* Cx486S A step */
			setCx86(CX86_CCR2, ccr2);
			*dir0 = 0xfe;
		}
	}
	else {
		setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */

		/* read DIR0 and DIR1 CPU registers */
		*dir0 = getCx86(CX86_DIR0);
		*dir1 = getCx86(CX86_DIR1);
	}
	local_irq_restore(flags);
}

/*
 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
 * order to identify the Cyrix CPU model after we're out of setup.c
 *
 * Actually since bugs.h doesn't even reference this perhaps someone should
 * fix the documentation ???
 */
static unsigned char Cx86_dir0_msb __cpuinitdata = 0;

static char Cx86_model[][9] __cpuinitdata = {
	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	"M II ", "Unknown"
};
static char Cx486_name[][5] __cpuinitdata = {
	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	"SRx2", "DRx2"
};
static char Cx486S_name[][4] __cpuinitdata = {
	"S", "S2", "Se", "S2e"
};
static char Cx486D_name[][4] __cpuinitdata = {
	"DX", "DX2", "?", "?", "?", "DX4"
};
static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
static char cyrix_model_mult1[] __cpuinitdata = "12??43";
static char cyrix_model_mult2[] __cpuinitdata = "12233445";

/*
 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
 * BIOSes for compatibility with DOS games.  This makes the udelay loop
 * work correctly, and improves performance.
 *
 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
 */

extern void calibrate_delay(void) __init;

static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
{
	unsigned long flags;
	
	if (Cx86_dir0_msb == 3) {
		unsigned char ccr3, ccr5;

		local_irq_save(flags);
		ccr3 = getCx86(CX86_CCR3);
		setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
		ccr5 = getCx86(CX86_CCR5);
		if (ccr5 & 2)
			setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
		setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
		local_irq_restore(flags);

		if (ccr5 & 2) { /* possible wrong calibration done */
			printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
			calibrate_delay();
			c->loops_per_jiffy = loops_per_jiffy;
		}
	}
}


static void __cpuinit set_cx86_reorder(void)
{
	u8 ccr3;

	printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
	ccr3 = getCx86(CX86_CCR3);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/delay.h>
	4	#include <linux/pci.h>
	5	#include <asm/dma.h>
	6	#include <asm/io.h>
f25f64ed	7	#include <asm/processor-cyrix.h>
1da177e4	8	#include <asm/timer.h>
120fad72	9	#include <asm/pci-direct.h>
e8edc6e0	10	#include <asm/tsc.h>
1da177e4 LT	11
	12	#include "cpu.h"
	13
	14	/*
	15	* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
	16	*/
5f0f1c16	17	static void __cpuinit do_cyrix_devid(unsigned char dir0, unsigned char dir1)
1da177e4 LT	18	{
	19	unsigned char ccr2, ccr3;
	20	unsigned long flags;
	21
	22	/* we test for DEVID by checking whether CCR3 is writable */
	23	local_irq_save(flags);
	24	ccr3 = getCx86(CX86_CCR3);
	25	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	26	getCx86(0xc0); /* dummy to change bus */
	27
	28	if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
	29	ccr2 = getCx86(CX86_CCR2);
	30	setCx86(CX86_CCR2, ccr2 ^ 0x04);
	31	getCx86(0xc0); /* dummy */
	32
	33	if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
	34	*dir0 = 0xfd;
	35	else { /* Cx486S A step */
	36	setCx86(CX86_CCR2, ccr2);
	37	*dir0 = 0xfe;
	38	}
	39	}
	40	else {
	41	setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
	42
	43	/* read DIR0 and DIR1 CPU registers */
	44	*dir0 = getCx86(CX86_DIR0);
	45	*dir1 = getCx86(CX86_DIR1);
	46	}
	47	local_irq_restore(flags);
	48	}
	49
	50	/*
	51	* Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
	52	* order to identify the Cyrix CPU model after we're out of setup.c
	53	*
	54	* Actually since bugs.h doesn't even reference this perhaps someone should
	55	* fix the documentation ???
	56	*/
b4af3f7c	57	static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
1da177e4	58
b4af3f7c	59	static char Cx86_model[][9] __cpuinitdata = {
1da177e4 LT	60	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	61	"M II ", "Unknown"
	62	};
b4af3f7c	63	static char Cx486_name[][5] __cpuinitdata = {
1da177e4 LT	64	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	65	"SRx2", "DRx2"
	66	};
b4af3f7c	67	static char Cx486S_name[][4] __cpuinitdata = {
1da177e4 LT	68	"S", "S2", "Se", "S2e"
1da177e4 LT	69	};
b4af3f7c	70	static char Cx486D_name[][4] __cpuinitdata = {
1da177e4 LT	71	"DX", "DX2", "?", "?", "?", "DX4"
1da177e4 LT	72	};
b4af3f7c MD	73	static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
	74	static char cyrix_model_mult1[] __cpuinitdata = "12??43";
	75	static char cyrix_model_mult2[] __cpuinitdata = "12233445";
1da177e4 LT	76
	77	/*
	78	* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
	79	* BIOSes for compatibility with DOS games. This makes the udelay loop
	80	* work correctly, and improves performance.
	81	*
	82	* FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
	83	*/
	84
	85	extern void calibrate_delay(void) __init;
	86
b4af3f7c	87	static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
1da177e4 LT	88	{
	89	unsigned long flags;
	90
	91	if (Cx86_dir0_msb == 3) {
	92	unsigned char ccr3, ccr5;
	93
	94	local_irq_save(flags);
	95	ccr3 = getCx86(CX86_CCR3);
	96	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
	97	ccr5 = getCx86(CX86_CCR5);
	98	if (ccr5 & 2)
	99	setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
	100	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
	101	local_irq_restore(flags);
	102
	103	if (ccr5 & 2) { /* possible wrong calibration done */
	104	printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
	105	calibrate_delay();
	106	c->loops_per_jiffy = loops_per_jiffy;
	107	}
	108	}
	109	}
	110
	111
b4af3f7c	112	static void __cpuinit set_cx86_reorder(void)
1da177e4 LT	113	{
	114	u8 ccr3;
	115
	116	printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
	117	ccr3 = getCx86(CX86_CCR3);
	118