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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
1da177e4 | 16 | #include <asm/mmu_context.h> |
9766cdbc JSR |
17 | #include <asm/hypervisor.h> |
18 | #include <asm/processor.h> | |
19 | #include <asm/sections.h> | |
0f3fa48a | 20 | #include <asm/topology.h> |
9766cdbc JSR |
21 | #include <asm/cpumask.h> |
22 | #include <asm/pgtable.h> | |
23 | #include <asm/atomic.h> | |
24 | #include <asm/proto.h> | |
25 | #include <asm/setup.h> | |
26 | #include <asm/apic.h> | |
27 | #include <asm/desc.h> | |
28 | #include <asm/i387.h> | |
27b07da7 | 29 | #include <asm/mtrr.h> |
9766cdbc JSR |
30 | #include <asm/numa.h> |
31 | #include <asm/asm.h> | |
32 | #include <asm/cpu.h> | |
a03a3e28 | 33 | #include <asm/mce.h> |
9766cdbc | 34 | #include <asm/msr.h> |
8d4a4300 | 35 | #include <asm/pat.h> |
b342797c | 36 | #include <asm/smp.h> |
e641f5f5 IM |
37 | |
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 39 | #include <asm/uv/uv.h> |
1da177e4 LT |
40 | #endif |
41 | ||
42 | #include "cpu.h" | |
43 | ||
c2d1cec1 | 44 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 45 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
46 | cpumask_var_t cpu_callout_mask; |
47 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
48 | |
49 | /* representing cpus for which sibling maps can be computed */ | |
50 | cpumask_var_t cpu_sibling_setup_mask; | |
51 | ||
2f2f52ba | 52 | /* correctly size the local cpu masks */ |
4369f1fb | 53 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
54 | { |
55 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
56 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
57 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
59 | } | |
60 | ||
02dde8b4 | 61 | static const struct cpu_dev *this_cpu __cpuinitdata; |
0a488a53 | 62 | |
06deef89 | 63 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 64 | #ifdef CONFIG_X86_64 |
06deef89 BG |
65 | /* |
66 | * We need valid kernel segments for data and code in long mode too | |
67 | * IRET will check the segment types kkeil 2000/10/28 | |
68 | * Also sysret mandates a special GDT layout | |
69 | * | |
9766cdbc | 70 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
71 | * Hopefully nobody expects them at a fixed place (Wine?) |
72 | */ | |
0f3fa48a IM |
73 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
74 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
75 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
76 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
77 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
78 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 79 | #else |
0f3fa48a IM |
80 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
81 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
82 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
83 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
84 | /* |
85 | * Segments used for calling PnP BIOS have byte granularity. | |
86 | * They code segments and data segments have fixed 64k limits, | |
87 | * the transfer segment sizes are set at run time. | |
88 | */ | |
6842ef0e | 89 | /* 32-bit code */ |
0f3fa48a | 90 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, |
6842ef0e | 91 | /* 16-bit code */ |
0f3fa48a | 92 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, |
6842ef0e | 93 | /* 16-bit data */ |
0f3fa48a | 94 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, |
6842ef0e | 95 | /* 16-bit data */ |
0f3fa48a | 96 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, |
6842ef0e | 97 | /* 16-bit data */ |
0f3fa48a | 98 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, |
bf504672 RR |
99 | /* |
100 | * The APM segments have byte granularity and their bases | |
101 | * are set at run time. All have 64k limits. | |
102 | */ | |
6842ef0e | 103 | /* 32-bit code */ |
0f3fa48a | 104 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, |
bf504672 | 105 | /* 16-bit code */ |
0f3fa48a | 106 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
6842ef0e | 107 | /* data */ |
0f3fa48a | 108 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, |
bf504672 | 109 | |
0f3fa48a IM |
110 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
111 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
60a5317f | 112 | GDT_STACK_CANARY_INIT |
950ad7ff | 113 | #endif |
06deef89 | 114 | } }; |
7a61d35d | 115 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 116 | |
0c752a93 SS |
117 | static int __init x86_xsave_setup(char *s) |
118 | { | |
119 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
120 | return 1; | |
121 | } | |
122 | __setup("noxsave", x86_xsave_setup); | |
123 | ||
ba51dced | 124 | #ifdef CONFIG_X86_32 |
3bc9b76b | 125 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 126 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 127 | |
0a488a53 YL |
128 | static int __init cachesize_setup(char *str) |
129 | { | |
130 | get_option(&str, &cachesize_override); | |
131 | return 1; | |
132 | } | |
133 | __setup("cachesize=", cachesize_setup); | |
134 | ||
0a488a53 YL |
135 | static int __init x86_fxsr_setup(char *s) |
136 | { | |
137 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
138 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
139 | return 1; | |
140 | } | |
141 | __setup("nofxsr", x86_fxsr_setup); | |
142 | ||
143 | static int __init x86_sep_setup(char *s) | |
144 | { | |
145 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
146 | return 1; | |
147 | } | |
148 | __setup("nosep", x86_sep_setup); | |
149 | ||
150 | /* Standard macro to see if a specific flag is changeable */ | |
151 | static inline int flag_is_changeable_p(u32 flag) | |
152 | { | |
153 | u32 f1, f2; | |
154 | ||
94f6bac1 KH |
155 | /* |
156 | * Cyrix and IDT cpus allow disabling of CPUID | |
157 | * so the code below may return different results | |
158 | * when it is executed before and after enabling | |
159 | * the CPUID. Add "volatile" to not allow gcc to | |
160 | * optimize the subsequent calls to this function. | |
161 | */ | |
0f3fa48a IM |
162 | asm volatile ("pushfl \n\t" |
163 | "pushfl \n\t" | |
164 | "popl %0 \n\t" | |
165 | "movl %0, %1 \n\t" | |
166 | "xorl %2, %0 \n\t" | |
167 | "pushl %0 \n\t" | |
168 | "popfl \n\t" | |
169 | "pushfl \n\t" | |
170 | "popl %0 \n\t" | |
171 | "popfl \n\t" | |
172 | ||
94f6bac1 KH |
173 | : "=&r" (f1), "=&r" (f2) |
174 | : "ir" (flag)); | |
0a488a53 YL |
175 | |
176 | return ((f1^f2) & flag) != 0; | |
177 | } | |
178 | ||
179 | /* Probe for the CPUID instruction */ | |
180 | static int __cpuinit have_cpuid_p(void) | |
181 | { | |
182 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
183 | } | |
184 | ||
185 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
186 | { | |
0f3fa48a IM |
187 | unsigned long lo, hi; |
188 | ||
189 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
190 | return; | |
191 | ||
192 | /* Disable processor serial number: */ | |
193 | ||
194 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
195 | lo |= 0x200000; | |
196 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | ||
198 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
199 | clear_cpu_cap(c, X86_FEATURE_PN); | |
200 | ||
201 | /* Disabling the serial number may affect the cpuid level */ | |
202 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
203 | } |
204 | ||
205 | static int __init x86_serial_nr_setup(char *s) | |
206 | { | |
207 | disable_x86_serial_nr = 0; | |
208 | return 1; | |
209 | } | |
210 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 211 | #else |
102bbe3a YL |
212 | static inline int flag_is_changeable_p(u32 flag) |
213 | { | |
214 | return 1; | |
215 | } | |
ba51dced YL |
216 | /* Probe for the CPUID instruction */ |
217 | static inline int have_cpuid_p(void) | |
218 | { | |
219 | return 1; | |
220 | } | |
102bbe3a YL |
221 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
222 | { | |
223 | } | |
ba51dced | 224 | #endif |
0a488a53 | 225 | |
b38b0665 PA |
226 | /* |
227 | * Some CPU features depend on higher CPUID levels, which may not always | |
228 | * be available due to CPUID level capping or broken virtualization | |
229 | * software. Add those features to this table to auto-disable them. | |
230 | */ | |
231 | struct cpuid_dependent_feature { | |
232 | u32 feature; | |
233 | u32 level; | |
234 | }; | |
0f3fa48a | 235 | |
b38b0665 PA |
236 | static const struct cpuid_dependent_feature __cpuinitconst |
237 | cpuid_dependent_features[] = { | |
238 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
239 | { X86_FEATURE_DCA, 0x00000009 }, | |
240 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
241 | { 0, 0 } | |
242 | }; | |
243 | ||
244 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
245 | { | |
246 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 247 | |
b38b0665 | 248 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
249 | |
250 | if (!cpu_has(c, df->feature)) | |
251 | continue; | |
b38b0665 PA |
252 | /* |
253 | * Note: cpuid_level is set to -1 if unavailable, but | |
254 | * extended_extended_level is set to 0 if unavailable | |
255 | * and the legitimate extended levels are all negative | |
256 | * when signed; hence the weird messing around with | |
257 | * signs here... | |
258 | */ | |
0f3fa48a | 259 | if (!((s32)df->level < 0 ? |
f6db44df | 260 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
261 | (s32)df->level > (s32)c->cpuid_level)) |
262 | continue; | |
263 | ||
264 | clear_cpu_cap(c, df->feature); | |
265 | if (!warn) | |
266 | continue; | |
267 | ||
268 | printk(KERN_WARNING | |
269 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
270 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 271 | } |
f6db44df | 272 | } |
b38b0665 | 273 | |
102bbe3a YL |
274 | /* |
275 | * Naming convention should be: <Name> [(<Codename>)] | |
276 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
277 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
278 | * isn't used | |
102bbe3a YL |
279 | */ |
280 | ||
281 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 282 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 283 | { |
02dde8b4 | 284 | const struct cpu_model_info *info; |
102bbe3a YL |
285 | |
286 | if (c->x86_model >= 16) | |
287 | return NULL; /* Range check */ | |
288 | ||
289 | if (!this_cpu) | |
290 | return NULL; | |
291 | ||
292 | info = this_cpu->c_models; | |
293 | ||
294 | while (info && info->family) { | |
295 | if (info->family == c->x86) | |
296 | return info->model_names[c->x86_model]; | |
297 | info++; | |
298 | } | |
299 | return NULL; /* Not found */ | |
300 | } | |
301 | ||
7d851c8d AK |
302 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
303 | ||
11e3a840 JF |
304 | void load_percpu_segment(int cpu) |
305 | { | |
306 | #ifdef CONFIG_X86_32 | |
307 | loadsegment(fs, __KERNEL_PERCPU); | |
308 | #else | |
309 | loadsegment(gs, 0); | |
310 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
311 | #endif | |
60a5317f | 312 | load_stack_canary_segment(); |
11e3a840 JF |
313 | } |
314 | ||
0f3fa48a IM |
315 | /* |
316 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
317 | * it's on the real one. | |
318 | */ | |
552be871 | 319 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
320 | { |
321 | struct desc_ptr gdt_descr; | |
322 | ||
2697fbd5 | 323 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
324 | gdt_descr.size = GDT_SIZE - 1; |
325 | load_gdt(&gdt_descr); | |
2697fbd5 | 326 | /* Reload the per-cpu base */ |
11e3a840 JF |
327 | |
328 | load_percpu_segment(cpu); | |
9d31d35b YL |
329 | } |
330 | ||
02dde8b4 | 331 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 332 | |
34048c9e | 333 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 334 | { |
b9e67f00 YL |
335 | #ifdef CONFIG_X86_64 |
336 | display_cacheinfo(c); | |
337 | #else | |
1da177e4 LT |
338 | /* Not much we can do here... */ |
339 | /* Check if at least it has cpuid */ | |
340 | if (c->cpuid_level == -1) { | |
341 | /* No cpuid. It must be an ancient CPU */ | |
342 | if (c->x86 == 4) | |
343 | strcpy(c->x86_model_id, "486"); | |
344 | else if (c->x86 == 3) | |
345 | strcpy(c->x86_model_id, "386"); | |
346 | } | |
b9e67f00 | 347 | #endif |
1da177e4 LT |
348 | } |
349 | ||
02dde8b4 | 350 | static const struct cpu_dev __cpuinitconst default_cpu = { |
1da177e4 | 351 | .c_init = default_init, |
fe38d855 | 352 | .c_vendor = "Unknown", |
10a434fc | 353 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 354 | }; |
1da177e4 | 355 | |
1b05d60d | 356 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
357 | { |
358 | unsigned int *v; | |
359 | char *p, *q; | |
360 | ||
3da99c97 | 361 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 362 | return; |
1da177e4 | 363 | |
0f3fa48a | 364 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
365 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
366 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
367 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
368 | c->x86_model_id[48] = 0; | |
369 | ||
0f3fa48a IM |
370 | /* |
371 | * Intel chips right-justify this string for some dumb reason; | |
372 | * undo that brain damage: | |
373 | */ | |
1da177e4 | 374 | p = q = &c->x86_model_id[0]; |
34048c9e | 375 | while (*p == ' ') |
9766cdbc | 376 | p++; |
34048c9e | 377 | if (p != q) { |
9766cdbc JSR |
378 | while (*p) |
379 | *q++ = *p++; | |
380 | while (q <= &c->x86_model_id[48]) | |
381 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 382 | } |
1da177e4 LT |
383 | } |
384 | ||
3bc9b76b | 385 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 386 | { |
9d31d35b | 387 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 388 | |
3da99c97 | 389 | n = c->extended_cpuid_level; |
1da177e4 LT |
390 | |
391 | if (n >= 0x80000005) { | |
9d31d35b | 392 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 393 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
394 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
395 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
396 | #ifdef CONFIG_X86_64 |
397 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
398 | c->x86_tlbsize = 0; | |
399 | #endif | |
1da177e4 LT |
400 | } |
401 | ||
402 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
403 | return; | |
404 | ||
0a488a53 | 405 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 406 | l2size = ecx >> 16; |
34048c9e | 407 | |
140fc727 YL |
408 | #ifdef CONFIG_X86_64 |
409 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
410 | #else | |
1da177e4 LT |
411 | /* do processor-specific cache resizing */ |
412 | if (this_cpu->c_size_cache) | |
34048c9e | 413 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
414 | |
415 | /* Allow user to override all this if necessary. */ | |
416 | if (cachesize_override != -1) | |
417 | l2size = cachesize_override; | |
418 | ||
34048c9e | 419 | if (l2size == 0) |
1da177e4 | 420 | return; /* Again, no L2 cache is possible */ |
140fc727 | 421 | #endif |
1da177e4 LT |
422 | |
423 | c->x86_cache_size = l2size; | |
424 | ||
425 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 426 | l2size, ecx & 0xFF); |
1da177e4 LT |
427 | } |
428 | ||
9d31d35b | 429 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 430 | { |
97e4db7c | 431 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
432 | u32 eax, ebx, ecx, edx; |
433 | int index_msb, core_bits; | |
1da177e4 | 434 | |
0a488a53 | 435 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 436 | return; |
1da177e4 | 437 | |
0a488a53 YL |
438 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
439 | goto out; | |
1da177e4 | 440 | |
1cd78776 YL |
441 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
442 | return; | |
1da177e4 | 443 | |
0a488a53 | 444 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 445 | |
9d31d35b YL |
446 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
447 | ||
448 | if (smp_num_siblings == 1) { | |
449 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
0f3fa48a IM |
450 | goto out; |
451 | } | |
9d31d35b | 452 | |
0f3fa48a IM |
453 | if (smp_num_siblings <= 1) |
454 | goto out; | |
9d31d35b | 455 | |
0f3fa48a IM |
456 | if (smp_num_siblings > nr_cpu_ids) { |
457 | pr_warning("CPU: Unsupported number of siblings %d", | |
458 | smp_num_siblings); | |
459 | smp_num_siblings = 1; | |
460 | return; | |
461 | } | |
9d31d35b | 462 | |
0f3fa48a IM |
463 | index_msb = get_count_order(smp_num_siblings); |
464 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 465 | |
0f3fa48a | 466 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 467 | |
0f3fa48a | 468 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 469 | |
0f3fa48a | 470 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 471 | |
0f3fa48a IM |
472 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
473 | ((1 << core_bits) - 1); | |
1da177e4 | 474 | |
0a488a53 YL |
475 | out: |
476 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
477 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
478 | c->phys_proc_id); | |
479 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
480 | c->cpu_core_id); | |
9d31d35b | 481 | } |
9d31d35b | 482 | #endif |
97e4db7c | 483 | } |
1da177e4 | 484 | |
3da99c97 | 485 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
486 | { |
487 | char *v = c->x86_vendor_id; | |
fe38d855 | 488 | static int printed; |
0f3fa48a | 489 | int i; |
1da177e4 LT |
490 | |
491 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
492 | if (!cpu_devs[i]) |
493 | break; | |
494 | ||
495 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
496 | (cpu_devs[i]->c_ident[1] && | |
497 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 498 | |
10a434fc YL |
499 | this_cpu = cpu_devs[i]; |
500 | c->x86_vendor = this_cpu->c_x86_vendor; | |
501 | return; | |
1da177e4 LT |
502 | } |
503 | } | |
10a434fc | 504 | |
fe38d855 CE |
505 | if (!printed) { |
506 | printed++; | |
0f3fa48a IM |
507 | printk(KERN_ERR |
508 | "CPU: vendor_id '%s' unknown, using generic init.\n", v); | |
509 | ||
fe38d855 CE |
510 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
511 | } | |
10a434fc | 512 | |
fe38d855 CE |
513 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
514 | this_cpu = &default_cpu; | |
1da177e4 LT |
515 | } |
516 | ||
9d31d35b | 517 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 518 | { |
1da177e4 | 519 | /* Get vendor name */ |
4a148513 HH |
520 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
521 | (unsigned int *)&c->x86_vendor_id[0], | |
522 | (unsigned int *)&c->x86_vendor_id[8], | |
523 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 524 | |
1da177e4 | 525 | c->x86 = 4; |
9d31d35b | 526 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
527 | if (c->cpuid_level >= 0x00000001) { |
528 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 529 | |
1da177e4 | 530 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
531 | c->x86 = (tfms >> 8) & 0xf; |
532 | c->x86_model = (tfms >> 4) & 0xf; | |
533 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 534 | |
f5f786d0 | 535 | if (c->x86 == 0xf) |
1da177e4 | 536 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 537 | if (c->x86 >= 0x6) |
9d31d35b | 538 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 539 | |
d4387bd3 | 540 | if (cap0 & (1<<19)) { |
d4387bd3 | 541 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 542 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 543 | } |
1da177e4 | 544 | } |
1da177e4 | 545 | } |
3da99c97 YL |
546 | |
547 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
548 | { |
549 | u32 tfms, xlvl; | |
3da99c97 | 550 | u32 ebx; |
093af8d7 | 551 | |
3da99c97 YL |
552 | /* Intel-defined flags: level 0x00000001 */ |
553 | if (c->cpuid_level >= 0x00000001) { | |
554 | u32 capability, excap; | |
0f3fa48a | 555 | |
3da99c97 YL |
556 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
557 | c->x86_capability[0] = capability; | |
558 | c->x86_capability[4] = excap; | |
559 | } | |
093af8d7 | 560 | |
3da99c97 YL |
561 | /* AMD-defined flags: level 0x80000001 */ |
562 | xlvl = cpuid_eax(0x80000000); | |
563 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 564 | |
3da99c97 YL |
565 | if ((xlvl & 0xffff0000) == 0x80000000) { |
566 | if (xlvl >= 0x80000001) { | |
567 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
568 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 569 | } |
093af8d7 | 570 | } |
093af8d7 | 571 | |
5122c890 YL |
572 | if (c->extended_cpuid_level >= 0x80000008) { |
573 | u32 eax = cpuid_eax(0x80000008); | |
574 | ||
575 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
576 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 577 | } |
13c6c532 JB |
578 | #ifdef CONFIG_X86_32 |
579 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
580 | c->x86_phys_bits = 36; | |
5122c890 | 581 | #endif |
e3224234 YL |
582 | |
583 | if (c->extended_cpuid_level >= 0x80000007) | |
584 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
585 | |
586 | } | |
1da177e4 | 587 | |
aef93c8b YL |
588 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
589 | { | |
590 | #ifdef CONFIG_X86_32 | |
591 | int i; | |
592 | ||
593 | /* | |
594 | * First of all, decide if this is a 486 or higher | |
595 | * It's a 486 if we can modify the AC flag | |
596 | */ | |
597 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
598 | c->x86 = 4; | |
599 | else | |
600 | c->x86 = 3; | |
601 | ||
602 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
603 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
604 | c->x86_vendor_id[0] = 0; | |
605 | cpu_devs[i]->c_identify(c); | |
606 | if (c->x86_vendor_id[0]) { | |
607 | get_cpu_vendor(c); | |
608 | break; | |
609 | } | |
610 | } | |
611 | #endif | |
612 | } | |
613 | ||
34048c9e PC |
614 | /* |
615 | * Do minimum CPU detection early. | |
616 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
617 | * cache alignment. | |
618 | * The others are not touched to avoid unwanted side effects. | |
619 | * | |
620 | * WARNING: this function is only called on the BP. Don't add code here | |
621 | * that is supposed to run on all CPUs. | |
622 | */ | |
3da99c97 | 623 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 624 | { |
6627d242 YL |
625 | #ifdef CONFIG_X86_64 |
626 | c->x86_clflush_size = 64; | |
13c6c532 JB |
627 | c->x86_phys_bits = 36; |
628 | c->x86_virt_bits = 48; | |
6627d242 | 629 | #else |
d4387bd3 | 630 | c->x86_clflush_size = 32; |
13c6c532 JB |
631 | c->x86_phys_bits = 32; |
632 | c->x86_virt_bits = 32; | |
6627d242 | 633 | #endif |
0a488a53 | 634 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 635 | |
3da99c97 | 636 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 637 | c->extended_cpuid_level = 0; |
d7cd5611 | 638 | |
aef93c8b YL |
639 | if (!have_cpuid_p()) |
640 | identify_cpu_without_cpuid(c); | |
641 | ||
642 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
643 | if (!have_cpuid_p()) |
644 | return; | |
645 | ||
646 | cpu_detect(c); | |
647 | ||
3da99c97 | 648 | get_cpu_vendor(c); |
2b16a235 | 649 | |
3da99c97 | 650 | get_cpu_cap(c); |
12cf105c | 651 | |
10a434fc YL |
652 | if (this_cpu->c_early_init) |
653 | this_cpu->c_early_init(c); | |
093af8d7 | 654 | |
1c4acdb4 | 655 | #ifdef CONFIG_SMP |
bfcb4c1b | 656 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 657 | #endif |
b38b0665 | 658 | filter_cpuid_features(c, false); |
d7cd5611 RR |
659 | } |
660 | ||
9d31d35b YL |
661 | void __init early_cpu_init(void) |
662 | { | |
02dde8b4 | 663 | const struct cpu_dev *const *cdev; |
10a434fc YL |
664 | int count = 0; |
665 | ||
9766cdbc | 666 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
10a434fc | 667 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 668 | const struct cpu_dev *cpudev = *cdev; |
10a434fc | 669 | unsigned int j; |
9d31d35b | 670 | |
10a434fc YL |
671 | if (count >= X86_VENDOR_NUM) |
672 | break; | |
673 | cpu_devs[count] = cpudev; | |
674 | count++; | |
675 | ||
676 | for (j = 0; j < 2; j++) { | |
677 | if (!cpudev->c_ident[j]) | |
678 | continue; | |
9766cdbc | 679 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, |
10a434fc YL |
680 | cpudev->c_ident[j]); |
681 | } | |
682 | } | |
9d31d35b | 683 | |
9d31d35b | 684 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 685 | } |
093af8d7 | 686 | |
b6734c35 PA |
687 | /* |
688 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 689 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 690 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
691 | * are not easy to detect. In the latter case it doesn't even *fail* |
692 | * reliably, so probing for it doesn't even work. Disable it completely | |
693 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
694 | */ |
695 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
696 | { | |
b6734c35 | 697 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
698 | } |
699 | ||
34048c9e | 700 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 701 | { |
aef93c8b | 702 | c->extended_cpuid_level = 0; |
1da177e4 | 703 | |
3da99c97 | 704 | if (!have_cpuid_p()) |
aef93c8b | 705 | identify_cpu_without_cpuid(c); |
1d67953f | 706 | |
aef93c8b | 707 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 708 | if (!have_cpuid_p()) |
aef93c8b | 709 | return; |
1da177e4 | 710 | |
3da99c97 | 711 | cpu_detect(c); |
1da177e4 | 712 | |
3da99c97 | 713 | get_cpu_vendor(c); |
1da177e4 | 714 | |
3da99c97 | 715 | get_cpu_cap(c); |
1da177e4 | 716 | |
3da99c97 YL |
717 | if (c->cpuid_level >= 0x00000001) { |
718 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
719 | #ifdef CONFIG_X86_32 |
720 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 721 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 722 | # else |
3da99c97 | 723 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
724 | # endif |
725 | #endif | |
1da177e4 | 726 | |
b89d3b3e YL |
727 | #ifdef CONFIG_X86_HT |
728 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 729 | #endif |
3da99c97 | 730 | } |
1da177e4 | 731 | |
1b05d60d | 732 | get_model_name(c); /* Default name */ |
1da177e4 | 733 | |
3da99c97 YL |
734 | init_scattered_cpuid_features(c); |
735 | detect_nopl(c); | |
1da177e4 | 736 | } |
1da177e4 LT |
737 | |
738 | /* | |
739 | * This does the hard work of actually picking apart the CPU stuff... | |
740 | */ | |
9a250347 | 741 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
742 | { |
743 | int i; | |
744 | ||
745 | c->loops_per_jiffy = loops_per_jiffy; | |
746 | c->x86_cache_size = -1; | |
747 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
748 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
749 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
750 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 751 | c->x86_max_cores = 1; |
102bbe3a | 752 | c->x86_coreid_bits = 0; |
11fdd252 | 753 | #ifdef CONFIG_X86_64 |
102bbe3a | 754 | c->x86_clflush_size = 64; |
13c6c532 JB |
755 | c->x86_phys_bits = 36; |
756 | c->x86_virt_bits = 48; | |
102bbe3a YL |
757 | #else |
758 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 759 | c->x86_clflush_size = 32; |
13c6c532 JB |
760 | c->x86_phys_bits = 32; |
761 | c->x86_virt_bits = 32; | |
102bbe3a YL |
762 | #endif |
763 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
764 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
765 | ||
1da177e4 LT |
766 | generic_identify(c); |
767 | ||
3898534d | 768 | if (this_cpu->c_identify) |
1da177e4 LT |
769 | this_cpu->c_identify(c); |
770 | ||
102bbe3a | 771 | #ifdef CONFIG_X86_64 |
cb8cc442 | 772 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
773 | #endif |
774 | ||
1da177e4 LT |
775 | /* |
776 | * Vendor-specific initialization. In this section we | |
777 | * canonicalize the feature flags, meaning if there are | |
778 | * features a certain CPU supports which CPUID doesn't | |
779 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
780 | * we handle them here. | |
781 | * | |
782 | * At the end of this section, c->x86_capability better | |
783 | * indicate the features this CPU genuinely supports! | |
784 | */ | |
785 | if (this_cpu->c_init) | |
786 | this_cpu->c_init(c); | |
787 | ||
788 | /* Disable the PN if appropriate */ | |
789 | squash_the_stupid_serial_number(c); | |
790 | ||
791 | /* | |
0f3fa48a IM |
792 | * The vendor-specific functions might have changed features. |
793 | * Now we do "generic changes." | |
1da177e4 LT |
794 | */ |
795 | ||
b38b0665 PA |
796 | /* Filter out anything that depends on CPUID levels we don't have */ |
797 | filter_cpuid_features(c, true); | |
798 | ||
1da177e4 | 799 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 800 | if (!c->x86_model_id[0]) { |
02dde8b4 | 801 | const char *p; |
1da177e4 | 802 | p = table_lookup_model(c); |
34048c9e | 803 | if (p) |
1da177e4 LT |
804 | strcpy(c->x86_model_id, p); |
805 | else | |
806 | /* Last resort... */ | |
807 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 808 | c->x86, c->x86_model); |
1da177e4 LT |
809 | } |
810 | ||
102bbe3a YL |
811 | #ifdef CONFIG_X86_64 |
812 | detect_ht(c); | |
813 | #endif | |
814 | ||
88b094fb | 815 | init_hypervisor(c); |
1da177e4 LT |
816 | /* |
817 | * On SMP, boot_cpu_data holds the common feature set between | |
818 | * all CPUs; so make sure that we indicate which features are | |
819 | * common between the CPUs. The first time this routine gets | |
820 | * executed, c == &boot_cpu_data. | |
821 | */ | |
34048c9e | 822 | if (c != &boot_cpu_data) { |
1da177e4 | 823 | /* AND the already accumulated flags with these */ |
9d31d35b | 824 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
825 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
826 | } | |
827 | ||
7d851c8d AK |
828 | /* Clear all flags overriden by options */ |
829 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 830 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 831 | |
102bbe3a | 832 | #ifdef CONFIG_X86_MCE |
1da177e4 | 833 | /* Init Machine Check Exception if available. */ |
1da177e4 | 834 | mcheck_init(c); |
102bbe3a | 835 | #endif |
30d432df AK |
836 | |
837 | select_idle_routine(c); | |
102bbe3a YL |
838 | |
839 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
840 | numa_add_cpu(smp_processor_id()); | |
841 | #endif | |
a6c4e076 | 842 | } |
31ab269a | 843 | |
e04d645f GC |
844 | #ifdef CONFIG_X86_64 |
845 | static void vgetcpu_set_mode(void) | |
846 | { | |
847 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
848 | vgetcpu_mode = VGETCPU_RDTSCP; | |
849 | else | |
850 | vgetcpu_mode = VGETCPU_LSL; | |
851 | } | |
852 | #endif | |
853 | ||
a6c4e076 JF |
854 | void __init identify_boot_cpu(void) |
855 | { | |
856 | identify_cpu(&boot_cpu_data); | |
30e1e6d1 | 857 | init_c1e_mask(); |
102bbe3a | 858 | #ifdef CONFIG_X86_32 |
a6c4e076 | 859 | sysenter_setup(); |
6fe940d6 | 860 | enable_sep_cpu(); |
e04d645f GC |
861 | #else |
862 | vgetcpu_set_mode(); | |
102bbe3a | 863 | #endif |
a6c4e076 | 864 | } |
3b520b23 | 865 | |
a6c4e076 JF |
866 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
867 | { | |
868 | BUG_ON(c == &boot_cpu_data); | |
869 | identify_cpu(c); | |
102bbe3a | 870 | #ifdef CONFIG_X86_32 |
a6c4e076 | 871 | enable_sep_cpu(); |
102bbe3a | 872 | #endif |
a6c4e076 | 873 | mtrr_ap_init(); |
1da177e4 LT |
874 | } |
875 | ||
a0854a46 | 876 | struct msr_range { |
0f3fa48a IM |
877 | unsigned min; |
878 | unsigned max; | |
a0854a46 | 879 | }; |
1da177e4 | 880 | |
02dde8b4 | 881 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
882 | { 0x00000000, 0x00000418}, |
883 | { 0xc0000000, 0xc000040b}, | |
884 | { 0xc0010000, 0xc0010142}, | |
885 | { 0xc0011000, 0xc001103b}, | |
886 | }; | |
1da177e4 | 887 | |
a0854a46 YL |
888 | static void __cpuinit print_cpu_msr(void) |
889 | { | |
0f3fa48a | 890 | unsigned index_min, index_max; |
a0854a46 YL |
891 | unsigned index; |
892 | u64 val; | |
893 | int i; | |
a0854a46 YL |
894 | |
895 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
896 | index_min = msr_range_array[i].min; | |
897 | index_max = msr_range_array[i].max; | |
0f3fa48a | 898 | |
a0854a46 YL |
899 | for (index = index_min; index < index_max; index++) { |
900 | if (rdmsrl_amd_safe(index, &val)) | |
901 | continue; | |
902 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 903 | } |
a0854a46 YL |
904 | } |
905 | } | |
94605eff | 906 | |
a0854a46 | 907 | static int show_msr __cpuinitdata; |
0f3fa48a | 908 | |
a0854a46 YL |
909 | static __init int setup_show_msr(char *arg) |
910 | { | |
911 | int num; | |
3dd9d514 | 912 | |
a0854a46 | 913 | get_option(&arg, &num); |
3dd9d514 | 914 | |
a0854a46 YL |
915 | if (num > 0) |
916 | show_msr = num; | |
917 | return 1; | |
1da177e4 | 918 | } |
a0854a46 | 919 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 920 | |
191679fd AK |
921 | static __init int setup_noclflush(char *arg) |
922 | { | |
923 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
924 | return 1; | |
925 | } | |
926 | __setup("noclflush", setup_noclflush); | |
927 | ||
3bc9b76b | 928 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 929 | { |
02dde8b4 | 930 | const char *vendor = NULL; |
1da177e4 | 931 | |
0f3fa48a | 932 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 933 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
934 | } else { |
935 | if (c->cpuid_level >= 0) | |
936 | vendor = c->x86_vendor_id; | |
937 | } | |
1da177e4 | 938 | |
bd32a8cf | 939 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 940 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 941 | |
9d31d35b YL |
942 | if (c->x86_model_id[0]) |
943 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 944 | else |
9d31d35b | 945 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 946 | |
34048c9e | 947 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 948 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 949 | else |
9d31d35b | 950 | printk(KERN_CONT "\n"); |
a0854a46 YL |
951 | |
952 | #ifdef CONFIG_SMP | |
953 | if (c->cpu_index < show_msr) | |
954 | print_cpu_msr(); | |
955 | #else | |
956 | if (show_msr) | |
957 | print_cpu_msr(); | |
958 | #endif | |
1da177e4 LT |
959 | } |
960 | ||
ac72e788 AK |
961 | static __init int setup_disablecpuid(char *arg) |
962 | { | |
963 | int bit; | |
0f3fa48a | 964 | |
ac72e788 AK |
965 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
966 | setup_clear_cpu_cap(bit); | |
967 | else | |
968 | return 0; | |
0f3fa48a | 969 | |
ac72e788 AK |
970 | return 1; |
971 | } | |
972 | __setup("clearcpuid=", setup_disablecpuid); | |
973 | ||
d5494d4f | 974 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
975 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
976 | ||
947e76cd BG |
977 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
978 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 979 | |
26f80bd6 | 980 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
2add8e23 | 981 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
d5494d4f | 982 | |
9af45651 BG |
983 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
984 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
985 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
d5494d4f | 986 | |
56895530 | 987 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 988 | |
0f3fa48a IM |
989 | /* |
990 | * Special IST stacks which the CPU switches to when it calls | |
991 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
992 | * limit), all of them are 4K, except the debug stack which | |
993 | * is 8K. | |
994 | */ | |
995 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
996 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
997 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
998 | }; | |
999 | ||
92d65b23 BG |
1000 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
1001 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
1002 | __aligned(PAGE_SIZE); | |
d5494d4f | 1003 | |
d5494d4f YL |
1004 | /* May not be marked __init: used by software suspend */ |
1005 | void syscall_init(void) | |
1da177e4 | 1006 | { |
d5494d4f YL |
1007 | /* |
1008 | * LSTAR and STAR live in a bit strange symbiosis. | |
1009 | * They both write to the same internal register. STAR allows to | |
1010 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1011 | */ | |
1012 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1013 | wrmsrl(MSR_LSTAR, system_call); | |
1014 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1015 | |
d5494d4f YL |
1016 | #ifdef CONFIG_IA32_EMULATION |
1017 | syscall32_cpu_init(); | |
1018 | #endif | |
03ae5768 | 1019 | |
d5494d4f YL |
1020 | /* Flags to clear on syscall */ |
1021 | wrmsrl(MSR_SYSCALL_MASK, | |
1022 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 1023 | } |
62111195 | 1024 | |
d5494d4f YL |
1025 | unsigned long kernel_eflags; |
1026 | ||
1027 | /* | |
1028 | * Copies of the original ist values from the tss are only accessed during | |
1029 | * debugging, no special alignment required. | |
1030 | */ | |
1031 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1032 | ||
0f3fa48a | 1033 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1034 | |
60a5317f TH |
1035 | #ifdef CONFIG_CC_STACKPROTECTOR |
1036 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
1037 | #endif | |
d5494d4f | 1038 | |
60a5317f | 1039 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1040 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1041 | { |
1042 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1043 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1044 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1045 | |
f95d47ca JF |
1046 | return regs; |
1047 | } | |
0f3fa48a | 1048 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1049 | |
9766cdbc JSR |
1050 | /* |
1051 | * Clear all 6 debug registers: | |
1052 | */ | |
1053 | static void clear_all_debug_regs(void) | |
1054 | { | |
1055 | int i; | |
1056 | ||
1057 | for (i = 0; i < 8; i++) { | |
1058 | /* Ignore db4, db5 */ | |
1059 | if ((i == 4) || (i == 5)) | |
1060 | continue; | |
1061 | ||
1062 | set_debugreg(0, i); | |
1063 | } | |
1064 | } | |
c5413fbe | 1065 | |
d2cbcc49 RR |
1066 | /* |
1067 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1068 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1069 | * and IDT. We reload them nevertheless, this function acts as a | |
1070 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1071 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1072 | */ |
1ba76586 | 1073 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1074 | |
1ba76586 YL |
1075 | void __cpuinit cpu_init(void) |
1076 | { | |
0f3fa48a | 1077 | struct orig_ist *orig_ist; |
1ba76586 | 1078 | struct task_struct *me; |
0f3fa48a IM |
1079 | struct tss_struct *t; |
1080 | unsigned long v; | |
1081 | int cpu; | |
1ba76586 YL |
1082 | int i; |
1083 | ||
0f3fa48a IM |
1084 | cpu = stack_smp_processor_id(); |
1085 | t = &per_cpu(init_tss, cpu); | |
1086 | orig_ist = &per_cpu(orig_ist, cpu); | |
1087 | ||
e7a22c1e BG |
1088 | #ifdef CONFIG_NUMA |
1089 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1090 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1091 | percpu_write(node_number, cpu_to_node(cpu)); | |
1092 | #endif | |
1ba76586 YL |
1093 | |
1094 | me = current; | |
1095 | ||
c2d1cec1 | 1096 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1097 | panic("CPU#%d already initialized!\n", cpu); |
1098 | ||
1099 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1100 | ||
1101 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1102 | ||
1103 | /* | |
1104 | * Initialize the per-CPU GDT with the boot GDT, | |
1105 | * and set up the GDT descriptor: | |
1106 | */ | |
1107 | ||
552be871 | 1108 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1109 | loadsegment(fs, 0); |
1110 | ||
1ba76586 YL |
1111 | load_idt((const struct desc_ptr *)&idt_descr); |
1112 | ||
1113 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1114 | syscall_init(); | |
1115 | ||
1116 | wrmsrl(MSR_FS_BASE, 0); | |
1117 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1118 | barrier(); | |
1119 | ||
1120 | check_efer(); | |
06cd9a7d | 1121 | if (cpu != 0) |
1ba76586 YL |
1122 | enable_x2apic(); |
1123 | ||
1124 | /* | |
1125 | * set up and load the per-CPU TSS | |
1126 | */ | |
1127 | if (!orig_ist->ist[0]) { | |
92d65b23 | 1128 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1129 | |
1ba76586 | 1130 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1131 | estacks += exception_stack_sizes[v]; |
1ba76586 YL |
1132 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1133 | (unsigned long)estacks; | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1138 | |
1ba76586 YL |
1139 | /* |
1140 | * <= is required because the CPU will access up to | |
1141 | * 8 bits beyond the end of the IO permission bitmap. | |
1142 | */ | |
1143 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1144 | t->io_bitmap[i] = ~0UL; | |
1145 | ||
1146 | atomic_inc(&init_mm.mm_count); | |
1147 | me->active_mm = &init_mm; | |
8c5dfd25 | 1148 | BUG_ON(me->mm); |
1ba76586 YL |
1149 | enter_lazy_tlb(&init_mm, me); |
1150 | ||
1151 | load_sp0(t, ¤t->thread); | |
1152 | set_tss_desc(cpu, t); | |
1153 | load_TR_desc(); | |
1154 | load_LDT(&init_mm.context); | |
1155 | ||
1156 | #ifdef CONFIG_KGDB | |
1157 | /* | |
1158 | * If the kgdb is connected no debug regs should be altered. This | |
1159 | * is only applicable when KGDB and a KGDB I/O module are built | |
1160 | * into the kernel and you are using early debugging with | |
1161 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1162 | */ | |
1163 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1164 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1165 | else |
1ba76586 | 1166 | #endif |
9766cdbc | 1167 | clear_all_debug_regs(); |
1ba76586 YL |
1168 | |
1169 | fpu_init(); | |
1170 | ||
1171 | raw_local_save_flags(kernel_eflags); | |
1172 | ||
1173 | if (is_uv_system()) | |
1174 | uv_cpu_init(); | |
1175 | } | |
1176 | ||
1177 | #else | |
1178 | ||
d2cbcc49 | 1179 | void __cpuinit cpu_init(void) |
9ee79a3d | 1180 | { |
d2cbcc49 RR |
1181 | int cpu = smp_processor_id(); |
1182 | struct task_struct *curr = current; | |
34048c9e | 1183 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1184 | struct thread_struct *thread = &curr->thread; |
62111195 | 1185 | |
c2d1cec1 | 1186 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1187 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1188 | for (;;) |
1189 | local_irq_enable(); | |
62111195 JF |
1190 | } |
1191 | ||
1192 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1193 | ||
1194 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1195 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1196 | |
4d37e7e3 | 1197 | load_idt(&idt_descr); |
552be871 | 1198 | switch_to_new_gdt(cpu); |
1da177e4 | 1199 | |
1da177e4 LT |
1200 | /* |
1201 | * Set up and load the per-CPU TSS and LDT | |
1202 | */ | |
1203 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1204 | curr->active_mm = &init_mm; |
8c5dfd25 | 1205 | BUG_ON(curr->mm); |
62111195 | 1206 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1207 | |
faca6227 | 1208 | load_sp0(t, thread); |
34048c9e | 1209 | set_tss_desc(cpu, t); |
1da177e4 LT |
1210 | load_TR_desc(); |
1211 | load_LDT(&init_mm.context); | |
1212 | ||
f9a196b8 TG |
1213 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1214 | ||
22c4e308 | 1215 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1216 | /* Set up doublefault TSS pointer in the GDT */ |
1217 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1218 | #endif |
1da177e4 | 1219 | |
9766cdbc | 1220 | clear_all_debug_regs(); |
1da177e4 LT |
1221 | |
1222 | /* | |
1223 | * Force FPU initialization: | |
1224 | */ | |
b359e8a4 SS |
1225 | if (cpu_has_xsave) |
1226 | current_thread_info()->status = TS_XSAVE; | |
1227 | else | |
1228 | current_thread_info()->status = 0; | |
1da177e4 LT |
1229 | clear_used_math(); |
1230 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1231 | |
1232 | /* | |
1233 | * Boot processor to setup the FP and extended state context info. | |
1234 | */ | |
b3572e36 | 1235 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1236 | init_thread_xstate(); |
1237 | ||
1238 | xsave_init(); | |
1da177e4 | 1239 | } |
1ba76586 | 1240 | #endif |