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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
4173a0e7 DN |
63 | #include <asm/uv/uv_hub.h> |
64 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 65 | |
7b6aa335 | 66 | #include <asm/apic.h> |
1da177e4 | 67 | |
32f71aff | 68 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
69 | #define for_each_irq_pin(entry, head) \ |
70 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 71 | |
1da177e4 | 72 | /* |
54168ed7 IM |
73 | * Is the SiS APIC rmw bug present ? |
74 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
75 | */ |
76 | int sis_apic_bug = -1; | |
77 | ||
efa2559f YL |
78 | static DEFINE_SPINLOCK(ioapic_lock); |
79 | static DEFINE_SPINLOCK(vector_lock); | |
80 | ||
1da177e4 LT |
81 | /* |
82 | * # of IRQ routing registers | |
83 | */ | |
84 | int nr_ioapic_registers[MAX_IO_APICS]; | |
85 | ||
9f640ccb | 86 | /* I/O APIC entries */ |
b5ba7e6d | 87 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
88 | int nr_ioapics; |
89 | ||
2a4ab640 FT |
90 | /* IO APIC gsi routing info */ |
91 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
92 | ||
584f734d | 93 | /* MP IRQ source entries */ |
c2c21745 | 94 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
95 | |
96 | /* # of MP IRQ source entries */ | |
97 | int mp_irq_entries; | |
98 | ||
8732fc4b AS |
99 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
100 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
101 | #endif | |
102 | ||
103 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
104 | ||
efa2559f YL |
105 | int skip_ioapic_setup; |
106 | ||
65a4e574 IM |
107 | void arch_disable_smp_support(void) |
108 | { | |
109 | #ifdef CONFIG_PCI | |
110 | noioapicquirk = 1; | |
111 | noioapicreroute = -1; | |
112 | #endif | |
113 | skip_ioapic_setup = 1; | |
114 | } | |
115 | ||
54168ed7 | 116 | static int __init parse_noapic(char *str) |
efa2559f YL |
117 | { |
118 | /* disable IO-APIC */ | |
65a4e574 | 119 | arch_disable_smp_support(); |
efa2559f YL |
120 | return 0; |
121 | } | |
122 | early_param("noapic", parse_noapic); | |
66759a01 | 123 | |
0b8f1efa YL |
124 | struct irq_pin_list { |
125 | int apic, pin; | |
126 | struct irq_pin_list *next; | |
127 | }; | |
128 | ||
85ac16d0 | 129 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
130 | { |
131 | struct irq_pin_list *pin; | |
0b8f1efa YL |
132 | |
133 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
134 | |
135 | return pin; | |
136 | } | |
137 | ||
8e13d697 JF |
138 | /* |
139 | * This is performance-critical, we want to do it O(1) | |
140 | * | |
141 | * Most irqs are mapped 1:1 with pins. | |
142 | */ | |
a1420f39 | 143 | struct irq_cfg { |
0f978f45 | 144 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
145 | cpumask_var_t domain; |
146 | cpumask_var_t old_domain; | |
497c9a19 | 147 | unsigned move_cleanup_count; |
a1420f39 | 148 | u8 vector; |
497c9a19 | 149 | u8 move_in_progress : 1; |
a1420f39 YL |
150 | }; |
151 | ||
a1420f39 | 152 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
153 | #ifdef CONFIG_SPARSE_IRQ |
154 | static struct irq_cfg irq_cfgx[] = { | |
155 | #else | |
d6c88a50 | 156 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 157 | #endif |
22f65d31 MT |
158 | [0] = { .vector = IRQ0_VECTOR, }, |
159 | [1] = { .vector = IRQ1_VECTOR, }, | |
160 | [2] = { .vector = IRQ2_VECTOR, }, | |
161 | [3] = { .vector = IRQ3_VECTOR, }, | |
162 | [4] = { .vector = IRQ4_VECTOR, }, | |
163 | [5] = { .vector = IRQ5_VECTOR, }, | |
164 | [6] = { .vector = IRQ6_VECTOR, }, | |
165 | [7] = { .vector = IRQ7_VECTOR, }, | |
166 | [8] = { .vector = IRQ8_VECTOR, }, | |
167 | [9] = { .vector = IRQ9_VECTOR, }, | |
168 | [10] = { .vector = IRQ10_VECTOR, }, | |
169 | [11] = { .vector = IRQ11_VECTOR, }, | |
170 | [12] = { .vector = IRQ12_VECTOR, }, | |
171 | [13] = { .vector = IRQ13_VECTOR, }, | |
172 | [14] = { .vector = IRQ14_VECTOR, }, | |
173 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
174 | }; |
175 | ||
13a0c3c2 | 176 | int __init arch_early_irq_init(void) |
8f09cd20 | 177 | { |
0b8f1efa YL |
178 | struct irq_cfg *cfg; |
179 | struct irq_desc *desc; | |
180 | int count; | |
dad213ae | 181 | int node; |
0b8f1efa | 182 | int i; |
d6c88a50 | 183 | |
0b8f1efa YL |
184 | cfg = irq_cfgx; |
185 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 186 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 187 | |
0b8f1efa YL |
188 | for (i = 0; i < count; i++) { |
189 | desc = irq_to_desc(i); | |
190 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
191 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
192 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
22f65d31 MT |
193 | if (i < NR_IRQS_LEGACY) |
194 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 195 | } |
13a0c3c2 YL |
196 | |
197 | return 0; | |
0b8f1efa | 198 | } |
8f09cd20 | 199 | |
0b8f1efa | 200 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 201 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 202 | { |
0b8f1efa YL |
203 | struct irq_cfg *cfg = NULL; |
204 | struct irq_desc *desc; | |
1da177e4 | 205 | |
0b8f1efa YL |
206 | desc = irq_to_desc(irq); |
207 | if (desc) | |
208 | cfg = desc->chip_data; | |
0f978f45 | 209 | |
0b8f1efa | 210 | return cfg; |
8f09cd20 | 211 | } |
d6c88a50 | 212 | |
85ac16d0 | 213 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 214 | { |
0b8f1efa | 215 | struct irq_cfg *cfg; |
0f978f45 | 216 | |
0b8f1efa | 217 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 218 | if (cfg) { |
80855f73 | 219 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
220 | kfree(cfg); |
221 | cfg = NULL; | |
80855f73 MT |
222 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
223 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
224 | free_cpumask_var(cfg->domain); |
225 | kfree(cfg); | |
226 | cfg = NULL; | |
227 | } else { | |
228 | cpumask_clear(cfg->domain); | |
229 | cpumask_clear(cfg->old_domain); | |
230 | } | |
231 | } | |
0f978f45 | 232 | |
0b8f1efa | 233 | return cfg; |
8f09cd20 YL |
234 | } |
235 | ||
85ac16d0 | 236 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 237 | { |
0b8f1efa | 238 | struct irq_cfg *cfg; |
d6c88a50 | 239 | |
0b8f1efa YL |
240 | cfg = desc->chip_data; |
241 | if (!cfg) { | |
85ac16d0 | 242 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
243 | if (!desc->chip_data) { |
244 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
245 | BUG_ON(1); | |
246 | } | |
247 | } | |
1da177e4 | 248 | |
13a0c3c2 | 249 | return 0; |
0b8f1efa | 250 | } |
0f978f45 | 251 | |
fcef5911 | 252 | /* for move_irq_desc */ |
48a1b10a | 253 | static void |
85ac16d0 | 254 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 255 | { |
48a1b10a YL |
256 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
257 | ||
258 | cfg->irq_2_pin = NULL; | |
259 | old_entry = old_cfg->irq_2_pin; | |
260 | if (!old_entry) | |
261 | return; | |
0f978f45 | 262 | |
85ac16d0 | 263 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
264 | if (!entry) |
265 | return; | |
0f978f45 | 266 | |
48a1b10a YL |
267 | entry->apic = old_entry->apic; |
268 | entry->pin = old_entry->pin; | |
269 | head = entry; | |
270 | tail = entry; | |
271 | old_entry = old_entry->next; | |
272 | while (old_entry) { | |
85ac16d0 | 273 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
274 | if (!entry) { |
275 | entry = head; | |
276 | while (entry) { | |
277 | head = entry->next; | |
278 | kfree(entry); | |
279 | entry = head; | |
280 | } | |
281 | /* still use the old one */ | |
282 | return; | |
283 | } | |
284 | entry->apic = old_entry->apic; | |
285 | entry->pin = old_entry->pin; | |
286 | tail->next = entry; | |
287 | tail = entry; | |
288 | old_entry = old_entry->next; | |
289 | } | |
0f978f45 | 290 | |
48a1b10a YL |
291 | tail->next = NULL; |
292 | cfg->irq_2_pin = head; | |
0f978f45 | 293 | } |
0f978f45 | 294 | |
48a1b10a | 295 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 296 | { |
48a1b10a | 297 | struct irq_pin_list *entry, *next; |
0f978f45 | 298 | |
48a1b10a YL |
299 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
300 | return; | |
301e6190 | 301 | |
48a1b10a | 302 | entry = old_cfg->irq_2_pin; |
0f978f45 | 303 | |
48a1b10a YL |
304 | while (entry) { |
305 | next = entry->next; | |
306 | kfree(entry); | |
307 | entry = next; | |
308 | } | |
309 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 310 | } |
0f978f45 | 311 | |
48a1b10a | 312 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 313 | struct irq_desc *desc, int node) |
0f978f45 | 314 | { |
48a1b10a YL |
315 | struct irq_cfg *cfg; |
316 | struct irq_cfg *old_cfg; | |
0f978f45 | 317 | |
85ac16d0 | 318 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 319 | |
48a1b10a YL |
320 | if (!cfg) |
321 | return; | |
322 | ||
323 | desc->chip_data = cfg; | |
324 | ||
325 | old_cfg = old_desc->chip_data; | |
326 | ||
327 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
328 | ||
85ac16d0 | 329 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 330 | } |
1da177e4 | 331 | |
48a1b10a YL |
332 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
333 | { | |
334 | kfree(old_cfg); | |
335 | } | |
336 | ||
337 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
338 | { | |
339 | struct irq_cfg *old_cfg, *cfg; | |
340 | ||
341 | old_cfg = old_desc->chip_data; | |
342 | cfg = desc->chip_data; | |
343 | ||
344 | if (old_cfg == cfg) | |
345 | return; | |
346 | ||
347 | if (old_cfg) { | |
348 | free_irq_2_pin(old_cfg, cfg); | |
349 | free_irq_cfg(old_cfg); | |
350 | old_desc->chip_data = NULL; | |
351 | } | |
352 | } | |
fcef5911 | 353 | /* end for move_irq_desc */ |
48a1b10a | 354 | |
0b8f1efa YL |
355 | #else |
356 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
357 | { | |
358 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 359 | } |
1da177e4 | 360 | |
0b8f1efa YL |
361 | #endif |
362 | ||
130fe05d LT |
363 | struct io_apic { |
364 | unsigned int index; | |
365 | unsigned int unused[3]; | |
366 | unsigned int data; | |
0280f7c4 SS |
367 | unsigned int unused2[11]; |
368 | unsigned int eoi; | |
130fe05d LT |
369 | }; |
370 | ||
371 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
372 | { | |
373 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 374 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
375 | } |
376 | ||
0280f7c4 SS |
377 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
378 | { | |
379 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
380 | writel(vector, &io_apic->eoi); | |
381 | } | |
382 | ||
130fe05d LT |
383 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
384 | { | |
385 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
386 | writel(reg, &io_apic->index); | |
387 | return readl(&io_apic->data); | |
388 | } | |
389 | ||
390 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
391 | { | |
392 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
393 | writel(reg, &io_apic->index); | |
394 | writel(value, &io_apic->data); | |
395 | } | |
396 | ||
397 | /* | |
398 | * Re-write a value: to be used for read-modify-write | |
399 | * cycles where the read already set up the index register. | |
400 | * | |
401 | * Older SiS APIC requires we rewrite the index register | |
402 | */ | |
403 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
404 | { | |
54168ed7 | 405 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
406 | |
407 | if (sis_apic_bug) | |
408 | writel(reg, &io_apic->index); | |
130fe05d LT |
409 | writel(value, &io_apic->data); |
410 | } | |
411 | ||
3145e941 | 412 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
413 | { |
414 | struct irq_pin_list *entry; | |
415 | unsigned long flags; | |
047c8fdb YL |
416 | |
417 | spin_lock_irqsave(&ioapic_lock, flags); | |
2977fb3f | 418 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
419 | unsigned int reg; |
420 | int pin; | |
421 | ||
047c8fdb YL |
422 | pin = entry->pin; |
423 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
424 | /* Is the remote IRR bit set? */ | |
425 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
426 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
427 | return true; | |
428 | } | |
047c8fdb YL |
429 | } |
430 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
431 | ||
432 | return false; | |
433 | } | |
047c8fdb | 434 | |
cf4c6a2f AK |
435 | union entry_union { |
436 | struct { u32 w1, w2; }; | |
437 | struct IO_APIC_route_entry entry; | |
438 | }; | |
439 | ||
440 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
441 | { | |
442 | union entry_union eu; | |
443 | unsigned long flags; | |
444 | spin_lock_irqsave(&ioapic_lock, flags); | |
445 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
446 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
447 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
448 | return eu.entry; | |
449 | } | |
450 | ||
f9dadfa7 LT |
451 | /* |
452 | * When we write a new IO APIC routing entry, we need to write the high | |
453 | * word first! If the mask bit in the low word is clear, we will enable | |
454 | * the interrupt, and we need to make sure the entry is fully populated | |
455 | * before that happens. | |
456 | */ | |
d15512f4 AK |
457 | static void |
458 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 459 | { |
50a8d4d2 F |
460 | union entry_union eu = {{0, 0}}; |
461 | ||
cf4c6a2f | 462 | eu.entry = e; |
f9dadfa7 LT |
463 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
464 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
465 | } |
466 | ||
ca97ab90 | 467 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
468 | { |
469 | unsigned long flags; | |
470 | spin_lock_irqsave(&ioapic_lock, flags); | |
471 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
472 | spin_unlock_irqrestore(&ioapic_lock, flags); |
473 | } | |
474 | ||
475 | /* | |
476 | * When we mask an IO APIC routing entry, we need to write the low | |
477 | * word first, in order to set the mask bit before we change the | |
478 | * high bits! | |
479 | */ | |
480 | static void ioapic_mask_entry(int apic, int pin) | |
481 | { | |
482 | unsigned long flags; | |
483 | union entry_union eu = { .entry.mask = 1 }; | |
484 | ||
cf4c6a2f AK |
485 | spin_lock_irqsave(&ioapic_lock, flags); |
486 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
487 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
488 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
489 | } | |
490 | ||
1da177e4 LT |
491 | /* |
492 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
493 | * shared ISA-space IRQs, so we have to support them. We are super | |
494 | * fast in the common case, and fast for shared ISA-space IRQs. | |
495 | */ | |
f3d1915a CG |
496 | static int |
497 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 498 | { |
2977fb3f | 499 | struct irq_pin_list **last, *entry; |
0f978f45 | 500 | |
2977fb3f CG |
501 | /* don't allow duplicates */ |
502 | last = &cfg->irq_2_pin; | |
503 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 504 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 505 | return 0; |
2977fb3f | 506 | last = &entry->next; |
1da177e4 | 507 | } |
0f978f45 | 508 | |
875e68ec | 509 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 510 | if (!entry) { |
f3d1915a CG |
511 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
512 | node, apic, pin); | |
513 | return -ENOMEM; | |
a7428cd2 | 514 | } |
1da177e4 LT |
515 | entry->apic = apic; |
516 | entry->pin = pin; | |
875e68ec | 517 | |
2977fb3f | 518 | *last = entry; |
f3d1915a CG |
519 | return 0; |
520 | } | |
521 | ||
522 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
523 | { | |
524 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
525 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
526 | } |
527 | ||
528 | /* | |
529 | * Reroute an IRQ to a different pin. | |
530 | */ | |
85ac16d0 | 531 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
532 | int oldapic, int oldpin, |
533 | int newapic, int newpin) | |
1da177e4 | 534 | { |
535b6429 | 535 | struct irq_pin_list *entry; |
1da177e4 | 536 | |
2977fb3f | 537 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
538 | if (entry->apic == oldapic && entry->pin == oldpin) { |
539 | entry->apic = newapic; | |
540 | entry->pin = newpin; | |
0f978f45 | 541 | /* every one is different, right? */ |
4eea6fff | 542 | return; |
0f978f45 | 543 | } |
1da177e4 | 544 | } |
0f978f45 | 545 | |
4eea6fff JF |
546 | /* old apic/pin didn't exist, so just add new ones */ |
547 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
548 | } |
549 | ||
2f210deb JF |
550 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
551 | int mask_and, int mask_or, | |
552 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 CG |
553 | { |
554 | int pin; | |
87783be4 | 555 | struct irq_pin_list *entry; |
047c8fdb | 556 | |
2977fb3f | 557 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
87783be4 CG |
558 | unsigned int reg; |
559 | pin = entry->pin; | |
560 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
561 | reg &= mask_and; | |
562 | reg |= mask_or; | |
563 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
564 | if (final) | |
565 | final(entry); | |
566 | } | |
567 | } | |
047c8fdb | 568 | |
3145e941 | 569 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 570 | { |
3145e941 | 571 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 572 | } |
047c8fdb | 573 | |
7f3e632f | 574 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 575 | { |
87783be4 CG |
576 | /* |
577 | * Synchronize the IO-APIC and the CPU by doing | |
578 | * a dummy read from the IO-APIC | |
579 | */ | |
580 | struct io_apic __iomem *io_apic; | |
581 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 582 | readl(&io_apic->data); |
1da177e4 LT |
583 | } |
584 | ||
3145e941 | 585 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 586 | { |
3145e941 | 587 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 588 | } |
1da177e4 | 589 | |
3145e941 | 590 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 591 | { |
3145e941 | 592 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
593 | IO_APIC_REDIR_MASKED, NULL); |
594 | } | |
1da177e4 | 595 | |
3145e941 | 596 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 597 | { |
3145e941 | 598 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
599 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
600 | } | |
047c8fdb | 601 | |
3145e941 | 602 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 603 | { |
3145e941 | 604 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
605 | unsigned long flags; |
606 | ||
3145e941 YL |
607 | BUG_ON(!cfg); |
608 | ||
1da177e4 | 609 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 610 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
611 | spin_unlock_irqrestore(&ioapic_lock, flags); |
612 | } | |
613 | ||
3145e941 | 614 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 615 | { |
3145e941 | 616 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
617 | unsigned long flags; |
618 | ||
619 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 620 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
621 | spin_unlock_irqrestore(&ioapic_lock, flags); |
622 | } | |
623 | ||
3145e941 YL |
624 | static void mask_IO_APIC_irq(unsigned int irq) |
625 | { | |
626 | struct irq_desc *desc = irq_to_desc(irq); | |
627 | ||
628 | mask_IO_APIC_irq_desc(desc); | |
629 | } | |
630 | static void unmask_IO_APIC_irq(unsigned int irq) | |
631 | { | |
632 | struct irq_desc *desc = irq_to_desc(irq); | |
633 | ||
634 | unmask_IO_APIC_irq_desc(desc); | |
635 | } | |
636 | ||
1da177e4 LT |
637 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
638 | { | |
639 | struct IO_APIC_route_entry entry; | |
36062448 | 640 | |
1da177e4 | 641 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 642 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
643 | if (entry.delivery_mode == dest_SMI) |
644 | return; | |
1da177e4 LT |
645 | /* |
646 | * Disable it in the IO-APIC irq-routing table: | |
647 | */ | |
f9dadfa7 | 648 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
649 | } |
650 | ||
54168ed7 | 651 | static void clear_IO_APIC (void) |
1da177e4 LT |
652 | { |
653 | int apic, pin; | |
654 | ||
655 | for (apic = 0; apic < nr_ioapics; apic++) | |
656 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
657 | clear_IO_APIC_pin(apic, pin); | |
658 | } | |
659 | ||
54168ed7 | 660 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
661 | /* |
662 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
663 | * specific CPU-side IRQs. | |
664 | */ | |
665 | ||
666 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
667 | static int pirq_entries[MAX_PIRQS] = { |
668 | [0 ... MAX_PIRQS - 1] = -1 | |
669 | }; | |
1da177e4 | 670 | |
1da177e4 LT |
671 | static int __init ioapic_pirq_setup(char *str) |
672 | { | |
673 | int i, max; | |
674 | int ints[MAX_PIRQS+1]; | |
675 | ||
676 | get_options(str, ARRAY_SIZE(ints), ints); | |
677 | ||
1da177e4 LT |
678 | apic_printk(APIC_VERBOSE, KERN_INFO |
679 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
680 | max = MAX_PIRQS; | |
681 | if (ints[0] < MAX_PIRQS) | |
682 | max = ints[0]; | |
683 | ||
684 | for (i = 0; i < max; i++) { | |
685 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
686 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
687 | /* | |
688 | * PIRQs are mapped upside down, usually. | |
689 | */ | |
690 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
691 | } | |
692 | return 1; | |
693 | } | |
694 | ||
695 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
696 | #endif /* CONFIG_X86_32 */ |
697 | ||
b24696bc FY |
698 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
699 | { | |
700 | int apic; | |
701 | struct IO_APIC_route_entry **ioapic_entries; | |
702 | ||
703 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
704 | GFP_ATOMIC); | |
705 | if (!ioapic_entries) | |
706 | return 0; | |
707 | ||
708 | for (apic = 0; apic < nr_ioapics; apic++) { | |
709 | ioapic_entries[apic] = | |
710 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
711 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
712 | if (!ioapic_entries[apic]) | |
713 | goto nomem; | |
714 | } | |
715 | ||
716 | return ioapic_entries; | |
717 | ||
718 | nomem: | |
719 | while (--apic >= 0) | |
720 | kfree(ioapic_entries[apic]); | |
721 | kfree(ioapic_entries); | |
722 | ||
723 | return 0; | |
724 | } | |
54168ed7 IM |
725 | |
726 | /* | |
05c3dc2c | 727 | * Saves all the IO-APIC RTE's |
54168ed7 | 728 | */ |
b24696bc | 729 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 730 | { |
54168ed7 IM |
731 | int apic, pin; |
732 | ||
b24696bc FY |
733 | if (!ioapic_entries) |
734 | return -ENOMEM; | |
54168ed7 IM |
735 | |
736 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
737 | if (!ioapic_entries[apic]) |
738 | return -ENOMEM; | |
54168ed7 | 739 | |
05c3dc2c | 740 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 741 | ioapic_entries[apic][pin] = |
54168ed7 | 742 | ioapic_read_entry(apic, pin); |
b24696bc | 743 | } |
5ffa4eb2 | 744 | |
54168ed7 IM |
745 | return 0; |
746 | } | |
747 | ||
b24696bc FY |
748 | /* |
749 | * Mask all IO APIC entries. | |
750 | */ | |
751 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
752 | { |
753 | int apic, pin; | |
754 | ||
b24696bc FY |
755 | if (!ioapic_entries) |
756 | return; | |
757 | ||
05c3dc2c | 758 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 759 | if (!ioapic_entries[apic]) |
05c3dc2c | 760 | break; |
b24696bc | 761 | |
05c3dc2c SS |
762 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
763 | struct IO_APIC_route_entry entry; | |
764 | ||
b24696bc | 765 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
766 | if (!entry.mask) { |
767 | entry.mask = 1; | |
768 | ioapic_write_entry(apic, pin, entry); | |
769 | } | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
b24696bc FY |
774 | /* |
775 | * Restore IO APIC entries which was saved in ioapic_entries. | |
776 | */ | |
777 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
778 | { |
779 | int apic, pin; | |
780 | ||
b24696bc FY |
781 | if (!ioapic_entries) |
782 | return -ENOMEM; | |
783 | ||
5ffa4eb2 | 784 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
785 | if (!ioapic_entries[apic]) |
786 | return -ENOMEM; | |
787 | ||
54168ed7 IM |
788 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
789 | ioapic_write_entry(apic, pin, | |
b24696bc | 790 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 791 | } |
b24696bc | 792 | return 0; |
54168ed7 IM |
793 | } |
794 | ||
b24696bc FY |
795 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
796 | { | |
797 | int apic; | |
798 | ||
799 | for (apic = 0; apic < nr_ioapics; apic++) | |
800 | kfree(ioapic_entries[apic]); | |
801 | ||
802 | kfree(ioapic_entries); | |
54168ed7 | 803 | } |
1da177e4 LT |
804 | |
805 | /* | |
806 | * Find the IRQ entry number of a certain pin. | |
807 | */ | |
808 | static int find_irq_entry(int apic, int pin, int type) | |
809 | { | |
810 | int i; | |
811 | ||
812 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
813 | if (mp_irqs[i].irqtype == type && |
814 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
815 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
816 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
817 | return i; |
818 | ||
819 | return -1; | |
820 | } | |
821 | ||
822 | /* | |
823 | * Find the pin to which IRQ[irq] (ISA) is connected | |
824 | */ | |
fcfd636a | 825 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
826 | { |
827 | int i; | |
828 | ||
829 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 830 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 831 | |
d27e2b8e | 832 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
833 | (mp_irqs[i].irqtype == type) && |
834 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 835 | |
c2c21745 | 836 | return mp_irqs[i].dstirq; |
1da177e4 LT |
837 | } |
838 | return -1; | |
839 | } | |
840 | ||
fcfd636a EB |
841 | static int __init find_isa_irq_apic(int irq, int type) |
842 | { | |
843 | int i; | |
844 | ||
845 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 846 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 847 | |
73b2961b | 848 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
849 | (mp_irqs[i].irqtype == type) && |
850 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
851 | break; |
852 | } | |
853 | if (i < mp_irq_entries) { | |
854 | int apic; | |
54168ed7 | 855 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 856 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
857 | return apic; |
858 | } | |
859 | } | |
860 | ||
861 | return -1; | |
862 | } | |
863 | ||
c0a282c2 | 864 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
865 | /* |
866 | * EISA Edge/Level control register, ELCR | |
867 | */ | |
868 | static int EISA_ELCR(unsigned int irq) | |
869 | { | |
99d093d1 | 870 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
871 | unsigned int port = 0x4d0 + (irq >> 3); |
872 | return (inb(port) >> (irq & 7)) & 1; | |
873 | } | |
874 | apic_printk(APIC_VERBOSE, KERN_INFO | |
875 | "Broken MPtable reports ISA irq %d\n", irq); | |
876 | return 0; | |
877 | } | |
54168ed7 | 878 | |
c0a282c2 | 879 | #endif |
1da177e4 | 880 | |
6728801d AS |
881 | /* ISA interrupts are always polarity zero edge triggered, |
882 | * when listed as conforming in the MP table. */ | |
883 | ||
884 | #define default_ISA_trigger(idx) (0) | |
885 | #define default_ISA_polarity(idx) (0) | |
886 | ||
1da177e4 LT |
887 | /* EISA interrupts are always polarity zero and can be edge or level |
888 | * trigger depending on the ELCR value. If an interrupt is listed as | |
889 | * EISA conforming in the MP table, that means its trigger type must | |
890 | * be read in from the ELCR */ | |
891 | ||
c2c21745 | 892 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 893 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
894 | |
895 | /* PCI interrupts are always polarity one level triggered, | |
896 | * when listed as conforming in the MP table. */ | |
897 | ||
898 | #define default_PCI_trigger(idx) (1) | |
899 | #define default_PCI_polarity(idx) (1) | |
900 | ||
901 | /* MCA interrupts are always polarity zero level triggered, | |
902 | * when listed as conforming in the MP table. */ | |
903 | ||
904 | #define default_MCA_trigger(idx) (1) | |
6728801d | 905 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 906 | |
61fd47e0 | 907 | static int MPBIOS_polarity(int idx) |
1da177e4 | 908 | { |
c2c21745 | 909 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
910 | int polarity; |
911 | ||
912 | /* | |
913 | * Determine IRQ line polarity (high active or low active): | |
914 | */ | |
c2c21745 | 915 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 916 | { |
54168ed7 IM |
917 | case 0: /* conforms, ie. bus-type dependent polarity */ |
918 | if (test_bit(bus, mp_bus_not_pci)) | |
919 | polarity = default_ISA_polarity(idx); | |
920 | else | |
921 | polarity = default_PCI_polarity(idx); | |
922 | break; | |
923 | case 1: /* high active */ | |
924 | { | |
925 | polarity = 0; | |
926 | break; | |
927 | } | |
928 | case 2: /* reserved */ | |
929 | { | |
930 | printk(KERN_WARNING "broken BIOS!!\n"); | |
931 | polarity = 1; | |
932 | break; | |
933 | } | |
934 | case 3: /* low active */ | |
935 | { | |
936 | polarity = 1; | |
937 | break; | |
938 | } | |
939 | default: /* invalid */ | |
940 | { | |
941 | printk(KERN_WARNING "broken BIOS!!\n"); | |
942 | polarity = 1; | |
943 | break; | |
944 | } | |
1da177e4 LT |
945 | } |
946 | return polarity; | |
947 | } | |
948 | ||
949 | static int MPBIOS_trigger(int idx) | |
950 | { | |
c2c21745 | 951 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
952 | int trigger; |
953 | ||
954 | /* | |
955 | * Determine IRQ trigger mode (edge or level sensitive): | |
956 | */ | |
c2c21745 | 957 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 958 | { |
54168ed7 IM |
959 | case 0: /* conforms, ie. bus-type dependent */ |
960 | if (test_bit(bus, mp_bus_not_pci)) | |
961 | trigger = default_ISA_trigger(idx); | |
962 | else | |
963 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 964 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
965 | switch (mp_bus_id_to_type[bus]) { |
966 | case MP_BUS_ISA: /* ISA pin */ | |
967 | { | |
968 | /* set before the switch */ | |
969 | break; | |
970 | } | |
971 | case MP_BUS_EISA: /* EISA pin */ | |
972 | { | |
973 | trigger = default_EISA_trigger(idx); | |
974 | break; | |
975 | } | |
976 | case MP_BUS_PCI: /* PCI pin */ | |
977 | { | |
978 | /* set before the switch */ | |
979 | break; | |
980 | } | |
981 | case MP_BUS_MCA: /* MCA pin */ | |
982 | { | |
983 | trigger = default_MCA_trigger(idx); | |
984 | break; | |
985 | } | |
986 | default: | |
987 | { | |
988 | printk(KERN_WARNING "broken BIOS!!\n"); | |
989 | trigger = 1; | |
990 | break; | |
991 | } | |
992 | } | |
993 | #endif | |
1da177e4 | 994 | break; |
54168ed7 | 995 | case 1: /* edge */ |
1da177e4 | 996 | { |
54168ed7 | 997 | trigger = 0; |
1da177e4 LT |
998 | break; |
999 | } | |
54168ed7 | 1000 | case 2: /* reserved */ |
1da177e4 | 1001 | { |
54168ed7 IM |
1002 | printk(KERN_WARNING "broken BIOS!!\n"); |
1003 | trigger = 1; | |
1da177e4 LT |
1004 | break; |
1005 | } | |
54168ed7 | 1006 | case 3: /* level */ |
1da177e4 | 1007 | { |
54168ed7 | 1008 | trigger = 1; |
1da177e4 LT |
1009 | break; |
1010 | } | |
54168ed7 | 1011 | default: /* invalid */ |
1da177e4 LT |
1012 | { |
1013 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1014 | trigger = 0; |
1da177e4 LT |
1015 | break; |
1016 | } | |
1017 | } | |
1018 | return trigger; | |
1019 | } | |
1020 | ||
1021 | static inline int irq_polarity(int idx) | |
1022 | { | |
1023 | return MPBIOS_polarity(idx); | |
1024 | } | |
1025 | ||
1026 | static inline int irq_trigger(int idx) | |
1027 | { | |
1028 | return MPBIOS_trigger(idx); | |
1029 | } | |
1030 | ||
efa2559f | 1031 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1032 | static int pin_2_irq(int idx, int apic, int pin) |
1033 | { | |
1034 | int irq, i; | |
c2c21745 | 1035 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1036 | |
1037 | /* | |
1038 | * Debugging check, we are in big trouble if this message pops up! | |
1039 | */ | |
c2c21745 | 1040 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1041 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1042 | ||
54168ed7 | 1043 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1044 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1045 | } else { |
643befed AS |
1046 | /* |
1047 | * PCI IRQs are mapped in order | |
1048 | */ | |
1049 | i = irq = 0; | |
1050 | while (i < apic) | |
1051 | irq += nr_ioapic_registers[i++]; | |
1052 | irq += pin; | |
d6c88a50 | 1053 | /* |
54168ed7 IM |
1054 | * For MPS mode, so far only needed by ES7000 platform |
1055 | */ | |
d6c88a50 TG |
1056 | if (ioapic_renumber_irq) |
1057 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1058 | } |
1059 | ||
54168ed7 | 1060 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1061 | /* |
1062 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1063 | */ | |
1064 | if ((pin >= 16) && (pin <= 23)) { | |
1065 | if (pirq_entries[pin-16] != -1) { | |
1066 | if (!pirq_entries[pin-16]) { | |
1067 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1068 | "disabling PIRQ%d\n", pin-16); | |
1069 | } else { | |
1070 | irq = pirq_entries[pin-16]; | |
1071 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1072 | "using PIRQ%d -> IRQ %d\n", | |
1073 | pin-16, irq); | |
1074 | } | |
1075 | } | |
1076 | } | |
54168ed7 IM |
1077 | #endif |
1078 | ||
1da177e4 LT |
1079 | return irq; |
1080 | } | |
1081 | ||
e20c06fd YL |
1082 | /* |
1083 | * Find a specific PCI IRQ entry. | |
1084 | * Not an __init, possibly needed by modules | |
1085 | */ | |
1086 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1087 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1088 | { |
1089 | int apic, i, best_guess = -1; | |
1090 | ||
1091 | apic_printk(APIC_DEBUG, | |
1092 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1093 | bus, slot, pin); | |
1094 | if (test_bit(bus, mp_bus_not_pci)) { | |
1095 | apic_printk(APIC_VERBOSE, | |
1096 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1097 | return -1; | |
1098 | } | |
1099 | for (i = 0; i < mp_irq_entries; i++) { | |
1100 | int lbus = mp_irqs[i].srcbus; | |
1101 | ||
1102 | for (apic = 0; apic < nr_ioapics; apic++) | |
1103 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1104 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1105 | break; | |
1106 | ||
1107 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1108 | !mp_irqs[i].irqtype && | |
1109 | (bus == lbus) && | |
1110 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1111 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1112 | ||
1113 | if (!(apic || IO_APIC_IRQ(irq))) | |
1114 | continue; | |
1115 | ||
1116 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1117 | set_io_apic_irq_attr(irq_attr, apic, |
1118 | mp_irqs[i].dstirq, | |
1119 | irq_trigger(i), | |
1120 | irq_polarity(i)); | |
e20c06fd YL |
1121 | return irq; |
1122 | } | |
1123 | /* | |
1124 | * Use the first all-but-pin matching entry as a | |
1125 | * best-guess fuzzy result for broken mptables. | |
1126 | */ | |
1127 | if (best_guess < 0) { | |
e5198075 YL |
1128 | set_io_apic_irq_attr(irq_attr, apic, |
1129 | mp_irqs[i].dstirq, | |
1130 | irq_trigger(i), | |
1131 | irq_polarity(i)); | |
e20c06fd YL |
1132 | best_guess = irq; |
1133 | } | |
1134 | } | |
1135 | } | |
1136 | return best_guess; | |
1137 | } | |
1138 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1139 | ||
497c9a19 YL |
1140 | void lock_vector_lock(void) |
1141 | { | |
1142 | /* Used to the online set of cpus does not change | |
1143 | * during assign_irq_vector. | |
1144 | */ | |
1145 | spin_lock(&vector_lock); | |
1146 | } | |
1da177e4 | 1147 | |
497c9a19 | 1148 | void unlock_vector_lock(void) |
1da177e4 | 1149 | { |
497c9a19 YL |
1150 | spin_unlock(&vector_lock); |
1151 | } | |
1da177e4 | 1152 | |
e7986739 MT |
1153 | static int |
1154 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1155 | { |
047c8fdb YL |
1156 | /* |
1157 | * NOTE! The local APIC isn't very good at handling | |
1158 | * multiple interrupts at the same interrupt level. | |
1159 | * As the interrupt level is determined by taking the | |
1160 | * vector number and shifting that right by 4, we | |
1161 | * want to spread these out a bit so that they don't | |
1162 | * all fall in the same interrupt level. | |
1163 | * | |
1164 | * Also, we've got to be careful not to trash gate | |
1165 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1166 | */ | |
54168ed7 IM |
1167 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1168 | unsigned int old_vector; | |
22f65d31 MT |
1169 | int cpu, err; |
1170 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1171 | |
54168ed7 IM |
1172 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1173 | return -EBUSY; | |
0a1ad60d | 1174 | |
22f65d31 MT |
1175 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1176 | return -ENOMEM; | |
ace80ab7 | 1177 | |
54168ed7 IM |
1178 | old_vector = cfg->vector; |
1179 | if (old_vector) { | |
22f65d31 MT |
1180 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1181 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1182 | if (!cpumask_empty(tmp_mask)) { | |
1183 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1184 | return 0; |
22f65d31 | 1185 | } |
54168ed7 | 1186 | } |
497c9a19 | 1187 | |
e7986739 | 1188 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1189 | err = -ENOSPC; |
1190 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1191 | int new_cpu; |
1192 | int vector, offset; | |
497c9a19 | 1193 | |
e2d40b18 | 1194 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1195 | |
54168ed7 IM |
1196 | vector = current_vector; |
1197 | offset = current_offset; | |
497c9a19 | 1198 | next: |
54168ed7 IM |
1199 | vector += 8; |
1200 | if (vector >= first_system_vector) { | |
e7986739 | 1201 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1202 | offset = (offset + 1) % 8; |
1203 | vector = FIRST_DEVICE_VECTOR + offset; | |
1204 | } | |
1205 | if (unlikely(current_vector == vector)) | |
1206 | continue; | |
b77b881f YL |
1207 | |
1208 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1209 | goto next; |
b77b881f | 1210 | |
22f65d31 | 1211 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1212 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1213 | goto next; | |
1214 | /* Found one! */ | |
1215 | current_vector = vector; | |
1216 | current_offset = offset; | |
1217 | if (old_vector) { | |
1218 | cfg->move_in_progress = 1; | |
22f65d31 | 1219 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1220 | } |
22f65d31 | 1221 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1222 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1223 | cfg->vector = vector; | |
22f65d31 MT |
1224 | cpumask_copy(cfg->domain, tmp_mask); |
1225 | err = 0; | |
1226 | break; | |
54168ed7 | 1227 | } |
22f65d31 MT |
1228 | free_cpumask_var(tmp_mask); |
1229 | return err; | |
497c9a19 YL |
1230 | } |
1231 | ||
e7986739 MT |
1232 | static int |
1233 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1234 | { |
1235 | int err; | |
ace80ab7 | 1236 | unsigned long flags; |
ace80ab7 EB |
1237 | |
1238 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1239 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1240 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1241 | return err; |
1242 | } | |
1243 | ||
3145e941 | 1244 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1245 | { |
497c9a19 YL |
1246 | int cpu, vector; |
1247 | ||
497c9a19 YL |
1248 | BUG_ON(!cfg->vector); |
1249 | ||
1250 | vector = cfg->vector; | |
22f65d31 | 1251 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1252 | per_cpu(vector_irq, cpu)[vector] = -1; |
1253 | ||
1254 | cfg->vector = 0; | |
22f65d31 | 1255 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1256 | |
1257 | if (likely(!cfg->move_in_progress)) | |
1258 | return; | |
22f65d31 | 1259 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1260 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1261 | vector++) { | |
1262 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1263 | continue; | |
1264 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1265 | break; | |
1266 | } | |
1267 | } | |
1268 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1269 | } |
1270 | ||
1271 | void __setup_vector_irq(int cpu) | |
1272 | { | |
1273 | /* Initialize vector_irq on a new cpu */ | |
1274 | /* This function must be called with vector_lock held */ | |
1275 | int irq, vector; | |
1276 | struct irq_cfg *cfg; | |
0b8f1efa | 1277 | struct irq_desc *desc; |
497c9a19 YL |
1278 | |
1279 | /* Mark the inuse vectors */ | |
0b8f1efa | 1280 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1281 | cfg = desc->chip_data; |
22f65d31 | 1282 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1283 | continue; |
1284 | vector = cfg->vector; | |
497c9a19 YL |
1285 | per_cpu(vector_irq, cpu)[vector] = irq; |
1286 | } | |
1287 | /* Mark the free vectors */ | |
1288 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1289 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1290 | if (irq < 0) | |
1291 | continue; | |
1292 | ||
1293 | cfg = irq_cfg(irq); | |
22f65d31 | 1294 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1295 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1296 | } |
1da177e4 | 1297 | } |
3fde6900 | 1298 | |
f5b9ed7a | 1299 | static struct irq_chip ioapic_chip; |
54168ed7 | 1300 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1301 | |
54168ed7 IM |
1302 | #define IOAPIC_AUTO -1 |
1303 | #define IOAPIC_EDGE 0 | |
1304 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1305 | |
047c8fdb | 1306 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1307 | static inline int IO_APIC_irq_trigger(int irq) |
1308 | { | |
d6c88a50 | 1309 | int apic, idx, pin; |
1d025192 | 1310 | |
d6c88a50 TG |
1311 | for (apic = 0; apic < nr_ioapics; apic++) { |
1312 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1313 | idx = find_irq_entry(apic, pin, mp_INT); | |
1314 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1315 | return irq_trigger(idx); | |
1316 | } | |
1317 | } | |
1318 | /* | |
54168ed7 IM |
1319 | * nonexistent IRQs are edge default |
1320 | */ | |
d6c88a50 | 1321 | return 0; |
1d025192 | 1322 | } |
047c8fdb YL |
1323 | #else |
1324 | static inline int IO_APIC_irq_trigger(int irq) | |
1325 | { | |
54168ed7 | 1326 | return 1; |
047c8fdb YL |
1327 | } |
1328 | #endif | |
1d025192 | 1329 | |
3145e941 | 1330 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1331 | { |
199751d7 | 1332 | |
6ebcc00e | 1333 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1334 | trigger == IOAPIC_LEVEL) |
08678b08 | 1335 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1336 | else |
1337 | desc->status &= ~IRQ_LEVEL; | |
1338 | ||
54168ed7 IM |
1339 | if (irq_remapped(irq)) { |
1340 | desc->status |= IRQ_MOVE_PCNTXT; | |
1341 | if (trigger) | |
1342 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1343 | handle_fasteoi_irq, | |
1344 | "fasteoi"); | |
1345 | else | |
1346 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1347 | handle_edge_irq, "edge"); | |
1348 | return; | |
1349 | } | |
29b61be6 | 1350 | |
047c8fdb YL |
1351 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1352 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1353 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1354 | handle_fasteoi_irq, |
1355 | "fasteoi"); | |
047c8fdb | 1356 | else |
a460e745 | 1357 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1358 | handle_edge_irq, "edge"); |
1da177e4 LT |
1359 | } |
1360 | ||
ca97ab90 JF |
1361 | int setup_ioapic_entry(int apic_id, int irq, |
1362 | struct IO_APIC_route_entry *entry, | |
1363 | unsigned int destination, int trigger, | |
0280f7c4 | 1364 | int polarity, int vector, int pin) |
1da177e4 | 1365 | { |
497c9a19 YL |
1366 | /* |
1367 | * add it to the IO-APIC irq-routing table: | |
1368 | */ | |
1369 | memset(entry,0,sizeof(*entry)); | |
1370 | ||
54168ed7 | 1371 | if (intr_remapping_enabled) { |
c8d46cf0 | 1372 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1373 | struct irte irte; |
1374 | struct IR_IO_APIC_route_entry *ir_entry = | |
1375 | (struct IR_IO_APIC_route_entry *) entry; | |
1376 | int index; | |
1377 | ||
1378 | if (!iommu) | |
c8d46cf0 | 1379 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1380 | |
1381 | index = alloc_irte(iommu, irq, 1); | |
1382 | if (index < 0) | |
c8d46cf0 | 1383 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1384 | |
1385 | memset(&irte, 0, sizeof(irte)); | |
1386 | ||
1387 | irte.present = 1; | |
9b5bc8dc | 1388 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1389 | /* |
1390 | * Trigger mode in the IRTE will always be edge, and the | |
1391 | * actual level or edge trigger will be setup in the IO-APIC | |
1392 | * RTE. This will help simplify level triggered irq migration. | |
1393 | * For more details, see the comments above explainig IO-APIC | |
1394 | * irq migration in the presence of interrupt-remapping. | |
1395 | */ | |
1396 | irte.trigger_mode = 0; | |
9b5bc8dc | 1397 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1398 | irte.vector = vector; |
1399 | irte.dest_id = IRTE_DEST(destination); | |
1400 | ||
f007e99c WH |
1401 | /* Set source-id of interrupt request */ |
1402 | set_ioapic_sid(&irte, apic_id); | |
1403 | ||
54168ed7 IM |
1404 | modify_irte(irq, &irte); |
1405 | ||
1406 | ir_entry->index2 = (index >> 15) & 0x1; | |
1407 | ir_entry->zero = 0; | |
1408 | ir_entry->format = 1; | |
1409 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1410 | /* |
1411 | * IO-APIC RTE will be configured with virtual vector. | |
1412 | * irq handler will do the explicit EOI to the io-apic. | |
1413 | */ | |
1414 | ir_entry->vector = pin; | |
29b61be6 | 1415 | } else { |
9b5bc8dc IM |
1416 | entry->delivery_mode = apic->irq_delivery_mode; |
1417 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1418 | entry->dest = destination; |
0280f7c4 | 1419 | entry->vector = vector; |
54168ed7 | 1420 | } |
497c9a19 | 1421 | |
54168ed7 | 1422 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1423 | entry->trigger = trigger; |
1424 | entry->polarity = polarity; | |
497c9a19 YL |
1425 | |
1426 | /* Mask level triggered irqs. | |
1427 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1428 | */ | |
1429 | if (trigger) | |
1430 | entry->mask = 1; | |
497c9a19 YL |
1431 | return 0; |
1432 | } | |
1433 | ||
c8d46cf0 | 1434 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1435 | int trigger, int polarity) |
497c9a19 YL |
1436 | { |
1437 | struct irq_cfg *cfg; | |
1da177e4 | 1438 | struct IO_APIC_route_entry entry; |
22f65d31 | 1439 | unsigned int dest; |
497c9a19 YL |
1440 | |
1441 | if (!IO_APIC_IRQ(irq)) | |
1442 | return; | |
1443 | ||
3145e941 | 1444 | cfg = desc->chip_data; |
497c9a19 | 1445 | |
fe402e1f | 1446 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1447 | return; |
1448 | ||
debccb3e | 1449 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1450 | |
1451 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1452 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1453 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1454 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1455 | irq, trigger, polarity); |
1456 | ||
1457 | ||
c8d46cf0 | 1458 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1459 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1460 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1461 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1462 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1463 | return; |
1464 | } | |
1465 | ||
3145e941 | 1466 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1467 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1468 | disable_8259A_irq(irq); |
1469 | ||
c8d46cf0 | 1470 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1471 | } |
1472 | ||
b9c61b70 YL |
1473 | static struct { |
1474 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1475 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1476 | ||
497c9a19 YL |
1477 | static void __init setup_IO_APIC_irqs(void) |
1478 | { | |
b9c61b70 | 1479 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1480 | int notcon = 0; |
0b8f1efa | 1481 | struct irq_desc *desc; |
3145e941 | 1482 | struct irq_cfg *cfg; |
85ac16d0 | 1483 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1484 | |
1485 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1486 | ||
b9c61b70 YL |
1487 | #ifdef CONFIG_ACPI |
1488 | if (!acpi_disabled && acpi_ioapic) { | |
1489 | apic_id = mp_find_ioapic(0); | |
1490 | if (apic_id < 0) | |
1491 | apic_id = 0; | |
1492 | } | |
1493 | #endif | |
3c2cbd24 | 1494 | |
b9c61b70 YL |
1495 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1496 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1497 | if (idx == -1) { | |
1498 | if (!notcon) { | |
1499 | notcon = 1; | |
1500 | apic_printk(APIC_VERBOSE, | |
1501 | KERN_DEBUG " %d-%d", | |
1502 | mp_ioapics[apic_id].apicid, pin); | |
1503 | } else | |
1504 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1505 | mp_ioapics[apic_id].apicid, pin); | |
1506 | continue; | |
1507 | } | |
1508 | if (notcon) { | |
1509 | apic_printk(APIC_VERBOSE, | |
1510 | " (apicid-pin) not connected\n"); | |
1511 | notcon = 0; | |
1512 | } | |
33a201fa | 1513 | |
b9c61b70 | 1514 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1515 | |
b9c61b70 YL |
1516 | /* |
1517 | * Skip the timer IRQ if there's a quirk handler | |
1518 | * installed and if it returns 1: | |
1519 | */ | |
1520 | if (apic->multi_timer_check && | |
1521 | apic->multi_timer_check(apic_id, irq)) | |
1522 | continue; | |
36062448 | 1523 | |
b9c61b70 YL |
1524 | desc = irq_to_desc_alloc_node(irq, node); |
1525 | if (!desc) { | |
1526 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1527 | continue; | |
3c2cbd24 | 1528 | } |
b9c61b70 YL |
1529 | cfg = desc->chip_data; |
1530 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1531 | /* |
1532 | * don't mark it in pin_programmed, so later acpi could | |
1533 | * set it correctly when irq < 16 | |
1534 | */ | |
b9c61b70 YL |
1535 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1536 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1537 | } |
1538 | ||
3c2cbd24 CG |
1539 | if (notcon) |
1540 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1541 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1542 | } |
1543 | ||
1544 | /* | |
f7633ce5 | 1545 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1546 | */ |
c8d46cf0 | 1547 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1548 | int vector) |
1da177e4 LT |
1549 | { |
1550 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1551 | |
54168ed7 IM |
1552 | if (intr_remapping_enabled) |
1553 | return; | |
54168ed7 | 1554 | |
36062448 | 1555 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1556 | |
1557 | /* | |
1558 | * We use logical delivery to get the timer IRQ | |
1559 | * to the first CPU. | |
1560 | */ | |
9b5bc8dc | 1561 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1562 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1563 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1564 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1565 | entry.polarity = 0; |
1566 | entry.trigger = 0; | |
1567 | entry.vector = vector; | |
1568 | ||
1569 | /* | |
1570 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1571 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1572 | */ |
54168ed7 | 1573 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1574 | |
1575 | /* | |
1576 | * Add it to the IO-APIC irq-routing table: | |
1577 | */ | |
c8d46cf0 | 1578 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1579 | } |
1580 | ||
32f71aff MR |
1581 | |
1582 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1583 | { |
1584 | int apic, i; | |
1585 | union IO_APIC_reg_00 reg_00; | |
1586 | union IO_APIC_reg_01 reg_01; | |
1587 | union IO_APIC_reg_02 reg_02; | |
1588 | union IO_APIC_reg_03 reg_03; | |
1589 | unsigned long flags; | |
0f978f45 | 1590 | struct irq_cfg *cfg; |
0b8f1efa | 1591 | struct irq_desc *desc; |
8f09cd20 | 1592 | unsigned int irq; |
1da177e4 LT |
1593 | |
1594 | if (apic_verbosity == APIC_QUIET) | |
1595 | return; | |
1596 | ||
36062448 | 1597 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1598 | for (i = 0; i < nr_ioapics; i++) |
1599 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1600 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1601 | |
1602 | /* | |
1603 | * We are a bit conservative about what we expect. We have to | |
1604 | * know about every hardware change ASAP. | |
1605 | */ | |
1606 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1607 | ||
1608 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1609 | ||
1610 | spin_lock_irqsave(&ioapic_lock, flags); | |
1611 | reg_00.raw = io_apic_read(apic, 0); | |
1612 | reg_01.raw = io_apic_read(apic, 1); | |
1613 | if (reg_01.bits.version >= 0x10) | |
1614 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1615 | if (reg_01.bits.version >= 0x20) |
1616 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1617 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1618 | ||
54168ed7 | 1619 | printk("\n"); |
b5ba7e6d | 1620 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1621 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1622 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1623 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1624 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1625 | |
54168ed7 | 1626 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1627 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1628 | |
1629 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1630 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1631 | |
1632 | /* | |
1633 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1634 | * but the value of reg_02 is read as the previous read register | |
1635 | * value, so ignore it if reg_02 == reg_01. | |
1636 | */ | |
1637 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1638 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1639 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1640 | } |
1641 | ||
1642 | /* | |
1643 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1644 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1645 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1646 | */ | |
1647 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1648 | reg_03.raw != reg_01.raw) { | |
1649 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1650 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1651 | } |
1652 | ||
1653 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1654 | ||
d83e94ac YL |
1655 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1656 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1657 | |
1658 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1659 | struct IO_APIC_route_entry entry; | |
1660 | ||
cf4c6a2f | 1661 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1662 | |
54168ed7 IM |
1663 | printk(KERN_DEBUG " %02x %03X ", |
1664 | i, | |
1665 | entry.dest | |
1666 | ); | |
1da177e4 LT |
1667 | |
1668 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1669 | entry.mask, | |
1670 | entry.trigger, | |
1671 | entry.irr, | |
1672 | entry.polarity, | |
1673 | entry.delivery_status, | |
1674 | entry.dest_mode, | |
1675 | entry.delivery_mode, | |
1676 | entry.vector | |
1677 | ); | |
1678 | } | |
1679 | } | |
1da177e4 | 1680 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1681 | for_each_irq_desc(irq, desc) { |
1682 | struct irq_pin_list *entry; | |
1683 | ||
0b8f1efa YL |
1684 | cfg = desc->chip_data; |
1685 | entry = cfg->irq_2_pin; | |
0f978f45 | 1686 | if (!entry) |
1da177e4 | 1687 | continue; |
8f09cd20 | 1688 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1689 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1690 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1691 | printk("\n"); |
1692 | } | |
1693 | ||
1694 | printk(KERN_INFO ".................................... done.\n"); | |
1695 | ||
1696 | return; | |
1697 | } | |
1698 | ||
251e1e44 | 1699 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1700 | { |
251e1e44 | 1701 | int i; |
1da177e4 LT |
1702 | |
1703 | if (apic_verbosity == APIC_QUIET) | |
1704 | return; | |
1705 | ||
251e1e44 IM |
1706 | printk(KERN_DEBUG); |
1707 | ||
1708 | for (i = 0; i < 8; i++) | |
1709 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1710 | ||
1711 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1712 | } |
1713 | ||
32f71aff | 1714 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1715 | { |
97a52714 | 1716 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1717 | u64 icr; |
1da177e4 LT |
1718 | |
1719 | if (apic_verbosity == APIC_QUIET) | |
1720 | return; | |
1721 | ||
251e1e44 | 1722 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1723 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1724 | v = apic_read(APIC_ID); |
54168ed7 | 1725 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1726 | v = apic_read(APIC_LVR); |
1727 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1728 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1729 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1730 | |
1731 | v = apic_read(APIC_TASKPRI); | |
1732 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1733 | ||
54168ed7 | 1734 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1735 | if (!APIC_XAPIC(ver)) { |
1736 | v = apic_read(APIC_ARBPRI); | |
1737 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1738 | v & APIC_ARBPRI_MASK); | |
1739 | } | |
1da177e4 LT |
1740 | v = apic_read(APIC_PROCPRI); |
1741 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1742 | } | |
1743 | ||
a11b5abe YL |
1744 | /* |
1745 | * Remote read supported only in the 82489DX and local APIC for | |
1746 | * Pentium processors. | |
1747 | */ | |
1748 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1749 | v = apic_read(APIC_RRR); | |
1750 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1751 | } | |
1752 | ||
1da177e4 LT |
1753 | v = apic_read(APIC_LDR); |
1754 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1755 | if (!x2apic_enabled()) { |
1756 | v = apic_read(APIC_DFR); | |
1757 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1758 | } | |
1da177e4 LT |
1759 | v = apic_read(APIC_SPIV); |
1760 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1761 | ||
1762 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1763 | print_APIC_field(APIC_ISR); |
1da177e4 | 1764 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1765 | print_APIC_field(APIC_TMR); |
1da177e4 | 1766 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1767 | print_APIC_field(APIC_IRR); |
1da177e4 | 1768 | |
54168ed7 IM |
1769 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1770 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1771 | apic_write(APIC_ESR, 0); |
54168ed7 | 1772 | |
1da177e4 LT |
1773 | v = apic_read(APIC_ESR); |
1774 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1775 | } | |
1776 | ||
7ab6af7a | 1777 | icr = apic_icr_read(); |
0c425cec IM |
1778 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1779 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1780 | |
1781 | v = apic_read(APIC_LVTT); | |
1782 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1783 | ||
1784 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1785 | v = apic_read(APIC_LVTPC); | |
1786 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1787 | } | |
1788 | v = apic_read(APIC_LVT0); | |
1789 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1790 | v = apic_read(APIC_LVT1); | |
1791 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1792 | ||
1793 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1794 | v = apic_read(APIC_LVTERR); | |
1795 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1796 | } | |
1797 | ||
1798 | v = apic_read(APIC_TMICT); | |
1799 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1800 | v = apic_read(APIC_TMCCT); | |
1801 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1802 | v = apic_read(APIC_TDCR); | |
1803 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1804 | |
1805 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1806 | v = apic_read(APIC_EFEAT); | |
1807 | maxlvt = (v >> 16) & 0xff; | |
1808 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1809 | v = apic_read(APIC_ECTRL); | |
1810 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1811 | for (i = 0; i < maxlvt; i++) { | |
1812 | v = apic_read(APIC_EILVTn(i)); | |
1813 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1814 | } | |
1815 | } | |
1da177e4 LT |
1816 | printk("\n"); |
1817 | } | |
1818 | ||
32f71aff | 1819 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1820 | { |
ffd5aae7 YL |
1821 | int cpu; |
1822 | ||
1823 | preempt_disable(); | |
1824 | for_each_online_cpu(cpu) | |
1825 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1826 | preempt_enable(); | |
1da177e4 LT |
1827 | } |
1828 | ||
32f71aff | 1829 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1830 | { |
1da177e4 LT |
1831 | unsigned int v; |
1832 | unsigned long flags; | |
1833 | ||
1834 | if (apic_verbosity == APIC_QUIET) | |
1835 | return; | |
1836 | ||
1837 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1838 | ||
1839 | spin_lock_irqsave(&i8259A_lock, flags); | |
1840 | ||
1841 | v = inb(0xa1) << 8 | inb(0x21); | |
1842 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1843 | ||
1844 | v = inb(0xa0) << 8 | inb(0x20); | |
1845 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1846 | ||
54168ed7 IM |
1847 | outb(0x0b,0xa0); |
1848 | outb(0x0b,0x20); | |
1da177e4 | 1849 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1850 | outb(0x0a,0xa0); |
1851 | outb(0x0a,0x20); | |
1da177e4 LT |
1852 | |
1853 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1854 | ||
1855 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1856 | ||
1857 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1858 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1859 | } | |
1860 | ||
32f71aff MR |
1861 | __apicdebuginit(int) print_all_ICs(void) |
1862 | { | |
1863 | print_PIC(); | |
4797f6b0 YL |
1864 | |
1865 | /* don't print out if apic is not there */ | |
8312136f | 1866 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1867 | return 0; |
1868 | ||
32f71aff MR |
1869 | print_all_local_APICs(); |
1870 | print_IO_APIC(); | |
1871 | ||
1872 | return 0; | |
1873 | } | |
1874 | ||
1875 | fs_initcall(print_all_ICs); | |
1876 | ||
1da177e4 | 1877 | |
efa2559f YL |
1878 | /* Where if anywhere is the i8259 connect in external int mode */ |
1879 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1880 | ||
54168ed7 | 1881 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1882 | { |
1883 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1884 | int i8259_apic, i8259_pin; |
54168ed7 | 1885 | int apic; |
1da177e4 LT |
1886 | unsigned long flags; |
1887 | ||
1da177e4 LT |
1888 | /* |
1889 | * The number of IO-APIC IRQ registers (== #pins): | |
1890 | */ | |
fcfd636a | 1891 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1892 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1893 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1894 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1895 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1896 | } | |
54168ed7 | 1897 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1898 | int pin; |
1899 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1900 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1901 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1902 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1903 | |
fcfd636a EB |
1904 | /* If the interrupt line is enabled and in ExtInt mode |
1905 | * I have found the pin where the i8259 is connected. | |
1906 | */ | |
1907 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1908 | ioapic_i8259.apic = apic; | |
1909 | ioapic_i8259.pin = pin; | |
1910 | goto found_i8259; | |
1911 | } | |
1912 | } | |
1913 | } | |
1914 | found_i8259: | |
1915 | /* Look to see what if the MP table has reported the ExtINT */ | |
1916 | /* If we could not find the appropriate pin by looking at the ioapic | |
1917 | * the i8259 probably is not connected the ioapic but give the | |
1918 | * mptable a chance anyway. | |
1919 | */ | |
1920 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1921 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1922 | /* Trust the MP table if nothing is setup in the hardware */ | |
1923 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1924 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1925 | ioapic_i8259.pin = i8259_pin; | |
1926 | ioapic_i8259.apic = i8259_apic; | |
1927 | } | |
1928 | /* Complain if the MP table and the hardware disagree */ | |
1929 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1930 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1931 | { | |
1932 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1933 | } |
1934 | ||
1935 | /* | |
1936 | * Do not trust the IO-APIC being empty at bootup | |
1937 | */ | |
1938 | clear_IO_APIC(); | |
1939 | } | |
1940 | ||
1941 | /* | |
1942 | * Not an __init, needed by the reboot code | |
1943 | */ | |
1944 | void disable_IO_APIC(void) | |
1945 | { | |
1946 | /* | |
1947 | * Clear the IO-APIC before rebooting: | |
1948 | */ | |
1949 | clear_IO_APIC(); | |
1950 | ||
650927ef | 1951 | /* |
0b968d23 | 1952 | * If the i8259 is routed through an IOAPIC |
650927ef | 1953 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1954 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1955 | * |
1956 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1957 | * as virtual wire B is little complex (need to configure both | |
1958 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1959 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1960 | */ |
7c6d9f97 | 1961 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1962 | struct IO_APIC_route_entry entry; |
650927ef EB |
1963 | |
1964 | memset(&entry, 0, sizeof(entry)); | |
1965 | entry.mask = 0; /* Enabled */ | |
1966 | entry.trigger = 0; /* Edge */ | |
1967 | entry.irr = 0; | |
1968 | entry.polarity = 0; /* High */ | |
1969 | entry.delivery_status = 0; | |
1970 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1971 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1972 | entry.vector = 0; |
54168ed7 | 1973 | entry.dest = read_apic_id(); |
650927ef EB |
1974 | |
1975 | /* | |
1976 | * Add it to the IO-APIC irq-routing table: | |
1977 | */ | |
cf4c6a2f | 1978 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1979 | } |
54168ed7 | 1980 | |
7c6d9f97 SS |
1981 | /* |
1982 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1983 | */ | |
8312136f | 1984 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1985 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1986 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1987 | } |
1988 | ||
54168ed7 | 1989 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1990 | /* |
1991 | * function to set the IO-APIC physical IDs based on the | |
1992 | * values stored in the MPC table. | |
1993 | * | |
1994 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1995 | */ | |
1996 | ||
1da177e4 LT |
1997 | static void __init setup_ioapic_ids_from_mpc(void) |
1998 | { | |
1999 | union IO_APIC_reg_00 reg_00; | |
2000 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2001 | int apic_id; |
1da177e4 LT |
2002 | int i; |
2003 | unsigned char old_id; | |
2004 | unsigned long flags; | |
2005 | ||
a4dbc34d | 2006 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2007 | return; |
d49c4288 | 2008 | |
ca05fea6 NP |
2009 | /* |
2010 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2011 | * no meaning without the serial APIC bus. | |
2012 | */ | |
7c5c1e42 SL |
2013 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2014 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2015 | return; |
1da177e4 LT |
2016 | /* |
2017 | * This is broken; anything with a real cpu count has to | |
2018 | * circumvent this idiocy regardless. | |
2019 | */ | |
d190cb87 | 2020 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
2021 | |
2022 | /* | |
2023 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2024 | */ | |
c8d46cf0 | 2025 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2026 | |
2027 | /* Read the register 0 value */ | |
2028 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2029 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2030 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2031 | |
c8d46cf0 | 2032 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2033 | |
c8d46cf0 | 2034 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2035 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2036 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2037 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2038 | reg_00.bits.ID); | |
c8d46cf0 | 2039 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2040 | } |
2041 | ||
1da177e4 LT |
2042 | /* |
2043 | * Sanity check, is the ID really free? Every APIC in a | |
2044 | * system must have a unique ID or we get lots of nice | |
2045 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2046 | */ | |
d1d7cae8 | 2047 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2048 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2049 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2050 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2051 | for (i = 0; i < get_physical_broadcast(); i++) |
2052 | if (!physid_isset(i, phys_id_present_map)) | |
2053 | break; | |
2054 | if (i >= get_physical_broadcast()) | |
2055 | panic("Max APIC ID exceeded!\n"); | |
2056 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2057 | i); | |
2058 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2059 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2060 | } else { |
2061 | physid_mask_t tmp; | |
8058714a | 2062 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2063 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2064 | "phys_id_present_map\n", | |
c8d46cf0 | 2065 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2066 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2067 | } | |
2068 | ||
2069 | ||
2070 | /* | |
2071 | * We need to adjust the IRQ routing table | |
2072 | * if the ID changed. | |
2073 | */ | |
c8d46cf0 | 2074 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2075 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2076 | if (mp_irqs[i].dstapic == old_id) |
2077 | mp_irqs[i].dstapic | |
c8d46cf0 | 2078 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2079 | |
2080 | /* | |
2081 | * Read the right value from the MPC table and | |
2082 | * write it into the ID register. | |
36062448 | 2083 | */ |
1da177e4 LT |
2084 | apic_printk(APIC_VERBOSE, KERN_INFO |
2085 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2086 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2087 | |
c8d46cf0 | 2088 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2089 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2090 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2091 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2092 | |
2093 | /* | |
2094 | * Sanity check | |
2095 | */ | |
2096 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2097 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2098 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2099 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2100 | printk("could not set ID!\n"); |
2101 | else | |
2102 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2103 | } | |
2104 | } | |
54168ed7 | 2105 | #endif |
1da177e4 | 2106 | |
7ce0bcfd | 2107 | int no_timer_check __initdata; |
8542b200 ZA |
2108 | |
2109 | static int __init notimercheck(char *s) | |
2110 | { | |
2111 | no_timer_check = 1; | |
2112 | return 1; | |
2113 | } | |
2114 | __setup("no_timer_check", notimercheck); | |
2115 | ||
1da177e4 LT |
2116 | /* |
2117 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2118 | * about the timer IRQ. We do the following to work around the situation: | |
2119 | * | |
2120 | * - timer IRQ defaults to IO-APIC IRQ | |
2121 | * - if this function detects that timer IRQs are defunct, then we fall | |
2122 | * back to ISA timer IRQs | |
2123 | */ | |
f0a7a5c9 | 2124 | static int __init timer_irq_works(void) |
1da177e4 LT |
2125 | { |
2126 | unsigned long t1 = jiffies; | |
4aae0702 | 2127 | unsigned long flags; |
1da177e4 | 2128 | |
8542b200 ZA |
2129 | if (no_timer_check) |
2130 | return 1; | |
2131 | ||
4aae0702 | 2132 | local_save_flags(flags); |
1da177e4 LT |
2133 | local_irq_enable(); |
2134 | /* Let ten ticks pass... */ | |
2135 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2136 | local_irq_restore(flags); |
1da177e4 LT |
2137 | |
2138 | /* | |
2139 | * Expect a few ticks at least, to be sure some possible | |
2140 | * glue logic does not lock up after one or two first | |
2141 | * ticks in a non-ExtINT mode. Also the local APIC | |
2142 | * might have cached one ExtINT interrupt. Finally, at | |
2143 | * least one tick may be lost due to delays. | |
2144 | */ | |
54168ed7 IM |
2145 | |
2146 | /* jiffies wrap? */ | |
1d16b53e | 2147 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2148 | return 1; |
1da177e4 LT |
2149 | return 0; |
2150 | } | |
2151 | ||
2152 | /* | |
2153 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2154 | * number of pending IRQ events unhandled. These cases are very rare, | |
2155 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2156 | * better to do it this way as thus we do not have to be aware of | |
2157 | * 'pending' interrupts in the IRQ path, except at this point. | |
2158 | */ | |
2159 | /* | |
2160 | * Edge triggered needs to resend any interrupt | |
2161 | * that was delayed but this is now handled in the device | |
2162 | * independent code. | |
2163 | */ | |
2164 | ||
2165 | /* | |
2166 | * Starting up a edge-triggered IO-APIC interrupt is | |
2167 | * nasty - we need to make sure that we get the edge. | |
2168 | * If it is already asserted for some reason, we need | |
2169 | * return 1 to indicate that is was pending. | |
2170 | * | |
2171 | * This is not complete - we should be able to fake | |
2172 | * an edge even if it isn't on the 8259A... | |
2173 | */ | |
54168ed7 | 2174 | |
f5b9ed7a | 2175 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2176 | { |
2177 | int was_pending = 0; | |
2178 | unsigned long flags; | |
0b8f1efa | 2179 | struct irq_cfg *cfg; |
1da177e4 LT |
2180 | |
2181 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2182 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2183 | disable_8259A_irq(irq); |
2184 | if (i8259A_irq_pending(irq)) | |
2185 | was_pending = 1; | |
2186 | } | |
0b8f1efa | 2187 | cfg = irq_cfg(irq); |
3145e941 | 2188 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2189 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2190 | ||
2191 | return was_pending; | |
2192 | } | |
2193 | ||
ace80ab7 | 2194 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2195 | { |
54168ed7 IM |
2196 | |
2197 | struct irq_cfg *cfg = irq_cfg(irq); | |
2198 | unsigned long flags; | |
2199 | ||
2200 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2201 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2202 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2203 | |
2204 | return 1; | |
2205 | } | |
497c9a19 | 2206 | |
54168ed7 IM |
2207 | /* |
2208 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2209 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2210 | * handled with the level-triggered descriptor, but that one has slightly | |
2211 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2212 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2213 | * races. | |
2214 | */ | |
497c9a19 | 2215 | |
54168ed7 | 2216 | #ifdef CONFIG_SMP |
e85abf8f GH |
2217 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2218 | { | |
2219 | cpumask_var_t cleanup_mask; | |
2220 | ||
2221 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2222 | unsigned int i; | |
2223 | cfg->move_cleanup_count = 0; | |
2224 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2225 | cfg->move_cleanup_count++; | |
2226 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2227 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2228 | } else { | |
2229 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2230 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2231 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2232 | free_cpumask_var(cleanup_mask); | |
2233 | } | |
2234 | cfg->move_in_progress = 0; | |
2235 | } | |
2236 | ||
4420471f | 2237 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2238 | { |
2239 | int apic, pin; | |
2240 | struct irq_pin_list *entry; | |
2241 | u8 vector = cfg->vector; | |
2242 | ||
2977fb3f | 2243 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2244 | unsigned int reg; |
2245 | ||
e85abf8f GH |
2246 | apic = entry->apic; |
2247 | pin = entry->pin; | |
2248 | /* | |
2249 | * With interrupt-remapping, destination information comes | |
2250 | * from interrupt-remapping table entry. | |
2251 | */ | |
2252 | if (!irq_remapped(irq)) | |
2253 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2254 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2255 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2256 | reg |= vector; | |
2257 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2258 | } |
2259 | } | |
2260 | ||
4420471f IM |
2261 | static int |
2262 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2263 | ||
e85abf8f GH |
2264 | /* |
2265 | * Either sets desc->affinity to a valid value, and returns | |
2266 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2267 | * leaves desc->affinity untouched. | |
2268 | */ | |
2269 | static unsigned int | |
2270 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2271 | { | |
2272 | struct irq_cfg *cfg; | |
2273 | unsigned int irq; | |
2274 | ||
2275 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2276 | return BAD_APICID; | |
2277 | ||
2278 | irq = desc->irq; | |
2279 | cfg = desc->chip_data; | |
2280 | if (assign_irq_vector(irq, cfg, mask)) | |
2281 | return BAD_APICID; | |
2282 | ||
e85abf8f GH |
2283 | cpumask_copy(desc->affinity, mask); |
2284 | ||
2285 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2286 | } | |
2287 | ||
4420471f | 2288 | static int |
e85abf8f GH |
2289 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2290 | { | |
2291 | struct irq_cfg *cfg; | |
2292 | unsigned long flags; | |
2293 | unsigned int dest; | |
2294 | unsigned int irq; | |
4420471f | 2295 | int ret = -1; |
e85abf8f GH |
2296 | |
2297 | irq = desc->irq; | |
2298 | cfg = desc->chip_data; | |
2299 | ||
2300 | spin_lock_irqsave(&ioapic_lock, flags); | |
2301 | dest = set_desc_affinity(desc, mask); | |
2302 | if (dest != BAD_APICID) { | |
2303 | /* Only the high 8 bits are valid. */ | |
2304 | dest = SET_APIC_LOGICAL_ID(dest); | |
2305 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2306 | ret = 0; |
e85abf8f GH |
2307 | } |
2308 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2309 | |
2310 | return ret; | |
e85abf8f GH |
2311 | } |
2312 | ||
4420471f | 2313 | static int |
e85abf8f GH |
2314 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2315 | { | |
2316 | struct irq_desc *desc; | |
2317 | ||
2318 | desc = irq_to_desc(irq); | |
2319 | ||
4420471f | 2320 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2321 | } |
497c9a19 | 2322 | |
54168ed7 | 2323 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2324 | |
54168ed7 IM |
2325 | /* |
2326 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2327 | * | |
0280f7c4 SS |
2328 | * For both level and edge triggered, irq migration is a simple atomic |
2329 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2330 | * |
0280f7c4 SS |
2331 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2332 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2333 | * Real vector that is used for interrupting cpu will be coming from | |
2334 | * the interrupt-remapping table entry. | |
54168ed7 | 2335 | */ |
d5dedd45 | 2336 | static int |
e7986739 | 2337 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2338 | { |
54168ed7 | 2339 | struct irq_cfg *cfg; |
54168ed7 | 2340 | struct irte irte; |
54168ed7 | 2341 | unsigned int dest; |
3145e941 | 2342 | unsigned int irq; |
d5dedd45 | 2343 | int ret = -1; |
497c9a19 | 2344 | |
22f65d31 | 2345 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2346 | return ret; |
497c9a19 | 2347 | |
3145e941 | 2348 | irq = desc->irq; |
54168ed7 | 2349 | if (get_irte(irq, &irte)) |
d5dedd45 | 2350 | return ret; |
497c9a19 | 2351 | |
3145e941 YL |
2352 | cfg = desc->chip_data; |
2353 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2354 | return ret; |
54168ed7 | 2355 | |
debccb3e | 2356 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2357 | |
54168ed7 IM |
2358 | irte.vector = cfg->vector; |
2359 | irte.dest_id = IRTE_DEST(dest); | |
2360 | ||
2361 | /* | |
2362 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2363 | */ | |
2364 | modify_irte(irq, &irte); | |
2365 | ||
22f65d31 MT |
2366 | if (cfg->move_in_progress) |
2367 | send_cleanup_vector(cfg); | |
54168ed7 | 2368 | |
7f7ace0c | 2369 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2370 | |
2371 | return 0; | |
54168ed7 IM |
2372 | } |
2373 | ||
54168ed7 IM |
2374 | /* |
2375 | * Migrates the IRQ destination in the process context. | |
2376 | */ | |
d5dedd45 | 2377 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2378 | const struct cpumask *mask) |
54168ed7 | 2379 | { |
d5dedd45 | 2380 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2381 | } |
d5dedd45 | 2382 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2383 | const struct cpumask *mask) |
3145e941 YL |
2384 | { |
2385 | struct irq_desc *desc = irq_to_desc(irq); | |
2386 | ||
d5dedd45 | 2387 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2388 | } |
29b61be6 | 2389 | #else |
d5dedd45 | 2390 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2391 | const struct cpumask *mask) |
2392 | { | |
d5dedd45 | 2393 | return 0; |
29b61be6 | 2394 | } |
54168ed7 IM |
2395 | #endif |
2396 | ||
2397 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2398 | { | |
2399 | unsigned vector, me; | |
8f2466f4 | 2400 | |
54168ed7 | 2401 | ack_APIC_irq(); |
54168ed7 | 2402 | exit_idle(); |
54168ed7 IM |
2403 | irq_enter(); |
2404 | ||
2405 | me = smp_processor_id(); | |
2406 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2407 | unsigned int irq; | |
68a8ca59 | 2408 | unsigned int irr; |
54168ed7 IM |
2409 | struct irq_desc *desc; |
2410 | struct irq_cfg *cfg; | |
2411 | irq = __get_cpu_var(vector_irq)[vector]; | |
2412 | ||
0b8f1efa YL |
2413 | if (irq == -1) |
2414 | continue; | |
2415 | ||
54168ed7 IM |
2416 | desc = irq_to_desc(irq); |
2417 | if (!desc) | |
2418 | continue; | |
2419 | ||
2420 | cfg = irq_cfg(irq); | |
2421 | spin_lock(&desc->lock); | |
2422 | if (!cfg->move_cleanup_count) | |
2423 | goto unlock; | |
2424 | ||
22f65d31 | 2425 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2426 | goto unlock; |
2427 | ||
68a8ca59 SS |
2428 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2429 | /* | |
2430 | * Check if the vector that needs to be cleanedup is | |
2431 | * registered at the cpu's IRR. If so, then this is not | |
2432 | * the best time to clean it up. Lets clean it up in the | |
2433 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2434 | * to myself. | |
2435 | */ | |
2436 | if (irr & (1 << (vector % 32))) { | |
2437 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2438 | goto unlock; | |
2439 | } | |
54168ed7 IM |
2440 | __get_cpu_var(vector_irq)[vector] = -1; |
2441 | cfg->move_cleanup_count--; | |
2442 | unlock: | |
2443 | spin_unlock(&desc->lock); | |
2444 | } | |
2445 | ||
2446 | irq_exit(); | |
2447 | } | |
2448 | ||
3145e941 | 2449 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2450 | { |
3145e941 YL |
2451 | struct irq_desc *desc = *descp; |
2452 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2453 | unsigned vector, me; |
2454 | ||
fcef5911 | 2455 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2456 | return; |
2457 | ||
2458 | vector = ~get_irq_regs()->orig_ax; | |
2459 | me = smp_processor_id(); | |
10b888d6 | 2460 | |
fcef5911 | 2461 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2462 | send_cleanup_vector(cfg); |
497c9a19 YL |
2463 | } |
2464 | #else | |
3145e941 | 2465 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2466 | #endif |
3145e941 | 2467 | |
1d025192 YL |
2468 | static void ack_apic_edge(unsigned int irq) |
2469 | { | |
3145e941 YL |
2470 | struct irq_desc *desc = irq_to_desc(irq); |
2471 | ||
2472 | irq_complete_move(&desc); | |
1d025192 YL |
2473 | move_native_irq(irq); |
2474 | ack_APIC_irq(); | |
2475 | } | |
2476 | ||
3eb2cce8 | 2477 | atomic_t irq_mis_count; |
3eb2cce8 | 2478 | |
047c8fdb YL |
2479 | static void ack_apic_level(unsigned int irq) |
2480 | { | |
3145e941 | 2481 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2482 | unsigned long v; |
2483 | int i; | |
3145e941 | 2484 | struct irq_cfg *cfg; |
54168ed7 | 2485 | int do_unmask_irq = 0; |
047c8fdb | 2486 | |
3145e941 | 2487 | irq_complete_move(&desc); |
047c8fdb | 2488 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2489 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2490 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2491 | do_unmask_irq = 1; |
3145e941 | 2492 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2493 | } |
047c8fdb YL |
2494 | #endif |
2495 | ||
3eb2cce8 | 2496 | /* |
916a0fe7 JF |
2497 | * It appears there is an erratum which affects at least version 0x11 |
2498 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2499 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2500 | * erroneously delivered as edge-triggered one but the respective IRR | |
2501 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2502 | * message but it will never arrive and further interrupts are blocked | |
2503 | * from the source. The exact reason is so far unknown, but the | |
2504 | * phenomenon was observed when two consecutive interrupt requests | |
2505 | * from a given source get delivered to the same CPU and the source is | |
2506 | * temporarily disabled in between. | |
2507 | * | |
2508 | * A workaround is to simulate an EOI message manually. We achieve it | |
2509 | * by setting the trigger mode to edge and then to level when the edge | |
2510 | * trigger mode gets detected in the TMR of a local APIC for a | |
2511 | * level-triggered interrupt. We mask the source for the time of the | |
2512 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2513 | * The idea is from Manfred Spraul. --macro | |
2514 | */ | |
3145e941 YL |
2515 | cfg = desc->chip_data; |
2516 | i = cfg->vector; | |
3eb2cce8 | 2517 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2518 | |
54168ed7 IM |
2519 | /* |
2520 | * We must acknowledge the irq before we move it or the acknowledge will | |
2521 | * not propagate properly. | |
2522 | */ | |
2523 | ack_APIC_irq(); | |
2524 | ||
2525 | /* Now we can move and renable the irq */ | |
2526 | if (unlikely(do_unmask_irq)) { | |
2527 | /* Only migrate the irq if the ack has been received. | |
2528 | * | |
2529 | * On rare occasions the broadcast level triggered ack gets | |
2530 | * delayed going to ioapics, and if we reprogram the | |
2531 | * vector while Remote IRR is still set the irq will never | |
2532 | * fire again. | |
2533 | * | |
2534 | * To prevent this scenario we read the Remote IRR bit | |
2535 | * of the ioapic. This has two effects. | |
2536 | * - On any sane system the read of the ioapic will | |
2537 | * flush writes (and acks) going to the ioapic from | |
2538 | * this cpu. | |
2539 | * - We get to see if the ACK has actually been delivered. | |
2540 | * | |
2541 | * Based on failed experiments of reprogramming the | |
2542 | * ioapic entry from outside of irq context starting | |
2543 | * with masking the ioapic entry and then polling until | |
2544 | * Remote IRR was clear before reprogramming the | |
2545 | * ioapic I don't trust the Remote IRR bit to be | |
2546 | * completey accurate. | |
2547 | * | |
2548 | * However there appears to be no other way to plug | |
2549 | * this race, so if the Remote IRR bit is not | |
2550 | * accurate and is causing problems then it is a hardware bug | |
2551 | * and you can go talk to the chipset vendor about it. | |
2552 | */ | |
3145e941 YL |
2553 | cfg = desc->chip_data; |
2554 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2555 | move_masked_irq(irq); |
3145e941 | 2556 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2557 | } |
1d025192 | 2558 | |
916a0fe7 | 2559 | /* Tail end of version 0x11 I/O APIC bug workaround */ |
1d025192 YL |
2560 | if (!(v & (1 << (i & 0x1f)))) { |
2561 | atomic_inc(&irq_mis_count); | |
2562 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2563 | __mask_and_edge_IO_APIC_irq(cfg); |
2564 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2565 | spin_unlock(&ioapic_lock); |
2566 | } | |
3eb2cce8 | 2567 | } |
1d025192 | 2568 | |
d0b03bd1 | 2569 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2570 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2571 | { | |
25629d81 SS |
2572 | struct irq_pin_list *entry; |
2573 | ||
2977fb3f CG |
2574 | for_each_irq_pin(entry, cfg->irq_2_pin) |
2575 | io_apic_eoi(entry->apic, entry->pin); | |
25629d81 SS |
2576 | } |
2577 | ||
2578 | static void | |
2579 | eoi_ioapic_irq(struct irq_desc *desc) | |
2580 | { | |
2581 | struct irq_cfg *cfg; | |
2582 | unsigned long flags; | |
2583 | unsigned int irq; | |
2584 | ||
2585 | irq = desc->irq; | |
2586 | cfg = desc->chip_data; | |
2587 | ||
2588 | spin_lock_irqsave(&ioapic_lock, flags); | |
2589 | __eoi_ioapic_irq(irq, cfg); | |
2590 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2591 | } | |
2592 | ||
d0b03bd1 HW |
2593 | static void ir_ack_apic_edge(unsigned int irq) |
2594 | { | |
5d0ae2db | 2595 | ack_APIC_irq(); |
d0b03bd1 HW |
2596 | } |
2597 | ||
2598 | static void ir_ack_apic_level(unsigned int irq) | |
2599 | { | |
5d0ae2db WH |
2600 | struct irq_desc *desc = irq_to_desc(irq); |
2601 | ||
2602 | ack_APIC_irq(); | |
2603 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2604 | } |
2605 | #endif /* CONFIG_INTR_REMAP */ | |
2606 | ||
f5b9ed7a | 2607 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2608 | .name = "IO-APIC", |
2609 | .startup = startup_ioapic_irq, | |
2610 | .mask = mask_IO_APIC_irq, | |
2611 | .unmask = unmask_IO_APIC_irq, | |
2612 | .ack = ack_apic_edge, | |
2613 | .eoi = ack_apic_level, | |
54d5d424 | 2614 | #ifdef CONFIG_SMP |
d6c88a50 | 2615 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2616 | #endif |
ace80ab7 | 2617 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2618 | }; |
2619 | ||
54168ed7 | 2620 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2621 | .name = "IR-IO-APIC", |
2622 | .startup = startup_ioapic_irq, | |
2623 | .mask = mask_IO_APIC_irq, | |
2624 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2625 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2626 | .ack = ir_ack_apic_edge, |
2627 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2628 | #ifdef CONFIG_SMP |
d6c88a50 | 2629 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2630 | #endif |
54168ed7 IM |
2631 | #endif |
2632 | .retrigger = ioapic_retrigger_irq, | |
2633 | }; | |
1da177e4 LT |
2634 | |
2635 | static inline void init_IO_APIC_traps(void) | |
2636 | { | |
2637 | int irq; | |
08678b08 | 2638 | struct irq_desc *desc; |
da51a821 | 2639 | struct irq_cfg *cfg; |
1da177e4 LT |
2640 | |
2641 | /* | |
2642 | * NOTE! The local APIC isn't very good at handling | |
2643 | * multiple interrupts at the same interrupt level. | |
2644 | * As the interrupt level is determined by taking the | |
2645 | * vector number and shifting that right by 4, we | |
2646 | * want to spread these out a bit so that they don't | |
2647 | * all fall in the same interrupt level. | |
2648 | * | |
2649 | * Also, we've got to be careful not to trash gate | |
2650 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2651 | */ | |
0b8f1efa | 2652 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2653 | cfg = desc->chip_data; |
2654 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2655 | /* |
2656 | * Hmm.. We don't have an entry for this, | |
2657 | * so default to an old-fashioned 8259 | |
2658 | * interrupt if we can.. | |
2659 | */ | |
99d093d1 | 2660 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2661 | make_8259A_irq(irq); |
0b8f1efa | 2662 | else |
1da177e4 | 2663 | /* Strange. Oh, well.. */ |
08678b08 | 2664 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2665 | } |
2666 | } | |
2667 | } | |
2668 | ||
f5b9ed7a IM |
2669 | /* |
2670 | * The local APIC irq-chip implementation: | |
2671 | */ | |
1da177e4 | 2672 | |
36062448 | 2673 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2674 | { |
2675 | unsigned long v; | |
2676 | ||
2677 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2678 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2679 | } |
2680 | ||
36062448 | 2681 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2682 | { |
f5b9ed7a | 2683 | unsigned long v; |
1da177e4 | 2684 | |
f5b9ed7a | 2685 | v = apic_read(APIC_LVT0); |
593f4a78 | 2686 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2687 | } |
1da177e4 | 2688 | |
3145e941 | 2689 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2690 | { |
2691 | ack_APIC_irq(); | |
2692 | } | |
2693 | ||
f5b9ed7a | 2694 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2695 | .name = "local-APIC", |
f5b9ed7a IM |
2696 | .mask = mask_lapic_irq, |
2697 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2698 | .ack = ack_lapic_irq, |
1da177e4 LT |
2699 | }; |
2700 | ||
3145e941 | 2701 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2702 | { |
08678b08 | 2703 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2704 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2705 | "edge"); | |
c88ac1df MR |
2706 | } |
2707 | ||
e9427101 | 2708 | static void __init setup_nmi(void) |
1da177e4 LT |
2709 | { |
2710 | /* | |
36062448 | 2711 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2712 | * We put the 8259A master into AEOI mode and |
2713 | * unmask on all local APICs LVT0 as NMI. | |
2714 | * | |
2715 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2716 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2717 | * the NMI handler or the timer interrupt. | |
36062448 | 2718 | */ |
1da177e4 LT |
2719 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2720 | ||
e9427101 | 2721 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2722 | |
2723 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2724 | } | |
2725 | ||
2726 | /* | |
2727 | * This looks a bit hackish but it's about the only one way of sending | |
2728 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2729 | * not support the ExtINT mode, unfortunately. We need to send these | |
2730 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2731 | * 8259A interrupt line asserted until INTA. --macro | |
2732 | */ | |
28acf285 | 2733 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2734 | { |
fcfd636a | 2735 | int apic, pin, i; |
1da177e4 LT |
2736 | struct IO_APIC_route_entry entry0, entry1; |
2737 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2738 | |
fcfd636a | 2739 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2740 | if (pin == -1) { |
2741 | WARN_ON_ONCE(1); | |
2742 | return; | |
2743 | } | |
fcfd636a | 2744 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2745 | if (apic == -1) { |
2746 | WARN_ON_ONCE(1); | |
1da177e4 | 2747 | return; |
956fb531 | 2748 | } |
1da177e4 | 2749 | |
cf4c6a2f | 2750 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2751 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2752 | |
2753 | memset(&entry1, 0, sizeof(entry1)); | |
2754 | ||
2755 | entry1.dest_mode = 0; /* physical delivery */ | |
2756 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2757 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2758 | entry1.delivery_mode = dest_ExtINT; |
2759 | entry1.polarity = entry0.polarity; | |
2760 | entry1.trigger = 0; | |
2761 | entry1.vector = 0; | |
2762 | ||
cf4c6a2f | 2763 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2764 | |
2765 | save_control = CMOS_READ(RTC_CONTROL); | |
2766 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2767 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2768 | RTC_FREQ_SELECT); | |
2769 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2770 | ||
2771 | i = 100; | |
2772 | while (i-- > 0) { | |
2773 | mdelay(10); | |
2774 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2775 | i -= 10; | |
2776 | } | |
2777 | ||
2778 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2779 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2780 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2781 | |
cf4c6a2f | 2782 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2783 | } |
2784 | ||
efa2559f | 2785 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2786 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2787 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2788 | { |
2789 | disable_timer_pin_1 = 1; | |
2790 | return 0; | |
2791 | } | |
54168ed7 | 2792 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2793 | |
2794 | int timer_through_8259 __initdata; | |
2795 | ||
1da177e4 LT |
2796 | /* |
2797 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2798 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2799 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2800 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2801 | * |
2802 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2803 | */ |
8542b200 | 2804 | static inline void __init check_timer(void) |
1da177e4 | 2805 | { |
3145e941 YL |
2806 | struct irq_desc *desc = irq_to_desc(0); |
2807 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2808 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2809 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2810 | unsigned long flags; |
047c8fdb | 2811 | int no_pin1 = 0; |
4aae0702 IM |
2812 | |
2813 | local_irq_save(flags); | |
d4d25dec | 2814 | |
1da177e4 LT |
2815 | /* |
2816 | * get/set the timer IRQ vector: | |
2817 | */ | |
2818 | disable_8259A_irq(0); | |
fe402e1f | 2819 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2820 | |
2821 | /* | |
d11d5794 MR |
2822 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2823 | * wire has to be disabled in the local APIC. Also | |
2824 | * timer interrupts need to be acknowledged manually in | |
2825 | * the 8259A for the i82489DX when using the NMI | |
2826 | * watchdog as that APIC treats NMIs as level-triggered. | |
2827 | * The AEOI mode will finish them in the 8259A | |
2828 | * automatically. | |
1da177e4 | 2829 | */ |
593f4a78 | 2830 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2831 | init_8259A(1); |
54168ed7 | 2832 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2833 | { |
2834 | unsigned int ver; | |
2835 | ||
2836 | ver = apic_read(APIC_LVR); | |
2837 | ver = GET_APIC_VERSION(ver); | |
2838 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2839 | } | |
54168ed7 | 2840 | #endif |
1da177e4 | 2841 | |
fcfd636a EB |
2842 | pin1 = find_isa_irq_pin(0, mp_INT); |
2843 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2844 | pin2 = ioapic_i8259.pin; | |
2845 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2846 | |
49a66a0b MR |
2847 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2848 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2849 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2850 | |
691874fa MR |
2851 | /* |
2852 | * Some BIOS writers are clueless and report the ExtINTA | |
2853 | * I/O APIC input from the cascaded 8259A as the timer | |
2854 | * interrupt input. So just in case, if only one pin | |
2855 | * was found above, try it both directly and through the | |
2856 | * 8259A. | |
2857 | */ | |
2858 | if (pin1 == -1) { | |
54168ed7 IM |
2859 | if (intr_remapping_enabled) |
2860 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2861 | pin1 = pin2; |
2862 | apic1 = apic2; | |
2863 | no_pin1 = 1; | |
2864 | } else if (pin2 == -1) { | |
2865 | pin2 = pin1; | |
2866 | apic2 = apic1; | |
2867 | } | |
2868 | ||
1da177e4 LT |
2869 | if (pin1 != -1) { |
2870 | /* | |
2871 | * Ok, does IRQ0 through the IOAPIC work? | |
2872 | */ | |
691874fa | 2873 | if (no_pin1) { |
85ac16d0 | 2874 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2875 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2876 | } else { |
2877 | /* for edge trigger, setup_IO_APIC_irq already | |
2878 | * leave it unmasked. | |
2879 | * so only need to unmask if it is level-trigger | |
2880 | * do we really have level trigger timer? | |
2881 | */ | |
2882 | int idx; | |
2883 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2884 | if (idx != -1 && irq_trigger(idx)) | |
2885 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2886 | } |
1da177e4 LT |
2887 | if (timer_irq_works()) { |
2888 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2889 | setup_nmi(); |
2890 | enable_8259A_irq(0); | |
1da177e4 | 2891 | } |
66759a01 CE |
2892 | if (disable_timer_pin_1 > 0) |
2893 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2894 | goto out; |
1da177e4 | 2895 | } |
54168ed7 IM |
2896 | if (intr_remapping_enabled) |
2897 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2898 | local_irq_disable(); |
fcfd636a | 2899 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2900 | if (!no_pin1) |
49a66a0b MR |
2901 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2902 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2903 | |
49a66a0b MR |
2904 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2905 | "(IRQ0) through the 8259A ...\n"); | |
2906 | apic_printk(APIC_QUIET, KERN_INFO | |
2907 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2908 | /* |
2909 | * legacy devices should be connected to IO APIC #0 | |
2910 | */ | |
85ac16d0 | 2911 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2912 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2913 | enable_8259A_irq(0); |
1da177e4 | 2914 | if (timer_irq_works()) { |
49a66a0b | 2915 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2916 | timer_through_8259 = 1; |
1da177e4 | 2917 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2918 | disable_8259A_irq(0); |
1da177e4 | 2919 | setup_nmi(); |
60134ebe | 2920 | enable_8259A_irq(0); |
1da177e4 | 2921 | } |
4aae0702 | 2922 | goto out; |
1da177e4 LT |
2923 | } |
2924 | /* | |
2925 | * Cleanup, just in case ... | |
2926 | */ | |
f72dccac | 2927 | local_irq_disable(); |
ecd29476 | 2928 | disable_8259A_irq(0); |
fcfd636a | 2929 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2930 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2931 | } |
1da177e4 LT |
2932 | |
2933 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2934 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2935 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2936 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2937 | } |
54168ed7 | 2938 | #ifdef CONFIG_X86_32 |
d11d5794 | 2939 | timer_ack = 0; |
54168ed7 | 2940 | #endif |
1da177e4 | 2941 | |
49a66a0b MR |
2942 | apic_printk(APIC_QUIET, KERN_INFO |
2943 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2944 | |
3145e941 | 2945 | lapic_register_intr(0, desc); |
497c9a19 | 2946 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2947 | enable_8259A_irq(0); |
2948 | ||
2949 | if (timer_irq_works()) { | |
49a66a0b | 2950 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2951 | goto out; |
1da177e4 | 2952 | } |
f72dccac | 2953 | local_irq_disable(); |
e67465f1 | 2954 | disable_8259A_irq(0); |
497c9a19 | 2955 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2956 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2957 | |
49a66a0b MR |
2958 | apic_printk(APIC_QUIET, KERN_INFO |
2959 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2960 | |
1da177e4 LT |
2961 | init_8259A(0); |
2962 | make_8259A_irq(0); | |
593f4a78 | 2963 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2964 | |
2965 | unlock_ExtINT_logic(); | |
2966 | ||
2967 | if (timer_irq_works()) { | |
49a66a0b | 2968 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2969 | goto out; |
1da177e4 | 2970 | } |
f72dccac | 2971 | local_irq_disable(); |
49a66a0b | 2972 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2973 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2974 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2975 | out: |
2976 | local_irq_restore(flags); | |
1da177e4 LT |
2977 | } |
2978 | ||
2979 | /* | |
af174783 MR |
2980 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2981 | * to devices. However there may be an I/O APIC pin available for | |
2982 | * this interrupt regardless. The pin may be left unconnected, but | |
2983 | * typically it will be reused as an ExtINT cascade interrupt for | |
2984 | * the master 8259A. In the MPS case such a pin will normally be | |
2985 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2986 | * there is no provision for ExtINT interrupts, and in the absence | |
2987 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2988 | * interrupt, that is edge-triggered and unmasked by default. We | |
2989 | * used to do this, but it caused problems on some systems because | |
2990 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2991 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2992 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2993 | * the I/O APIC in all cases now. No actual device should request | |
2994 | * it anyway. --macro | |
1da177e4 LT |
2995 | */ |
2996 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2997 | ||
2998 | void __init setup_IO_APIC(void) | |
2999 | { | |
54168ed7 | 3000 | |
54168ed7 IM |
3001 | /* |
3002 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3003 | */ | |
1da177e4 | 3004 | |
af174783 | 3005 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3006 | |
54168ed7 | 3007 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3008 | /* |
54168ed7 IM |
3009 | * Set up IO-APIC IRQ routing. |
3010 | */ | |
3011 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3012 | if (!acpi_ioapic) |
3013 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3014 | #endif |
1da177e4 LT |
3015 | sync_Arb_IDs(); |
3016 | setup_IO_APIC_irqs(); | |
3017 | init_IO_APIC_traps(); | |
1e4c85f9 | 3018 | check_timer(); |
1da177e4 LT |
3019 | } |
3020 | ||
3021 | /* | |
54168ed7 IM |
3022 | * Called after all the initialization is done. If we didnt find any |
3023 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3024 | */ |
36062448 | 3025 | |
1da177e4 LT |
3026 | static int __init io_apic_bug_finalize(void) |
3027 | { | |
d6c88a50 TG |
3028 | if (sis_apic_bug == -1) |
3029 | sis_apic_bug = 0; | |
3030 | return 0; | |
1da177e4 LT |
3031 | } |
3032 | ||
3033 | late_initcall(io_apic_bug_finalize); | |
3034 | ||
3035 | struct sysfs_ioapic_data { | |
3036 | struct sys_device dev; | |
3037 | struct IO_APIC_route_entry entry[0]; | |
3038 | }; | |
54168ed7 | 3039 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3040 | |
438510f6 | 3041 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3042 | { |
3043 | struct IO_APIC_route_entry *entry; | |
3044 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3045 | int i; |
36062448 | 3046 | |
1da177e4 LT |
3047 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3048 | entry = data->entry; | |
54168ed7 IM |
3049 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3050 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3051 | |
3052 | return 0; | |
3053 | } | |
3054 | ||
3055 | static int ioapic_resume(struct sys_device *dev) | |
3056 | { | |
3057 | struct IO_APIC_route_entry *entry; | |
3058 | struct sysfs_ioapic_data *data; | |
3059 | unsigned long flags; | |
3060 | union IO_APIC_reg_00 reg_00; | |
3061 | int i; | |
36062448 | 3062 | |
1da177e4 LT |
3063 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3064 | entry = data->entry; | |
3065 | ||
3066 | spin_lock_irqsave(&ioapic_lock, flags); | |
3067 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3068 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3069 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3070 | io_apic_write(dev->id, 0, reg_00.raw); |
3071 | } | |
1da177e4 | 3072 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3073 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3074 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3075 | |
3076 | return 0; | |
3077 | } | |
3078 | ||
3079 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3080 | .name = "ioapic", |
1da177e4 LT |
3081 | .suspend = ioapic_suspend, |
3082 | .resume = ioapic_resume, | |
3083 | }; | |
3084 | ||
3085 | static int __init ioapic_init_sysfs(void) | |
3086 | { | |
54168ed7 IM |
3087 | struct sys_device * dev; |
3088 | int i, size, error; | |
1da177e4 LT |
3089 | |
3090 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3091 | if (error) | |
3092 | return error; | |
3093 | ||
54168ed7 | 3094 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3095 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3096 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3097 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3098 | if (!mp_ioapic_data[i]) { |
3099 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3100 | continue; | |
3101 | } | |
1da177e4 | 3102 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3103 | dev->id = i; |
1da177e4 LT |
3104 | dev->cls = &ioapic_sysdev_class; |
3105 | error = sysdev_register(dev); | |
3106 | if (error) { | |
3107 | kfree(mp_ioapic_data[i]); | |
3108 | mp_ioapic_data[i] = NULL; | |
3109 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3110 | continue; | |
3111 | } | |
3112 | } | |
3113 | ||
3114 | return 0; | |
3115 | } | |
3116 | ||
3117 | device_initcall(ioapic_init_sysfs); | |
3118 | ||
abcaa2b8 | 3119 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3120 | /* |
95d77884 | 3121 | * Dynamic irq allocate and deallocation |
3fc471ed | 3122 | */ |
d047f53a | 3123 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3124 | { |
ace80ab7 | 3125 | /* Allocate an unused irq */ |
54168ed7 IM |
3126 | unsigned int irq; |
3127 | unsigned int new; | |
3fc471ed | 3128 | unsigned long flags; |
0b8f1efa | 3129 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3130 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3131 | |
3132 | irq = 0; | |
abcaa2b8 YL |
3133 | if (irq_want < nr_irqs_gsi) |
3134 | irq_want = nr_irqs_gsi; | |
3135 | ||
ace80ab7 | 3136 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3137 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3138 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3139 | if (!desc_new) { |
3140 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3141 | continue; |
0b8f1efa YL |
3142 | } |
3143 | cfg_new = desc_new->chip_data; | |
3144 | ||
3145 | if (cfg_new->vector != 0) | |
ace80ab7 | 3146 | continue; |
d047f53a | 3147 | |
15e957d0 | 3148 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3149 | |
fe402e1f | 3150 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3151 | irq = new; |
3152 | break; | |
3153 | } | |
3154 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3155 | |
199751d7 | 3156 | if (irq > 0) { |
3fc471ed | 3157 | dynamic_irq_init(irq); |
0b8f1efa YL |
3158 | /* restore it, in case dynamic_irq_init clear it */ |
3159 | if (desc_new) | |
3160 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3161 | } |
3162 | return irq; | |
3163 | } | |
3164 | ||
199751d7 YL |
3165 | int create_irq(void) |
3166 | { | |
d047f53a | 3167 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3168 | unsigned int irq_want; |
54168ed7 IM |
3169 | int irq; |
3170 | ||
be5d5350 | 3171 | irq_want = nr_irqs_gsi; |
d047f53a | 3172 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3173 | |
3174 | if (irq == 0) | |
3175 | irq = -1; | |
3176 | ||
3177 | return irq; | |
199751d7 YL |
3178 | } |
3179 | ||
3fc471ed EB |
3180 | void destroy_irq(unsigned int irq) |
3181 | { | |
3182 | unsigned long flags; | |
0b8f1efa YL |
3183 | struct irq_cfg *cfg; |
3184 | struct irq_desc *desc; | |
3fc471ed | 3185 | |
0b8f1efa YL |
3186 | /* store it, in case dynamic_irq_cleanup clear it */ |
3187 | desc = irq_to_desc(irq); | |
3188 | cfg = desc->chip_data; | |
3fc471ed | 3189 | dynamic_irq_cleanup(irq); |
0b8f1efa | 3190 | /* connect back irq_cfg */ |
25f6e89b | 3191 | desc->chip_data = cfg; |
3fc471ed | 3192 | |
54168ed7 | 3193 | free_irte(irq); |
3fc471ed | 3194 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3195 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3196 | spin_unlock_irqrestore(&vector_lock, flags); |
3197 | } | |
3fc471ed | 3198 | |
2d3fcc1c | 3199 | /* |
27b46d76 | 3200 | * MSI message composition |
2d3fcc1c EB |
3201 | */ |
3202 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3203 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3204 | { |
497c9a19 YL |
3205 | struct irq_cfg *cfg; |
3206 | int err; | |
2d3fcc1c EB |
3207 | unsigned dest; |
3208 | ||
f1182638 JB |
3209 | if (disable_apic) |
3210 | return -ENXIO; | |
3211 | ||
3145e941 | 3212 | cfg = irq_cfg(irq); |
fe402e1f | 3213 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3214 | if (err) |
3215 | return err; | |
2d3fcc1c | 3216 | |
debccb3e | 3217 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3218 | |
54168ed7 IM |
3219 | if (irq_remapped(irq)) { |
3220 | struct irte irte; | |
3221 | int ir_index; | |
3222 | u16 sub_handle; | |
3223 | ||
3224 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3225 | BUG_ON(ir_index == -1); | |
3226 | ||
3227 | memset (&irte, 0, sizeof(irte)); | |
3228 | ||
3229 | irte.present = 1; | |
9b5bc8dc | 3230 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3231 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3232 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3233 | irte.vector = cfg->vector; |
3234 | irte.dest_id = IRTE_DEST(dest); | |
3235 | ||
f007e99c WH |
3236 | /* Set source-id of interrupt request */ |
3237 | set_msi_sid(&irte, pdev); | |
3238 | ||
54168ed7 IM |
3239 | modify_irte(irq, &irte); |
3240 | ||
3241 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3242 | msg->data = sub_handle; | |
3243 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3244 | MSI_ADDR_IR_SHV | | |
3245 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3246 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3247 | } else { |
9d783ba0 SS |
3248 | if (x2apic_enabled()) |
3249 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3250 | MSI_ADDR_EXT_DEST_ID(dest); | |
3251 | else | |
3252 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3253 | ||
54168ed7 IM |
3254 | msg->address_lo = |
3255 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3256 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3257 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3258 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3259 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3260 | MSI_ADDR_REDIRECTION_CPU: |
3261 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3262 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3263 | |
54168ed7 IM |
3264 | msg->data = |
3265 | MSI_DATA_TRIGGER_EDGE | | |
3266 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3267 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3268 | MSI_DATA_DELIVERY_FIXED: |
3269 | MSI_DATA_DELIVERY_LOWPRI) | | |
3270 | MSI_DATA_VECTOR(cfg->vector); | |
3271 | } | |
497c9a19 | 3272 | return err; |
2d3fcc1c EB |
3273 | } |
3274 | ||
3b7d1921 | 3275 | #ifdef CONFIG_SMP |
d5dedd45 | 3276 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3277 | { |
3145e941 | 3278 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3279 | struct irq_cfg *cfg; |
3b7d1921 EB |
3280 | struct msi_msg msg; |
3281 | unsigned int dest; | |
3b7d1921 | 3282 | |
22f65d31 MT |
3283 | dest = set_desc_affinity(desc, mask); |
3284 | if (dest == BAD_APICID) | |
d5dedd45 | 3285 | return -1; |
2d3fcc1c | 3286 | |
3145e941 | 3287 | cfg = desc->chip_data; |
2d3fcc1c | 3288 | |
3145e941 | 3289 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3290 | |
3291 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3292 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3293 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3294 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3295 | ||
3145e941 | 3296 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3297 | |
3298 | return 0; | |
2d3fcc1c | 3299 | } |
54168ed7 IM |
3300 | #ifdef CONFIG_INTR_REMAP |
3301 | /* | |
3302 | * Migrate the MSI irq to another cpumask. This migration is | |
3303 | * done in the process context using interrupt-remapping hardware. | |
3304 | */ | |
d5dedd45 | 3305 | static int |
e7986739 | 3306 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3307 | { |
3145e941 | 3308 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3309 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3310 | unsigned int dest; |
54168ed7 | 3311 | struct irte irte; |
54168ed7 IM |
3312 | |
3313 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3314 | return -1; |
54168ed7 | 3315 | |
22f65d31 MT |
3316 | dest = set_desc_affinity(desc, mask); |
3317 | if (dest == BAD_APICID) | |
d5dedd45 | 3318 | return -1; |
54168ed7 | 3319 | |
54168ed7 IM |
3320 | irte.vector = cfg->vector; |
3321 | irte.dest_id = IRTE_DEST(dest); | |
3322 | ||
3323 | /* | |
3324 | * atomically update the IRTE with the new destination and vector. | |
3325 | */ | |
3326 | modify_irte(irq, &irte); | |
3327 | ||
3328 | /* | |
3329 | * After this point, all the interrupts will start arriving | |
3330 | * at the new destination. So, time to cleanup the previous | |
3331 | * vector allocation. | |
3332 | */ | |
22f65d31 MT |
3333 | if (cfg->move_in_progress) |
3334 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3335 | |
3336 | return 0; | |
54168ed7 | 3337 | } |
3145e941 | 3338 | |
54168ed7 | 3339 | #endif |
3b7d1921 | 3340 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3341 | |
3b7d1921 EB |
3342 | /* |
3343 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3344 | * which implement the MSI or MSI-X Capability Structure. | |
3345 | */ | |
3346 | static struct irq_chip msi_chip = { | |
3347 | .name = "PCI-MSI", | |
3348 | .unmask = unmask_msi_irq, | |
3349 | .mask = mask_msi_irq, | |
1d025192 | 3350 | .ack = ack_apic_edge, |
3b7d1921 EB |
3351 | #ifdef CONFIG_SMP |
3352 | .set_affinity = set_msi_irq_affinity, | |
3353 | #endif | |
3354 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3355 | }; |
3356 | ||
54168ed7 IM |
3357 | static struct irq_chip msi_ir_chip = { |
3358 | .name = "IR-PCI-MSI", | |
3359 | .unmask = unmask_msi_irq, | |
3360 | .mask = mask_msi_irq, | |
a1e38ca5 | 3361 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3362 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3363 | #ifdef CONFIG_SMP |
3364 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3365 | #endif |
54168ed7 IM |
3366 | #endif |
3367 | .retrigger = ioapic_retrigger_irq, | |
3368 | }; | |
3369 | ||
3370 | /* | |
3371 | * Map the PCI dev to the corresponding remapping hardware unit | |
3372 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3373 | * in it. | |
3374 | */ | |
3375 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3376 | { | |
3377 | struct intel_iommu *iommu; | |
3378 | int index; | |
3379 | ||
3380 | iommu = map_dev_to_ir(dev); | |
3381 | if (!iommu) { | |
3382 | printk(KERN_ERR | |
3383 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3384 | return -ENOENT; | |
3385 | } | |
3386 | ||
3387 | index = alloc_irte(iommu, irq, nvec); | |
3388 | if (index < 0) { | |
3389 | printk(KERN_ERR | |
3390 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3391 | pci_name(dev)); |
54168ed7 IM |
3392 | return -ENOSPC; |
3393 | } | |
3394 | return index; | |
3395 | } | |
1d025192 | 3396 | |
3145e941 | 3397 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3398 | { |
3399 | int ret; | |
3400 | struct msi_msg msg; | |
3401 | ||
3402 | ret = msi_compose_msg(dev, irq, &msg); | |
3403 | if (ret < 0) | |
3404 | return ret; | |
3405 | ||
3145e941 | 3406 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3407 | write_msi_msg(irq, &msg); |
3408 | ||
54168ed7 IM |
3409 | if (irq_remapped(irq)) { |
3410 | struct irq_desc *desc = irq_to_desc(irq); | |
3411 | /* | |
3412 | * irq migration in process context | |
3413 | */ | |
3414 | desc->status |= IRQ_MOVE_PCNTXT; | |
3415 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3416 | } else | |
54168ed7 | 3417 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3418 | |
c81bba49 YL |
3419 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3420 | ||
1d025192 YL |
3421 | return 0; |
3422 | } | |
3423 | ||
047c8fdb YL |
3424 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3425 | { | |
54168ed7 IM |
3426 | unsigned int irq; |
3427 | int ret, sub_handle; | |
0b8f1efa | 3428 | struct msi_desc *msidesc; |
54168ed7 | 3429 | unsigned int irq_want; |
1cc18521 | 3430 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3431 | int index = 0; |
d047f53a | 3432 | int node; |
54168ed7 | 3433 | |
1c8d7b0a MW |
3434 | /* x86 doesn't support multiple MSI yet */ |
3435 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3436 | return 1; | |
3437 | ||
d047f53a | 3438 | node = dev_to_node(&dev->dev); |
be5d5350 | 3439 | irq_want = nr_irqs_gsi; |
54168ed7 | 3440 | sub_handle = 0; |
0b8f1efa | 3441 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3442 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3443 | if (irq == 0) |
3444 | return -1; | |
f1ee5548 | 3445 | irq_want = irq + 1; |
54168ed7 IM |
3446 | if (!intr_remapping_enabled) |
3447 | goto no_ir; | |
3448 | ||
3449 | if (!sub_handle) { | |
3450 | /* | |
3451 | * allocate the consecutive block of IRTE's | |
3452 | * for 'nvec' | |
3453 | */ | |
3454 | index = msi_alloc_irte(dev, irq, nvec); | |
3455 | if (index < 0) { | |
3456 | ret = index; | |
3457 | goto error; | |
3458 | } | |
3459 | } else { | |
3460 | iommu = map_dev_to_ir(dev); | |
3461 | if (!iommu) { | |
3462 | ret = -ENOENT; | |
3463 | goto error; | |
3464 | } | |
3465 | /* | |
3466 | * setup the mapping between the irq and the IRTE | |
3467 | * base index, the sub_handle pointing to the | |
3468 | * appropriate interrupt remap table entry. | |
3469 | */ | |
3470 | set_irte_irq(irq, iommu, index, sub_handle); | |
3471 | } | |
3472 | no_ir: | |
0b8f1efa | 3473 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3474 | if (ret < 0) |
3475 | goto error; | |
3476 | sub_handle++; | |
3477 | } | |
3478 | return 0; | |
047c8fdb YL |
3479 | |
3480 | error: | |
54168ed7 IM |
3481 | destroy_irq(irq); |
3482 | return ret; | |
047c8fdb YL |
3483 | } |
3484 | ||
3b7d1921 EB |
3485 | void arch_teardown_msi_irq(unsigned int irq) |
3486 | { | |
f7feaca7 | 3487 | destroy_irq(irq); |
3b7d1921 EB |
3488 | } |
3489 | ||
9d783ba0 | 3490 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3491 | #ifdef CONFIG_SMP |
d5dedd45 | 3492 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3493 | { |
3145e941 | 3494 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3495 | struct irq_cfg *cfg; |
3496 | struct msi_msg msg; | |
3497 | unsigned int dest; | |
54168ed7 | 3498 | |
22f65d31 MT |
3499 | dest = set_desc_affinity(desc, mask); |
3500 | if (dest == BAD_APICID) | |
d5dedd45 | 3501 | return -1; |
54168ed7 | 3502 | |
3145e941 | 3503 | cfg = desc->chip_data; |
54168ed7 IM |
3504 | |
3505 | dmar_msi_read(irq, &msg); | |
3506 | ||
3507 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3508 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3509 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3510 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3511 | ||
3512 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3513 | |
3514 | return 0; | |
54168ed7 | 3515 | } |
3145e941 | 3516 | |
54168ed7 IM |
3517 | #endif /* CONFIG_SMP */ |
3518 | ||
8f7007aa | 3519 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3520 | .name = "DMAR_MSI", |
3521 | .unmask = dmar_msi_unmask, | |
3522 | .mask = dmar_msi_mask, | |
3523 | .ack = ack_apic_edge, | |
3524 | #ifdef CONFIG_SMP | |
3525 | .set_affinity = dmar_msi_set_affinity, | |
3526 | #endif | |
3527 | .retrigger = ioapic_retrigger_irq, | |
3528 | }; | |
3529 | ||
3530 | int arch_setup_dmar_msi(unsigned int irq) | |
3531 | { | |
3532 | int ret; | |
3533 | struct msi_msg msg; | |
2d3fcc1c | 3534 | |
54168ed7 IM |
3535 | ret = msi_compose_msg(NULL, irq, &msg); |
3536 | if (ret < 0) | |
3537 | return ret; | |
3538 | dmar_msi_write(irq, &msg); | |
3539 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3540 | "edge"); | |
3541 | return 0; | |
3542 | } | |
3543 | #endif | |
3544 | ||
58ac1e76 | 3545 | #ifdef CONFIG_HPET_TIMER |
3546 | ||
3547 | #ifdef CONFIG_SMP | |
d5dedd45 | 3548 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3549 | { |
3145e941 | 3550 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3551 | struct irq_cfg *cfg; |
58ac1e76 | 3552 | struct msi_msg msg; |
3553 | unsigned int dest; | |
58ac1e76 | 3554 | |
22f65d31 MT |
3555 | dest = set_desc_affinity(desc, mask); |
3556 | if (dest == BAD_APICID) | |
d5dedd45 | 3557 | return -1; |
58ac1e76 | 3558 | |
3145e941 | 3559 | cfg = desc->chip_data; |
58ac1e76 | 3560 | |
3561 | hpet_msi_read(irq, &msg); | |
3562 | ||
3563 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3564 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3565 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3566 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3567 | ||
3568 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3569 | |
3570 | return 0; | |
58ac1e76 | 3571 | } |
3145e941 | 3572 | |
58ac1e76 | 3573 | #endif /* CONFIG_SMP */ |
3574 | ||
1cc18521 | 3575 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3576 | .name = "HPET_MSI", |
3577 | .unmask = hpet_msi_unmask, | |
3578 | .mask = hpet_msi_mask, | |
3579 | .ack = ack_apic_edge, | |
3580 | #ifdef CONFIG_SMP | |
3581 | .set_affinity = hpet_msi_set_affinity, | |
3582 | #endif | |
3583 | .retrigger = ioapic_retrigger_irq, | |
3584 | }; | |
3585 | ||
3586 | int arch_setup_hpet_msi(unsigned int irq) | |
3587 | { | |
3588 | int ret; | |
3589 | struct msi_msg msg; | |
6ec3cfec | 3590 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3591 | |
3592 | ret = msi_compose_msg(NULL, irq, &msg); | |
3593 | if (ret < 0) | |
3594 | return ret; | |
3595 | ||
3596 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3597 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3598 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3599 | "edge"); | |
c81bba49 | 3600 | |
58ac1e76 | 3601 | return 0; |
3602 | } | |
3603 | #endif | |
3604 | ||
54168ed7 | 3605 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3606 | /* |
3607 | * Hypertransport interrupt support | |
3608 | */ | |
3609 | #ifdef CONFIG_HT_IRQ | |
3610 | ||
3611 | #ifdef CONFIG_SMP | |
3612 | ||
497c9a19 | 3613 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3614 | { |
ec68307c EB |
3615 | struct ht_irq_msg msg; |
3616 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3617 | |
497c9a19 | 3618 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3619 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3620 | |
497c9a19 | 3621 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3622 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3623 | |
ec68307c | 3624 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3625 | } |
3626 | ||
d5dedd45 | 3627 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3628 | { |
3145e941 | 3629 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3630 | struct irq_cfg *cfg; |
8b955b0d | 3631 | unsigned int dest; |
8b955b0d | 3632 | |
22f65d31 MT |
3633 | dest = set_desc_affinity(desc, mask); |
3634 | if (dest == BAD_APICID) | |
d5dedd45 | 3635 | return -1; |
8b955b0d | 3636 | |
3145e941 | 3637 | cfg = desc->chip_data; |
8b955b0d | 3638 | |
497c9a19 | 3639 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3640 | |
3641 | return 0; | |
8b955b0d | 3642 | } |
3145e941 | 3643 | |
8b955b0d EB |
3644 | #endif |
3645 | ||
c37e108d | 3646 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3647 | .name = "PCI-HT", |
3648 | .mask = mask_ht_irq, | |
3649 | .unmask = unmask_ht_irq, | |
1d025192 | 3650 | .ack = ack_apic_edge, |
8b955b0d EB |
3651 | #ifdef CONFIG_SMP |
3652 | .set_affinity = set_ht_irq_affinity, | |
3653 | #endif | |
3654 | .retrigger = ioapic_retrigger_irq, | |
3655 | }; | |
3656 | ||
3657 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3658 | { | |
497c9a19 YL |
3659 | struct irq_cfg *cfg; |
3660 | int err; | |
8b955b0d | 3661 | |
f1182638 JB |
3662 | if (disable_apic) |
3663 | return -ENXIO; | |
3664 | ||
3145e941 | 3665 | cfg = irq_cfg(irq); |
fe402e1f | 3666 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3667 | if (!err) { |
ec68307c | 3668 | struct ht_irq_msg msg; |
8b955b0d | 3669 | unsigned dest; |
8b955b0d | 3670 | |
debccb3e IM |
3671 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3672 | apic->target_cpus()); | |
8b955b0d | 3673 | |
ec68307c | 3674 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3675 | |
ec68307c EB |
3676 | msg.address_lo = |
3677 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3678 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3679 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3680 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3681 | HT_IRQ_LOW_DM_PHYSICAL : |
3682 | HT_IRQ_LOW_DM_LOGICAL) | | |
3683 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3684 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3685 | HT_IRQ_LOW_MT_FIXED : |
3686 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3687 | HT_IRQ_LOW_IRQ_MASKED; | |
3688 | ||
ec68307c | 3689 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3690 | |
a460e745 IM |
3691 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3692 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3693 | |
3694 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3695 | } |
497c9a19 | 3696 | return err; |
8b955b0d EB |
3697 | } |
3698 | #endif /* CONFIG_HT_IRQ */ | |
3699 | ||
03b48632 | 3700 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3701 | /* |
3702 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3703 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3704 | */ | |
3705 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3706 | unsigned long mmr_offset) | |
3707 | { | |
22f65d31 | 3708 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3709 | struct irq_cfg *cfg; |
3710 | int mmr_pnode; | |
3711 | unsigned long mmr_value; | |
3712 | struct uv_IO_APIC_route_entry *entry; | |
3713 | unsigned long flags; | |
3714 | int err; | |
3715 | ||
1cbac972 CG |
3716 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3717 | ||
3145e941 YL |
3718 | cfg = irq_cfg(irq); |
3719 | ||
e7986739 | 3720 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3721 | if (err != 0) |
3722 | return err; | |
3723 | ||
3724 | spin_lock_irqsave(&vector_lock, flags); | |
3725 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3726 | irq_name); | |
3727 | spin_unlock_irqrestore(&vector_lock, flags); | |
3728 | ||
4173a0e7 DN |
3729 | mmr_value = 0; |
3730 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
1cbac972 CG |
3731 | entry->vector = cfg->vector; |
3732 | entry->delivery_mode = apic->irq_delivery_mode; | |
3733 | entry->dest_mode = apic->irq_dest_mode; | |
3734 | entry->polarity = 0; | |
3735 | entry->trigger = 0; | |
3736 | entry->mask = 0; | |
3737 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | |
4173a0e7 DN |
3738 | |
3739 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3740 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3741 | ||
2a5ef416 JS |
3742 | if (cfg->move_in_progress) |
3743 | send_cleanup_vector(cfg); | |
3744 | ||
4173a0e7 DN |
3745 | return irq; |
3746 | } | |
3747 | ||
3748 | /* | |
3749 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3750 | * longer allowed to be sent. | |
3751 | */ | |
3752 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3753 | { | |
3754 | unsigned long mmr_value; | |
3755 | struct uv_IO_APIC_route_entry *entry; | |
3756 | int mmr_pnode; | |
3757 | ||
1cbac972 CG |
3758 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3759 | ||
4173a0e7 DN |
3760 | mmr_value = 0; |
3761 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
4173a0e7 DN |
3762 | entry->mask = 1; |
3763 | ||
3764 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3765 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3766 | } | |
3767 | #endif /* CONFIG_X86_64 */ | |
3768 | ||
9d6a4d08 YL |
3769 | int __init io_apic_get_redir_entries (int ioapic) |
3770 | { | |
3771 | union IO_APIC_reg_01 reg_01; | |
3772 | unsigned long flags; | |
3773 | ||
3774 | spin_lock_irqsave(&ioapic_lock, flags); | |
3775 | reg_01.raw = io_apic_read(ioapic, 1); | |
3776 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3777 | ||
3778 | return reg_01.bits.entries; | |
3779 | } | |
3780 | ||
be5d5350 | 3781 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3782 | { |
be5d5350 YL |
3783 | int nr = 0; |
3784 | ||
cc6c5006 YL |
3785 | nr = acpi_probe_gsi(); |
3786 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3787 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3788 | } else { |
3789 | /* for acpi=off or acpi is not compiled in */ | |
3790 | int idx; | |
3791 | ||
3792 | nr = 0; | |
3793 | for (idx = 0; idx < nr_ioapics; idx++) | |
3794 | nr += io_apic_get_redir_entries(idx) + 1; | |
3795 | ||
3796 | if (nr > nr_irqs_gsi) | |
3797 | nr_irqs_gsi = nr; | |
3798 | } | |
3799 | ||
3800 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3801 | } |
3802 | ||
4a046d17 YL |
3803 | #ifdef CONFIG_SPARSE_IRQ |
3804 | int __init arch_probe_nr_irqs(void) | |
3805 | { | |
3806 | int nr; | |
3807 | ||
f1ee5548 YL |
3808 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3809 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3810 | |
f1ee5548 YL |
3811 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3812 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3813 | /* | |
3814 | * for MSI and HT dyn irq | |
3815 | */ | |
3816 | nr += nr_irqs_gsi * 16; | |
3817 | #endif | |
3818 | if (nr < nr_irqs) | |
4a046d17 YL |
3819 | nr_irqs = nr; |
3820 | ||
3821 | return 0; | |
3822 | } | |
3823 | #endif | |
3824 | ||
e5198075 YL |
3825 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3826 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3827 | { |
3828 | struct irq_desc *desc; | |
3829 | struct irq_cfg *cfg; | |
3830 | int node; | |
e5198075 YL |
3831 | int ioapic, pin; |
3832 | int trigger, polarity; | |
5ef21837 | 3833 | |
e5198075 | 3834 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3835 | if (!IO_APIC_IRQ(irq)) { |
3836 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3837 | ioapic); | |
3838 | return -EINVAL; | |
3839 | } | |
3840 | ||
3841 | if (dev) | |
3842 | node = dev_to_node(dev); | |
3843 | else | |
3844 | node = cpu_to_node(boot_cpu_id); | |
3845 | ||
3846 | desc = irq_to_desc_alloc_node(irq, node); | |
3847 | if (!desc) { | |
3848 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3849 | return 0; | |
3850 | } | |
3851 | ||
e5198075 YL |
3852 | pin = irq_attr->ioapic_pin; |
3853 | trigger = irq_attr->trigger; | |
3854 | polarity = irq_attr->polarity; | |
3855 | ||
5ef21837 YL |
3856 | /* |
3857 | * IRQs < 16 are already in the irq_2_pin[] map | |
3858 | */ | |
3859 | if (irq >= NR_IRQS_LEGACY) { | |
3860 | cfg = desc->chip_data; | |
f3d1915a CG |
3861 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3862 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3863 | pin, irq); | |
3864 | return 0; | |
3865 | } | |
5ef21837 YL |
3866 | } |
3867 | ||
e5198075 | 3868 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3869 | |
3870 | return 0; | |
3871 | } | |
3872 | ||
e5198075 YL |
3873 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3874 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3875 | { |
e5198075 | 3876 | int ioapic, pin; |
5ef21837 YL |
3877 | /* |
3878 | * Avoid pin reprogramming. PRTs typically include entries | |
3879 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3880 | * we only program the IOAPIC on the first. | |
3881 | */ | |
e5198075 YL |
3882 | ioapic = irq_attr->ioapic; |
3883 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3884 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3885 | pr_debug("Pin %d-%d already programmed\n", | |
3886 | mp_ioapics[ioapic].apicid, pin); | |
3887 | return 0; | |
3888 | } | |
3889 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3890 | ||
e5198075 | 3891 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3892 | } |
3893 | ||
2a4ab640 FT |
3894 | u8 __init io_apic_unique_id(u8 id) |
3895 | { | |
3896 | #ifdef CONFIG_X86_32 | |
3897 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3898 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3899 | return io_apic_get_unique_id(nr_ioapics, id); | |
3900 | else | |
3901 | return id; | |
3902 | #else | |
3903 | int i; | |
3904 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3905 | |
2a4ab640 FT |
3906 | bitmap_zero(used, 256); |
3907 | for (i = 0; i < nr_ioapics; i++) { | |
3908 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3909 | __set_bit(ia->apicid, used); | |
3910 | } | |
3911 | if (!test_bit(id, used)) | |
3912 | return id; | |
3913 | return find_first_zero_bit(used, 256); | |
3914 | #endif | |
3915 | } | |
1da177e4 | 3916 | |
54168ed7 | 3917 | #ifdef CONFIG_X86_32 |
36062448 | 3918 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3919 | { |
3920 | union IO_APIC_reg_00 reg_00; | |
3921 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3922 | physid_mask_t tmp; | |
3923 | unsigned long flags; | |
3924 | int i = 0; | |
3925 | ||
3926 | /* | |
36062448 PC |
3927 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3928 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3929 | * supports up to 16 on one shared APIC bus. |
36062448 | 3930 | * |
1da177e4 LT |
3931 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3932 | * advantage of new APIC bus architecture. | |
3933 | */ | |
3934 | ||
3935 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3936 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3937 | |
3938 | spin_lock_irqsave(&ioapic_lock, flags); | |
3939 | reg_00.raw = io_apic_read(ioapic, 0); | |
3940 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3941 | ||
3942 | if (apic_id >= get_physical_broadcast()) { | |
3943 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3944 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3945 | apic_id = reg_00.bits.ID; | |
3946 | } | |
3947 | ||
3948 | /* | |
36062448 | 3949 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3950 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3951 | */ | |
d1d7cae8 | 3952 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3953 | |
3954 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3955 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3956 | break; |
3957 | } | |
3958 | ||
3959 | if (i == get_physical_broadcast()) | |
3960 | panic("Max apic_id exceeded!\n"); | |
3961 | ||
3962 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3963 | "trying %d\n", ioapic, apic_id, i); | |
3964 | ||
3965 | apic_id = i; | |
36062448 | 3966 | } |
1da177e4 | 3967 | |
8058714a | 3968 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3969 | physids_or(apic_id_map, apic_id_map, tmp); |
3970 | ||
3971 | if (reg_00.bits.ID != apic_id) { | |
3972 | reg_00.bits.ID = apic_id; | |
3973 | ||
3974 | spin_lock_irqsave(&ioapic_lock, flags); | |
3975 | io_apic_write(ioapic, 0, reg_00.raw); | |
3976 | reg_00.raw = io_apic_read(ioapic, 0); | |
3977 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3978 | ||
3979 | /* Sanity check */ | |
6070f9ec AD |
3980 | if (reg_00.bits.ID != apic_id) { |
3981 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3982 | return -1; | |
3983 | } | |
1da177e4 LT |
3984 | } |
3985 | ||
3986 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3987 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3988 | ||
3989 | return apic_id; | |
3990 | } | |
58f892e0 | 3991 | #endif |
1da177e4 | 3992 | |
36062448 | 3993 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3994 | { |
3995 | union IO_APIC_reg_01 reg_01; | |
3996 | unsigned long flags; | |
3997 | ||
3998 | spin_lock_irqsave(&ioapic_lock, flags); | |
3999 | reg_01.raw = io_apic_read(ioapic, 1); | |
4000 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4001 | ||
4002 | return reg_01.bits.version; | |
4003 | } | |
4004 | ||
61fd47e0 SL |
4005 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4006 | { | |
4007 | int i; | |
4008 | ||
4009 | if (skip_ioapic_setup) | |
4010 | return -1; | |
4011 | ||
4012 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4013 | if (mp_irqs[i].irqtype == mp_INT && |
4014 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4015 | break; |
4016 | if (i >= mp_irq_entries) | |
4017 | return -1; | |
4018 | ||
4019 | *trigger = irq_trigger(i); | |
4020 | *polarity = irq_polarity(i); | |
4021 | return 0; | |
4022 | } | |
4023 | ||
497c9a19 YL |
4024 | /* |
4025 | * This function currently is only a helper for the i386 smp boot process where | |
4026 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4027 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4028 | */ |
4029 | #ifdef CONFIG_SMP | |
4030 | void __init setup_ioapic_dest(void) | |
4031 | { | |
b9c61b70 | 4032 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4033 | struct irq_desc *desc; |
22f65d31 | 4034 | const struct cpumask *mask; |
497c9a19 YL |
4035 | |
4036 | if (skip_ioapic_setup == 1) | |
4037 | return; | |
4038 | ||
b9c61b70 YL |
4039 | #ifdef CONFIG_ACPI |
4040 | if (!acpi_disabled && acpi_ioapic) { | |
4041 | ioapic = mp_find_ioapic(0); | |
4042 | if (ioapic < 0) | |
4043 | ioapic = 0; | |
4044 | } | |
4045 | #endif | |
6c2e9403 | 4046 | |
b9c61b70 YL |
4047 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4048 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4049 | if (irq_entry == -1) | |
4050 | continue; | |
4051 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4052 | |
b9c61b70 | 4053 | desc = irq_to_desc(irq); |
6c2e9403 | 4054 | |
b9c61b70 YL |
4055 | /* |
4056 | * Honour affinities which have been set in early boot | |
4057 | */ | |
4058 | if (desc->status & | |
4059 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4060 | mask = desc->affinity; | |
4061 | else | |
4062 | mask = apic->target_cpus(); | |
497c9a19 | 4063 | |
b9c61b70 YL |
4064 | if (intr_remapping_enabled) |
4065 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4066 | else | |
4067 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4068 | } |
b9c61b70 | 4069 | |
497c9a19 YL |
4070 | } |
4071 | #endif | |
4072 | ||
54168ed7 IM |
4073 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4074 | ||
4075 | static struct resource *ioapic_resources; | |
4076 | ||
ffc43836 | 4077 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4078 | { |
4079 | unsigned long n; | |
4080 | struct resource *res; | |
4081 | char *mem; | |
4082 | int i; | |
4083 | ||
4084 | if (nr_ioapics <= 0) | |
4085 | return NULL; | |
4086 | ||
4087 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4088 | n *= nr_ioapics; | |
4089 | ||
4090 | mem = alloc_bootmem(n); | |
4091 | res = (void *)mem; | |
4092 | ||
ffc43836 | 4093 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4094 | |
ffc43836 CG |
4095 | for (i = 0; i < nr_ioapics; i++) { |
4096 | res[i].name = mem; | |
4097 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4098 | sprintf(mem, "IOAPIC %u", i); | |
4099 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
54168ed7 IM |
4100 | } |
4101 | ||
4102 | ioapic_resources = res; | |
4103 | ||
4104 | return res; | |
4105 | } | |
54168ed7 | 4106 | |
f3294a33 YL |
4107 | void __init ioapic_init_mappings(void) |
4108 | { | |
4109 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4110 | struct resource *ioapic_res; |
d6c88a50 | 4111 | int i; |
f3294a33 | 4112 | |
ffc43836 | 4113 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4114 | for (i = 0; i < nr_ioapics; i++) { |
4115 | if (smp_found_config) { | |
b5ba7e6d | 4116 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4117 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4118 | if (!ioapic_phys) { |
4119 | printk(KERN_ERR | |
4120 | "WARNING: bogus zero IO-APIC " | |
4121 | "address found in MPTABLE, " | |
4122 | "disabling IO/APIC support!\n"); | |
4123 | smp_found_config = 0; | |
4124 | skip_ioapic_setup = 1; | |
4125 | goto fake_ioapic_page; | |
4126 | } | |
54168ed7 | 4127 | #endif |
f3294a33 | 4128 | } else { |
54168ed7 | 4129 | #ifdef CONFIG_X86_32 |
f3294a33 | 4130 | fake_ioapic_page: |
54168ed7 | 4131 | #endif |
f3294a33 | 4132 | ioapic_phys = (unsigned long) |
54168ed7 | 4133 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4134 | ioapic_phys = __pa(ioapic_phys); |
4135 | } | |
4136 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4137 | apic_printk(APIC_VERBOSE, |
4138 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4139 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4140 | idx++; |
54168ed7 | 4141 | |
ffc43836 CG |
4142 | ioapic_res->start = ioapic_phys; |
4143 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4144 | ioapic_res++; | |
f3294a33 YL |
4145 | } |
4146 | } | |
4147 | ||
857fdc53 | 4148 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4149 | { |
4150 | int i; | |
4151 | struct resource *r = ioapic_resources; | |
4152 | ||
4153 | if (!r) { | |
857fdc53 | 4154 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4155 | printk(KERN_ERR |
4156 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4157 | return; |
54168ed7 IM |
4158 | } |
4159 | ||
4160 | for (i = 0; i < nr_ioapics; i++) { | |
4161 | insert_resource(&iomem_resource, r); | |
4162 | r++; | |
4163 | } | |
54168ed7 | 4164 | } |
2a4ab640 FT |
4165 | |
4166 | int mp_find_ioapic(int gsi) | |
4167 | { | |
4168 | int i = 0; | |
4169 | ||
4170 | /* Find the IOAPIC that manages this GSI. */ | |
4171 | for (i = 0; i < nr_ioapics; i++) { | |
4172 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4173 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4174 | return i; | |
4175 | } | |
54168ed7 | 4176 | |
2a4ab640 FT |
4177 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4178 | return -1; | |
4179 | } | |
4180 | ||
4181 | int mp_find_ioapic_pin(int ioapic, int gsi) | |
4182 | { | |
4183 | if (WARN_ON(ioapic == -1)) | |
4184 | return -1; | |
4185 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4186 | return -1; | |
4187 | ||
4188 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4189 | } | |
4190 | ||
4191 | static int bad_ioapic(unsigned long address) | |
4192 | { | |
4193 | if (nr_ioapics >= MAX_IO_APICS) { | |
4194 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4195 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4196 | return 1; | |
4197 | } | |
4198 | if (!address) { | |
4199 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4200 | " found in table, skipping!\n"); | |
4201 | return 1; | |
4202 | } | |
54168ed7 IM |
4203 | return 0; |
4204 | } | |
4205 | ||
2a4ab640 FT |
4206 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4207 | { | |
4208 | int idx = 0; | |
4209 | ||
4210 | if (bad_ioapic(address)) | |
4211 | return; | |
4212 | ||
4213 | idx = nr_ioapics; | |
4214 | ||
4215 | mp_ioapics[idx].type = MP_IOAPIC; | |
4216 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4217 | mp_ioapics[idx].apicaddr = address; | |
4218 | ||
4219 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4220 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4221 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4222 | ||
4223 | /* | |
4224 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4225 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4226 | */ | |
4227 | mp_gsi_routing[idx].gsi_base = gsi_base; | |
4228 | mp_gsi_routing[idx].gsi_end = gsi_base + | |
4229 | io_apic_get_redir_entries(idx); | |
4230 | ||
4231 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4232 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4233 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4234 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4235 | ||
4236 | nr_ioapics++; | |
4237 | } |