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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
f6e2e6b6 JR |
31 | |
32 | /* | |
33 | * definitions for the ACPI scanning code | |
34 | */ | |
f6e2e6b6 | 35 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
36 | |
37 | #define ACPI_IVHD_TYPE 0x10 | |
38 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
39 | #define ACPI_IVMD_TYPE 0x21 | |
40 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
41 | ||
42 | #define IVHD_DEV_ALL 0x01 | |
43 | #define IVHD_DEV_SELECT 0x02 | |
44 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
45 | #define IVHD_DEV_RANGE_END 0x04 | |
46 | #define IVHD_DEV_ALIAS 0x42 | |
47 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
48 | #define IVHD_DEV_EXT_SELECT 0x46 | |
49 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
50 | ||
51 | #define IVHD_FLAG_HT_TUN_EN 0x00 | |
52 | #define IVHD_FLAG_PASSPW_EN 0x01 | |
53 | #define IVHD_FLAG_RESPASSPW_EN 0x02 | |
54 | #define IVHD_FLAG_ISOC_EN 0x03 | |
55 | ||
56 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
57 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
58 | ||
59 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
60 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
61 | #define ACPI_DEVFLAG_NMI 0x04 | |
62 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
63 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
64 | #define ACPI_DEVFLAG_LINT0 0x40 | |
65 | #define ACPI_DEVFLAG_LINT1 0x80 | |
66 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
67 | ||
b65233a9 JR |
68 | /* |
69 | * ACPI table definitions | |
70 | * | |
71 | * These data structures are laid over the table to parse the important values | |
72 | * out of it. | |
73 | */ | |
74 | ||
75 | /* | |
76 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
77 | * or more ivhd_entrys. | |
78 | */ | |
f6e2e6b6 JR |
79 | struct ivhd_header { |
80 | u8 type; | |
81 | u8 flags; | |
82 | u16 length; | |
83 | u16 devid; | |
84 | u16 cap_ptr; | |
85 | u64 mmio_phys; | |
86 | u16 pci_seg; | |
87 | u16 info; | |
88 | u32 reserved; | |
89 | } __attribute__((packed)); | |
90 | ||
b65233a9 JR |
91 | /* |
92 | * A device entry describing which devices a specific IOMMU translates and | |
93 | * which requestor ids they use. | |
94 | */ | |
f6e2e6b6 JR |
95 | struct ivhd_entry { |
96 | u8 type; | |
97 | u16 devid; | |
98 | u8 flags; | |
99 | u32 ext; | |
100 | } __attribute__((packed)); | |
101 | ||
b65233a9 JR |
102 | /* |
103 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
104 | * ranges for devices and regions that should be unity mapped. | |
105 | */ | |
f6e2e6b6 JR |
106 | struct ivmd_header { |
107 | u8 type; | |
108 | u8 flags; | |
109 | u16 length; | |
110 | u16 devid; | |
111 | u16 aux; | |
112 | u64 resv; | |
113 | u64 range_start; | |
114 | u64 range_length; | |
115 | } __attribute__((packed)); | |
116 | ||
c1cbebee JR |
117 | static int __initdata amd_iommu_detected; |
118 | ||
b65233a9 JR |
119 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
120 | to handle */ | |
2e22847f | 121 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 JR |
122 | we find in ACPI */ |
123 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
124 | int amd_iommu_isolate; /* if 1, device isolation is enabled */ | |
928abd25 | 125 | |
2e22847f | 126 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 127 | system */ |
928abd25 | 128 | |
b65233a9 JR |
129 | /* |
130 | * Pointer to the device table which is shared by all AMD IOMMUs | |
131 | * it is indexed by the PCI device id or the HT unit id and contains | |
132 | * information about the domain the device belongs to as well as the | |
133 | * page table root pointer. | |
134 | */ | |
928abd25 | 135 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
136 | |
137 | /* | |
138 | * The alias table is a driver specific data structure which contains the | |
139 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
140 | * More than one device can share the same requestor id. | |
141 | */ | |
928abd25 | 142 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
143 | |
144 | /* | |
145 | * The rlookup table is used to find the IOMMU which is responsible | |
146 | * for a specific device. It is also indexed by the PCI device id. | |
147 | */ | |
928abd25 | 148 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
149 | |
150 | /* | |
151 | * The pd table (protection domain table) is used to find the protection domain | |
152 | * data structure a device belongs to. Indexed with the PCI device id too. | |
153 | */ | |
928abd25 | 154 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
155 | |
156 | /* | |
157 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
158 | * to know which ones are already in use. | |
159 | */ | |
928abd25 JR |
160 | unsigned long *amd_iommu_pd_alloc_bitmap; |
161 | ||
b65233a9 JR |
162 | static u32 dev_table_size; /* size of the device table */ |
163 | static u32 alias_table_size; /* size of the alias table */ | |
164 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 165 | |
208ec8c9 JR |
166 | static inline void update_last_devid(u16 devid) |
167 | { | |
168 | if (devid > amd_iommu_last_bdf) | |
169 | amd_iommu_last_bdf = devid; | |
170 | } | |
171 | ||
c571484e JR |
172 | static inline unsigned long tbl_size(int entry_size) |
173 | { | |
174 | unsigned shift = PAGE_SHIFT + | |
175 | get_order(amd_iommu_last_bdf * entry_size); | |
176 | ||
177 | return 1UL << shift; | |
178 | } | |
179 | ||
b65233a9 JR |
180 | /**************************************************************************** |
181 | * | |
182 | * AMD IOMMU MMIO register space handling functions | |
183 | * | |
184 | * These functions are used to program the IOMMU device registers in | |
185 | * MMIO space required for that driver. | |
186 | * | |
187 | ****************************************************************************/ | |
3e8064ba | 188 | |
b65233a9 JR |
189 | /* |
190 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
191 | * exclusion range are passed through untranslated | |
192 | */ | |
b2026aa2 JR |
193 | static void __init iommu_set_exclusion_range(struct amd_iommu *iommu) |
194 | { | |
195 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
196 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
197 | u64 entry; | |
198 | ||
199 | if (!iommu->exclusion_start) | |
200 | return; | |
201 | ||
202 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
203 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
204 | &entry, sizeof(entry)); | |
205 | ||
206 | entry = limit; | |
207 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
208 | &entry, sizeof(entry)); | |
209 | } | |
210 | ||
b65233a9 | 211 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
212 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
213 | { | |
214 | u32 entry; | |
215 | ||
216 | BUG_ON(iommu->mmio_base == NULL); | |
217 | ||
218 | entry = virt_to_phys(amd_iommu_dev_table); | |
219 | entry |= (dev_table_size >> 12) - 1; | |
220 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
221 | &entry, sizeof(entry)); | |
222 | } | |
223 | ||
b65233a9 | 224 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
b2026aa2 JR |
225 | static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
226 | { | |
227 | u32 ctrl; | |
228 | ||
229 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
230 | ctrl |= (1 << bit); | |
231 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
232 | } | |
233 | ||
234 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
235 | { | |
236 | u32 ctrl; | |
237 | ||
238 | ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
239 | ctrl &= ~(1 << bit); | |
240 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
241 | } | |
242 | ||
b65233a9 | 243 | /* Function to enable the hardware */ |
b2026aa2 JR |
244 | void __init iommu_enable(struct amd_iommu *iommu) |
245 | { | |
3eaf28a1 JR |
246 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU " |
247 | "at %02x:%02x.%x cap 0x%hx\n", | |
248 | iommu->dev->bus->number, | |
249 | PCI_SLOT(iommu->dev->devfn), | |
250 | PCI_FUNC(iommu->dev->devfn), | |
251 | iommu->cap_ptr); | |
b2026aa2 JR |
252 | |
253 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
254 | } |
255 | ||
126c52be JR |
256 | /* Function to enable IOMMU event logging and event interrupts */ |
257 | void __init iommu_enable_event_logging(struct amd_iommu *iommu) | |
258 | { | |
259 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); | |
260 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
261 | } | |
262 | ||
b65233a9 JR |
263 | /* |
264 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
265 | * the system has one. | |
266 | */ | |
6c56747b JR |
267 | static u8 * __init iommu_map_mmio_space(u64 address) |
268 | { | |
269 | u8 *ret; | |
270 | ||
271 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
272 | return NULL; | |
273 | ||
274 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
275 | if (ret != NULL) | |
276 | return ret; | |
277 | ||
278 | release_mem_region(address, MMIO_REGION_LENGTH); | |
279 | ||
280 | return NULL; | |
281 | } | |
282 | ||
283 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
284 | { | |
285 | if (iommu->mmio_base) | |
286 | iounmap(iommu->mmio_base); | |
287 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
288 | } | |
289 | ||
b65233a9 JR |
290 | /**************************************************************************** |
291 | * | |
292 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
293 | * parsing. In this pass we try to find out the highest device id this | |
294 | * code has to handle. Upon this information the size of the shared data | |
295 | * structures is determined later. | |
296 | * | |
297 | ****************************************************************************/ | |
298 | ||
299 | /* | |
300 | * This function reads the last device id the IOMMU has to handle from the PCI | |
301 | * capability header for this IOMMU | |
302 | */ | |
3e8064ba JR |
303 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
304 | { | |
305 | u32 cap; | |
306 | ||
307 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 308 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
309 | |
310 | return 0; | |
311 | } | |
312 | ||
b65233a9 JR |
313 | /* |
314 | * After reading the highest device id from the IOMMU PCI capability header | |
315 | * this function looks if there is a higher device id defined in the ACPI table | |
316 | */ | |
3e8064ba JR |
317 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
318 | { | |
319 | u8 *p = (void *)h, *end = (void *)h; | |
320 | struct ivhd_entry *dev; | |
321 | ||
322 | p += sizeof(*h); | |
323 | end += h->length; | |
324 | ||
325 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
326 | PCI_SLOT(h->devid), | |
327 | PCI_FUNC(h->devid), | |
328 | h->cap_ptr); | |
329 | ||
330 | while (p < end) { | |
331 | dev = (struct ivhd_entry *)p; | |
332 | switch (dev->type) { | |
333 | case IVHD_DEV_SELECT: | |
334 | case IVHD_DEV_RANGE_END: | |
335 | case IVHD_DEV_ALIAS: | |
336 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 337 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 338 | update_last_devid(dev->devid); |
3e8064ba JR |
339 | break; |
340 | default: | |
341 | break; | |
342 | } | |
343 | p += 0x04 << (*p >> 6); | |
344 | } | |
345 | ||
346 | WARN_ON(p != end); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
b65233a9 JR |
351 | /* |
352 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
353 | * id which we need to handle. This is the first of three functions which parse | |
354 | * the ACPI table. So we check the checksum here. | |
355 | */ | |
3e8064ba JR |
356 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
357 | { | |
358 | int i; | |
359 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
360 | struct ivhd_header *h; | |
361 | ||
362 | /* | |
363 | * Validate checksum here so we don't need to do it when | |
364 | * we actually parse the table | |
365 | */ | |
366 | for (i = 0; i < table->length; ++i) | |
367 | checksum += p[i]; | |
368 | if (checksum != 0) | |
369 | /* ACPI table corrupt */ | |
370 | return -ENODEV; | |
371 | ||
372 | p += IVRS_HEADER_LENGTH; | |
373 | ||
374 | end += table->length; | |
375 | while (p < end) { | |
376 | h = (struct ivhd_header *)p; | |
377 | switch (h->type) { | |
378 | case ACPI_IVHD_TYPE: | |
379 | find_last_devid_from_ivhd(h); | |
380 | break; | |
381 | default: | |
382 | break; | |
383 | } | |
384 | p += h->length; | |
385 | } | |
386 | WARN_ON(p != end); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
b65233a9 JR |
391 | /**************************************************************************** |
392 | * | |
393 | * The following functions belong the the code path which parses the ACPI table | |
394 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
395 | * data structures, initialize the device/alias/rlookup table and also | |
396 | * basically initialize the hardware. | |
397 | * | |
398 | ****************************************************************************/ | |
399 | ||
400 | /* | |
401 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
402 | * write commands to that buffer later and the IOMMU will execute them | |
403 | * asynchronously | |
404 | */ | |
b36ca91e JR |
405 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
406 | { | |
d0312b21 | 407 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 408 | get_order(CMD_BUFFER_SIZE)); |
d0312b21 | 409 | u64 entry; |
b36ca91e JR |
410 | |
411 | if (cmd_buf == NULL) | |
412 | return NULL; | |
413 | ||
414 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
415 | ||
b36ca91e JR |
416 | entry = (u64)virt_to_phys(cmd_buf); |
417 | entry |= MMIO_CMD_SIZE_512; | |
418 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, | |
419 | &entry, sizeof(entry)); | |
420 | ||
421 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
422 | ||
423 | return cmd_buf; | |
424 | } | |
425 | ||
426 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
427 | { | |
9a836de0 | 428 | free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
429 | } |
430 | ||
335503e5 JR |
431 | /* allocates the memory where the IOMMU will log its events to */ |
432 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
433 | { | |
434 | u64 entry; | |
435 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
436 | get_order(EVT_BUFFER_SIZE)); | |
437 | ||
438 | if (iommu->evt_buf == NULL) | |
439 | return NULL; | |
440 | ||
441 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; | |
442 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, | |
443 | &entry, sizeof(entry)); | |
444 | ||
445 | iommu->evt_buf_size = EVT_BUFFER_SIZE; | |
446 | ||
447 | return iommu->evt_buf; | |
448 | } | |
449 | ||
450 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
451 | { | |
452 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
453 | } | |
454 | ||
b65233a9 | 455 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
456 | static void set_dev_entry_bit(u16 devid, u8 bit) |
457 | { | |
458 | int i = (bit >> 5) & 0x07; | |
459 | int _bit = bit & 0x1f; | |
460 | ||
461 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
462 | } | |
463 | ||
5ff4789d JR |
464 | /* Writes the specific IOMMU for a device into the rlookup table */ |
465 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
466 | { | |
467 | amd_iommu_rlookup_table[devid] = iommu; | |
468 | } | |
469 | ||
b65233a9 JR |
470 | /* |
471 | * This function takes the device specific flags read from the ACPI | |
472 | * table and sets up the device table entry with that information | |
473 | */ | |
5ff4789d JR |
474 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
475 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
476 | { |
477 | if (flags & ACPI_DEVFLAG_INITPASS) | |
478 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
479 | if (flags & ACPI_DEVFLAG_EXTINT) | |
480 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
481 | if (flags & ACPI_DEVFLAG_NMI) | |
482 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
483 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
484 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
485 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
486 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
487 | if (flags & ACPI_DEVFLAG_LINT0) | |
488 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
489 | if (flags & ACPI_DEVFLAG_LINT1) | |
490 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 491 | |
5ff4789d | 492 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
493 | } |
494 | ||
b65233a9 JR |
495 | /* |
496 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
497 | * it | |
498 | */ | |
3566b778 JR |
499 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
500 | { | |
501 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
502 | ||
503 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
504 | return; | |
505 | ||
506 | if (iommu) { | |
b65233a9 JR |
507 | /* |
508 | * We only can configure exclusion ranges per IOMMU, not | |
509 | * per device. But we can enable the exclusion range per | |
510 | * device. This is done here | |
511 | */ | |
3566b778 JR |
512 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
513 | iommu->exclusion_start = m->range_start; | |
514 | iommu->exclusion_length = m->range_length; | |
515 | } | |
516 | } | |
517 | ||
b65233a9 JR |
518 | /* |
519 | * This function reads some important data from the IOMMU PCI space and | |
520 | * initializes the driver data structure with it. It reads the hardware | |
521 | * capabilities and the first/last device entries | |
522 | */ | |
5d0c8e49 JR |
523 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
524 | { | |
5d0c8e49 | 525 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 526 | u32 range, misc; |
5d0c8e49 | 527 | |
3eaf28a1 JR |
528 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
529 | &iommu->cap); | |
530 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
531 | &range); | |
a80dc3e0 JR |
532 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
533 | &misc); | |
5d0c8e49 | 534 | |
d591b0a3 JR |
535 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
536 | MMIO_GET_FD(range)); | |
537 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
538 | MMIO_GET_LD(range)); | |
a80dc3e0 | 539 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
540 | } |
541 | ||
b65233a9 JR |
542 | /* |
543 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
544 | * initializes the hardware and our data structures with it. | |
545 | */ | |
5d0c8e49 JR |
546 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
547 | struct ivhd_header *h) | |
548 | { | |
549 | u8 *p = (u8 *)h; | |
550 | u8 *end = p, flags = 0; | |
551 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
552 | u32 ext_flags = 0; | |
58a3bee5 | 553 | bool alias = false; |
5d0c8e49 JR |
554 | struct ivhd_entry *e; |
555 | ||
556 | /* | |
557 | * First set the recommended feature enable bits from ACPI | |
558 | * into the IOMMU control registers | |
559 | */ | |
560 | h->flags & IVHD_FLAG_HT_TUN_EN ? | |
561 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
562 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
563 | ||
564 | h->flags & IVHD_FLAG_PASSPW_EN ? | |
565 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
566 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
567 | ||
568 | h->flags & IVHD_FLAG_RESPASSPW_EN ? | |
569 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
570 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
571 | ||
572 | h->flags & IVHD_FLAG_ISOC_EN ? | |
573 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
574 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
575 | ||
576 | /* | |
577 | * make IOMMU memory accesses cache coherent | |
578 | */ | |
579 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
580 | ||
581 | /* | |
582 | * Done. Now parse the device entries | |
583 | */ | |
584 | p += sizeof(struct ivhd_header); | |
585 | end += h->length; | |
586 | ||
587 | while (p < end) { | |
588 | e = (struct ivhd_entry *)p; | |
589 | switch (e->type) { | |
590 | case IVHD_DEV_ALL: | |
591 | for (dev_i = iommu->first_device; | |
592 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
593 | set_dev_entry_from_acpi(iommu, dev_i, |
594 | e->flags, 0); | |
5d0c8e49 JR |
595 | break; |
596 | case IVHD_DEV_SELECT: | |
597 | devid = e->devid; | |
5ff4789d | 598 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
599 | break; |
600 | case IVHD_DEV_SELECT_RANGE_START: | |
601 | devid_start = e->devid; | |
602 | flags = e->flags; | |
603 | ext_flags = 0; | |
58a3bee5 | 604 | alias = false; |
5d0c8e49 JR |
605 | break; |
606 | case IVHD_DEV_ALIAS: | |
607 | devid = e->devid; | |
608 | devid_to = e->ext >> 8; | |
5ff4789d | 609 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
610 | amd_iommu_alias_table[devid] = devid_to; |
611 | break; | |
612 | case IVHD_DEV_ALIAS_RANGE: | |
613 | devid_start = e->devid; | |
614 | flags = e->flags; | |
615 | devid_to = e->ext >> 8; | |
616 | ext_flags = 0; | |
58a3bee5 | 617 | alias = true; |
5d0c8e49 JR |
618 | break; |
619 | case IVHD_DEV_EXT_SELECT: | |
620 | devid = e->devid; | |
5ff4789d JR |
621 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
622 | e->ext); | |
5d0c8e49 JR |
623 | break; |
624 | case IVHD_DEV_EXT_SELECT_RANGE: | |
625 | devid_start = e->devid; | |
626 | flags = e->flags; | |
627 | ext_flags = e->ext; | |
58a3bee5 | 628 | alias = false; |
5d0c8e49 JR |
629 | break; |
630 | case IVHD_DEV_RANGE_END: | |
631 | devid = e->devid; | |
632 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
633 | if (alias) | |
634 | amd_iommu_alias_table[dev_i] = devid_to; | |
5ff4789d | 635 | set_dev_entry_from_acpi(iommu, |
5d0c8e49 JR |
636 | amd_iommu_alias_table[dev_i], |
637 | flags, ext_flags); | |
638 | } | |
639 | break; | |
640 | default: | |
641 | break; | |
642 | } | |
643 | ||
644 | p += 0x04 << (e->type >> 6); | |
645 | } | |
646 | } | |
647 | ||
b65233a9 | 648 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
649 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
650 | { | |
651 | u16 i; | |
652 | ||
653 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
654 | set_iommu_for_device(iommu, i); | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
e47d402d JR |
659 | static void __init free_iommu_one(struct amd_iommu *iommu) |
660 | { | |
661 | free_command_buffer(iommu); | |
335503e5 | 662 | free_event_buffer(iommu); |
e47d402d JR |
663 | iommu_unmap_mmio_space(iommu); |
664 | } | |
665 | ||
666 | static void __init free_iommu_all(void) | |
667 | { | |
668 | struct amd_iommu *iommu, *next; | |
669 | ||
670 | list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) { | |
671 | list_del(&iommu->list); | |
672 | free_iommu_one(iommu); | |
673 | kfree(iommu); | |
674 | } | |
675 | } | |
676 | ||
b65233a9 JR |
677 | /* |
678 | * This function clues the initialization function for one IOMMU | |
679 | * together and also allocates the command buffer and programs the | |
680 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
681 | */ | |
e47d402d JR |
682 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
683 | { | |
684 | spin_lock_init(&iommu->lock); | |
685 | list_add_tail(&iommu->list, &amd_iommu_list); | |
686 | ||
687 | /* | |
688 | * Copy data from ACPI table entry to the iommu struct | |
689 | */ | |
3eaf28a1 JR |
690 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
691 | if (!iommu->dev) | |
692 | return 1; | |
693 | ||
e47d402d | 694 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 695 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
696 | iommu->mmio_phys = h->mmio_phys; |
697 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
698 | if (!iommu->mmio_base) | |
699 | return -ENOMEM; | |
700 | ||
701 | iommu_set_device_table(iommu); | |
702 | iommu->cmd_buf = alloc_command_buffer(iommu); | |
703 | if (!iommu->cmd_buf) | |
704 | return -ENOMEM; | |
705 | ||
335503e5 JR |
706 | iommu->evt_buf = alloc_event_buffer(iommu); |
707 | if (!iommu->evt_buf) | |
708 | return -ENOMEM; | |
709 | ||
a80dc3e0 JR |
710 | iommu->int_enabled = false; |
711 | ||
e47d402d JR |
712 | init_iommu_from_pci(iommu); |
713 | init_iommu_from_acpi(iommu, h); | |
714 | init_iommu_devices(iommu); | |
715 | ||
3eaf28a1 JR |
716 | pci_enable_device(iommu->dev); |
717 | ||
e47d402d JR |
718 | return 0; |
719 | } | |
720 | ||
b65233a9 JR |
721 | /* |
722 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
723 | * IOMMU structure and initializes it with init_iommu_one() | |
724 | */ | |
e47d402d JR |
725 | static int __init init_iommu_all(struct acpi_table_header *table) |
726 | { | |
727 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
728 | struct ivhd_header *h; | |
729 | struct amd_iommu *iommu; | |
730 | int ret; | |
731 | ||
e47d402d JR |
732 | end += table->length; |
733 | p += IVRS_HEADER_LENGTH; | |
734 | ||
735 | while (p < end) { | |
736 | h = (struct ivhd_header *)p; | |
737 | switch (*p) { | |
738 | case ACPI_IVHD_TYPE: | |
739 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
740 | if (iommu == NULL) | |
741 | return -ENOMEM; | |
742 | ret = init_iommu_one(iommu, h); | |
743 | if (ret) | |
744 | return ret; | |
745 | break; | |
746 | default: | |
747 | break; | |
748 | } | |
749 | p += h->length; | |
750 | ||
751 | } | |
752 | WARN_ON(p != end); | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
a80dc3e0 JR |
757 | /**************************************************************************** |
758 | * | |
759 | * The following functions initialize the MSI interrupts for all IOMMUs | |
760 | * in the system. Its a bit challenging because there could be multiple | |
761 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
762 | * pci_dev. | |
763 | * | |
764 | ****************************************************************************/ | |
765 | ||
766 | static int __init iommu_setup_msix(struct amd_iommu *iommu) | |
767 | { | |
768 | struct amd_iommu *curr; | |
769 | struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */ | |
770 | int nvec = 0, i; | |
771 | ||
772 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
773 | if (curr->dev == iommu->dev) { | |
774 | entries[nvec].entry = curr->evt_msi_num; | |
775 | entries[nvec].vector = 0; | |
776 | curr->int_enabled = true; | |
777 | nvec++; | |
778 | } | |
779 | } | |
780 | ||
781 | if (pci_enable_msix(iommu->dev, entries, nvec)) { | |
782 | pci_disable_msix(iommu->dev); | |
783 | return 1; | |
784 | } | |
785 | ||
786 | for (i = 0; i < nvec; ++i) { | |
787 | int r = request_irq(entries->vector, amd_iommu_int_handler, | |
788 | IRQF_SAMPLE_RANDOM, | |
789 | "AMD IOMMU", | |
790 | NULL); | |
791 | if (r) | |
792 | goto out_free; | |
793 | } | |
794 | ||
795 | return 0; | |
796 | ||
797 | out_free: | |
798 | for (i -= 1; i >= 0; --i) | |
799 | free_irq(entries->vector, NULL); | |
800 | ||
801 | pci_disable_msix(iommu->dev); | |
802 | ||
803 | return 1; | |
804 | } | |
805 | ||
806 | static int __init iommu_setup_msi(struct amd_iommu *iommu) | |
807 | { | |
808 | int r; | |
809 | struct amd_iommu *curr; | |
810 | ||
811 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
812 | if (curr->dev == iommu->dev) | |
813 | curr->int_enabled = true; | |
814 | } | |
815 | ||
816 | ||
817 | if (pci_enable_msi(iommu->dev)) | |
818 | return 1; | |
819 | ||
820 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
821 | IRQF_SAMPLE_RANDOM, | |
822 | "AMD IOMMU", | |
823 | NULL); | |
824 | ||
825 | if (r) { | |
826 | pci_disable_msi(iommu->dev); | |
827 | return 1; | |
828 | } | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
833 | static int __init iommu_init_msi(struct amd_iommu *iommu) | |
834 | { | |
835 | if (iommu->int_enabled) | |
836 | return 0; | |
837 | ||
838 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX)) | |
839 | return iommu_setup_msix(iommu); | |
840 | else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) | |
841 | return iommu_setup_msi(iommu); | |
842 | ||
843 | return 1; | |
844 | } | |
845 | ||
b65233a9 JR |
846 | /**************************************************************************** |
847 | * | |
848 | * The next functions belong to the third pass of parsing the ACPI | |
849 | * table. In this last pass the memory mapping requirements are | |
850 | * gathered (like exclusion and unity mapping reanges). | |
851 | * | |
852 | ****************************************************************************/ | |
853 | ||
be2a022c JR |
854 | static void __init free_unity_maps(void) |
855 | { | |
856 | struct unity_map_entry *entry, *next; | |
857 | ||
858 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
859 | list_del(&entry->list); | |
860 | kfree(entry); | |
861 | } | |
862 | } | |
863 | ||
b65233a9 | 864 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
865 | static int __init init_exclusion_range(struct ivmd_header *m) |
866 | { | |
867 | int i; | |
868 | ||
869 | switch (m->type) { | |
870 | case ACPI_IVMD_TYPE: | |
871 | set_device_exclusion_range(m->devid, m); | |
872 | break; | |
873 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 874 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
875 | set_device_exclusion_range(i, m); |
876 | break; | |
877 | case ACPI_IVMD_TYPE_RANGE: | |
878 | for (i = m->devid; i <= m->aux; ++i) | |
879 | set_device_exclusion_range(i, m); | |
880 | break; | |
881 | default: | |
882 | break; | |
883 | } | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
b65233a9 | 888 | /* called for unity map ACPI definition */ |
be2a022c JR |
889 | static int __init init_unity_map_range(struct ivmd_header *m) |
890 | { | |
891 | struct unity_map_entry *e = 0; | |
892 | ||
893 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
894 | if (e == NULL) | |
895 | return -ENOMEM; | |
896 | ||
897 | switch (m->type) { | |
898 | default: | |
899 | case ACPI_IVMD_TYPE: | |
900 | e->devid_start = e->devid_end = m->devid; | |
901 | break; | |
902 | case ACPI_IVMD_TYPE_ALL: | |
903 | e->devid_start = 0; | |
904 | e->devid_end = amd_iommu_last_bdf; | |
905 | break; | |
906 | case ACPI_IVMD_TYPE_RANGE: | |
907 | e->devid_start = m->devid; | |
908 | e->devid_end = m->aux; | |
909 | break; | |
910 | } | |
911 | e->address_start = PAGE_ALIGN(m->range_start); | |
912 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
913 | e->prot = m->flags >> 1; | |
914 | ||
915 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
b65233a9 | 920 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
921 | static int __init init_memory_definitions(struct acpi_table_header *table) |
922 | { | |
923 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
924 | struct ivmd_header *m; | |
925 | ||
be2a022c JR |
926 | end += table->length; |
927 | p += IVRS_HEADER_LENGTH; | |
928 | ||
929 | while (p < end) { | |
930 | m = (struct ivmd_header *)p; | |
931 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
932 | init_exclusion_range(m); | |
933 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
934 | init_unity_map_range(m); | |
935 | ||
936 | p += m->length; | |
937 | } | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
9f5f5fb3 JR |
942 | /* |
943 | * Init the device table to not allow DMA access for devices and | |
944 | * suppress all page faults | |
945 | */ | |
946 | static void init_device_table(void) | |
947 | { | |
948 | u16 devid; | |
949 | ||
950 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
951 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
952 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
953 | } |
954 | } | |
955 | ||
b65233a9 JR |
956 | /* |
957 | * This function finally enables all IOMMUs found in the system after | |
958 | * they have been initialized | |
959 | */ | |
8736197b JR |
960 | static void __init enable_iommus(void) |
961 | { | |
962 | struct amd_iommu *iommu; | |
963 | ||
964 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
965 | iommu_set_exclusion_range(iommu); | |
a80dc3e0 | 966 | iommu_init_msi(iommu); |
126c52be | 967 | iommu_enable_event_logging(iommu); |
8736197b JR |
968 | iommu_enable(iommu); |
969 | } | |
970 | } | |
971 | ||
7441e9cb JR |
972 | /* |
973 | * Suspend/Resume support | |
974 | * disable suspend until real resume implemented | |
975 | */ | |
976 | ||
977 | static int amd_iommu_resume(struct sys_device *dev) | |
978 | { | |
979 | return 0; | |
980 | } | |
981 | ||
982 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
983 | { | |
984 | return -EINVAL; | |
985 | } | |
986 | ||
987 | static struct sysdev_class amd_iommu_sysdev_class = { | |
988 | .name = "amd_iommu", | |
989 | .suspend = amd_iommu_suspend, | |
990 | .resume = amd_iommu_resume, | |
991 | }; | |
992 | ||
993 | static struct sys_device device_amd_iommu = { | |
994 | .id = 0, | |
995 | .cls = &amd_iommu_sysdev_class, | |
996 | }; | |
997 | ||
b65233a9 JR |
998 | /* |
999 | * This is the core init function for AMD IOMMU hardware in the system. | |
1000 | * This function is called from the generic x86 DMA layer initialization | |
1001 | * code. | |
1002 | * | |
1003 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1004 | * three times: | |
1005 | * | |
1006 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1007 | * Upon this information the size of the data structures is | |
1008 | * determined that needs to be allocated. | |
1009 | * | |
1010 | * 2 pass) Initialize the data structures just allocated with the | |
1011 | * information in the ACPI table about available AMD IOMMUs | |
1012 | * in the system. It also maps the PCI devices in the | |
1013 | * system to specific IOMMUs | |
1014 | * | |
1015 | * 3 pass) After the basic data structures are allocated and | |
1016 | * initialized we update them with information about memory | |
1017 | * remapping requirements parsed out of the ACPI table in | |
1018 | * this last pass. | |
1019 | * | |
1020 | * After that the hardware is initialized and ready to go. In the last | |
1021 | * step we do some Linux specific things like registering the driver in | |
1022 | * the dma_ops interface and initializing the suspend/resume support | |
1023 | * functions. Finally it prints some information about AMD IOMMUs and | |
1024 | * the driver state and enables the hardware. | |
1025 | */ | |
fe74c9cf JR |
1026 | int __init amd_iommu_init(void) |
1027 | { | |
1028 | int i, ret = 0; | |
1029 | ||
1030 | ||
8b14518f | 1031 | if (no_iommu) { |
fe74c9cf JR |
1032 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
1033 | return 0; | |
1034 | } | |
1035 | ||
c1cbebee JR |
1036 | if (!amd_iommu_detected) |
1037 | return -ENODEV; | |
1038 | ||
fe74c9cf JR |
1039 | /* |
1040 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1041 | * we need to handle. Upon this information the shared data | |
1042 | * structures for the IOMMUs in the system will be allocated | |
1043 | */ | |
1044 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1045 | return -ENODEV; | |
1046 | ||
c571484e JR |
1047 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1048 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1049 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1050 | |
1051 | ret = -ENOMEM; | |
1052 | ||
1053 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1054 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1055 | get_order(dev_table_size)); |
1056 | if (amd_iommu_dev_table == NULL) | |
1057 | goto out; | |
1058 | ||
1059 | /* | |
1060 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1061 | * IOMMU see for that device | |
1062 | */ | |
1063 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1064 | get_order(alias_table_size)); | |
1065 | if (amd_iommu_alias_table == NULL) | |
1066 | goto free; | |
1067 | ||
1068 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
1069 | amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL, | |
1070 | get_order(rlookup_table_size)); | |
1071 | if (amd_iommu_rlookup_table == NULL) | |
1072 | goto free; | |
1073 | ||
1074 | /* | |
1075 | * Protection Domain table - maps devices to protection domains | |
1076 | * This table has the same size as the rlookup_table | |
1077 | */ | |
5dc8bff0 | 1078 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1079 | get_order(rlookup_table_size)); |
1080 | if (amd_iommu_pd_table == NULL) | |
1081 | goto free; | |
1082 | ||
5dc8bff0 JR |
1083 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1084 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1085 | get_order(MAX_DOMAIN_ID/8)); |
1086 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1087 | goto free; | |
1088 | ||
9f5f5fb3 JR |
1089 | /* init the device table */ |
1090 | init_device_table(); | |
1091 | ||
fe74c9cf | 1092 | /* |
5dc8bff0 | 1093 | * let all alias entries point to itself |
fe74c9cf | 1094 | */ |
3a61ec38 | 1095 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1096 | amd_iommu_alias_table[i] = i; |
1097 | ||
fe74c9cf JR |
1098 | /* |
1099 | * never allocate domain 0 because its used as the non-allocated and | |
1100 | * error value placeholder | |
1101 | */ | |
1102 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1103 | ||
1104 | /* | |
1105 | * now the data structures are allocated and basically initialized | |
1106 | * start the real acpi table scan | |
1107 | */ | |
1108 | ret = -ENODEV; | |
1109 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1110 | goto free; | |
1111 | ||
1112 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1113 | goto free; | |
1114 | ||
129d6aba | 1115 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1116 | if (ret) |
1117 | goto free; | |
1118 | ||
129d6aba | 1119 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1120 | if (ret) |
1121 | goto free; | |
1122 | ||
129d6aba | 1123 | ret = amd_iommu_init_dma_ops(); |
7441e9cb JR |
1124 | if (ret) |
1125 | goto free; | |
1126 | ||
8736197b JR |
1127 | enable_iommus(); |
1128 | ||
fe74c9cf JR |
1129 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
1130 | (1 << (amd_iommu_aperture_order-20))); | |
1131 | ||
1132 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
1133 | if (amd_iommu_isolate) | |
1134 | printk("enabled\n"); | |
1135 | else | |
1136 | printk("disabled\n"); | |
1137 | ||
1c655773 JR |
1138 | if (iommu_fullflush) |
1139 | printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n"); | |
1140 | else | |
1141 | printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n"); | |
1142 | ||
fe74c9cf JR |
1143 | out: |
1144 | return ret; | |
1145 | ||
1146 | free: | |
d58befd3 JR |
1147 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1148 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1149 | |
9a836de0 JR |
1150 | free_pages((unsigned long)amd_iommu_pd_table, |
1151 | get_order(rlookup_table_size)); | |
fe74c9cf | 1152 | |
9a836de0 JR |
1153 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1154 | get_order(rlookup_table_size)); | |
fe74c9cf | 1155 | |
9a836de0 JR |
1156 | free_pages((unsigned long)amd_iommu_alias_table, |
1157 | get_order(alias_table_size)); | |
fe74c9cf | 1158 | |
9a836de0 JR |
1159 | free_pages((unsigned long)amd_iommu_dev_table, |
1160 | get_order(dev_table_size)); | |
fe74c9cf JR |
1161 | |
1162 | free_iommu_all(); | |
1163 | ||
1164 | free_unity_maps(); | |
1165 | ||
1166 | goto out; | |
1167 | } | |
1168 | ||
b65233a9 JR |
1169 | /**************************************************************************** |
1170 | * | |
1171 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1172 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1173 | * IOMMUs | |
1174 | * | |
1175 | ****************************************************************************/ | |
ae7877de JR |
1176 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1177 | { | |
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | void __init amd_iommu_detect(void) | |
1182 | { | |
299a140d | 1183 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1184 | return; |
1185 | ||
ae7877de JR |
1186 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1187 | iommu_detected = 1; | |
c1cbebee | 1188 | amd_iommu_detected = 1; |
92af4e29 | 1189 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1190 | gart_iommu_aperture_disabled = 1; |
1191 | gart_iommu_aperture = 0; | |
92af4e29 | 1192 | #endif |
ae7877de JR |
1193 | } |
1194 | } | |
1195 | ||
b65233a9 JR |
1196 | /**************************************************************************** |
1197 | * | |
1198 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1199 | * options. | |
1200 | * | |
1201 | ****************************************************************************/ | |
1202 | ||
918ad6c5 JR |
1203 | static int __init parse_amd_iommu_options(char *str) |
1204 | { | |
1205 | for (; *str; ++str) { | |
1c655773 | 1206 | if (strncmp(str, "isolate", 7) == 0) |
918ad6c5 JR |
1207 | amd_iommu_isolate = 1; |
1208 | } | |
1209 | ||
1210 | return 1; | |
1211 | } | |
1212 | ||
1213 | static int __init parse_amd_iommu_size_options(char *str) | |
1214 | { | |
0906372e JR |
1215 | unsigned order = PAGE_SHIFT + get_order(memparse(str, &str)); |
1216 | ||
1217 | if ((order > 24) && (order < 31)) | |
1218 | amd_iommu_aperture_order = order; | |
918ad6c5 JR |
1219 | |
1220 | return 1; | |
1221 | } | |
1222 | ||
1223 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1224 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |