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f6e2e6b6 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 | 27 | #include <asm/pci-direct.h> |
6a9401a7 | 28 | #include <asm/amd_iommu_proto.h> |
f6e2e6b6 | 29 | #include <asm/amd_iommu_types.h> |
c6da992e | 30 | #include <asm/amd_iommu.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
ea1b0d39 | 33 | #include <asm/x86_init.h> |
f6e2e6b6 JR |
34 | |
35 | /* | |
36 | * definitions for the ACPI scanning code | |
37 | */ | |
f6e2e6b6 | 38 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
39 | |
40 | #define ACPI_IVHD_TYPE 0x10 | |
41 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
42 | #define ACPI_IVMD_TYPE 0x21 | |
43 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
44 | ||
45 | #define IVHD_DEV_ALL 0x01 | |
46 | #define IVHD_DEV_SELECT 0x02 | |
47 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
48 | #define IVHD_DEV_RANGE_END 0x04 | |
49 | #define IVHD_DEV_ALIAS 0x42 | |
50 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
51 | #define IVHD_DEV_EXT_SELECT 0x46 | |
52 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
53 | ||
6da7342f JR |
54 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
55 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
56 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
57 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
58 | |
59 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
60 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
61 | ||
62 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
63 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
64 | #define ACPI_DEVFLAG_NMI 0x04 | |
65 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
66 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
67 | #define ACPI_DEVFLAG_LINT0 0x40 | |
68 | #define ACPI_DEVFLAG_LINT1 0x80 | |
69 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
70 | ||
b65233a9 JR |
71 | /* |
72 | * ACPI table definitions | |
73 | * | |
74 | * These data structures are laid over the table to parse the important values | |
75 | * out of it. | |
76 | */ | |
77 | ||
78 | /* | |
79 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
80 | * or more ivhd_entrys. | |
81 | */ | |
f6e2e6b6 JR |
82 | struct ivhd_header { |
83 | u8 type; | |
84 | u8 flags; | |
85 | u16 length; | |
86 | u16 devid; | |
87 | u16 cap_ptr; | |
88 | u64 mmio_phys; | |
89 | u16 pci_seg; | |
90 | u16 info; | |
91 | u32 reserved; | |
92 | } __attribute__((packed)); | |
93 | ||
b65233a9 JR |
94 | /* |
95 | * A device entry describing which devices a specific IOMMU translates and | |
96 | * which requestor ids they use. | |
97 | */ | |
f6e2e6b6 JR |
98 | struct ivhd_entry { |
99 | u8 type; | |
100 | u16 devid; | |
101 | u8 flags; | |
102 | u32 ext; | |
103 | } __attribute__((packed)); | |
104 | ||
b65233a9 JR |
105 | /* |
106 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
107 | * ranges for devices and regions that should be unity mapped. | |
108 | */ | |
f6e2e6b6 JR |
109 | struct ivmd_header { |
110 | u8 type; | |
111 | u8 flags; | |
112 | u16 length; | |
113 | u16 devid; | |
114 | u16 aux; | |
115 | u64 resv; | |
116 | u64 range_start; | |
117 | u64 range_length; | |
118 | } __attribute__((packed)); | |
119 | ||
fefda117 JR |
120 | bool amd_iommu_dump; |
121 | ||
c1cbebee | 122 | static int __initdata amd_iommu_detected; |
a5235725 | 123 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 124 | |
b65233a9 JR |
125 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
126 | to handle */ | |
2e22847f | 127 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 128 | we find in ACPI */ |
afa9fdc2 | 129 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 130 | |
2e22847f | 131 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 132 | system */ |
928abd25 | 133 | |
bb52777e JR |
134 | /* Array to assign indices to IOMMUs*/ |
135 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
136 | int amd_iommus_present; | |
137 | ||
318afd41 JR |
138 | /* IOMMUs have a non-present cache? */ |
139 | bool amd_iommu_np_cache __read_mostly; | |
140 | ||
0f764806 | 141 | /* |
3551a708 | 142 | * The ACPI table parsing functions set this variable on an error |
0f764806 | 143 | */ |
3551a708 | 144 | static int __initdata amd_iommu_init_err; |
0f764806 | 145 | |
aeb26f55 JR |
146 | /* |
147 | * List of protection domains - used during resume | |
148 | */ | |
149 | LIST_HEAD(amd_iommu_pd_list); | |
150 | spinlock_t amd_iommu_pd_lock; | |
151 | ||
b65233a9 JR |
152 | /* |
153 | * Pointer to the device table which is shared by all AMD IOMMUs | |
154 | * it is indexed by the PCI device id or the HT unit id and contains | |
155 | * information about the domain the device belongs to as well as the | |
156 | * page table root pointer. | |
157 | */ | |
928abd25 | 158 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
159 | |
160 | /* | |
161 | * The alias table is a driver specific data structure which contains the | |
162 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
163 | * More than one device can share the same requestor id. | |
164 | */ | |
928abd25 | 165 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
166 | |
167 | /* | |
168 | * The rlookup table is used to find the IOMMU which is responsible | |
169 | * for a specific device. It is also indexed by the PCI device id. | |
170 | */ | |
928abd25 | 171 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 172 | |
b65233a9 JR |
173 | /* |
174 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
175 | * to know which ones are already in use. | |
176 | */ | |
928abd25 JR |
177 | unsigned long *amd_iommu_pd_alloc_bitmap; |
178 | ||
b65233a9 JR |
179 | static u32 dev_table_size; /* size of the device table */ |
180 | static u32 alias_table_size; /* size of the alias table */ | |
181 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 182 | |
208ec8c9 JR |
183 | static inline void update_last_devid(u16 devid) |
184 | { | |
185 | if (devid > amd_iommu_last_bdf) | |
186 | amd_iommu_last_bdf = devid; | |
187 | } | |
188 | ||
c571484e JR |
189 | static inline unsigned long tbl_size(int entry_size) |
190 | { | |
191 | unsigned shift = PAGE_SHIFT + | |
421f909c | 192 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
193 | |
194 | return 1UL << shift; | |
195 | } | |
196 | ||
b65233a9 JR |
197 | /**************************************************************************** |
198 | * | |
199 | * AMD IOMMU MMIO register space handling functions | |
200 | * | |
201 | * These functions are used to program the IOMMU device registers in | |
202 | * MMIO space required for that driver. | |
203 | * | |
204 | ****************************************************************************/ | |
3e8064ba | 205 | |
b65233a9 JR |
206 | /* |
207 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
208 | * exclusion range are passed through untranslated | |
209 | */ | |
05f92db9 | 210 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
211 | { |
212 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
213 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
214 | u64 entry; | |
215 | ||
216 | if (!iommu->exclusion_start) | |
217 | return; | |
218 | ||
219 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
220 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
221 | &entry, sizeof(entry)); | |
222 | ||
223 | entry = limit; | |
224 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
225 | &entry, sizeof(entry)); | |
226 | } | |
227 | ||
b65233a9 | 228 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
229 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
230 | { | |
f609891f | 231 | u64 entry; |
b2026aa2 JR |
232 | |
233 | BUG_ON(iommu->mmio_base == NULL); | |
234 | ||
235 | entry = virt_to_phys(amd_iommu_dev_table); | |
236 | entry |= (dev_table_size >> 12) - 1; | |
237 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
238 | &entry, sizeof(entry)); | |
239 | } | |
240 | ||
b65233a9 | 241 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 242 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
243 | { |
244 | u32 ctrl; | |
245 | ||
246 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
247 | ctrl |= (1 << bit); | |
248 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
249 | } | |
250 | ||
ca020711 | 251 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
252 | { |
253 | u32 ctrl; | |
254 | ||
199d0d50 | 255 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
256 | ctrl &= ~(1 << bit); |
257 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
258 | } | |
259 | ||
b65233a9 | 260 | /* Function to enable the hardware */ |
05f92db9 | 261 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 262 | { |
4c6f40d4 | 263 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n", |
a4e267c8 | 264 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 JR |
265 | |
266 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
267 | } |
268 | ||
92ac4320 | 269 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 270 | { |
a8c485bb CW |
271 | /* Disable command buffer */ |
272 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
273 | ||
274 | /* Disable event logging and event interrupts */ | |
275 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
276 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
277 | ||
278 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 279 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
280 | } |
281 | ||
b65233a9 JR |
282 | /* |
283 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
284 | * the system has one. | |
285 | */ | |
6c56747b JR |
286 | static u8 * __init iommu_map_mmio_space(u64 address) |
287 | { | |
288 | u8 *ret; | |
289 | ||
e82752d8 JR |
290 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { |
291 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | |
292 | address); | |
293 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | |
6c56747b | 294 | return NULL; |
e82752d8 | 295 | } |
6c56747b JR |
296 | |
297 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
298 | if (ret != NULL) | |
299 | return ret; | |
300 | ||
301 | release_mem_region(address, MMIO_REGION_LENGTH); | |
302 | ||
303 | return NULL; | |
304 | } | |
305 | ||
306 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
307 | { | |
308 | if (iommu->mmio_base) | |
309 | iounmap(iommu->mmio_base); | |
310 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
311 | } | |
312 | ||
b65233a9 JR |
313 | /**************************************************************************** |
314 | * | |
315 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
316 | * parsing. In this pass we try to find out the highest device id this | |
317 | * code has to handle. Upon this information the size of the shared data | |
318 | * structures is determined later. | |
319 | * | |
320 | ****************************************************************************/ | |
321 | ||
b514e555 JR |
322 | /* |
323 | * This function calculates the length of a given IVHD entry | |
324 | */ | |
325 | static inline int ivhd_entry_length(u8 *ivhd) | |
326 | { | |
327 | return 0x04 << (*ivhd >> 6); | |
328 | } | |
329 | ||
b65233a9 JR |
330 | /* |
331 | * This function reads the last device id the IOMMU has to handle from the PCI | |
332 | * capability header for this IOMMU | |
333 | */ | |
3e8064ba JR |
334 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
335 | { | |
336 | u32 cap; | |
337 | ||
338 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 339 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
340 | |
341 | return 0; | |
342 | } | |
343 | ||
b65233a9 JR |
344 | /* |
345 | * After reading the highest device id from the IOMMU PCI capability header | |
346 | * this function looks if there is a higher device id defined in the ACPI table | |
347 | */ | |
3e8064ba JR |
348 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
349 | { | |
350 | u8 *p = (void *)h, *end = (void *)h; | |
351 | struct ivhd_entry *dev; | |
352 | ||
353 | p += sizeof(*h); | |
354 | end += h->length; | |
355 | ||
356 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
357 | PCI_SLOT(h->devid), | |
358 | PCI_FUNC(h->devid), | |
359 | h->cap_ptr); | |
360 | ||
361 | while (p < end) { | |
362 | dev = (struct ivhd_entry *)p; | |
363 | switch (dev->type) { | |
364 | case IVHD_DEV_SELECT: | |
365 | case IVHD_DEV_RANGE_END: | |
366 | case IVHD_DEV_ALIAS: | |
367 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 368 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 369 | update_last_devid(dev->devid); |
3e8064ba JR |
370 | break; |
371 | default: | |
372 | break; | |
373 | } | |
b514e555 | 374 | p += ivhd_entry_length(p); |
3e8064ba JR |
375 | } |
376 | ||
377 | WARN_ON(p != end); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
b65233a9 JR |
382 | /* |
383 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
384 | * id which we need to handle. This is the first of three functions which parse | |
385 | * the ACPI table. So we check the checksum here. | |
386 | */ | |
3e8064ba JR |
387 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
388 | { | |
389 | int i; | |
390 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
391 | struct ivhd_header *h; | |
392 | ||
393 | /* | |
394 | * Validate checksum here so we don't need to do it when | |
395 | * we actually parse the table | |
396 | */ | |
397 | for (i = 0; i < table->length; ++i) | |
398 | checksum += p[i]; | |
3551a708 | 399 | if (checksum != 0) { |
3e8064ba | 400 | /* ACPI table corrupt */ |
3551a708 JR |
401 | amd_iommu_init_err = -ENODEV; |
402 | return 0; | |
403 | } | |
3e8064ba JR |
404 | |
405 | p += IVRS_HEADER_LENGTH; | |
406 | ||
407 | end += table->length; | |
408 | while (p < end) { | |
409 | h = (struct ivhd_header *)p; | |
410 | switch (h->type) { | |
411 | case ACPI_IVHD_TYPE: | |
412 | find_last_devid_from_ivhd(h); | |
413 | break; | |
414 | default: | |
415 | break; | |
416 | } | |
417 | p += h->length; | |
418 | } | |
419 | WARN_ON(p != end); | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
b65233a9 JR |
424 | /**************************************************************************** |
425 | * | |
426 | * The following functions belong the the code path which parses the ACPI table | |
427 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
428 | * data structures, initialize the device/alias/rlookup table and also | |
429 | * basically initialize the hardware. | |
430 | * | |
431 | ****************************************************************************/ | |
432 | ||
433 | /* | |
434 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
435 | * write commands to that buffer later and the IOMMU will execute them | |
436 | * asynchronously | |
437 | */ | |
b36ca91e JR |
438 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
439 | { | |
d0312b21 | 440 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 441 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
442 | |
443 | if (cmd_buf == NULL) | |
444 | return NULL; | |
445 | ||
549c90dc | 446 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 447 | |
58492e12 JR |
448 | return cmd_buf; |
449 | } | |
450 | ||
93f1cc67 JR |
451 | /* |
452 | * This function resets the command buffer if the IOMMU stopped fetching | |
453 | * commands from it. | |
454 | */ | |
455 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
456 | { | |
457 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
458 | ||
459 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
460 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
461 | ||
462 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
463 | } | |
464 | ||
58492e12 JR |
465 | /* |
466 | * This function writes the command buffer address to the hardware and | |
467 | * enables it. | |
468 | */ | |
469 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
470 | { | |
471 | u64 entry; | |
472 | ||
473 | BUG_ON(iommu->cmd_buf == NULL); | |
474 | ||
475 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 476 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 477 | |
b36ca91e | 478 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 479 | &entry, sizeof(entry)); |
b36ca91e | 480 | |
93f1cc67 | 481 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 482 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
483 | } |
484 | ||
485 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
486 | { | |
23c1713f | 487 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 488 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
489 | } |
490 | ||
335503e5 JR |
491 | /* allocates the memory where the IOMMU will log its events to */ |
492 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
493 | { | |
335503e5 JR |
494 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
495 | get_order(EVT_BUFFER_SIZE)); | |
496 | ||
497 | if (iommu->evt_buf == NULL) | |
498 | return NULL; | |
499 | ||
1bc6f838 JR |
500 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
501 | ||
58492e12 JR |
502 | return iommu->evt_buf; |
503 | } | |
504 | ||
505 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
506 | { | |
507 | u64 entry; | |
508 | ||
509 | BUG_ON(iommu->evt_buf == NULL); | |
510 | ||
335503e5 | 511 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 512 | |
335503e5 JR |
513 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
514 | &entry, sizeof(entry)); | |
515 | ||
09067207 JR |
516 | /* set head and tail to zero manually */ |
517 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
518 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
519 | ||
58492e12 | 520 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
521 | } |
522 | ||
523 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
524 | { | |
525 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
526 | } | |
527 | ||
b65233a9 | 528 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
529 | static void set_dev_entry_bit(u16 devid, u8 bit) |
530 | { | |
531 | int i = (bit >> 5) & 0x07; | |
532 | int _bit = bit & 0x1f; | |
533 | ||
534 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
535 | } | |
536 | ||
c5cca146 JR |
537 | static int get_dev_entry_bit(u16 devid, u8 bit) |
538 | { | |
539 | int i = (bit >> 5) & 0x07; | |
540 | int _bit = bit & 0x1f; | |
541 | ||
542 | return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit; | |
543 | } | |
544 | ||
545 | ||
546 | void amd_iommu_apply_erratum_63(u16 devid) | |
547 | { | |
548 | int sysmgt; | |
549 | ||
550 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
551 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
552 | ||
553 | if (sysmgt == 0x01) | |
554 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
555 | } | |
556 | ||
5ff4789d JR |
557 | /* Writes the specific IOMMU for a device into the rlookup table */ |
558 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
559 | { | |
560 | amd_iommu_rlookup_table[devid] = iommu; | |
561 | } | |
562 | ||
b65233a9 JR |
563 | /* |
564 | * This function takes the device specific flags read from the ACPI | |
565 | * table and sets up the device table entry with that information | |
566 | */ | |
5ff4789d JR |
567 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
568 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
569 | { |
570 | if (flags & ACPI_DEVFLAG_INITPASS) | |
571 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
572 | if (flags & ACPI_DEVFLAG_EXTINT) | |
573 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
574 | if (flags & ACPI_DEVFLAG_NMI) | |
575 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
576 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
577 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
578 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
579 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
580 | if (flags & ACPI_DEVFLAG_LINT0) | |
581 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
582 | if (flags & ACPI_DEVFLAG_LINT1) | |
583 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 584 | |
c5cca146 JR |
585 | amd_iommu_apply_erratum_63(devid); |
586 | ||
5ff4789d | 587 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
588 | } |
589 | ||
b65233a9 JR |
590 | /* |
591 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
592 | * it | |
593 | */ | |
3566b778 JR |
594 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
595 | { | |
596 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
597 | ||
598 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
599 | return; | |
600 | ||
601 | if (iommu) { | |
b65233a9 JR |
602 | /* |
603 | * We only can configure exclusion ranges per IOMMU, not | |
604 | * per device. But we can enable the exclusion range per | |
605 | * device. This is done here | |
606 | */ | |
3566b778 JR |
607 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
608 | iommu->exclusion_start = m->range_start; | |
609 | iommu->exclusion_length = m->range_length; | |
610 | } | |
611 | } | |
612 | ||
b65233a9 JR |
613 | /* |
614 | * This function reads some important data from the IOMMU PCI space and | |
615 | * initializes the driver data structure with it. It reads the hardware | |
616 | * capabilities and the first/last device entries | |
617 | */ | |
5d0c8e49 JR |
618 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
619 | { | |
5d0c8e49 | 620 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 621 | u32 range, misc; |
5d0c8e49 | 622 | |
3eaf28a1 JR |
623 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
624 | &iommu->cap); | |
625 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
626 | &range); | |
a80dc3e0 JR |
627 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
628 | &misc); | |
5d0c8e49 | 629 | |
d591b0a3 JR |
630 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
631 | MMIO_GET_FD(range)); | |
632 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
633 | MMIO_GET_LD(range)); | |
a80dc3e0 | 634 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
4c894f47 JR |
635 | |
636 | if (is_rd890_iommu(iommu->dev)) { | |
637 | pci_read_config_dword(iommu->dev, 0xf0, &iommu->cache_cfg[0]); | |
638 | pci_read_config_dword(iommu->dev, 0xf4, &iommu->cache_cfg[1]); | |
639 | pci_read_config_dword(iommu->dev, 0xf8, &iommu->cache_cfg[2]); | |
640 | pci_read_config_dword(iommu->dev, 0xfc, &iommu->cache_cfg[3]); | |
641 | } | |
5d0c8e49 JR |
642 | } |
643 | ||
b65233a9 JR |
644 | /* |
645 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
646 | * initializes the hardware and our data structures with it. | |
647 | */ | |
5d0c8e49 JR |
648 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
649 | struct ivhd_header *h) | |
650 | { | |
651 | u8 *p = (u8 *)h; | |
652 | u8 *end = p, flags = 0; | |
653 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
654 | u32 ext_flags = 0; | |
58a3bee5 | 655 | bool alias = false; |
5d0c8e49 JR |
656 | struct ivhd_entry *e; |
657 | ||
658 | /* | |
e9bf5197 | 659 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 660 | */ |
e9bf5197 | 661 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
662 | |
663 | /* | |
664 | * Done. Now parse the device entries | |
665 | */ | |
666 | p += sizeof(struct ivhd_header); | |
667 | end += h->length; | |
668 | ||
42a698f4 | 669 | |
5d0c8e49 JR |
670 | while (p < end) { |
671 | e = (struct ivhd_entry *)p; | |
672 | switch (e->type) { | |
673 | case IVHD_DEV_ALL: | |
42a698f4 JR |
674 | |
675 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
676 | " last device %02x:%02x.%x flags: %02x\n", | |
677 | PCI_BUS(iommu->first_device), | |
678 | PCI_SLOT(iommu->first_device), | |
679 | PCI_FUNC(iommu->first_device), | |
680 | PCI_BUS(iommu->last_device), | |
681 | PCI_SLOT(iommu->last_device), | |
682 | PCI_FUNC(iommu->last_device), | |
683 | e->flags); | |
684 | ||
5d0c8e49 JR |
685 | for (dev_i = iommu->first_device; |
686 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
687 | set_dev_entry_from_acpi(iommu, dev_i, |
688 | e->flags, 0); | |
5d0c8e49 JR |
689 | break; |
690 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
691 | |
692 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
693 | "flags: %02x\n", | |
694 | PCI_BUS(e->devid), | |
695 | PCI_SLOT(e->devid), | |
696 | PCI_FUNC(e->devid), | |
697 | e->flags); | |
698 | ||
5d0c8e49 | 699 | devid = e->devid; |
5ff4789d | 700 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
701 | break; |
702 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
703 | |
704 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
705 | "devid: %02x:%02x.%x flags: %02x\n", | |
706 | PCI_BUS(e->devid), | |
707 | PCI_SLOT(e->devid), | |
708 | PCI_FUNC(e->devid), | |
709 | e->flags); | |
710 | ||
5d0c8e49 JR |
711 | devid_start = e->devid; |
712 | flags = e->flags; | |
713 | ext_flags = 0; | |
58a3bee5 | 714 | alias = false; |
5d0c8e49 JR |
715 | break; |
716 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
717 | |
718 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
719 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
720 | PCI_BUS(e->devid), | |
721 | PCI_SLOT(e->devid), | |
722 | PCI_FUNC(e->devid), | |
723 | e->flags, | |
724 | PCI_BUS(e->ext >> 8), | |
725 | PCI_SLOT(e->ext >> 8), | |
726 | PCI_FUNC(e->ext >> 8)); | |
727 | ||
5d0c8e49 JR |
728 | devid = e->devid; |
729 | devid_to = e->ext >> 8; | |
7a6a3a08 | 730 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 731 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
732 | amd_iommu_alias_table[devid] = devid_to; |
733 | break; | |
734 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
735 | |
736 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
737 | "devid: %02x:%02x.%x flags: %02x " | |
738 | "devid_to: %02x:%02x.%x\n", | |
739 | PCI_BUS(e->devid), | |
740 | PCI_SLOT(e->devid), | |
741 | PCI_FUNC(e->devid), | |
742 | e->flags, | |
743 | PCI_BUS(e->ext >> 8), | |
744 | PCI_SLOT(e->ext >> 8), | |
745 | PCI_FUNC(e->ext >> 8)); | |
746 | ||
5d0c8e49 JR |
747 | devid_start = e->devid; |
748 | flags = e->flags; | |
749 | devid_to = e->ext >> 8; | |
750 | ext_flags = 0; | |
58a3bee5 | 751 | alias = true; |
5d0c8e49 JR |
752 | break; |
753 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
754 | |
755 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
756 | "flags: %02x ext: %08x\n", | |
757 | PCI_BUS(e->devid), | |
758 | PCI_SLOT(e->devid), | |
759 | PCI_FUNC(e->devid), | |
760 | e->flags, e->ext); | |
761 | ||
5d0c8e49 | 762 | devid = e->devid; |
5ff4789d JR |
763 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
764 | e->ext); | |
5d0c8e49 JR |
765 | break; |
766 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
767 | |
768 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
769 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
770 | PCI_BUS(e->devid), | |
771 | PCI_SLOT(e->devid), | |
772 | PCI_FUNC(e->devid), | |
773 | e->flags, e->ext); | |
774 | ||
5d0c8e49 JR |
775 | devid_start = e->devid; |
776 | flags = e->flags; | |
777 | ext_flags = e->ext; | |
58a3bee5 | 778 | alias = false; |
5d0c8e49 JR |
779 | break; |
780 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
781 | |
782 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
783 | PCI_BUS(e->devid), | |
784 | PCI_SLOT(e->devid), | |
785 | PCI_FUNC(e->devid)); | |
786 | ||
5d0c8e49 JR |
787 | devid = e->devid; |
788 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 789 | if (alias) { |
5d0c8e49 | 790 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
791 | set_dev_entry_from_acpi(iommu, |
792 | devid_to, flags, ext_flags); | |
793 | } | |
794 | set_dev_entry_from_acpi(iommu, dev_i, | |
795 | flags, ext_flags); | |
5d0c8e49 JR |
796 | } |
797 | break; | |
798 | default: | |
799 | break; | |
800 | } | |
801 | ||
b514e555 | 802 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
803 | } |
804 | } | |
805 | ||
b65233a9 | 806 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
807 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
808 | { | |
809 | u16 i; | |
810 | ||
811 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
812 | set_iommu_for_device(iommu, i); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
e47d402d JR |
817 | static void __init free_iommu_one(struct amd_iommu *iommu) |
818 | { | |
819 | free_command_buffer(iommu); | |
335503e5 | 820 | free_event_buffer(iommu); |
e47d402d JR |
821 | iommu_unmap_mmio_space(iommu); |
822 | } | |
823 | ||
824 | static void __init free_iommu_all(void) | |
825 | { | |
826 | struct amd_iommu *iommu, *next; | |
827 | ||
3bd22172 | 828 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
829 | list_del(&iommu->list); |
830 | free_iommu_one(iommu); | |
831 | kfree(iommu); | |
832 | } | |
833 | } | |
834 | ||
b65233a9 JR |
835 | /* |
836 | * This function clues the initialization function for one IOMMU | |
837 | * together and also allocates the command buffer and programs the | |
838 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
839 | */ | |
e47d402d JR |
840 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
841 | { | |
842 | spin_lock_init(&iommu->lock); | |
bb52777e JR |
843 | |
844 | /* Add IOMMU to internal data structures */ | |
e47d402d | 845 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
846 | iommu->index = amd_iommus_present++; |
847 | ||
848 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
849 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
850 | return -ENOSYS; | |
851 | } | |
852 | ||
853 | /* Index is fine - add IOMMU to the array */ | |
854 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
855 | |
856 | /* | |
857 | * Copy data from ACPI table entry to the iommu struct | |
858 | */ | |
3eaf28a1 JR |
859 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
860 | if (!iommu->dev) | |
861 | return 1; | |
862 | ||
e47d402d | 863 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 864 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
865 | iommu->mmio_phys = h->mmio_phys; |
866 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
867 | if (!iommu->mmio_base) | |
868 | return -ENOMEM; | |
869 | ||
e47d402d JR |
870 | iommu->cmd_buf = alloc_command_buffer(iommu); |
871 | if (!iommu->cmd_buf) | |
872 | return -ENOMEM; | |
873 | ||
335503e5 JR |
874 | iommu->evt_buf = alloc_event_buffer(iommu); |
875 | if (!iommu->evt_buf) | |
876 | return -ENOMEM; | |
877 | ||
a80dc3e0 JR |
878 | iommu->int_enabled = false; |
879 | ||
e47d402d JR |
880 | init_iommu_from_pci(iommu); |
881 | init_iommu_from_acpi(iommu, h); | |
882 | init_iommu_devices(iommu); | |
883 | ||
318afd41 JR |
884 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) |
885 | amd_iommu_np_cache = true; | |
886 | ||
8a66712b | 887 | return pci_enable_device(iommu->dev); |
e47d402d JR |
888 | } |
889 | ||
b65233a9 JR |
890 | /* |
891 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
892 | * IOMMU structure and initializes it with init_iommu_one() | |
893 | */ | |
e47d402d JR |
894 | static int __init init_iommu_all(struct acpi_table_header *table) |
895 | { | |
896 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
897 | struct ivhd_header *h; | |
898 | struct amd_iommu *iommu; | |
899 | int ret; | |
900 | ||
e47d402d JR |
901 | end += table->length; |
902 | p += IVRS_HEADER_LENGTH; | |
903 | ||
904 | while (p < end) { | |
905 | h = (struct ivhd_header *)p; | |
906 | switch (*p) { | |
907 | case ACPI_IVHD_TYPE: | |
9c72041f | 908 | |
ae908c22 | 909 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
910 | "seg: %d flags: %01x info %04x\n", |
911 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
912 | PCI_FUNC(h->devid), h->cap_ptr, | |
913 | h->pci_seg, h->flags, h->info); | |
914 | DUMP_printk(" mmio-addr: %016llx\n", | |
915 | h->mmio_phys); | |
916 | ||
e47d402d | 917 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
3551a708 JR |
918 | if (iommu == NULL) { |
919 | amd_iommu_init_err = -ENOMEM; | |
920 | return 0; | |
921 | } | |
922 | ||
e47d402d | 923 | ret = init_iommu_one(iommu, h); |
3551a708 JR |
924 | if (ret) { |
925 | amd_iommu_init_err = ret; | |
926 | return 0; | |
927 | } | |
e47d402d JR |
928 | break; |
929 | default: | |
930 | break; | |
931 | } | |
932 | p += h->length; | |
933 | ||
934 | } | |
935 | WARN_ON(p != end); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
a80dc3e0 JR |
940 | /**************************************************************************** |
941 | * | |
942 | * The following functions initialize the MSI interrupts for all IOMMUs | |
943 | * in the system. Its a bit challenging because there could be multiple | |
944 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
945 | * pci_dev. | |
946 | * | |
947 | ****************************************************************************/ | |
948 | ||
9f800de3 | 949 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
950 | { |
951 | int r; | |
a80dc3e0 JR |
952 | |
953 | if (pci_enable_msi(iommu->dev)) | |
954 | return 1; | |
955 | ||
956 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
957 | IRQF_SAMPLE_RANDOM, | |
4c6f40d4 | 958 | "AMD-Vi", |
a80dc3e0 JR |
959 | NULL); |
960 | ||
961 | if (r) { | |
962 | pci_disable_msi(iommu->dev); | |
963 | return 1; | |
964 | } | |
965 | ||
fab6afa3 | 966 | iommu->int_enabled = true; |
58492e12 JR |
967 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
968 | ||
a80dc3e0 JR |
969 | return 0; |
970 | } | |
971 | ||
05f92db9 | 972 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
973 | { |
974 | if (iommu->int_enabled) | |
975 | return 0; | |
976 | ||
d91cecdd | 977 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
978 | return iommu_setup_msi(iommu); |
979 | ||
980 | return 1; | |
981 | } | |
982 | ||
b65233a9 JR |
983 | /**************************************************************************** |
984 | * | |
985 | * The next functions belong to the third pass of parsing the ACPI | |
986 | * table. In this last pass the memory mapping requirements are | |
987 | * gathered (like exclusion and unity mapping reanges). | |
988 | * | |
989 | ****************************************************************************/ | |
990 | ||
be2a022c JR |
991 | static void __init free_unity_maps(void) |
992 | { | |
993 | struct unity_map_entry *entry, *next; | |
994 | ||
995 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
996 | list_del(&entry->list); | |
997 | kfree(entry); | |
998 | } | |
999 | } | |
1000 | ||
b65233a9 | 1001 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1002 | static int __init init_exclusion_range(struct ivmd_header *m) |
1003 | { | |
1004 | int i; | |
1005 | ||
1006 | switch (m->type) { | |
1007 | case ACPI_IVMD_TYPE: | |
1008 | set_device_exclusion_range(m->devid, m); | |
1009 | break; | |
1010 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1011 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1012 | set_device_exclusion_range(i, m); |
1013 | break; | |
1014 | case ACPI_IVMD_TYPE_RANGE: | |
1015 | for (i = m->devid; i <= m->aux; ++i) | |
1016 | set_device_exclusion_range(i, m); | |
1017 | break; | |
1018 | default: | |
1019 | break; | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
b65233a9 | 1025 | /* called for unity map ACPI definition */ |
be2a022c JR |
1026 | static int __init init_unity_map_range(struct ivmd_header *m) |
1027 | { | |
1028 | struct unity_map_entry *e = 0; | |
02acc43a | 1029 | char *s; |
be2a022c JR |
1030 | |
1031 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1032 | if (e == NULL) | |
1033 | return -ENOMEM; | |
1034 | ||
1035 | switch (m->type) { | |
1036 | default: | |
0bc252f4 JR |
1037 | kfree(e); |
1038 | return 0; | |
be2a022c | 1039 | case ACPI_IVMD_TYPE: |
02acc43a | 1040 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1041 | e->devid_start = e->devid_end = m->devid; |
1042 | break; | |
1043 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1044 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1045 | e->devid_start = 0; |
1046 | e->devid_end = amd_iommu_last_bdf; | |
1047 | break; | |
1048 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1049 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1050 | e->devid_start = m->devid; |
1051 | e->devid_end = m->aux; | |
1052 | break; | |
1053 | } | |
1054 | e->address_start = PAGE_ALIGN(m->range_start); | |
1055 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1056 | e->prot = m->flags >> 1; | |
1057 | ||
02acc43a JR |
1058 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1059 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1060 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1061 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1062 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1063 | e->address_start, e->address_end, m->flags); | |
1064 | ||
be2a022c JR |
1065 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
b65233a9 | 1070 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1071 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1072 | { | |
1073 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1074 | struct ivmd_header *m; | |
1075 | ||
be2a022c JR |
1076 | end += table->length; |
1077 | p += IVRS_HEADER_LENGTH; | |
1078 | ||
1079 | while (p < end) { | |
1080 | m = (struct ivmd_header *)p; | |
1081 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1082 | init_exclusion_range(m); | |
1083 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1084 | init_unity_map_range(m); | |
1085 | ||
1086 | p += m->length; | |
1087 | } | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
9f5f5fb3 JR |
1092 | /* |
1093 | * Init the device table to not allow DMA access for devices and | |
1094 | * suppress all page faults | |
1095 | */ | |
1096 | static void init_device_table(void) | |
1097 | { | |
1098 | u16 devid; | |
1099 | ||
1100 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1101 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1102 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1103 | } |
1104 | } | |
1105 | ||
e9bf5197 JR |
1106 | static void iommu_init_flags(struct amd_iommu *iommu) |
1107 | { | |
1108 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1109 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1110 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1111 | ||
1112 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1113 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1114 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1115 | ||
1116 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1117 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1118 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1119 | ||
1120 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1121 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1122 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1123 | ||
1124 | /* | |
1125 | * make IOMMU memory accesses cache coherent | |
1126 | */ | |
1127 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1128 | } | |
1129 | ||
4c894f47 JR |
1130 | static void iommu_apply_quirks(struct amd_iommu *iommu) |
1131 | { | |
1132 | if (is_rd890_iommu(iommu->dev)) { | |
1133 | pci_write_config_dword(iommu->dev, 0xf0, iommu->cache_cfg[0]); | |
1134 | pci_write_config_dword(iommu->dev, 0xf4, iommu->cache_cfg[1]); | |
1135 | pci_write_config_dword(iommu->dev, 0xf8, iommu->cache_cfg[2]); | |
1136 | pci_write_config_dword(iommu->dev, 0xfc, iommu->cache_cfg[3]); | |
1137 | } | |
1138 | } | |
1139 | ||
b65233a9 JR |
1140 | /* |
1141 | * This function finally enables all IOMMUs found in the system after | |
1142 | * they have been initialized | |
1143 | */ | |
05f92db9 | 1144 | static void enable_iommus(void) |
8736197b JR |
1145 | { |
1146 | struct amd_iommu *iommu; | |
1147 | ||
3bd22172 | 1148 | for_each_iommu(iommu) { |
a8c485bb | 1149 | iommu_disable(iommu); |
4c894f47 | 1150 | iommu_apply_quirks(iommu); |
e9bf5197 | 1151 | iommu_init_flags(iommu); |
58492e12 JR |
1152 | iommu_set_device_table(iommu); |
1153 | iommu_enable_command_buffer(iommu); | |
1154 | iommu_enable_event_buffer(iommu); | |
8736197b | 1155 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1156 | iommu_init_msi(iommu); |
8736197b JR |
1157 | iommu_enable(iommu); |
1158 | } | |
1159 | } | |
1160 | ||
92ac4320 JR |
1161 | static void disable_iommus(void) |
1162 | { | |
1163 | struct amd_iommu *iommu; | |
1164 | ||
1165 | for_each_iommu(iommu) | |
1166 | iommu_disable(iommu); | |
1167 | } | |
1168 | ||
7441e9cb JR |
1169 | /* |
1170 | * Suspend/Resume support | |
1171 | * disable suspend until real resume implemented | |
1172 | */ | |
1173 | ||
1174 | static int amd_iommu_resume(struct sys_device *dev) | |
1175 | { | |
736501ee JR |
1176 | /* re-load the hardware */ |
1177 | enable_iommus(); | |
1178 | ||
1179 | /* | |
1180 | * we have to flush after the IOMMUs are enabled because a | |
1181 | * disabled IOMMU will never execute the commands we send | |
1182 | */ | |
736501ee | 1183 | amd_iommu_flush_all_devices(); |
6a047d8b | 1184 | amd_iommu_flush_all_domains(); |
736501ee | 1185 | |
7441e9cb JR |
1186 | return 0; |
1187 | } | |
1188 | ||
1189 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
1190 | { | |
736501ee JR |
1191 | /* disable IOMMUs to go out of the way for BIOS */ |
1192 | disable_iommus(); | |
1193 | ||
1194 | return 0; | |
7441e9cb JR |
1195 | } |
1196 | ||
1197 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1198 | .name = "amd_iommu", | |
1199 | .suspend = amd_iommu_suspend, | |
1200 | .resume = amd_iommu_resume, | |
1201 | }; | |
1202 | ||
1203 | static struct sys_device device_amd_iommu = { | |
1204 | .id = 0, | |
1205 | .cls = &amd_iommu_sysdev_class, | |
1206 | }; | |
1207 | ||
b65233a9 JR |
1208 | /* |
1209 | * This is the core init function for AMD IOMMU hardware in the system. | |
1210 | * This function is called from the generic x86 DMA layer initialization | |
1211 | * code. | |
1212 | * | |
1213 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1214 | * three times: | |
1215 | * | |
1216 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1217 | * Upon this information the size of the data structures is | |
1218 | * determined that needs to be allocated. | |
1219 | * | |
1220 | * 2 pass) Initialize the data structures just allocated with the | |
1221 | * information in the ACPI table about available AMD IOMMUs | |
1222 | * in the system. It also maps the PCI devices in the | |
1223 | * system to specific IOMMUs | |
1224 | * | |
1225 | * 3 pass) After the basic data structures are allocated and | |
1226 | * initialized we update them with information about memory | |
1227 | * remapping requirements parsed out of the ACPI table in | |
1228 | * this last pass. | |
1229 | * | |
1230 | * After that the hardware is initialized and ready to go. In the last | |
1231 | * step we do some Linux specific things like registering the driver in | |
1232 | * the dma_ops interface and initializing the suspend/resume support | |
1233 | * functions. Finally it prints some information about AMD IOMMUs and | |
1234 | * the driver state and enables the hardware. | |
1235 | */ | |
ea1b0d39 | 1236 | static int __init amd_iommu_init(void) |
fe74c9cf JR |
1237 | { |
1238 | int i, ret = 0; | |
1239 | ||
fe74c9cf JR |
1240 | /* |
1241 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1242 | * we need to handle. Upon this information the shared data | |
1243 | * structures for the IOMMUs in the system will be allocated | |
1244 | */ | |
1245 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1246 | return -ENODEV; | |
1247 | ||
3551a708 JR |
1248 | ret = amd_iommu_init_err; |
1249 | if (ret) | |
1250 | goto out; | |
1251 | ||
c571484e JR |
1252 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1253 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1254 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1255 | |
1256 | ret = -ENOMEM; | |
1257 | ||
1258 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1259 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1260 | get_order(dev_table_size)); |
1261 | if (amd_iommu_dev_table == NULL) | |
1262 | goto out; | |
1263 | ||
1264 | /* | |
1265 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1266 | * IOMMU see for that device | |
1267 | */ | |
1268 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1269 | get_order(alias_table_size)); | |
1270 | if (amd_iommu_alias_table == NULL) | |
1271 | goto free; | |
1272 | ||
1273 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1274 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1275 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1276 | get_order(rlookup_table_size)); |
1277 | if (amd_iommu_rlookup_table == NULL) | |
1278 | goto free; | |
1279 | ||
5dc8bff0 JR |
1280 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1281 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1282 | get_order(MAX_DOMAIN_ID/8)); |
1283 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1284 | goto free; | |
1285 | ||
9f5f5fb3 JR |
1286 | /* init the device table */ |
1287 | init_device_table(); | |
1288 | ||
fe74c9cf | 1289 | /* |
5dc8bff0 | 1290 | * let all alias entries point to itself |
fe74c9cf | 1291 | */ |
3a61ec38 | 1292 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1293 | amd_iommu_alias_table[i] = i; |
1294 | ||
fe74c9cf JR |
1295 | /* |
1296 | * never allocate domain 0 because its used as the non-allocated and | |
1297 | * error value placeholder | |
1298 | */ | |
1299 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1300 | ||
aeb26f55 JR |
1301 | spin_lock_init(&amd_iommu_pd_lock); |
1302 | ||
fe74c9cf JR |
1303 | /* |
1304 | * now the data structures are allocated and basically initialized | |
1305 | * start the real acpi table scan | |
1306 | */ | |
1307 | ret = -ENODEV; | |
1308 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1309 | goto free; | |
1310 | ||
3551a708 JR |
1311 | if (amd_iommu_init_err) { |
1312 | ret = amd_iommu_init_err; | |
0f764806 | 1313 | goto free; |
3551a708 | 1314 | } |
0f764806 | 1315 | |
fe74c9cf JR |
1316 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) |
1317 | goto free; | |
1318 | ||
3551a708 JR |
1319 | if (amd_iommu_init_err) { |
1320 | ret = amd_iommu_init_err; | |
1321 | goto free; | |
1322 | } | |
1323 | ||
129d6aba | 1324 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1325 | if (ret) |
1326 | goto free; | |
1327 | ||
129d6aba | 1328 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1329 | if (ret) |
1330 | goto free; | |
1331 | ||
b7cc9554 JR |
1332 | ret = amd_iommu_init_devices(); |
1333 | if (ret) | |
1334 | goto free; | |
1335 | ||
75f66533 CW |
1336 | enable_iommus(); |
1337 | ||
4751a951 JR |
1338 | if (iommu_pass_through) |
1339 | ret = amd_iommu_init_passthrough(); | |
1340 | else | |
1341 | ret = amd_iommu_init_dma_ops(); | |
f5325094 | 1342 | |
7441e9cb | 1343 | if (ret) |
e82752d8 | 1344 | goto free_disable; |
7441e9cb | 1345 | |
f5325094 JR |
1346 | amd_iommu_init_api(); |
1347 | ||
8638c491 JR |
1348 | amd_iommu_init_notifier(); |
1349 | ||
4751a951 JR |
1350 | if (iommu_pass_through) |
1351 | goto out; | |
1352 | ||
afa9fdc2 | 1353 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1354 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1355 | else |
4c6f40d4 | 1356 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1357 | |
338bac52 | 1358 | x86_platform.iommu_shutdown = disable_iommus; |
fe74c9cf JR |
1359 | out: |
1360 | return ret; | |
1361 | ||
e82752d8 | 1362 | free_disable: |
75f66533 | 1363 | disable_iommus(); |
b7cc9554 | 1364 | |
e82752d8 | 1365 | free: |
b7cc9554 JR |
1366 | amd_iommu_uninit_devices(); |
1367 | ||
d58befd3 JR |
1368 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1369 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1370 | |
9a836de0 JR |
1371 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1372 | get_order(rlookup_table_size)); | |
fe74c9cf | 1373 | |
9a836de0 JR |
1374 | free_pages((unsigned long)amd_iommu_alias_table, |
1375 | get_order(alias_table_size)); | |
fe74c9cf | 1376 | |
9a836de0 JR |
1377 | free_pages((unsigned long)amd_iommu_dev_table, |
1378 | get_order(dev_table_size)); | |
fe74c9cf JR |
1379 | |
1380 | free_iommu_all(); | |
1381 | ||
1382 | free_unity_maps(); | |
1383 | ||
d7f07769 JR |
1384 | #ifdef CONFIG_GART_IOMMU |
1385 | /* | |
1386 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1387 | * if possible. | |
1388 | */ | |
1389 | gart_iommu_init(); | |
1390 | ||
1391 | #endif | |
1392 | ||
fe74c9cf JR |
1393 | goto out; |
1394 | } | |
1395 | ||
b65233a9 JR |
1396 | /**************************************************************************** |
1397 | * | |
1398 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1399 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1400 | * IOMMUs | |
1401 | * | |
1402 | ****************************************************************************/ | |
ae7877de JR |
1403 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1404 | { | |
1405 | return 0; | |
1406 | } | |
1407 | ||
1408 | void __init amd_iommu_detect(void) | |
1409 | { | |
75f1cdf1 | 1410 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1411 | return; |
1412 | ||
a5235725 JR |
1413 | if (amd_iommu_disabled) |
1414 | return; | |
1415 | ||
ae7877de JR |
1416 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1417 | iommu_detected = 1; | |
c1cbebee | 1418 | amd_iommu_detected = 1; |
ea1b0d39 | 1419 | x86_init.iommu.iommu_init = amd_iommu_init; |
11bd04f6 | 1420 | |
5d990b62 CW |
1421 | /* Make sure ACS will be enabled */ |
1422 | pci_request_acs(); | |
ae7877de JR |
1423 | } |
1424 | } | |
1425 | ||
b65233a9 JR |
1426 | /**************************************************************************** |
1427 | * | |
1428 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1429 | * options. | |
1430 | * | |
1431 | ****************************************************************************/ | |
1432 | ||
fefda117 JR |
1433 | static int __init parse_amd_iommu_dump(char *str) |
1434 | { | |
1435 | amd_iommu_dump = true; | |
1436 | ||
1437 | return 1; | |
1438 | } | |
1439 | ||
918ad6c5 JR |
1440 | static int __init parse_amd_iommu_options(char *str) |
1441 | { | |
1442 | for (; *str; ++str) { | |
695b5676 | 1443 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1444 | amd_iommu_unmap_flush = true; |
a5235725 JR |
1445 | if (strncmp(str, "off", 3) == 0) |
1446 | amd_iommu_disabled = true; | |
918ad6c5 JR |
1447 | } |
1448 | ||
1449 | return 1; | |
1450 | } | |
1451 | ||
fefda117 | 1452 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1453 | __setup("amd_iommu=", parse_amd_iommu_options); |