[net-next-2.6.git] / arch / x86 / include / asm / pgtable_32.h

#ifndef _ASM_X86_PGTABLE_32_H
#define _ASM_X86_PGTABLE_32_H

#include <asm/pgtable_32_types.h>

/*
 * The Linux memory management assumes a three-level page table setup. On
 * the i386, we use that, but "fold" the mid level into the top-level page
 * table, so that we physically have the same two-level page table as the
 * i386 mmu expects.
 *
 * This file contains the functions and defines necessary to modify and use
 * the i386 page table tree.
 */
#ifndef __ASSEMBLY__
#include <asm/processor.h>
#include <asm/fixmap.h>
#include <linux/threads.h>
#include <asm/paravirt.h>

#include <linux/bitops.h>
#include <linux/list.h>
#include <linux/spinlock.h>

struct mm_struct;
struct vm_area_struct;

extern pgd_t swapper_pg_dir[1024];
extern pgd_t initial_page_table[1024];

static inline void pgtable_cache_init(void) { }
static inline void check_pgt_cache(void) { }
void paging_init(void);

extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t);


/*
 * Define this if things work differently on an i386 and an i486:
 * it will (on an i486) warn about kernel memory accesses that are
 * done without a 'access_ok(VERIFY_WRITE,..)'
 */
#undef TEST_ACCESS_OK

#ifdef CONFIG_X86_PAE
# include <asm/pgtable-3level.h>
#else
# include <asm/pgtable-2level.h>
#endif

#if defined(CONFIG_HIGHPTE)
#define pte_offset_map(dir, address)					\
	((pte_t *)kmap_atomic(pmd_page(*(dir))) +		\
	 pte_index((address)))
#define pte_unmap(pte) kunmap_atomic((pte))
#else
#define pte_offset_map(dir, address)					\
	((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
#define pte_unmap(pte) do { } while (0)
#endif

/* Clear a kernel PTE and flush it from the TLB */
#define kpte_clear_flush(ptep, vaddr)		\
do {						\
	pte_clear(&init_mm, (vaddr), (ptep));	\
	__flush_tlb_one((vaddr));		\
} while (0)

/*
 * The i386 doesn't have any external MMU info: the kernel page
 * tables contain all the necessary information.
 */
#define update_mmu_cache(vma, address, ptep) do { } while (0)

#endif /* !__ASSEMBLY__ */

/*
 * kern_addr_valid() is (1) for FLATMEM and (0) for
 * SPARSEMEM and DISCONTIGMEM
 */
#ifdef CONFIG_FLATMEM
#define kern_addr_valid(addr)	(1)
#else
#define kern_addr_valid(kaddr)	(0)
#endif

#endif /* _ASM_X86_PGTABLE_32_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_PGTABLE_32_H
1965aae3 PA	2	#define _ASM_X86_PGTABLE_32_H
1da177e4	3
f402a65f	4	#include <asm/pgtable_32_types.h>
1da177e4 LT	5
	6	/*
	7	* The Linux memory management assumes a three-level page table setup. On
	8	* the i386, we use that, but "fold" the mid level into the top-level page
	9	* table, so that we physically have the same two-level page table as the
	10	* i386 mmu expects.
	11	*
	12	* This file contains the functions and defines necessary to modify and use
	13	* the i386 page table tree.
	14	*/
	15	#ifndef __ASSEMBLY__
	16	#include <asm/processor.h>
	17	#include <asm/fixmap.h>
	18	#include <linux/threads.h>
da181a8b	19	#include <asm/paravirt.h>
1da177e4	20
1977f032	21	#include <linux/bitops.h>
1da177e4 LT	22	#include <linux/list.h>
	23	#include <linux/spinlock.h>
	24
8c65b4a6 TS	25	struct mm_struct;
	26	struct vm_area_struct;
	27
1da177e4	28	extern pgd_t swapper_pg_dir[1024];
b40827fa	29	extern pgd_t initial_page_table[1024];
1da177e4	30
985a34bd TG	31	static inline void pgtable_cache_init(void) { }
985a34bd TG	32	static inline void check_pgt_cache(void) { }
1da177e4 LT	33	void paging_init(void);
1da177e4 LT	34
01eb7858	35	extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t);
f1d1a842	36
e621bd18	37
1da177e4 LT	38	/*
	39	* Define this if things work differently on an i386 and an i486:
	40	* it will (on an i486) warn about kernel memory accesses that are
e49332bd	41	* done without a 'access_ok(VERIFY_WRITE,..)'
1da177e4	42	*/
e49332bd	43	#undef TEST_ACCESS_OK
1da177e4	44
1da177e4 LT	45	#ifdef CONFIG_X86_PAE
	46	# include <asm/pgtable-3level.h>
	47	#else
	48	# include <asm/pgtable-2level.h>
	49	#endif
	50
1da177e4	51	#if defined(CONFIG_HIGHPTE)
cf840147	52	#define pte_offset_map(dir, address) \
ece0e2b6	53	((pte_t )kmap_atomic(pmd_page((dir))) + \
cf840147	54	pte_index((address)))
ece0e2b6	55	#define pte_unmap(pte) kunmap_atomic((pte))
1da177e4	56	#else
cf840147 JP	57	#define pte_offset_map(dir, address) \
cf840147 JP	58	((pte_t )page_address(pmd_page((dir))) + pte_index((address)))
1da177e4	59	#define pte_unmap(pte) do { } while (0)
1da177e4 LT	60	#endif
1da177e4 LT	61
23002d88	62	/* Clear a kernel PTE and flush it from the TLB */
cf840147 JP	63	#define kpte_clear_flush(ptep, vaddr) \
	64	do { \
	65	pte_clear(&init_mm, (vaddr), (ptep)); \
	66	__flush_tlb_one((vaddr)); \
23002d88 ZA	67	} while (0)
23002d88 ZA	68
1da177e4 LT	69	/*
	70	* The i386 doesn't have any external MMU info: the kernel page
	71	* tables contain all the necessary information.
1da177e4	72	*/
4b3073e1	73	#define update_mmu_cache(vma, address, ptep) do { } while (0)
b239fb25	74
1da177e4 LT	75	#endif /* !__ASSEMBLY__ */
1da177e4 LT	76
4757d7d8 TG	77	/*
	78	* kern_addr_valid() is (1) for FLATMEM and (0) for
	79	* SPARSEMEM and DISCONTIGMEM
	80	*/
05b79bdc	81	#ifdef CONFIG_FLATMEM
1da177e4	82	#define kern_addr_valid(addr) (1)
4757d7d8 TG	83	#else
	84	#define kern_addr_valid(kaddr) (0)
	85	#endif
1da177e4	86
1965aae3	87	#endif /* _ASM_X86_PGTABLE_32_H */