[net-next-2.6.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define X86_PMC_MAX_GENERIC				       32
#define X86_PMC_MAX_FIXED					3

#define X86_PMC_IDX_GENERIC				        0
#define X86_PMC_IDX_FIXED				       32
#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_ENABLE			  (1 << 22)
#define ARCH_PERFMON_EVENTSEL_ANY			  (1 << 21)
#define ARCH_PERFMON_EVENTSEL_INT			  (1 << 20)
#define ARCH_PERFMON_EVENTSEL_OS			  (1 << 17)
#define ARCH_PERFMON_EVENTSEL_USR			  (1 << 16)

/*
 * Includes eventsel and unit mask as well:
 */


#define INTEL_ARCH_EVTSEL_MASK		0x000000FFULL
#define INTEL_ARCH_UNIT_MASK		0x0000FF00ULL
#define INTEL_ARCH_EDGE_MASK		0x00040000ULL
#define INTEL_ARCH_INV_MASK		0x00800000ULL
#define INTEL_ARCH_CNT_MASK		0xFF000000ULL
#define INTEL_ARCH_EVENT_MASK	(INTEL_ARCH_UNIT_MASK|INTEL_ARCH_EVTSEL_MASK)

/*
 * filter mask to validate fixed counter events.
 * the following filters disqualify for fixed counters:
 *  - inv
 *  - edge
 *  - cnt-mask
 *  The other filters are supported by fixed counters.
 *  The any-thread option is supported starting with v3.
 */
#define INTEL_ARCH_FIXED_MASK \
	(INTEL_ARCH_CNT_MASK| \
	 INTEL_ARCH_INV_MASK| \
	 INTEL_ARCH_EDGE_MASK|\
	 INTEL_ARCH_UNIT_MASK|\
	 INTEL_ARCH_EVENT_MASK)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		      0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX			 0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED			 6

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:4;
		unsigned int reserved:28;
	} split;
	unsigned int full;
};


/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL			0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0			0x309
#define X86_PMC_IDX_FIXED_INSTRUCTIONS			(X86_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1			0x30a
#define X86_PMC_IDX_FIXED_CPU_CYCLES			(X86_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2			0x30b
#define X86_PMC_IDX_FIXED_BUS_CYCLES			(X86_PMC_IDX_FIXED + 2)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)

/* IbsFetchCtl bits/masks */
#define IBS_FETCH_RAND_EN		(1ULL<<57)
#define IBS_FETCH_VAL			(1ULL<<49)
#define IBS_FETCH_ENABLE		(1ULL<<48)
#define IBS_FETCH_CNT			0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT		0x0000FFFFULL

/* IbsOpCtl bits */
#define IBS_OP_CNT_CTL			(1ULL<<19)
#define IBS_OP_VAL			(1ULL<<18)
#define IBS_OP_ENABLE			(1ULL<<17)
#define IBS_OP_MAX_CNT			0x0000FFFFULL

#ifdef CONFIG_PERF_EVENTS
extern void init_hw_perf_events(void);
extern void perf_events_lapic_init(void);

#define PERF_EVENT_INDEX_OFFSET			0

/*
 * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
 * This flag is otherwise unused and ABI specified to be 0, so nobody should
 * care what we do with it.
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)

#define perf_misc_flags(regs)				\
({	int misc = 0;					\
	if (user_mode(regs))				\
		misc |= PERF_RECORD_MISC_USER;		\
	else						\
		misc |= PERF_RECORD_MISC_KERNEL;	\
	if (regs->flags & PERF_EFLAGS_EXACT)		\
		misc |= PERF_RECORD_MISC_EXACT;		\
	misc; })

#define perf_instruction_pointer(regs)	((regs)->ip)

#else
static inline void init_hw_perf_events(void)		{ }
static inline void perf_events_lapic_init(void)	{ }
#endif

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
eb2b8618 IM	7
a072738e	8	#define X86_PMC_MAX_GENERIC 32
eb2b8618 IM	9	#define X86_PMC_MAX_FIXED 3
eb2b8618 IM	10
862a1a5f IM	11	#define X86_PMC_IDX_GENERIC 0
	12	#define X86_PMC_IDX_FIXED 32
	13	#define X86_PMC_IDX_MAX 64
	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
bb1165d6	21	#define ARCH_PERFMON_EVENTSEL_ENABLE (1 << 22)
b27d515a	22	#define ARCH_PERFMON_EVENTSEL_ANY (1 << 21)
241771ef IM	23	#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
	24	#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
	25	#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
003a46cf	26
2f18d1e8 IM	27	/*
	28	* Includes eventsel and unit mask as well:
	29	*/
1da53e02 SE	30
	31
	32	#define INTEL_ARCH_EVTSEL_MASK 0x000000FFULL
	33	#define INTEL_ARCH_UNIT_MASK 0x0000FF00ULL
	34	#define INTEL_ARCH_EDGE_MASK 0x00040000ULL
	35	#define INTEL_ARCH_INV_MASK 0x00800000ULL
	36	#define INTEL_ARCH_CNT_MASK 0xFF000000ULL
	37	#define INTEL_ARCH_EVENT_MASK (INTEL_ARCH_UNIT_MASK\|INTEL_ARCH_EVTSEL_MASK)
2f18d1e8	38
04a705df SE	39	/*
	40	* filter mask to validate fixed counter events.
	41	* the following filters disqualify for fixed counters:
	42	* - inv
	43	* - edge
	44	* - cnt-mask
	45	* The other filters are supported by fixed counters.
	46	* The any-thread option is supported starting with v3.
	47	*/
1da53e02 SE	48	#define INTEL_ARCH_FIXED_MASK \
	49	(INTEL_ARCH_CNT_MASK\| \
	50	INTEL_ARCH_INV_MASK\| \
	51	INTEL_ARCH_EDGE_MASK\|\
	52	INTEL_ARCH_UNIT_MASK\|\
b622d644	53	INTEL_ARCH_EVENT_MASK)
04a705df	54
241771ef IM	55	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef IM	56	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
04a705df	57	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	58	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	59	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
	60
	61	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
003a46cf	62
eb2b8618 IM	63	/*
	64	* Intel "Architectural Performance Monitoring" CPUID
	65	* detection/enumeration details:
	66	*/
003a46cf TG	67	union cpuid10_eax {
	68	struct {
	69	unsigned int version_id:8;
948b1bb8	70	unsigned int num_counters:8;
003a46cf TG	71	unsigned int bit_width:8;
	72	unsigned int mask_length:8;
	73	} split;
	74	unsigned int full;
	75	};
	76
703e937c IM	77	union cpuid10_edx {
703e937c IM	78	struct {
948b1bb8	79	unsigned int num_counters_fixed:4;
703e937c IM	80	unsigned int reserved:28;
	81	} split;
	82	unsigned int full;
	83	};
	84
	85
	86	/*
cdd6c482	87	* Fixed-purpose performance events:
703e937c IM	88	*/
703e937c IM	89
862a1a5f IM	90	/*
	91	* All 3 fixed-mode PMCs are configured via this single MSR:
	92	*/
	93	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
	94
	95	/*
	96	* The counts are available in three separate MSRs:
	97	*/
	98
703e937c IM	99	/* Instr_Retired.Any: */
703e937c IM	100	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
2f18d1e8	101	#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
703e937c IM	102
	103	/* CPU_CLK_Unhalted.Core: */
	104	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
2f18d1e8	105	#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
703e937c IM	106
	107	/* CPU_CLK_Unhalted.Ref: */
	108	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
2f18d1e8	109	#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
703e937c	110
30dd568c MM	111	/*
	112	* We model BTS tracing as another fixed-mode PMC.
	113	*
cdd6c482 IM	114	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	115	* values are used by actual fixed events and higher values are used
30dd568c MM	116	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
	117	*/
	118	#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
	119
1d6040f1 RR	120	/* IbsFetchCtl bits/masks */
	121	#define IBS_FETCH_RAND_EN (1ULL<<57)
	122	#define IBS_FETCH_VAL (1ULL<<49)
	123	#define IBS_FETCH_ENABLE (1ULL<<48)
a163b109 RR	124	#define IBS_FETCH_CNT 0xFFFF0000ULL
a163b109 RR	125	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1 RR	126
	127	/* IbsOpCtl bits */
	128	#define IBS_OP_CNT_CTL (1ULL<<19)
	129	#define IBS_OP_VAL (1ULL<<18)
	130	#define IBS_OP_ENABLE (1ULL<<17)
a163b109	131	#define IBS_OP_MAX_CNT 0x0000FFFFULL
30dd568c	132
cdd6c482 IM	133	#ifdef CONFIG_PERF_EVENTS
	134	extern void init_hw_perf_events(void);
	135	extern void perf_events_lapic_init(void);
194002b2	136
cdd6c482	137	#define PERF_EVENT_INDEX_OFFSET 0
194002b2	138
ef21f683 PZ	139	/*
	140	* Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
	141	* This flag is otherwise unused and ABI specified to be 0, so nobody should
	142	* care what we do with it.
	143	*/
	144	#define PERF_EFLAGS_EXACT (1UL << 3)
	145
	146	#define perf_misc_flags(regs) \
	147	({ int misc = 0; \
	148	if (user_mode(regs)) \
	149	misc \|= PERF_RECORD_MISC_USER; \
	150	else \
	151	misc \|= PERF_RECORD_MISC_KERNEL; \
	152	if (regs->flags & PERF_EFLAGS_EXACT) \
	153	misc \|= PERF_RECORD_MISC_EXACT; \
	154	misc; })
	155
	156	#define perf_instruction_pointer(regs) ((regs)->ip)
	157
241771ef	158	#else
cdd6c482 IM	159	static inline void init_hw_perf_events(void) { }
cdd6c482 IM	160	static inline void perf_events_lapic_init(void) { }
241771ef IM	161	#endif
241771ef IM	162
cdd6c482	163	#endif /* _ASM_X86_PERF_EVENT_H */