git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| af2730f6 JP |
1 | /* |
| 2 | * mrst.h: Intel Moorestown platform specific setup code | |
| 3 | * | |
| 4 | * (C) Copyright 2009 Intel Corporation | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * as published by the Free Software Foundation; version 2 | |
| 9 | * of the License. | |
| 10 | */ | |
| 11 | #ifndef _ASM_X86_MRST_H | |
| 12 | #define _ASM_X86_MRST_H | |
| 13 | extern int pci_mrst_init(void); | |
| cf089455 | 14 | int __init sfi_parse_mrtc(struct sfi_table_header *table); |
| af2730f6 | 15 | |
| a0c173bd JP |
16 | /* |
| 17 | * Medfield is the follow-up of Moorestown, it combines two chip solution into | |
| 18 | * one. Other than that it also added always-on and constant tsc and lapic | |
| 19 | * timers. Medfield is the platform name, and the chip name is called Penwell | |
| 20 | * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be | |
| 21 | * identified via MSRs. | |
| 22 | */ | |
| 23 | enum mrst_cpu_type { | |
| 24 | MRST_CPU_CHIP_LINCROFT = 1, | |
| 25 | MRST_CPU_CHIP_PENWELL, | |
| 26 | }; | |
| 27 | ||
| a75af580 PA |
28 | extern enum mrst_cpu_type __mrst_cpu_chip; |
| 29 | static enum mrst_cpu_type mrst_identify_cpu(void) | |
| 30 | { | |
| 31 | return __mrst_cpu_chip; | |
| 32 | } | |
| 33 | ||
| a0c173bd JP |
34 | enum mrst_timer_options { |
| 35 | MRST_TIMER_DEFAULT, | |
| 36 | MRST_TIMER_APBT_ONLY, | |
| 37 | MRST_TIMER_LAPIC_APBT, | |
| 38 | }; | |
| 39 | ||
| 14671386 PA |
40 | extern enum mrst_timer_options mrst_timer_options; |
| 41 | ||
| 16ab5395 | 42 | #define SFI_MTMR_MAX_NUM 8 |
| cf089455 | 43 | #define SFI_MRTC_MAX 8 |
| 16ab5395 | 44 | |
| af2730f6 | 45 | #endif /* _ASM_X86_MRST_H */ |