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Commit | Line | Data |
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1eeaed76 RM |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
1965aae3 PA |
10 | #ifndef _ASM_X86_I387_H |
11 | #define _ASM_X86_I387_H | |
1eeaed76 | 12 | |
3b0d6596 HX |
13 | #ifndef __ASSEMBLY__ |
14 | ||
1eeaed76 RM |
15 | #include <linux/sched.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/regset.h> | |
e4914012 | 18 | #include <linux/hardirq.h> |
86603283 | 19 | #include <linux/slab.h> |
92c37fa3 | 20 | #include <asm/asm.h> |
c9775b4c | 21 | #include <asm/cpufeature.h> |
1eeaed76 RM |
22 | #include <asm/processor.h> |
23 | #include <asm/sigcontext.h> | |
24 | #include <asm/user.h> | |
25 | #include <asm/uaccess.h> | |
dc1e35c6 | 26 | #include <asm/xsave.h> |
1eeaed76 | 27 | |
3c1c7f10 | 28 | extern unsigned int sig_xstate_size; |
1eeaed76 | 29 | extern void fpu_init(void); |
1eeaed76 | 30 | extern void mxcsr_feature_mask_init(void); |
aa283f49 | 31 | extern int init_fpu(struct task_struct *child); |
1eeaed76 | 32 | extern asmlinkage void math_state_restore(void); |
e6e9cac8 | 33 | extern void __math_state_restore(void); |
36454936 | 34 | extern int dump_fpu(struct pt_regs *, struct user_i387_struct *); |
1eeaed76 RM |
35 | |
36 | extern user_regset_active_fn fpregs_active, xfpregs_active; | |
5b3efd50 SS |
37 | extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get, |
38 | xstateregs_get; | |
39 | extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, | |
40 | xstateregs_set; | |
41 | ||
42 | /* | |
43 | * xstateregs_active == fpregs_active. Please refer to the comment | |
44 | * at the definition of fpregs_active. | |
45 | */ | |
46 | #define xstateregs_active fpregs_active | |
1eeaed76 | 47 | |
c37b5efe | 48 | extern struct _fpx_sw_bytes fx_sw_reserved; |
1eeaed76 | 49 | #ifdef CONFIG_IA32_EMULATION |
3c1c7f10 | 50 | extern unsigned int sig_xstate_ia32_size; |
c37b5efe | 51 | extern struct _fpx_sw_bytes fx_sw_reserved_ia32; |
1eeaed76 | 52 | struct _fpstate_ia32; |
ab513701 SS |
53 | struct _xstate_ia32; |
54 | extern int save_i387_xstate_ia32(void __user *buf); | |
55 | extern int restore_i387_xstate_ia32(void __user *buf); | |
1eeaed76 RM |
56 | #endif |
57 | ||
b359e8a4 SS |
58 | #define X87_FSW_ES (1 << 7) /* Exception Summary */ |
59 | ||
29104e10 SS |
60 | static __always_inline __pure bool use_xsaveopt(void) |
61 | { | |
6bad06b7 | 62 | return static_cpu_has(X86_FEATURE_XSAVEOPT); |
29104e10 SS |
63 | } |
64 | ||
c9775b4c | 65 | static __always_inline __pure bool use_xsave(void) |
c9ad4882 | 66 | { |
c9775b4c | 67 | return static_cpu_has(X86_FEATURE_XSAVE); |
c9ad4882 AK |
68 | } |
69 | ||
29104e10 SS |
70 | extern void __sanitize_i387_state(struct task_struct *); |
71 | ||
72 | static inline void sanitize_i387_state(struct task_struct *tsk) | |
73 | { | |
74 | if (!use_xsaveopt()) | |
75 | return; | |
76 | __sanitize_i387_state(tsk); | |
77 | } | |
78 | ||
1eeaed76 RM |
79 | #ifdef CONFIG_X86_64 |
80 | ||
81 | /* Ignore delayed exceptions from user space */ | |
82 | static inline void tolerant_fwait(void) | |
83 | { | |
84 | asm volatile("1: fwait\n" | |
85 | "2:\n" | |
affe6637 | 86 | _ASM_EXTABLE(1b, 2b)); |
1eeaed76 RM |
87 | } |
88 | ||
b359e8a4 | 89 | static inline int fxrstor_checking(struct i387_fxsave_struct *fx) |
1eeaed76 RM |
90 | { |
91 | int err; | |
92 | ||
93 | asm volatile("1: rex64/fxrstor (%[fx])\n\t" | |
94 | "2:\n" | |
95 | ".section .fixup,\"ax\"\n" | |
96 | "3: movl $-1,%[err]\n" | |
97 | " jmp 2b\n" | |
98 | ".previous\n" | |
affe6637 | 99 | _ASM_EXTABLE(1b, 3b) |
1eeaed76 | 100 | : [err] "=r" (err) |
4ecf4584 | 101 | #if 0 /* See comment in fxsave() below. */ |
1eeaed76 RM |
102 | : [fx] "r" (fx), "m" (*fx), "0" (0)); |
103 | #else | |
104 | : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0)); | |
105 | #endif | |
1eeaed76 RM |
106 | return err; |
107 | } | |
108 | ||
1eeaed76 RM |
109 | /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception |
110 | is pending. Clear the x87 state here by setting it to fixed | |
111 | values. The kernel data segment can be sometimes 0 and sometimes | |
112 | new user value. Both should be ok. | |
113 | Use the PDA as safe address because it should be already in L1. */ | |
86603283 | 114 | static inline void fpu_clear(struct fpu *fpu) |
1eeaed76 | 115 | { |
86603283 AK |
116 | struct xsave_struct *xstate = &fpu->state->xsave; |
117 | struct i387_fxsave_struct *fx = &fpu->state->fxsave; | |
b359e8a4 SS |
118 | |
119 | /* | |
120 | * xsave header may indicate the init state of the FP. | |
121 | */ | |
c9ad4882 | 122 | if (use_xsave() && |
b359e8a4 SS |
123 | !(xstate->xsave_hdr.xstate_bv & XSTATE_FP)) |
124 | return; | |
125 | ||
1eeaed76 | 126 | if (unlikely(fx->swd & X87_FSW_ES)) |
affe6637 | 127 | asm volatile("fnclex"); |
1eeaed76 | 128 | alternative_input(ASM_NOP8 ASM_NOP2, |
affe6637 JP |
129 | " emms\n" /* clear stack tags */ |
130 | " fildl %%gs:0", /* load to clear state */ | |
131 | X86_FEATURE_FXSAVE_LEAK); | |
1eeaed76 RM |
132 | } |
133 | ||
86603283 AK |
134 | static inline void clear_fpu_state(struct task_struct *tsk) |
135 | { | |
136 | fpu_clear(&tsk->thread.fpu); | |
137 | } | |
138 | ||
c37b5efe | 139 | static inline int fxsave_user(struct i387_fxsave_struct __user *fx) |
1eeaed76 RM |
140 | { |
141 | int err; | |
142 | ||
8e221b6d SS |
143 | /* |
144 | * Clear the bytes not touched by the fxsave and reserved | |
145 | * for the SW usage. | |
146 | */ | |
147 | err = __clear_user(&fx->sw_reserved, | |
148 | sizeof(struct _fpx_sw_bytes)); | |
149 | if (unlikely(err)) | |
150 | return -EFAULT; | |
151 | ||
1eeaed76 RM |
152 | asm volatile("1: rex64/fxsave (%[fx])\n\t" |
153 | "2:\n" | |
154 | ".section .fixup,\"ax\"\n" | |
155 | "3: movl $-1,%[err]\n" | |
156 | " jmp 2b\n" | |
157 | ".previous\n" | |
affe6637 | 158 | _ASM_EXTABLE(1b, 3b) |
1eeaed76 | 159 | : [err] "=r" (err), "=m" (*fx) |
4ecf4584 | 160 | #if 0 /* See comment in fxsave() below. */ |
1eeaed76 RM |
161 | : [fx] "r" (fx), "0" (0)); |
162 | #else | |
163 | : [fx] "cdaSDb" (fx), "0" (0)); | |
164 | #endif | |
affe6637 JP |
165 | if (unlikely(err) && |
166 | __clear_user(fx, sizeof(struct i387_fxsave_struct))) | |
1eeaed76 RM |
167 | err = -EFAULT; |
168 | /* No need to clear here because the caller clears USED_MATH */ | |
169 | return err; | |
170 | } | |
171 | ||
86603283 | 172 | static inline void fpu_fxsave(struct fpu *fpu) |
1eeaed76 RM |
173 | { |
174 | /* Using "rex64; fxsave %0" is broken because, if the memory operand | |
175 | uses any extended registers for addressing, a second REX prefix | |
176 | will be generated (to the assembler, rex64 followed by semicolon | |
177 | is a separate instruction), and hence the 64-bitness is lost. */ | |
d7acb92f | 178 | #ifdef CONFIG_AS_FXSAVEQ |
1eeaed76 RM |
179 | /* Using "fxsaveq %0" would be the ideal choice, but is only supported |
180 | starting with gas 2.16. */ | |
181 | __asm__ __volatile__("fxsaveq %0" | |
86603283 | 182 | : "=m" (fpu->state->fxsave)); |
1eeaed76 RM |
183 | #elif 0 |
184 | /* Using, as a workaround, the properly prefixed form below isn't | |
185 | accepted by any binutils version so far released, complaining that | |
186 | the same type of prefix is used twice if an extended register is | |
187 | needed for addressing (fix submitted to mainline 2005-11-21). */ | |
188 | __asm__ __volatile__("rex64/fxsave %0" | |
86603283 | 189 | : "=m" (fpu->state->fxsave)); |
1eeaed76 RM |
190 | #else |
191 | /* This, however, we can work around by forcing the compiler to select | |
192 | an addressing mode that doesn't require extended registers. */ | |
61c4628b | 193 | __asm__ __volatile__("rex64/fxsave (%1)" |
86603283 AK |
194 | : "=m" (fpu->state->fxsave) |
195 | : "cdaSDb" (&fpu->state->fxsave)); | |
1eeaed76 | 196 | #endif |
b359e8a4 SS |
197 | } |
198 | ||
86603283 | 199 | static inline void fpu_save_init(struct fpu *fpu) |
b359e8a4 | 200 | { |
c9ad4882 | 201 | if (use_xsave()) |
86603283 | 202 | fpu_xsave(fpu); |
b359e8a4 | 203 | else |
86603283 | 204 | fpu_fxsave(fpu); |
b359e8a4 | 205 | |
86603283 AK |
206 | fpu_clear(fpu); |
207 | } | |
208 | ||
209 | static inline void __save_init_fpu(struct task_struct *tsk) | |
210 | { | |
211 | fpu_save_init(&tsk->thread.fpu); | |
1eeaed76 RM |
212 | task_thread_info(tsk)->status &= ~TS_USEDFPU; |
213 | } | |
214 | ||
1eeaed76 RM |
215 | #else /* CONFIG_X86_32 */ |
216 | ||
ab9e1858 | 217 | #ifdef CONFIG_MATH_EMULATION |
86603283 | 218 | extern void finit_soft_fpu(struct i387_soft_struct *soft); |
ab9e1858 | 219 | #else |
86603283 | 220 | static inline void finit_soft_fpu(struct i387_soft_struct *soft) {} |
ab9e1858 | 221 | #endif |
e8a496ac | 222 | |
1eeaed76 RM |
223 | static inline void tolerant_fwait(void) |
224 | { | |
225 | asm volatile("fnclex ; fwait"); | |
226 | } | |
227 | ||
34ba476a JS |
228 | /* perform fxrstor iff the processor has extended states, otherwise frstor */ |
229 | static inline int fxrstor_checking(struct i387_fxsave_struct *fx) | |
1eeaed76 RM |
230 | { |
231 | /* | |
232 | * The "nop" is needed to make the instructions the same | |
233 | * length. | |
234 | */ | |
235 | alternative_input( | |
236 | "nop ; frstor %1", | |
237 | "fxrstor %1", | |
238 | X86_FEATURE_FXSR, | |
34ba476a JS |
239 | "m" (*fx)); |
240 | ||
fcb2ac5b | 241 | return 0; |
1eeaed76 RM |
242 | } |
243 | ||
244 | /* We need a safe address that is cheap to find and that is already | |
245 | in L1 during context switch. The best choices are unfortunately | |
246 | different for UP and SMP */ | |
247 | #ifdef CONFIG_SMP | |
248 | #define safe_address (__per_cpu_offset[0]) | |
249 | #else | |
250 | #define safe_address (kstat_cpu(0).cpustat.user) | |
251 | #endif | |
252 | ||
253 | /* | |
254 | * These must be called with preempt disabled | |
255 | */ | |
86603283 | 256 | static inline void fpu_save_init(struct fpu *fpu) |
1eeaed76 | 257 | { |
c9ad4882 | 258 | if (use_xsave()) { |
86603283 AK |
259 | struct xsave_struct *xstate = &fpu->state->xsave; |
260 | struct i387_fxsave_struct *fx = &fpu->state->fxsave; | |
b359e8a4 | 261 | |
86603283 | 262 | fpu_xsave(fpu); |
b359e8a4 SS |
263 | |
264 | /* | |
265 | * xsave header may indicate the init state of the FP. | |
266 | */ | |
267 | if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP)) | |
268 | goto end; | |
269 | ||
270 | if (unlikely(fx->swd & X87_FSW_ES)) | |
271 | asm volatile("fnclex"); | |
272 | ||
273 | /* | |
274 | * we can do a simple return here or be paranoid :) | |
275 | */ | |
276 | goto clear_state; | |
277 | } | |
278 | ||
1eeaed76 RM |
279 | /* Use more nops than strictly needed in case the compiler |
280 | varies code */ | |
281 | alternative_input( | |
282 | "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4, | |
283 | "fxsave %[fx]\n" | |
284 | "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:", | |
285 | X86_FEATURE_FXSR, | |
86603283 AK |
286 | [fx] "m" (fpu->state->fxsave), |
287 | [fsw] "m" (fpu->state->fxsave.swd) : "memory"); | |
b359e8a4 | 288 | clear_state: |
1eeaed76 RM |
289 | /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception |
290 | is pending. Clear the x87 state here by setting it to fixed | |
291 | values. safe_address is a random variable that should be in L1 */ | |
292 | alternative_input( | |
293 | GENERIC_NOP8 GENERIC_NOP2, | |
294 | "emms\n\t" /* clear stack tags */ | |
295 | "fildl %[addr]", /* set F?P to defined value */ | |
296 | X86_FEATURE_FXSAVE_LEAK, | |
297 | [addr] "m" (safe_address)); | |
b359e8a4 | 298 | end: |
86603283 AK |
299 | ; |
300 | } | |
301 | ||
302 | static inline void __save_init_fpu(struct task_struct *tsk) | |
303 | { | |
304 | fpu_save_init(&tsk->thread.fpu); | |
1eeaed76 RM |
305 | task_thread_info(tsk)->status &= ~TS_USEDFPU; |
306 | } | |
307 | ||
86603283 | 308 | |
ab513701 SS |
309 | #endif /* CONFIG_X86_64 */ |
310 | ||
86603283 AK |
311 | static inline int fpu_fxrstor_checking(struct fpu *fpu) |
312 | { | |
313 | return fxrstor_checking(&fpu->state->fxsave); | |
314 | } | |
315 | ||
316 | static inline int fpu_restore_checking(struct fpu *fpu) | |
34ba476a | 317 | { |
c9ad4882 | 318 | if (use_xsave()) |
86603283 | 319 | return fpu_xrstor_checking(fpu); |
34ba476a | 320 | else |
86603283 AK |
321 | return fpu_fxrstor_checking(fpu); |
322 | } | |
323 | ||
324 | static inline int restore_fpu_checking(struct task_struct *tsk) | |
325 | { | |
326 | return fpu_restore_checking(&tsk->thread.fpu); | |
34ba476a JS |
327 | } |
328 | ||
1eeaed76 RM |
329 | /* |
330 | * Signal frame handlers... | |
331 | */ | |
ab513701 SS |
332 | extern int save_i387_xstate(void __user *buf); |
333 | extern int restore_i387_xstate(void __user *buf); | |
1eeaed76 RM |
334 | |
335 | static inline void __unlazy_fpu(struct task_struct *tsk) | |
336 | { | |
337 | if (task_thread_info(tsk)->status & TS_USEDFPU) { | |
338 | __save_init_fpu(tsk); | |
339 | stts(); | |
340 | } else | |
341 | tsk->fpu_counter = 0; | |
342 | } | |
343 | ||
344 | static inline void __clear_fpu(struct task_struct *tsk) | |
345 | { | |
346 | if (task_thread_info(tsk)->status & TS_USEDFPU) { | |
347 | tolerant_fwait(); | |
348 | task_thread_info(tsk)->status &= ~TS_USEDFPU; | |
349 | stts(); | |
350 | } | |
351 | } | |
352 | ||
353 | static inline void kernel_fpu_begin(void) | |
354 | { | |
355 | struct thread_info *me = current_thread_info(); | |
356 | preempt_disable(); | |
357 | if (me->status & TS_USEDFPU) | |
358 | __save_init_fpu(me->task); | |
359 | else | |
360 | clts(); | |
361 | } | |
362 | ||
363 | static inline void kernel_fpu_end(void) | |
364 | { | |
365 | stts(); | |
366 | preempt_enable(); | |
367 | } | |
368 | ||
ae4b688d HY |
369 | static inline bool irq_fpu_usable(void) |
370 | { | |
371 | struct pt_regs *regs; | |
372 | ||
373 | return !in_interrupt() || !(regs = get_irq_regs()) || \ | |
374 | user_mode(regs) || (read_cr0() & X86_CR0_TS); | |
375 | } | |
376 | ||
e4914012 SS |
377 | /* |
378 | * Some instructions like VIA's padlock instructions generate a spurious | |
379 | * DNA fault but don't modify SSE registers. And these instructions | |
0b8c3d5a CE |
380 | * get used from interrupt context as well. To prevent these kernel instructions |
381 | * in interrupt context interacting wrongly with other user/kernel fpu usage, we | |
e4914012 SS |
382 | * should use them only in the context of irq_ts_save/restore() |
383 | */ | |
384 | static inline int irq_ts_save(void) | |
385 | { | |
386 | /* | |
0b8c3d5a CE |
387 | * If in process context and not atomic, we can take a spurious DNA fault. |
388 | * Otherwise, doing clts() in process context requires disabling preemption | |
389 | * or some heavy lifting like kernel_fpu_begin() | |
e4914012 | 390 | */ |
0b8c3d5a | 391 | if (!in_atomic()) |
e4914012 SS |
392 | return 0; |
393 | ||
394 | if (read_cr0() & X86_CR0_TS) { | |
395 | clts(); | |
396 | return 1; | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static inline void irq_ts_restore(int TS_state) | |
403 | { | |
404 | if (TS_state) | |
405 | stts(); | |
406 | } | |
407 | ||
1eeaed76 RM |
408 | #ifdef CONFIG_X86_64 |
409 | ||
410 | static inline void save_init_fpu(struct task_struct *tsk) | |
411 | { | |
412 | __save_init_fpu(tsk); | |
413 | stts(); | |
414 | } | |
415 | ||
416 | #define unlazy_fpu __unlazy_fpu | |
417 | #define clear_fpu __clear_fpu | |
418 | ||
419 | #else /* CONFIG_X86_32 */ | |
420 | ||
421 | /* | |
422 | * These disable preemption on their own and are safe | |
423 | */ | |
424 | static inline void save_init_fpu(struct task_struct *tsk) | |
425 | { | |
426 | preempt_disable(); | |
427 | __save_init_fpu(tsk); | |
428 | stts(); | |
429 | preempt_enable(); | |
430 | } | |
431 | ||
432 | static inline void unlazy_fpu(struct task_struct *tsk) | |
433 | { | |
434 | preempt_disable(); | |
435 | __unlazy_fpu(tsk); | |
436 | preempt_enable(); | |
437 | } | |
438 | ||
439 | static inline void clear_fpu(struct task_struct *tsk) | |
440 | { | |
441 | preempt_disable(); | |
442 | __clear_fpu(tsk); | |
443 | preempt_enable(); | |
444 | } | |
445 | ||
446 | #endif /* CONFIG_X86_64 */ | |
447 | ||
1eeaed76 RM |
448 | /* |
449 | * i387 state interaction | |
450 | */ | |
451 | static inline unsigned short get_fpu_cwd(struct task_struct *tsk) | |
452 | { | |
453 | if (cpu_has_fxsr) { | |
86603283 | 454 | return tsk->thread.fpu.state->fxsave.cwd; |
1eeaed76 | 455 | } else { |
86603283 | 456 | return (unsigned short)tsk->thread.fpu.state->fsave.cwd; |
1eeaed76 RM |
457 | } |
458 | } | |
459 | ||
460 | static inline unsigned short get_fpu_swd(struct task_struct *tsk) | |
461 | { | |
462 | if (cpu_has_fxsr) { | |
86603283 | 463 | return tsk->thread.fpu.state->fxsave.swd; |
1eeaed76 | 464 | } else { |
86603283 | 465 | return (unsigned short)tsk->thread.fpu.state->fsave.swd; |
1eeaed76 RM |
466 | } |
467 | } | |
468 | ||
469 | static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk) | |
470 | { | |
471 | if (cpu_has_xmm) { | |
86603283 | 472 | return tsk->thread.fpu.state->fxsave.mxcsr; |
1eeaed76 RM |
473 | } else { |
474 | return MXCSR_DEFAULT; | |
475 | } | |
476 | } | |
477 | ||
86603283 AK |
478 | static bool fpu_allocated(struct fpu *fpu) |
479 | { | |
480 | return fpu->state != NULL; | |
481 | } | |
482 | ||
483 | static inline int fpu_alloc(struct fpu *fpu) | |
484 | { | |
485 | if (fpu_allocated(fpu)) | |
486 | return 0; | |
487 | fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL); | |
488 | if (!fpu->state) | |
489 | return -ENOMEM; | |
490 | WARN_ON((unsigned long)fpu->state & 15); | |
491 | return 0; | |
492 | } | |
493 | ||
494 | static inline void fpu_free(struct fpu *fpu) | |
495 | { | |
496 | if (fpu->state) { | |
497 | kmem_cache_free(task_xstate_cachep, fpu->state); | |
498 | fpu->state = NULL; | |
499 | } | |
500 | } | |
501 | ||
502 | static inline void fpu_copy(struct fpu *dst, struct fpu *src) | |
503 | { | |
504 | memcpy(dst->state, src->state, xstate_size); | |
505 | } | |
506 | ||
5ee481da SY |
507 | extern void fpu_finit(struct fpu *fpu); |
508 | ||
3b0d6596 HX |
509 | #endif /* __ASSEMBLY__ */ |
510 | ||
511 | #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5 | |
512 | #define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5 | |
513 | ||
1965aae3 | 514 | #endif /* _ASM_X86_I387_H */ |