[net-next-2.6.git] / arch / x86 / include / asm / gart.h

#ifndef _ASM_X86_GART_H
#define _ASM_X86_GART_H

#include <asm/e820.h>

extern void set_up_gart_resume(u32, u32);

extern int fallback_aper_order;
extern int fallback_aper_force;
extern int fix_aperture;

/* PTE bits. */
#define GPTE_VALID	1
#define GPTE_COHERENT	2

/* Aperture control register bits. */
#define GARTEN		(1<<0)
#define DISGARTCPU	(1<<4)
#define DISGARTIO	(1<<5)
#define DISTLBWALKPRB	(1<<6)

/* GART cache control register bits. */
#define INVGART		(1<<0)
#define GARTPTEERR	(1<<1)

/* K8 On-cpu GART registers */
#define AMD64_GARTAPERTURECTL	0x90
#define AMD64_GARTAPERTUREBASE	0x94
#define AMD64_GARTTABLEBASE	0x98
#define AMD64_GARTCACHECTL	0x9c

#ifdef CONFIG_GART_IOMMU
extern int gart_iommu_aperture;
extern int gart_iommu_aperture_allowed;
extern int gart_iommu_aperture_disabled;

extern void early_gart_iommu_check(void);
extern int gart_iommu_init(void);
extern void __init gart_parse_options(char *);
extern void gart_iommu_hole_init(void);

#else
#define gart_iommu_aperture            0
#define gart_iommu_aperture_allowed    0
#define gart_iommu_aperture_disabled   1

static inline void early_gart_iommu_check(void)
{
}
static inline void gart_parse_options(char *options)
{
}
static inline void gart_iommu_hole_init(void)
{
}
#endif

extern int agp_amd64_init(void);

static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
{
	u32 ctl;

	/*
	 * Don't enable translation but enable GART IO and CPU accesses.
	 * Also, set DISTLBWALKPRB since GART tables memory is UC.
	 */
	ctl = DISTLBWALKPRB | order << 1;

	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
}

static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
{
	u32 tmp, ctl;

        /* address of the mappings table */
        addr >>= 12;
        tmp = (u32) addr<<4;
        tmp &= ~0xf;
        pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);

        /* Enable GART translation for this hammer. */
        pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
        ctl |= GARTEN;
        ctl &= ~(DISGARTCPU | DISGARTIO);
        pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
}

static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
{
	if (!aper_base)
		return 0;

	if (aper_base + aper_size > 0x100000000ULL) {
		printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
		return 0;
	}
	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
		printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
		return 0;
	}
	if (aper_size < min_size) {
		printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
				 aper_size>>20, min_size>>20);
		return 0;
	}

	return 1;
}

#endif /* _ASM_X86_GART_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_GART_H
1965aae3 PA	2	#define _ASM_X86_GART_H
395624fc	3
0abbc78a PM	4	#include <asm/e820.h>
0abbc78a PM	5
6703f6d1	6	extern void set_up_gart_resume(u32, u32);
e93be88d	7
395624fc JR	8	extern int fallback_aper_order;
395624fc JR	9	extern int fallback_aper_force;
395624fc	10	extern int fix_aperture;
395624fc	11
aa134f1b PM	12	/* PTE bits. */
	13	#define GPTE_VALID 1
	14	#define GPTE_COHERENT 2
	15
	16	/* Aperture control register bits. */
	17	#define GARTEN (1<<0)
	18	#define DISGARTCPU (1<<4)
	19	#define DISGARTIO (1<<5)
260133ab	20	#define DISTLBWALKPRB (1<<6)
aa134f1b PM	21
	22	/* GART cache control register bits. */
	23	#define INVGART (1<<0)
	24	#define GARTPTEERR (1<<1)
	25
	26	/* K8 On-cpu GART registers */
	27	#define AMD64_GARTAPERTURECTL 0x90
	28	#define AMD64_GARTAPERTUREBASE 0x94
	29	#define AMD64_GARTTABLEBASE 0x98
	30	#define AMD64_GARTCACHECTL 0x9c
aa134f1b	31
1d9b16d1 JR	32	#ifdef CONFIG_GART_IOMMU
	33	extern int gart_iommu_aperture;
	34	extern int gart_iommu_aperture_allowed;
	35	extern int gart_iommu_aperture_disabled;
	36
	37	extern void early_gart_iommu_check(void);
de957628	38	extern int gart_iommu_init(void);
1d9b16d1 JR	39	extern void __init gart_parse_options(char *);
	40	extern void gart_iommu_hole_init(void);
	41
	42	#else
	43	#define gart_iommu_aperture 0
	44	#define gart_iommu_aperture_allowed 0
	45	#define gart_iommu_aperture_disabled 1
	46
	47	static inline void early_gart_iommu_check(void)
	48	{
	49	}
1d9b16d1 JR	50	static inline void gart_parse_options(char *options)
	51	{
	52	}
	53	static inline void gart_iommu_hole_init(void)
	54	{
	55	}
	56	#endif
	57
237a6224 JR	58	extern int agp_amd64_init(void);
237a6224 JR	59
260133ab BP	60	static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
	61	{
	62	u32 ctl;
	63
	64	/*
	65	* Don't enable translation but enable GART IO and CPU accesses.
	66	* Also, set DISTLBWALKPRB since GART tables memory is UC.
	67	*/
	68	ctl = DISTLBWALKPRB \| order << 1;
	69
	70	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
	71	}
	72
3bb6fbf9 PM	73	static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
	74	{
	75	u32 tmp, ctl;
	76
	77	/* address of the mappings table */
	78	addr >>= 12;
	79	tmp = (u32) addr<<4;
	80	tmp &= ~0xf;
	81	pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
	82
	83	/* Enable GART translation for this hammer. */
	84	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
	85	ctl \|= GARTEN;
	86	ctl &= ~(DISGARTCPU \| DISGARTIO);
	87	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
	88	}
	89
0abbc78a PM	90	static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
	91	{
	92	if (!aper_base)
	93	return 0;
	94
	95	if (aper_base + aper_size > 0x100000000ULL) {
9b156845	96	printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
0abbc78a PM	97	return 0;
	98	}
	99	if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
9b156845	100	printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
0abbc78a PM	101	return 0;
	102	}
	103	if (aper_size < min_size) {
9b156845	104	printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
0abbc78a PM	105	aper_size>>20, min_size>>20);
	106	return 0;
	107	}
	108
	109	return 1;
	110	}
	111
1965aae3	112	#endif /* _ASM_X86_GART_H */