[net-next-2.6.git] / arch / x86 / include / asm / apic.h

#ifndef _ASM_X86_APIC_H
#define _ASM_X86_APIC_H

#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/pm.h>

#include <asm/alternative.h>
#include <asm/cpufeature.h>
#include <asm/processor.h>
#include <asm/apicdef.h>
#include <asm/atomic.h>
#include <asm/fixmap.h>
#include <asm/mpspec.h>
#include <asm/system.h>
#include <asm/msr.h>

#define ARCH_APICTIMER_STOPS_ON_C3	1

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)


#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
extern void generic_apic_probe(void);
#else
static inline void generic_apic_probe(void)
{
}
#endif

#ifdef CONFIG_X86_LOCAL_APIC

extern unsigned int apic_verbosity;
extern int local_apic_timer_c2_ok;

extern int disable_apic;

#ifdef CONFIG_SMP
extern void __inquire_remote_apic(int apicid);
#else /* CONFIG_SMP */
static inline void __inquire_remote_apic(int apicid)
{
}
#endif /* CONFIG_SMP */

static inline void default_inquire_remote_apic(int apicid)
{
	if (apic_verbosity >= APIC_DEBUG)
		__inquire_remote_apic(apicid);
}

/*
 * With 82489DX we can't rely on apic feature bit
 * retrieved via cpuid but still have to deal with
 * such an apic chip so we assume that SMP configuration
 * is found from MP table (64bit case uses ACPI mostly
 * which set smp presence flag as well so we are safe
 * to use this helper too).
 */
static inline bool apic_from_smp_config(void)
{
	return smp_found_config && !disable_apic;
}

/*
 * Basic functions accessing APICs.
 */
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#endif

#ifdef CONFIG_X86_64
extern int is_vsmp_box(void);
#else
static inline int is_vsmp_box(void)
{
	return 0;
}
#endif
extern void xapic_wait_icr_idle(void);
extern u32 safe_xapic_wait_icr_idle(void);
extern void xapic_icr_write(u32, u32);
extern int setup_profiling_timer(unsigned int);

static inline void native_apic_mem_write(u32 reg, u32 v)
{
	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);

	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
		       ASM_OUTPUT2("0" (v), "m" (*addr)));
}

static inline u32 native_apic_mem_read(u32 reg)
{
	return *((volatile u32 *)(APIC_BASE + reg));
}

extern void native_apic_wait_icr_idle(void);
extern u32 native_safe_apic_wait_icr_idle(void);
extern void native_apic_icr_write(u32 low, u32 id);
extern u64 native_apic_icr_read(void);

extern int x2apic_mode;

#ifdef CONFIG_X86_X2APIC
/*
 * Make previous memory operations globally visible before
 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 * mfence for this.
 */
static inline void x2apic_wrmsr_fence(void)
{
	asm volatile("mfence" : : : "memory");
}

static inline void native_apic_msr_write(u32 reg, u32 v)
{
	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
	    reg == APIC_LVR)
		return;

	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
}

static inline u32 native_apic_msr_read(u32 reg)
{
	u64 msr;

	if (reg == APIC_DFR)
		return -1;

	rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
	return (u32)msr;
}

static inline void native_x2apic_wait_icr_idle(void)
{
	/* no need to wait for icr idle in x2apic */
	return;
}

static inline u32 native_safe_x2apic_wait_icr_idle(void)
{
	/* no need to wait for icr idle in x2apic */
	return 0;
}

static inline void native_x2apic_icr_write(u32 low, u32 id)
{
	wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
}

static inline u64 native_x2apic_icr_read(void)
{
	unsigned long val;

	rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
	return val;
}

extern int x2apic_phys;
extern void check_x2apic(void);
extern void enable_x2apic(void);
extern void x2apic_icr_write(u32 low, u32 id);
static inline int x2apic_enabled(void)
{
	u64 msr;

	if (!cpu_has_x2apic)
		return 0;

	rdmsrl(MSR_IA32_APICBASE, msr);
	if (msr & X2APIC_ENABLE)
		return 1;
	return 0;
}

#define x2apic_supported()	(cpu_has_x2apic)
static inline void x2apic_force_phys(void)
{
	x2apic_phys = 1;
}
#else
static inline void check_x2apic(void)
{
}
static inline void enable_x2apic(void)
{
}
static inline int x2apic_enabled(void)
{
	return 0;
}
static inline void x2apic_force_phys(void)
{
}

#define	x2apic_preenabled 0
#define	x2apic_supported()	0
#endif

extern void enable_IR_x2apic(void);

extern int get_physical_broadcast(void);

extern void apic_disable(void);
extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
extern void lapic_shutdown(void);
extern int verify_local_APIC(void);
extern void cache_APIC_registers(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void setup_local_APIC(void);
extern void end_local_APIC_setup(void);
extern void init_apic_mappings(void);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern int APIC_init_uniprocessor(void);
extern void enable_NMI_through_LVT0(void);

/*
 * On 32bit this is mach-xxx local
 */
#ifdef CONFIG_X86_64
extern void early_init_lapic_mapping(void);
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
	return 0;
}
#endif

extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);

#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok		1
static inline void init_apic_mappings(void) { }
static inline void disable_local_APIC(void) { }
static inline void apic_disable(void) { }
# define setup_boot_APIC_clock x86_init_noop
# define setup_secondary_APIC_clock x86_init_noop
#endif /* !CONFIG_X86_LOCAL_APIC */

#ifdef CONFIG_X86_64
#define	SET_APIC_ID(x)		(apic->set_apic_id(x))
#else

#endif

/*
 * Copyright 2004 James Cleverdon, IBM.
 * Subject to the GNU Public License, v.2
 *
 * Generic APIC sub-arch data struct.
 *
 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 * James Cleverdon.
 */
struct apic {
	char *name;

	int (*probe)(void);
	int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
	int (*apic_id_registered)(void);

	u32 irq_delivery_mode;
	u32 irq_dest_mode;

	const struct cpumask *(*target_cpus)(void);

	int disable_esr;

	int dest_logical;
	unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
	unsigned long (*check_apicid_present)(int apicid);

	void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
	void (*init_apic_ldr)(void);

	void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);

	void (*setup_apic_routing)(void);
	int (*multi_timer_check)(int apic, int irq);
	int (*apicid_to_node)(int logical_apicid);
	int (*cpu_to_logical_apicid)(int cpu);
	int (*cpu_present_to_apicid)(int mps_cpu);
	void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
	void (*setup_portio_remap)(void);
	int (*check_phys_apicid_present)(int phys_apicid);
	void (*enable_apic_mode)(void);
	int (*phys_pkg_id)(int cpuid_apic, int index_msb);

	/*
	 * When one of the next two hooks returns 1 the apic
	 * is switched to this. Essentially they are additional
	 * probe functions:
	 */
	int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);

	unsigned int (*get_apic_id)(unsigned long x);
	unsigned long (*set_apic_id)(unsigned int id);
	unsigned long apic_id_mask;

	unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
	unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
					       const struct cpumask *andmask);

	/* ipi */
	void (*send_IPI_mask)(const struct cpumask *mask, int vector);
	void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
					 int vector);
	void (*send_IPI_allbutself)(int vector);
	void (*send_IPI_all)(int vector);
	void (*send_IPI_self)(int vector);

	/* wakeup_secondary_cpu */
	int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);

	int trampoline_phys_low;
	int trampoline_phys_high;

	void (*wait_for_init_deassert)(atomic_t *deassert);
	void (*smp_callin_clear_local_apic)(void);
	void (*inquire_remote_apic)(int apicid);

	/* apic ops */
	u32 (*read)(u32 reg);
	void (*write)(u32 reg, u32 v);
	u64 (*icr_read)(void);
	void (*icr_write)(u32 low, u32 high);
	void (*wait_icr_idle)(void);
	u32 (*safe_wait_icr_idle)(void);
};

/*
 * Pointer to the local APIC driver in use on this system (there's
 * always just one such driver in use - the kernel decides via an
 * early probing process which one it picks - and then sticks to it):
 */
extern struct apic *apic;

/*
 * APIC functionality to boot other CPUs - only used on SMP:
 */
#ifdef CONFIG_SMP
extern atomic_t init_deasserted;
extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
#endif

#ifdef CONFIG_X86_LOCAL_APIC
static inline u32 apic_read(u32 reg)
{
	return apic->read(reg);
}

static inline void apic_write(u32 reg, u32 val)
{
	apic->write(reg, val);
}

static inline u64 apic_icr_read(void)
{
	return apic->icr_read();
}

static inline void apic_icr_write(u32 low, u32 high)
{
	apic->icr_write(low, high);
}

static inline void apic_wait_icr_idle(void)
{
	apic->wait_icr_idle();
}

static inline u32 safe_apic_wait_icr_idle(void)
{
	return apic->safe_wait_icr_idle();
}

#else /* CONFIG_X86_LOCAL_APIC */

static inline u32 apic_read(u32 reg) { return 0; }
static inline void apic_write(u32 reg, u32 val) { }
static inline u64 apic_icr_read(void) { return 0; }
static inline void apic_icr_write(u32 low, u32 high) { }
static inline void apic_wait_icr_idle(void) { }
static inline u32 safe_apic_wait_icr_idle(void) { return 0; }

#endif /* CONFIG_X86_LOCAL_APIC */

static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction
	 * ... yummie.
	 */

	/* Docs say use 0 for future compatibility */
	apic_write(APIC_EOI, 0);
}

static inline unsigned default_get_apic_id(unsigned long x)
{
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));

	if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
		return (x >> 24) & 0xFF;
	else
		return (x >> 24) & 0x0F;
}

/*
 * Warm reset vector default position:
 */
#define DEFAULT_TRAMPOLINE_PHYS_LOW		0x467
#define DEFAULT_TRAMPOLINE_PHYS_HIGH		0x469

#ifdef CONFIG_X86_64
extern struct apic apic_flat;
extern struct apic apic_physflat;
extern struct apic apic_x2apic_cluster;
extern struct apic apic_x2apic_phys;
extern int default_acpi_madt_oem_check(char *, char *);

extern void apic_send_IPI_self(int vector);

extern struct apic apic_x2apic_uv_x;
DECLARE_PER_CPU(int, x2apic_extra_bits);

extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);
#endif

static inline void default_wait_for_init_deassert(atomic_t *deassert)
{
	while (!atomic_read(deassert))
		cpu_relax();
	return;
}

extern void generic_bigsmp_probe(void);


#ifdef CONFIG_X86_LOCAL_APIC

#include <asm/smp.h>

#define APIC_DFR_VALUE	(APIC_DFR_FLAT)

static inline const struct cpumask *default_target_cpus(void)
{
#ifdef CONFIG_SMP
	return cpu_online_mask;
#else
	return cpumask_of(0);
#endif
}

DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);


static inline unsigned int read_apic_id(void)
{
	unsigned int reg;

	reg = apic_read(APIC_ID);

	return apic->get_apic_id(reg);
}

extern void default_setup_apic_routing(void);

extern struct apic apic_noop;

#ifdef CONFIG_X86_32

extern struct apic apic_default;

/*
 * Set up the logical destination ID.
 *
 * Intel recommends to set DFR, LDR and TPR before enabling
 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 * document number 292116).  So here it goes...
 */
extern void default_init_apic_ldr(void);

static inline int default_apic_id_registered(void)
{
	return physid_isset(read_apic_id(), phys_cpu_present_map);
}

static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
{
	return cpuid_apic >> index_msb;
}

extern int default_apicid_to_node(int logical_apicid);

#endif

static inline unsigned int
default_cpu_mask_to_apicid(const struct cpumask *cpumask)
{
	return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
}

static inline unsigned int
default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
			       const struct cpumask *andmask)
{
	unsigned long mask1 = cpumask_bits(cpumask)[0];
	unsigned long mask2 = cpumask_bits(andmask)[0];
	unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];

	return (unsigned int)(mask1 & mask2 & mask3);
}

static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
{
	return physid_isset(apicid, *map);
}

static inline unsigned long default_check_apicid_present(int bit)
{
	return physid_isset(bit, phys_cpu_present_map);
}

static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
{
	*retmap = *phys_map;
}

/* Mapping from cpu number to logical apicid */
static inline int default_cpu_to_logical_apicid(int cpu)
{
	return 1 << cpu;
}

static inline int __default_cpu_present_to_apicid(int mps_cpu)
{
	if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
	else
		return BAD_APICID;
}

static inline int
__default_check_phys_apicid_present(int phys_apicid)
{
	return physid_isset(phys_apicid, phys_cpu_present_map);
}

#ifdef CONFIG_X86_32
static inline int default_cpu_present_to_apicid(int mps_cpu)
{
	return __default_cpu_present_to_apicid(mps_cpu);
}

static inline int
default_check_phys_apicid_present(int phys_apicid)
{
	return __default_check_phys_apicid_present(phys_apicid);
}
#else
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);
#endif

#endif /* CONFIG_X86_LOCAL_APIC */

#ifdef CONFIG_X86_32
extern u8 cpu_2_logical_apicid[NR_CPUS];
#endif

#endif /* _ASM_X86_APIC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_APIC_H
1965aae3 PA	2	#define _ASM_X86_APIC_H
67c5fc5c	3
e2780a68	4	#include <linux/cpumask.h>
67c5fc5c	5	#include <linux/delay.h>
e2780a68	6	#include <linux/pm.h>
593f4a78 MR	7
593f4a78 MR	8	#include <asm/alternative.h>
e2780a68	9	#include <asm/cpufeature.h>
67c5fc5c	10	#include <asm/processor.h>
e2780a68 IM	11	#include <asm/apicdef.h>
	12	#include <asm/atomic.h>
	13	#include <asm/fixmap.h>
	14	#include <asm/mpspec.h>
67c5fc5c	15	#include <asm/system.h>
13c88fb5	16	#include <asm/msr.h>
67c5fc5c TG	17
	18	#define ARCH_APICTIMER_STOPS_ON_C3 1
	19
67c5fc5c TG	20	/*
	21	* Debugging macros
	22	*/
	23	#define APIC_QUIET 0
	24	#define APIC_VERBOSE 1
	25	#define APIC_DEBUG 2
	26
	27	/*
	28	* Define the default level of output to be very little
	29	* This can be turned up by using apic=verbose for more
	30	* information and apic=debug for _lots_ of information.
	31	* apic_verbosity is defined in apic.c
	32	*/
	33	#define apic_printk(v, s, a...) do { \
	34	if ((v) <= apic_verbosity) \
	35	printk(s, ##a); \
	36	} while (0)
	37
	38
160d8dac	39	#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
67c5fc5c	40	extern void generic_apic_probe(void);
160d8dac IM	41	#else
	42	static inline void generic_apic_probe(void)
	43	{
	44	}
	45	#endif
67c5fc5c TG	46
	47	#ifdef CONFIG_X86_LOCAL_APIC
	48
baa13188	49	extern unsigned int apic_verbosity;
67c5fc5c	50	extern int local_apic_timer_c2_ok;
67c5fc5c	51
3c999f14	52	extern int disable_apic;
0939e4fd IM	53
	54	#ifdef CONFIG_SMP
	55	extern void __inquire_remote_apic(int apicid);
	56	#else /* CONFIG_SMP */
	57	static inline void __inquire_remote_apic(int apicid)
	58	{
	59	}
	60	#endif /* CONFIG_SMP */
	61
	62	static inline void default_inquire_remote_apic(int apicid)
	63	{
	64	if (apic_verbosity >= APIC_DEBUG)
	65	__inquire_remote_apic(apicid);
	66	}
	67
8312136f CG	68	/*
	69	* With 82489DX we can't rely on apic feature bit
	70	* retrieved via cpuid but still have to deal with
	71	* such an apic chip so we assume that SMP configuration
	72	* is found from MP table (64bit case uses ACPI mostly
	73	* which set smp presence flag as well so we are safe
	74	* to use this helper too).
	75	*/
	76	static inline bool apic_from_smp_config(void)
	77	{
	78	return smp_found_config && !disable_apic;
	79	}
	80
67c5fc5c TG	81	/*
	82	* Basic functions accessing APICs.
	83	*/
	84	#ifdef CONFIG_PARAVIRT
	85	#include <asm/paravirt.h>
96a388de	86	#endif
67c5fc5c	87
70511134	88	#ifdef CONFIG_X86_64
aa7d8e25	89	extern int is_vsmp_box(void);
129d8bc8 YL	90	#else
	91	static inline int is_vsmp_box(void)
	92	{
	93	return 0;
	94	}
	95	#endif
2b97df06 JS	96	extern void xapic_wait_icr_idle(void);
2b97df06 JS	97	extern u32 safe_xapic_wait_icr_idle(void);
2b97df06 JS	98	extern void xapic_icr_write(u32, u32);
2b97df06 JS	99	extern int setup_profiling_timer(unsigned int);
aa7d8e25	100
1b374e4d	101	static inline void native_apic_mem_write(u32 reg, u32 v)
67c5fc5c	102	{
593f4a78	103	volatile u32 addr = (volatile u32 )(APIC_BASE + reg);
67c5fc5c	104
593f4a78 MR	105	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
	106	ASM_OUTPUT2("=r" (v), "=m" (*addr)),
	107	ASM_OUTPUT2("0" (v), "m" (*addr)));
67c5fc5c TG	108	}
67c5fc5c TG	109
1b374e4d	110	static inline u32 native_apic_mem_read(u32 reg)
67c5fc5c TG	111	{
	112	return ((volatile u32 )(APIC_BASE + reg));
	113	}
	114
c1eeb2de YL	115	extern void native_apic_wait_icr_idle(void);
	116	extern u32 native_safe_apic_wait_icr_idle(void);
	117	extern void native_apic_icr_write(u32 low, u32 id);
	118	extern u64 native_apic_icr_read(void);
	119
fc1edaf9	120	extern int x2apic_mode;
b24696bc	121
d0b03bd1	122	#ifdef CONFIG_X86_X2APIC
ce4e240c SS	123	/*
	124	* Make previous memory operations globally visible before
	125	* sending the IPI through x2apic wrmsr. We need a serializing instruction or
	126	* mfence for this.
	127	*/
	128	static inline void x2apic_wrmsr_fence(void)
	129	{
	130	asm volatile("mfence" : : : "memory");
	131	}
	132
13c88fb5 SS	133	static inline void native_apic_msr_write(u32 reg, u32 v)
	134	{
	135	if (reg == APIC_DFR \|\| reg == APIC_ID \|\| reg == APIC_LDR \|\|
	136	reg == APIC_LVR)
	137	return;
	138
	139	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
	140	}
	141
	142	static inline u32 native_apic_msr_read(u32 reg)
	143	{
0059b243	144	u64 msr;
13c88fb5 SS	145
	146	if (reg == APIC_DFR)
	147	return -1;
	148
0059b243 AK	149	rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
0059b243 AK	150	return (u32)msr;
13c88fb5 SS	151	}
13c88fb5 SS	152
c1eeb2de YL	153	static inline void native_x2apic_wait_icr_idle(void)
	154	{
	155	/* no need to wait for icr idle in x2apic */
	156	return;
	157	}
	158
	159	static inline u32 native_safe_x2apic_wait_icr_idle(void)
	160	{
	161	/* no need to wait for icr idle in x2apic */
	162	return 0;
	163	}
	164
	165	static inline void native_x2apic_icr_write(u32 low, u32 id)
	166	{
	167	wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 \| low);
	168	}
	169
	170	static inline u64 native_x2apic_icr_read(void)
	171	{
	172	unsigned long val;
	173
	174	rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
	175	return val;
	176	}
	177
fc1edaf9	178	extern int x2apic_phys;
6e1cb38a SS	179	extern void check_x2apic(void);
6e1cb38a SS	180	extern void enable_x2apic(void);
6e1cb38a	181	extern void x2apic_icr_write(u32 low, u32 id);
a11b5abe YL	182	static inline int x2apic_enabled(void)
a11b5abe YL	183	{
0059b243	184	u64 msr;
a11b5abe YL	185
	186	if (!cpu_has_x2apic)
	187	return 0;
	188
0059b243	189	rdmsrl(MSR_IA32_APICBASE, msr);
a11b5abe YL	190	if (msr & X2APIC_ENABLE)
	191	return 1;
	192	return 0;
	193	}
fc1edaf9 SS	194
fc1edaf9 SS	195	#define x2apic_supported() (cpu_has_x2apic)
ce69a784 GN	196	static inline void x2apic_force_phys(void)
	197	{
	198	x2apic_phys = 1;
	199	}
a11b5abe	200	#else
06cd9a7d YL	201	static inline void check_x2apic(void)
	202	{
	203	}
	204	static inline void enable_x2apic(void)
	205	{
	206	}
06cd9a7d YL	207	static inline int x2apic_enabled(void)
	208	{
	209	return 0;
	210	}
ce69a784 GN	211	static inline void x2apic_force_phys(void)
	212	{
	213	}
cf6567fe	214
93758238	215	#define x2apic_preenabled 0
fc1edaf9	216	#define x2apic_supported() 0
c535b6a1	217	#endif
1b374e4d	218
93758238 WH	219	extern void enable_IR_x2apic(void);
93758238 WH	220
67c5fc5c TG	221	extern int get_physical_broadcast(void);
67c5fc5c TG	222
08306ce6	223	extern void apic_disable(void);
67c5fc5c TG	224	extern int lapic_get_maxlvt(void);
	225	extern void clear_local_APIC(void);
	226	extern void connect_bsp_APIC(void);
	227	extern void disconnect_bsp_APIC(int virt_wire_setup);
	228	extern void disable_local_APIC(void);
	229	extern void lapic_shutdown(void);
	230	extern int verify_local_APIC(void);
	231	extern void cache_APIC_registers(void);
	232	extern void sync_Arb_IDs(void);
	233	extern void init_bsp_APIC(void);
	234	extern void setup_local_APIC(void);
739f33b3	235	extern void end_local_APIC_setup(void);
67c5fc5c	236	extern void init_apic_mappings(void);
67c5fc5c TG	237	extern void setup_boot_APIC_clock(void);
	238	extern void setup_secondary_APIC_clock(void);
	239	extern int APIC_init_uniprocessor(void);
e9427101	240	extern void enable_NMI_through_LVT0(void);
67c5fc5c TG	241
	242	/*
	243	* On 32bit this is mach-xxx local
	244	*/
	245	#ifdef CONFIG_X86_64
8643f9d0	246	extern void early_init_lapic_mapping(void);
8fbbc4b4 AK	247	extern int apic_is_clustered_box(void);
	248	#else
	249	static inline int apic_is_clustered_box(void)
	250	{
	251	return 0;
	252	}
67c5fc5c TG	253	#endif
67c5fc5c TG	254
27afdf20	255	extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
67c5fc5c TG	256
	257	#else /* !CONFIG_X86_LOCAL_APIC */
	258	static inline void lapic_shutdown(void) { }
	259	#define local_apic_timer_c2_ok 1
f3294a33	260	static inline void init_apic_mappings(void) { }
d3ec5cae	261	static inline void disable_local_APIC(void) { }
08306ce6	262	static inline void apic_disable(void) { }
736decac TG	263	# define setup_boot_APIC_clock x86_init_noop
736decac TG	264	# define setup_secondary_APIC_clock x86_init_noop
67c5fc5c TG	265	#endif /* !CONFIG_X86_LOCAL_APIC */
67c5fc5c TG	266
1f75ed0c IM	267	#ifdef CONFIG_X86_64
	268	#define SET_APIC_ID(x) (apic->set_apic_id(x))
	269	#else
	270
1f75ed0c IM	271	#endif
1f75ed0c IM	272
e2780a68 IM	273	/*
	274	* Copyright 2004 James Cleverdon, IBM.
	275	* Subject to the GNU Public License, v.2
	276	*
	277	* Generic APIC sub-arch data struct.
	278	*
	279	* Hacked for x86-64 by James Cleverdon from i386 architecture code by
	280	* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
	281	* James Cleverdon.
	282	*/
be163a15	283	struct apic {
e2780a68 IM	284	char *name;
	285
	286	int (*probe)(void);
	287	int (acpi_madt_oem_check)(char oem_id, char *oem_table_id);
	288	int (*apic_id_registered)(void);
	289
	290	u32 irq_delivery_mode;
	291	u32 irq_dest_mode;
	292
	293	const struct cpumask (target_cpus)(void);
	294
	295	int disable_esr;
	296
	297	int dest_logical;
7abc0753	298	unsigned long (check_apicid_used)(physid_mask_t map, int apicid);
e2780a68 IM	299	unsigned long (*check_apicid_present)(int apicid);
	300
	301	void (vector_allocation_domain)(int cpu, struct cpumask retmask);
	302	void (*init_apic_ldr)(void);
	303
7abc0753	304	void (ioapic_phys_id_map)(physid_mask_t phys_map, physid_mask_t *retmap);
e2780a68 IM	305
	306	void (*setup_apic_routing)(void);
	307	int (*multi_timer_check)(int apic, int irq);
	308	int (*apicid_to_node)(int logical_apicid);
	309	int (*cpu_to_logical_apicid)(int cpu);
	310	int (*cpu_present_to_apicid)(int mps_cpu);
7abc0753	311	void (apicid_to_cpu_present)(int phys_apicid, physid_mask_t retmap);
e2780a68	312	void (*setup_portio_remap)(void);
e11dadab	313	int (*check_phys_apicid_present)(int phys_apicid);
e2780a68 IM	314	void (*enable_apic_mode)(void);
	315	int (*phys_pkg_id)(int cpuid_apic, int index_msb);
	316
	317	/*
be163a15	318	* When one of the next two hooks returns 1 the apic
e2780a68 IM	319	* is switched to this. Essentially they are additional
	320	* probe functions:
	321	*/
	322	int (mps_oem_check)(struct mpc_table mpc, char oem, char productid);
	323
	324	unsigned int (*get_apic_id)(unsigned long x);
	325	unsigned long (*set_apic_id)(unsigned int id);
	326	unsigned long apic_id_mask;
	327
	328	unsigned int (cpu_mask_to_apicid)(const struct cpumask cpumask);
	329	unsigned int (cpu_mask_to_apicid_and)(const struct cpumask cpumask,
	330	const struct cpumask *andmask);
	331
	332	/* ipi */
	333	void (send_IPI_mask)(const struct cpumask mask, int vector);
	334	void (send_IPI_mask_allbutself)(const struct cpumask mask,
	335	int vector);
	336	void (*send_IPI_allbutself)(int vector);
	337	void (*send_IPI_all)(int vector);
	338	void (*send_IPI_self)(int vector);
	339
	340	/* wakeup_secondary_cpu */
1f5bcabf	341	int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
e2780a68 IM	342
	343	int trampoline_phys_low;
	344	int trampoline_phys_high;
	345
	346	void (wait_for_init_deassert)(atomic_t deassert);
	347	void (*smp_callin_clear_local_apic)(void);
e2780a68 IM	348	void (*inquire_remote_apic)(int apicid);
	349
	350	/* apic ops */
	351	u32 (*read)(u32 reg);
	352	void (*write)(u32 reg, u32 v);
	353	u64 (*icr_read)(void);
	354	void (*icr_write)(u32 low, u32 high);
	355	void (*wait_icr_idle)(void);
	356	u32 (*safe_wait_icr_idle)(void);
	357	};
	358
0917c01f IM	359	/*
	360	* Pointer to the local APIC driver in use on this system (there's
	361	* always just one such driver in use - the kernel decides via an
	362	* early probing process which one it picks - and then sticks to it):
	363	*/
be163a15	364	extern struct apic *apic;
0917c01f IM	365
	366	/*
	367	* APIC functionality to boot other CPUs - only used on SMP:
	368	*/
	369	#ifdef CONFIG_SMP
2b6163bf YL	370	extern atomic_t init_deasserted;
2b6163bf YL	371	extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
0917c01f	372	#endif
e2780a68	373
d674cd19	374	#ifdef CONFIG_X86_LOCAL_APIC
e2780a68 IM	375	static inline u32 apic_read(u32 reg)
	376	{
	377	return apic->read(reg);
	378	}
	379
	380	static inline void apic_write(u32 reg, u32 val)
	381	{
	382	apic->write(reg, val);
	383	}
	384
	385	static inline u64 apic_icr_read(void)
	386	{
	387	return apic->icr_read();
	388	}
	389
	390	static inline void apic_icr_write(u32 low, u32 high)
	391	{
	392	apic->icr_write(low, high);
	393	}
	394
	395	static inline void apic_wait_icr_idle(void)
	396	{
	397	apic->wait_icr_idle();
	398	}
	399
	400	static inline u32 safe_apic_wait_icr_idle(void)
	401	{
	402	return apic->safe_wait_icr_idle();
	403	}
	404
d674cd19 CG	405	#else /* CONFIG_X86_LOCAL_APIC */
	406
	407	static inline u32 apic_read(u32 reg) { return 0; }
	408	static inline void apic_write(u32 reg, u32 val) { }
	409	static inline u64 apic_icr_read(void) { return 0; }
	410	static inline void apic_icr_write(u32 low, u32 high) { }
	411	static inline void apic_wait_icr_idle(void) { }
	412	static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
	413
	414	#endif /* CONFIG_X86_LOCAL_APIC */
e2780a68 IM	415
	416	static inline void ack_APIC_irq(void)
	417	{
	418	/*
	419	* ack_APIC_irq() actually gets compiled as a single instruction
	420	* ... yummie.
	421	*/
	422
	423	/* Docs say use 0 for future compatibility */
	424	apic_write(APIC_EOI, 0);
	425	}
	426
	427	static inline unsigned default_get_apic_id(unsigned long x)
	428	{
	429	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	430
42937e81	431	if (APIC_XAPIC(ver) \|\| boot_cpu_has(X86_FEATURE_EXTD_APICID))
e2780a68 IM	432	return (x >> 24) & 0xFF;
	433	else
	434	return (x >> 24) & 0x0F;
	435	}
	436
	437	/*
	438	* Warm reset vector default position:
	439	*/
	440	#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
	441	#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
	442
2b6163bf	443	#ifdef CONFIG_X86_64
be163a15 IM	444	extern struct apic apic_flat;
	445	extern struct apic apic_physflat;
	446	extern struct apic apic_x2apic_cluster;
	447	extern struct apic apic_x2apic_phys;
e2780a68 IM	448	extern int default_acpi_madt_oem_check(char , char );
	449
	450	extern void apic_send_IPI_self(int vector);
	451
be163a15	452	extern struct apic apic_x2apic_uv_x;
e2780a68 IM	453	DECLARE_PER_CPU(int, x2apic_extra_bits);
	454
	455	extern int default_cpu_present_to_apicid(int mps_cpu);
e11dadab	456	extern int default_check_phys_apicid_present(int phys_apicid);
e2780a68 IM	457	#endif
	458
	459	static inline void default_wait_for_init_deassert(atomic_t *deassert)
	460	{
	461	while (!atomic_read(deassert))
	462	cpu_relax();
	463	return;
	464	}
	465
	466	extern void generic_bigsmp_probe(void);
	467
	468
	469	#ifdef CONFIG_X86_LOCAL_APIC
	470
	471	#include <asm/smp.h>
	472
	473	#define APIC_DFR_VALUE (APIC_DFR_FLAT)
	474
	475	static inline const struct cpumask *default_target_cpus(void)
	476	{
	477	#ifdef CONFIG_SMP
	478	return cpu_online_mask;
	479	#else
	480	return cpumask_of(0);
	481	#endif
	482	}
	483
	484	DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
	485
	486
	487	static inline unsigned int read_apic_id(void)
	488	{
	489	unsigned int reg;
	490
	491	reg = apic_read(APIC_ID);
	492
	493	return apic->get_apic_id(reg);
	494	}
	495
	496	extern void default_setup_apic_routing(void);
	497
9844ab11 CG	498	extern struct apic apic_noop;
9844ab11 CG	499
e2780a68	500	#ifdef CONFIG_X86_32
2c1b284e JSR	501
	502	extern struct apic apic_default;
	503
e2780a68 IM	504	/*
	505	* Set up the logical destination ID.
	506	*
	507	* Intel recommends to set DFR, LDR and TPR before enabling
	508	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	509	* document number 292116). So here it goes...
	510	*/
	511	extern void default_init_apic_ldr(void);
	512
	513	static inline int default_apic_id_registered(void)
	514	{
	515	return physid_isset(read_apic_id(), phys_cpu_present_map);
	516	}
	517
f56e5034 YL	518	static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
	519	{
	520	return cpuid_apic >> index_msb;
	521	}
	522
	523	extern int default_apicid_to_node(int logical_apicid);
	524
	525	#endif
	526
e2780a68 IM	527	static inline unsigned int
	528	default_cpu_mask_to_apicid(const struct cpumask *cpumask)
	529	{
f56e5034	530	return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
e2780a68 IM	531	}
	532
	533	static inline unsigned int
	534	default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
	535	const struct cpumask *andmask)
	536	{
	537	unsigned long mask1 = cpumask_bits(cpumask)[0];
	538	unsigned long mask2 = cpumask_bits(andmask)[0];
	539	unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
	540
	541	return (unsigned int)(mask1 & mask2 & mask3);
	542	}
	543
7abc0753	544	static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
e2780a68	545	{
7abc0753	546	return physid_isset(apicid, *map);
e2780a68 IM	547	}
	548
	549	static inline unsigned long default_check_apicid_present(int bit)
	550	{
	551	return physid_isset(bit, phys_cpu_present_map);
	552	}
	553
7abc0753	554	static inline void default_ioapic_phys_id_map(physid_mask_t phys_map, physid_mask_t retmap)
e2780a68	555	{
7abc0753	556	retmap = phys_map;
e2780a68 IM	557	}
	558
	559	/* Mapping from cpu number to logical apicid */
	560	static inline int default_cpu_to_logical_apicid(int cpu)
	561	{
	562	return 1 << cpu;
	563	}
	564
	565	static inline int __default_cpu_present_to_apicid(int mps_cpu)
	566	{
	567	if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
	568	return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
	569	else
	570	return BAD_APICID;
	571	}
	572
	573	static inline int
e11dadab	574	__default_check_phys_apicid_present(int phys_apicid)
e2780a68	575	{
e11dadab	576	return physid_isset(phys_apicid, phys_cpu_present_map);
e2780a68 IM	577	}
	578
	579	#ifdef CONFIG_X86_32
	580	static inline int default_cpu_present_to_apicid(int mps_cpu)
	581	{
	582	return __default_cpu_present_to_apicid(mps_cpu);
	583	}
	584
	585	static inline int
e11dadab	586	default_check_phys_apicid_present(int phys_apicid)
e2780a68	587	{
e11dadab	588	return __default_check_phys_apicid_present(phys_apicid);
e2780a68 IM	589	}
	590	#else
	591	extern int default_cpu_present_to_apicid(int mps_cpu);
e11dadab	592	extern int default_check_phys_apicid_present(int phys_apicid);
e2780a68 IM	593	#endif
e2780a68 IM	594
e2780a68 IM	595	#endif /* CONFIG_X86_LOCAL_APIC */
e2780a68 IM	596
2f205bc4 IM	597	#ifdef CONFIG_X86_32
	598	extern u8 cpu_2_logical_apicid[NR_CPUS];
	599	#endif
	600
1965aae3	601	#endif /* _ASM_X86_APIC_H */