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867e359b CM |
1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * Support the cycle counter clocksource and tile timer clock event device. | |
15 | */ | |
16 | ||
17 | #include <linux/time.h> | |
18 | #include <linux/timex.h> | |
19 | #include <linux/clocksource.h> | |
20 | #include <linux/clockchips.h> | |
21 | #include <linux/hardirq.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/delay.h> | |
25 | #include <asm/irq_regs.h> | |
0707ad30 | 26 | #include <asm/traps.h> |
867e359b CM |
27 | #include <hv/hypervisor.h> |
28 | #include <arch/interrupts.h> | |
29 | #include <arch/spr_def.h> | |
30 | ||
31 | ||
32 | /* | |
33 | * Define the cycle counter clock source. | |
34 | */ | |
35 | ||
36 | /* How many cycles per second we are running at. */ | |
37 | static cycles_t cycles_per_sec __write_once; | |
38 | ||
39 | /* | |
40 | * We set up shift and multiply values with a minsec of five seconds, | |
41 | * since our timer counter counts down 31 bits at a frequency of | |
42 | * no less than 500 MHz. See @minsec for clocks_calc_mult_shift(). | |
43 | * We could use a different value for the 64-bit free-running | |
44 | * cycle counter, but we use the same one for consistency, and since | |
45 | * we will be reasonably precise with this value anyway. | |
46 | */ | |
47 | #define TILE_MINSEC 5 | |
48 | ||
0707ad30 | 49 | cycles_t get_clock_rate(void) |
867e359b CM |
50 | { |
51 | return cycles_per_sec; | |
52 | } | |
53 | ||
54 | #if CHIP_HAS_SPLIT_CYCLE() | |
0707ad30 | 55 | cycles_t get_cycles(void) |
867e359b CM |
56 | { |
57 | unsigned int high = __insn_mfspr(SPR_CYCLE_HIGH); | |
58 | unsigned int low = __insn_mfspr(SPR_CYCLE_LOW); | |
59 | unsigned int high2 = __insn_mfspr(SPR_CYCLE_HIGH); | |
60 | ||
61 | while (unlikely(high != high2)) { | |
62 | low = __insn_mfspr(SPR_CYCLE_LOW); | |
63 | high = high2; | |
64 | high2 = __insn_mfspr(SPR_CYCLE_HIGH); | |
65 | } | |
66 | ||
67 | return (((cycles_t)high) << 32) | low; | |
68 | } | |
69 | #endif | |
70 | ||
0707ad30 | 71 | static cycles_t clocksource_get_cycles(struct clocksource *cs) |
867e359b CM |
72 | { |
73 | return get_cycles(); | |
74 | } | |
75 | ||
76 | static struct clocksource cycle_counter_cs = { | |
77 | .name = "cycle counter", | |
78 | .rating = 300, | |
79 | .read = clocksource_get_cycles, | |
80 | .mask = CLOCKSOURCE_MASK(64), | |
81 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
82 | }; | |
83 | ||
84 | /* | |
85 | * Called very early from setup_arch() to set cycles_per_sec. | |
86 | * We initialize it early so we can use it to set up loops_per_jiffy. | |
87 | */ | |
88 | void __init setup_clock(void) | |
89 | { | |
90 | cycles_per_sec = hv_sysconf(HV_SYSCONF_CPU_SPEED); | |
91 | clocksource_calc_mult_shift(&cycle_counter_cs, cycles_per_sec, | |
92 | TILE_MINSEC); | |
93 | } | |
94 | ||
95 | void __init calibrate_delay(void) | |
96 | { | |
97 | loops_per_jiffy = get_clock_rate() / HZ; | |
98 | pr_info("Clock rate yields %lu.%02lu BogoMIPS (lpj=%lu)\n", | |
99 | loops_per_jiffy/(500000/HZ), | |
100 | (loops_per_jiffy/(5000/HZ)) % 100, loops_per_jiffy); | |
101 | } | |
102 | ||
103 | /* Called fairly late in init/main.c, but before we go smp. */ | |
104 | void __init time_init(void) | |
105 | { | |
106 | /* Initialize and register the clock source. */ | |
107 | clocksource_register(&cycle_counter_cs); | |
108 | ||
109 | /* Start up the tile-timer interrupt source on the boot cpu. */ | |
110 | setup_tile_timer(); | |
111 | } | |
112 | ||
113 | ||
114 | /* | |
115 | * Define the tile timer clock event device. The timer is driven by | |
116 | * the TILE_TIMER_CONTROL register, which consists of a 31-bit down | |
117 | * counter, plus bit 31, which signifies that the counter has wrapped | |
118 | * from zero to (2**31) - 1. The INT_TILE_TIMER interrupt will be | |
119 | * raised as long as bit 31 is set. | |
120 | */ | |
121 | ||
122 | #define MAX_TICK 0x7fffffff /* we have 31 bits of countdown timer */ | |
123 | ||
124 | static int tile_timer_set_next_event(unsigned long ticks, | |
125 | struct clock_event_device *evt) | |
126 | { | |
127 | BUG_ON(ticks > MAX_TICK); | |
128 | __insn_mtspr(SPR_TILE_TIMER_CONTROL, ticks); | |
129 | raw_local_irq_unmask_now(INT_TILE_TIMER); | |
130 | return 0; | |
131 | } | |
132 | ||
133 | /* | |
134 | * Whenever anyone tries to change modes, we just mask interrupts | |
135 | * and wait for the next event to get set. | |
136 | */ | |
137 | static void tile_timer_set_mode(enum clock_event_mode mode, | |
138 | struct clock_event_device *evt) | |
139 | { | |
140 | raw_local_irq_mask_now(INT_TILE_TIMER); | |
141 | } | |
142 | ||
143 | /* | |
144 | * Set min_delta_ns to 1 microsecond, since it takes about | |
145 | * that long to fire the interrupt. | |
146 | */ | |
147 | static DEFINE_PER_CPU(struct clock_event_device, tile_timer) = { | |
148 | .name = "tile timer", | |
149 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
150 | .min_delta_ns = 1000, | |
151 | .rating = 100, | |
152 | .irq = -1, | |
153 | .set_next_event = tile_timer_set_next_event, | |
154 | .set_mode = tile_timer_set_mode, | |
155 | }; | |
156 | ||
157 | void __cpuinit setup_tile_timer(void) | |
158 | { | |
159 | struct clock_event_device *evt = &__get_cpu_var(tile_timer); | |
160 | ||
161 | /* Fill in fields that are speed-specific. */ | |
162 | clockevents_calc_mult_shift(evt, cycles_per_sec, TILE_MINSEC); | |
163 | evt->max_delta_ns = clockevent_delta2ns(MAX_TICK, evt); | |
164 | ||
165 | /* Mark as being for this cpu only. */ | |
166 | evt->cpumask = cpumask_of(smp_processor_id()); | |
167 | ||
168 | /* Start out with timer not firing. */ | |
169 | raw_local_irq_mask_now(INT_TILE_TIMER); | |
170 | ||
171 | /* Register tile timer. */ | |
172 | clockevents_register_device(evt); | |
173 | } | |
174 | ||
175 | /* Called from the interrupt vector. */ | |
176 | void do_timer_interrupt(struct pt_regs *regs, int fault_num) | |
177 | { | |
178 | struct pt_regs *old_regs = set_irq_regs(regs); | |
179 | struct clock_event_device *evt = &__get_cpu_var(tile_timer); | |
180 | ||
181 | /* | |
182 | * Mask the timer interrupt here, since we are a oneshot timer | |
183 | * and there are now by definition no events pending. | |
184 | */ | |
185 | raw_local_irq_mask(INT_TILE_TIMER); | |
186 | ||
187 | /* Track time spent here in an interrupt context */ | |
188 | irq_enter(); | |
189 | ||
190 | /* Track interrupt count. */ | |
191 | __get_cpu_var(irq_stat).irq_timer_count++; | |
192 | ||
193 | /* Call the generic timer handler */ | |
194 | evt->event_handler(evt); | |
195 | ||
196 | /* | |
197 | * Track time spent against the current process again and | |
198 | * process any softirqs if they are waiting. | |
199 | */ | |
200 | irq_exit(); | |
201 | ||
202 | set_irq_regs(old_regs); | |
203 | } | |
204 | ||
205 | /* | |
206 | * Scheduler clock - returns current time in nanosec units. | |
207 | * Note that with LOCKDEP, this is called during lockdep_init(), and | |
208 | * we will claim that sched_clock() is zero for a little while, until | |
209 | * we run setup_clock(), above. | |
210 | */ | |
211 | unsigned long long sched_clock(void) | |
212 | { | |
213 | return clocksource_cyc2ns(get_cycles(), | |
214 | cycle_counter_cs.mult, | |
215 | cycle_counter_cs.shift); | |
216 | } | |
217 | ||
218 | int setup_profiling_timer(unsigned int multiplier) | |
219 | { | |
220 | return -EINVAL; | |
221 | } |