[net-next-2.6.git] / arch / tile / kernel / irq.c

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/uaccess.h>
#include <hv/drv_pcie_rc_intf.h>
#include <arch/spr_def.h>
#include <asm/traps.h>

/* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
#define IS_HW_CLEARED 1

/*
 * The set of interrupts we enable for raw_local_irq_enable().
 * This is initialized to have just a single interrupt that the kernel
 * doesn't actually use as a sentinel.  During kernel init,
 * interrupts are added as the kernel gets prepared to support them.
 * NOTE: we could probably initialize them all statically up front.
 */
DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) =
  INITIAL_INTERRUPTS_ENABLED;
EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask);

/* Define per-tile device interrupt statistics state. */
DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
EXPORT_PER_CPU_SYMBOL(irq_stat);

/*
 * Define per-tile irq disable mask; the hardware/HV only has a single
 * mask that we use to implement both masking and disabling.
 */
static DEFINE_PER_CPU(unsigned long, irq_disable_mask)
	____cacheline_internodealigned_in_smp;

/*
 * Per-tile IRQ nesting depth.  Used to make sure we enable newly
 * enabled IRQs before exiting the outermost interrupt.
 */
static DEFINE_PER_CPU(int, irq_depth);

/* State for allocating IRQs on Gx. */
#if CHIP_HAS_IPI()
static unsigned long available_irqs = ~(1UL << IRQ_RESCHEDULE);
static DEFINE_SPINLOCK(available_irqs_lock);
#endif

#if CHIP_HAS_IPI()
/* Use SPRs to manipulate device interrupts. */
#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
#else
/* Use HV to manipulate device interrupts. */
#define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
#define unmask_irqs(irq_mask) hv_enable_intr(irq_mask)
#define clear_irqs(irq_mask) hv_clear_intr(irq_mask)
#endif

/*
 * The interrupt handling path, implemented in terms of HV interrupt
 * emulation on TILE64 and TILEPro, and IPI hardware on TILE-Gx.
 */
void tile_dev_intr(struct pt_regs *regs, int intnum)
{
	int depth = __get_cpu_var(irq_depth)++;
	unsigned long original_irqs;
	unsigned long remaining_irqs;
	struct pt_regs *old_regs;

#if CHIP_HAS_IPI()
	/*
	 * Pending interrupts are listed in an SPR.  We might be
	 * nested, so be sure to only handle irqs that weren't already
	 * masked by a previous interrupt.  Then, mask out the ones
	 * we're going to handle.
	 */
	unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
	original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
	__insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
#else
	/*
	 * Hypervisor performs the equivalent of the Gx code above and
	 * then puts the pending interrupt mask into a system save reg
	 * for us to find.
	 */
	original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
#endif
	remaining_irqs = original_irqs;

	/* Track time spent here in an interrupt context. */
	old_regs = set_irq_regs(regs);
	irq_enter();

#ifdef CONFIG_DEBUG_STACKOVERFLOW
	/* Debugging check for stack overflow: less than 1/8th stack free? */
	{
		long sp = stack_pointer - (long) current_thread_info();
		if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
			pr_emerg("tile_dev_intr: "
			       "stack overflow: %ld\n",
			       sp - sizeof(struct thread_info));
			dump_stack();
		}
	}
#endif
	while (remaining_irqs) {
		unsigned long irq = __ffs(remaining_irqs);
		remaining_irqs &= ~(1UL << irq);

		/* Count device irqs; Linux IPIs are counted elsewhere. */
		if (irq != IRQ_RESCHEDULE)
			__get_cpu_var(irq_stat).irq_dev_intr_count++;

		generic_handle_irq(irq);
	}

	/*
	 * If we weren't nested, turn on all enabled interrupts,
	 * including any that were reenabled during interrupt
	 * handling.
	 */
	if (depth == 0)
		unmask_irqs(~__get_cpu_var(irq_disable_mask));

	__get_cpu_var(irq_depth)--;

	/*
	 * Track time spent against the current process again and
	 * process any softirqs if they are waiting.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}


/*
 * Remove an irq from the disabled mask.  If we're in an interrupt
 * context, defer enabling the HW interrupt until we leave.
 */
void enable_percpu_irq(unsigned int irq)
{
	get_cpu_var(irq_disable_mask) &= ~(1UL << irq);
	if (__get_cpu_var(irq_depth) == 0)
		unmask_irqs(1UL << irq);
	put_cpu_var(irq_disable_mask);
}
EXPORT_SYMBOL(enable_percpu_irq);

/*
 * Add an irq to the disabled mask.  We disable the HW interrupt
 * immediately so that there's no possibility of it firing.  If we're
 * in an interrupt context, the return path is careful to avoid
 * unmasking a newly disabled interrupt.
 */
void disable_percpu_irq(unsigned int irq)
{
	get_cpu_var(irq_disable_mask) |= (1UL << irq);
	mask_irqs(1UL << irq);
	put_cpu_var(irq_disable_mask);
}
EXPORT_SYMBOL(disable_percpu_irq);

/* Mask an interrupt. */
static void tile_irq_chip_mask(unsigned int irq)
{
	mask_irqs(1UL << irq);
}

/* Unmask an interrupt. */
static void tile_irq_chip_unmask(unsigned int irq)
{
	unmask_irqs(1UL << irq);
}

/*
 * Clear an interrupt before processing it so that any new assertions
 * will trigger another irq.
 */
static void tile_irq_chip_ack(unsigned int irq)
{
	if ((unsigned long)get_irq_chip_data(irq) != IS_HW_CLEARED)
		clear_irqs(1UL << irq);
}

/*
 * For per-cpu interrupts, we need to avoid unmasking any interrupts
 * that we disabled via disable_percpu_irq().
 */
static void tile_irq_chip_eoi(unsigned int irq)
{
	if (!(__get_cpu_var(irq_disable_mask) & (1UL << irq)))
		unmask_irqs(1UL << irq);
}

static struct irq_chip tile_irq_chip = {
	.name = "tile_irq_chip",
	.ack = tile_irq_chip_ack,
	.eoi = tile_irq_chip_eoi,
	.mask = tile_irq_chip_mask,
	.unmask = tile_irq_chip_unmask,
};

void __init init_IRQ(void)
{
	ipi_init();
}

void __cpuinit setup_irq_regs(void)
{
	/* Enable interrupt delivery. */
	unmask_irqs(~0UL);
#if CHIP_HAS_IPI()
	raw_local_irq_unmask(INT_IPI_K);
#endif
}

void tile_irq_activate(unsigned int irq, int tile_irq_type)
{
	/*
	 * We use handle_level_irq() by default because the pending
	 * interrupt vector (whether modeled by the HV on TILE64 and
	 * TILEPro or implemented in hardware on TILE-Gx) has
	 * level-style semantics for each bit.  An interrupt fires
	 * whenever a bit is high, not just at edges.
	 */
	irq_flow_handler_t handle = handle_level_irq;
	if (tile_irq_type == TILE_IRQ_PERCPU)
		handle = handle_percpu_irq;
	set_irq_chip_and_handler(irq, &tile_irq_chip, handle);

	/*
	 * Flag interrupts that are hardware-cleared so that ack()
	 * won't clear them.
	 */
	if (tile_irq_type == TILE_IRQ_HW_CLEAR)
		set_irq_chip_data(irq, (void *)IS_HW_CLEARED);
}
EXPORT_SYMBOL(tile_irq_activate);


void ack_bad_irq(unsigned int irq)
{
	pr_err("unexpected IRQ trap at vector %02x\n", irq);
}

/*
 * Generic, controller-independent functions:
 */

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	struct irqaction *action;
	unsigned long flags;

	if (i == 0) {
		seq_printf(p, "           ");
		for (j = 0; j < NR_CPUS; j++)
			if (cpu_online(j))
				seq_printf(p, "CPU%-8d", j);
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ", i);
#ifndef CONFIG_SMP
		seq_printf(p, "%10u ", kstat_irqs(i));
#else
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif
		seq_printf(p, " %14s", irq_desc[i].chip->name);
		seq_printf(p, "  %s", action->name);

		for (action = action->next; action; action = action->next)
			seq_printf(p, ", %s", action->name);

		seq_putc(p, '\n');
skip:
		raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	}
	return 0;
}

#if CHIP_HAS_IPI()
int create_irq(void)
{
	unsigned long flags;
	int result;

	spin_lock_irqsave(&available_irqs_lock, flags);
	if (available_irqs == 0)
		result = -ENOMEM;
	else {
		result = __ffs(available_irqs);
		available_irqs &= ~(1UL << result);
		dynamic_irq_init(result);
	}
	spin_unlock_irqrestore(&available_irqs_lock, flags);

	return result;
}
EXPORT_SYMBOL(create_irq);

void destroy_irq(unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&available_irqs_lock, flags);
	available_irqs |= (1UL << irq);
	dynamic_irq_cleanup(irq);
	spin_unlock_irqrestore(&available_irqs_lock, flags);
}
EXPORT_SYMBOL(destroy_irq);
#endif
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/seq_file.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
	19	#include <linux/kernel_stat.h>
	20	#include <linux/uaccess.h>
	21	#include <hv/drv_pcie_rc_intf.h>
fb702b94 CM	22	#include <arch/spr_def.h>
	23	#include <asm/traps.h>
	24
	25	/* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
	26	#define IS_HW_CLEARED 1
867e359b CM	27
	28	/*
	29	* The set of interrupts we enable for raw_local_irq_enable().
	30	* This is initialized to have just a single interrupt that the kernel
	31	* doesn't actually use as a sentinel. During kernel init,
	32	* interrupts are added as the kernel gets prepared to support them.
	33	* NOTE: we could probably initialize them all statically up front.
	34	*/
	35	DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) =
	36	INITIAL_INTERRUPTS_ENABLED;
	37	EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask);
	38
fb702b94	39	/* Define per-tile device interrupt statistics state. */
867e359b CM	40	DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
	41	EXPORT_PER_CPU_SYMBOL(irq_stat);
	42
fb702b94 CM	43	/*
	44	* Define per-tile irq disable mask; the hardware/HV only has a single
	45	* mask that we use to implement both masking and disabling.
	46	*/
	47	static DEFINE_PER_CPU(unsigned long, irq_disable_mask)
	48	____cacheline_internodealigned_in_smp;
	49
	50	/*
	51	* Per-tile IRQ nesting depth. Used to make sure we enable newly
	52	* enabled IRQs before exiting the outermost interrupt.
	53	*/
	54	static DEFINE_PER_CPU(int, irq_depth);
	55
	56	/* State for allocating IRQs on Gx. */
	57	#if CHIP_HAS_IPI()
	58	static unsigned long available_irqs = ~(1UL << IRQ_RESCHEDULE);
	59	static DEFINE_SPINLOCK(available_irqs_lock);
	60	#endif
867e359b	61
fb702b94 CM	62	#if CHIP_HAS_IPI()
fb702b94 CM	63	/* Use SPRs to manipulate device interrupts. */
a78c942d CM	64	#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
	65	#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
	66	#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
fb702b94 CM	67	#else
	68	/* Use HV to manipulate device interrupts. */
	69	#define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
	70	#define unmask_irqs(irq_mask) hv_enable_intr(irq_mask)
	71	#define clear_irqs(irq_mask) hv_clear_intr(irq_mask)
	72	#endif
867e359b CM	73
867e359b CM	74	/*
fb702b94 CM	75	* The interrupt handling path, implemented in terms of HV interrupt
fb702b94 CM	76	* emulation on TILE64 and TILEPro, and IPI hardware on TILE-Gx.
867e359b CM	77	*/
	78	void tile_dev_intr(struct pt_regs *regs, int intnum)
	79	{
fb702b94 CM	80	int depth = __get_cpu_var(irq_depth)++;
	81	unsigned long original_irqs;
	82	unsigned long remaining_irqs;
	83	struct pt_regs *old_regs;
867e359b	84
fb702b94	85	#if CHIP_HAS_IPI()
867e359b	86	/*
fb702b94 CM	87	* Pending interrupts are listed in an SPR. We might be
	88	* nested, so be sure to only handle irqs that weren't already
	89	* masked by a previous interrupt. Then, mask out the ones
	90	* we're going to handle.
867e359b	91	*/
a78c942d CM	92	unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
	93	original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
	94	__insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
fb702b94 CM	95	#else
	96	/*
	97	* Hypervisor performs the equivalent of the Gx code above and
	98	* then puts the pending interrupt mask into a system save reg
	99	* for us to find.
	100	*/
a78c942d	101	original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
fb702b94 CM	102	#endif
fb702b94 CM	103	remaining_irqs = original_irqs;
867e359b CM	104
867e359b CM	105	/* Track time spent here in an interrupt context. */
fb702b94	106	old_regs = set_irq_regs(regs);
867e359b CM	107	irq_enter();
	108
	109	#ifdef CONFIG_DEBUG_STACKOVERFLOW
	110	/* Debugging check for stack overflow: less than 1/8th stack free? */
	111	{
	112	long sp = stack_pointer - (long) current_thread_info();
	113	if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
fb702b94	114	pr_emerg("tile_dev_intr: "
867e359b CM	115	"stack overflow: %ld\n",
	116	sp - sizeof(struct thread_info));
	117	dump_stack();
	118	}
	119	}
	120	#endif
fb702b94 CM	121	while (remaining_irqs) {
	122	unsigned long irq = __ffs(remaining_irqs);
	123	remaining_irqs &= ~(1UL << irq);
867e359b	124
fb702b94 CM	125	/* Count device irqs; Linux IPIs are counted elsewhere. */
	126	if (irq != IRQ_RESCHEDULE)
	127	__get_cpu_var(irq_stat).irq_dev_intr_count++;
867e359b	128
fb702b94	129	generic_handle_irq(irq);
867e359b CM	130	}
867e359b CM	131
fb702b94 CM	132	/*
	133	* If we weren't nested, turn on all enabled interrupts,
	134	* including any that were reenabled during interrupt
	135	* handling.
	136	*/
	137	if (depth == 0)
	138	unmask_irqs(~__get_cpu_var(irq_disable_mask));
	139
	140	__get_cpu_var(irq_depth)--;
	141
867e359b CM	142	/*
	143	* Track time spent against the current process again and
	144	* process any softirqs if they are waiting.
	145	*/
	146	irq_exit();
	147	set_irq_regs(old_regs);
	148	}
	149
	150
fb702b94 CM	151	/*
	152	* Remove an irq from the disabled mask. If we're in an interrupt
	153	* context, defer enabling the HW interrupt until we leave.
	154	*/
	155	void enable_percpu_irq(unsigned int irq)
	156	{
	157	get_cpu_var(irq_disable_mask) &= ~(1UL << irq);
	158	if (__get_cpu_var(irq_depth) == 0)
	159	unmask_irqs(1UL << irq);
	160	put_cpu_var(irq_disable_mask);
	161	}
	162	EXPORT_SYMBOL(enable_percpu_irq);
	163
	164	/*
	165	* Add an irq to the disabled mask. We disable the HW interrupt
	166	* immediately so that there's no possibility of it firing. If we're
	167	* in an interrupt context, the return path is careful to avoid
	168	* unmasking a newly disabled interrupt.
	169	*/
	170	void disable_percpu_irq(unsigned int irq)
	171	{
	172	get_cpu_var(irq_disable_mask) \|= (1UL << irq);
	173	mask_irqs(1UL << irq);
	174	put_cpu_var(irq_disable_mask);
	175	}
	176	EXPORT_SYMBOL(disable_percpu_irq);
	177
867e359b	178	/* Mask an interrupt. */
fb702b94	179	static void tile_irq_chip_mask(unsigned int irq)
867e359b	180	{
fb702b94	181	mask_irqs(1UL << irq);
867e359b CM	182	}
	183
	184	/* Unmask an interrupt. */
fb702b94	185	static void tile_irq_chip_unmask(unsigned int irq)
867e359b	186	{
fb702b94	187	unmask_irqs(1UL << irq);
867e359b CM	188	}
	189
	190	/*
fb702b94 CM	191	* Clear an interrupt before processing it so that any new assertions
fb702b94 CM	192	* will trigger another irq.
867e359b	193	*/
fb702b94	194	static void tile_irq_chip_ack(unsigned int irq)
867e359b	195	{
fb702b94 CM	196	if ((unsigned long)get_irq_chip_data(irq) != IS_HW_CLEARED)
fb702b94 CM	197	clear_irqs(1UL << irq);
867e359b CM	198	}
	199
	200	/*
fb702b94 CM	201	* For per-cpu interrupts, we need to avoid unmasking any interrupts
fb702b94 CM	202	* that we disabled via disable_percpu_irq().
867e359b	203	*/
fb702b94	204	static void tile_irq_chip_eoi(unsigned int irq)
867e359b	205	{
fb702b94 CM	206	if (!(__get_cpu_var(irq_disable_mask) & (1UL << irq)))
fb702b94 CM	207	unmask_irqs(1UL << irq);
867e359b CM	208	}
867e359b CM	209
fb702b94	210	static struct irq_chip tile_irq_chip = {
d1ea13c6	211	.name = "tile_irq_chip",
fb702b94 CM	212	.ack = tile_irq_chip_ack,
	213	.eoi = tile_irq_chip_eoi,
	214	.mask = tile_irq_chip_mask,
	215	.unmask = tile_irq_chip_unmask,
867e359b CM	216	};
	217
	218	void __init init_IRQ(void)
	219	{
fb702b94	220	ipi_init();
867e359b CM	221	}
867e359b CM	222
fb702b94	223	void __cpuinit setup_irq_regs(void)
867e359b	224	{
fb702b94 CM	225	/* Enable interrupt delivery. */
	226	unmask_irqs(~0UL);
	227	#if CHIP_HAS_IPI()
a78c942d	228	raw_local_irq_unmask(INT_IPI_K);
fb702b94	229	#endif
867e359b CM	230	}
867e359b CM	231
fb702b94	232	void tile_irq_activate(unsigned int irq, int tile_irq_type)
867e359b CM	233	{
867e359b CM	234	/*
fb702b94 CM	235	* We use handle_level_irq() by default because the pending
	236	* interrupt vector (whether modeled by the HV on TILE64 and
	237	* TILEPro or implemented in hardware on TILE-Gx) has
	238	* level-style semantics for each bit. An interrupt fires
	239	* whenever a bit is high, not just at edges.
	240	*/
	241	irq_flow_handler_t handle = handle_level_irq;
	242	if (tile_irq_type == TILE_IRQ_PERCPU)
	243	handle = handle_percpu_irq;
	244	set_irq_chip_and_handler(irq, &tile_irq_chip, handle);
	245
	246	/*
	247	* Flag interrupts that are hardware-cleared so that ack()
	248	* won't clear them.
867e359b	249	*/
fb702b94 CM	250	if (tile_irq_type == TILE_IRQ_HW_CLEAR)
fb702b94 CM	251	set_irq_chip_data(irq, (void *)IS_HW_CLEARED);
867e359b	252	}
fb702b94 CM	253	EXPORT_SYMBOL(tile_irq_activate);
fb702b94 CM	254
867e359b CM	255
	256	void ack_bad_irq(unsigned int irq)
	257	{
fb702b94	258	pr_err("unexpected IRQ trap at vector %02x\n", irq);
867e359b CM	259	}
	260
	261	/*
	262	* Generic, controller-independent functions:
	263	*/
	264
	265	int show_interrupts(struct seq_file p, void v)
	266	{
	267	int i = (loff_t ) v, j;
	268	struct irqaction *action;
	269	unsigned long flags;
	270
	271	if (i == 0) {
	272	seq_printf(p, " ");
	273	for (j = 0; j < NR_CPUS; j++)
	274	if (cpu_online(j))
	275	seq_printf(p, "CPU%-8d", j);
	276	seq_putc(p, '\n');
	277	}
	278
	279	if (i < NR_IRQS) {
	280	raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
	281	action = irq_desc[i].action;
	282	if (!action)
	283	goto skip;
	284	seq_printf(p, "%3d: ", i);
	285	#ifndef CONFIG_SMP
	286	seq_printf(p, "%10u ", kstat_irqs(i));
	287	#else
	288	for_each_online_cpu(j)
	289	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
	290	#endif
d1ea13c6	291	seq_printf(p, " %14s", irq_desc[i].chip->name);
867e359b CM	292	seq_printf(p, " %s", action->name);
	293
	294	for (action = action->next; action; action = action->next)
	295	seq_printf(p, ", %s", action->name);
	296
	297	seq_putc(p, '\n');
	298	skip:
	299	raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	300	}
	301	return 0;
	302	}
fb702b94 CM	303
	304	#if CHIP_HAS_IPI()
	305	int create_irq(void)
	306	{
	307	unsigned long flags;
	308	int result;
	309
	310	spin_lock_irqsave(&available_irqs_lock, flags);
	311	if (available_irqs == 0)
	312	result = -ENOMEM;
	313	else {
	314	result = __ffs(available_irqs);
	315	available_irqs &= ~(1UL << result);
	316	dynamic_irq_init(result);
	317	}
	318	spin_unlock_irqrestore(&available_irqs_lock, flags);
	319
	320	return result;
	321	}
	322	EXPORT_SYMBOL(create_irq);
	323
	324	void destroy_irq(unsigned int irq)
	325	{
	326	unsigned long flags;
	327
	328	spin_lock_irqsave(&available_irqs_lock, flags);
	329	available_irqs \|= (1UL << irq);
	330	dynamic_irq_cleanup(irq);
	331	spin_unlock_irqrestore(&available_irqs_lock, flags);
	332	}
	333	EXPORT_SYMBOL(destroy_irq);
	334	#endif