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64d329ee 1/* linux/arch/sparc/kernel/time.c
1da177e4 2 *
64d329ee 3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4
LT
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 *
6 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
7 * Added support for the intersil on the sun4/4200
8 *
9 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
10 * Support for MicroSPARC-IIep, PCI CPU.
11 *
12 * This file handles the Sparc specific time handling details.
13 *
14 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
15 * "A Kernel Model for Precision Timekeeping" by Dave Mills
16 */
1da177e4
LT
17#include <linux/errno.h>
18#include <linux/module.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/string.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
c4cbe6f9
DM
26#include <linux/rtc.h>
27#include <linux/rtc/m48t59.h>
1da177e4
LT
28#include <linux/timex.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/ioport.h>
32#include <linux/profile.h>
454eeb2d 33#include <linux/of.h>
764f2579 34#include <linux/of_device.h>
c4cbe6f9 35#include <linux/platform_device.h>
1da177e4
LT
36
37#include <asm/oplib.h>
0299b137 38#include <asm/timex.h>
1da177e4 39#include <asm/timer.h>
1da177e4
LT
40#include <asm/system.h>
41#include <asm/irq.h>
42#include <asm/io.h>
43#include <asm/idprom.h>
44#include <asm/machines.h>
1da177e4
LT
45#include <asm/page.h>
46#include <asm/pcic.h>
0d84438d 47#include <asm/irq_regs.h>
1da177e4 48
32231a66
AV
49#include "irq.h"
50
1da177e4 51DEFINE_SPINLOCK(rtc_lock);
6943f3da
SR
52EXPORT_SYMBOL(rtc_lock);
53
1da177e4 54static int set_rtc_mmss(unsigned long);
1da177e4 55
1da177e4
LT
56unsigned long profile_pc(struct pt_regs *regs)
57{
58 extern char __copy_user_begin[], __copy_user_end[];
59 extern char __atomic_begin[], __atomic_end[];
60 extern char __bzero_begin[], __bzero_end[];
1da177e4
LT
61
62 unsigned long pc = regs->pc;
63
64 if (in_lock_functions(pc) ||
65 (pc >= (unsigned long) __copy_user_begin &&
66 pc < (unsigned long) __copy_user_end) ||
67 (pc >= (unsigned long) __atomic_begin &&
68 pc < (unsigned long) __atomic_end) ||
69 (pc >= (unsigned long) __bzero_begin &&
8a8b836b 70 pc < (unsigned long) __bzero_end))
1da177e4
LT
71 pc = regs->u_regs[UREG_RETPC];
72 return pc;
73}
74
9550e59c
MH
75EXPORT_SYMBOL(profile_pc);
76
1da177e4 77__volatile__ unsigned int *master_l10_counter;
1da177e4 78
0299b137
JS
79u32 (*do_arch_gettimeoffset)(void);
80
1da177e4
LT
81/*
82 * timer_interrupt() needs to keep up the real-time clock,
83 * as well as call the "do_timer()" routine every clocktick
84 */
85
86#define TICK_SIZE (tick_nsec / 1000)
87
5dc0742b 88static irqreturn_t timer_interrupt(int dummy, void *dev_id)
1da177e4
LT
89{
90 /* last time the cmos clock got updated */
91 static long last_rtc_update;
92
93#ifndef CONFIG_SMP
0d84438d 94 profile_tick(CPU_PROFILING);
1da177e4
LT
95#endif
96
97 /* Protect counter clear so that do_gettimeoffset works */
98 write_seqlock(&xtime_lock);
5110bd21 99
1da177e4
LT
100 clear_clock_irq();
101
3171a030 102 do_timer(1);
1da177e4
LT
103
104 /* Determine when to update the Mostek clock. */
b149ee22 105 if (ntp_synced() &&
1da177e4
LT
106 xtime.tv_sec > last_rtc_update + 660 &&
107 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
108 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
109 if (set_rtc_mmss(xtime.tv_sec) == 0)
110 last_rtc_update = xtime.tv_sec;
111 else
112 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
113 }
114 write_sequnlock(&xtime_lock);
115
aa02cd2d
PZ
116#ifndef CONFIG_SMP
117 update_process_times(user_mode(get_irq_regs()));
118#endif
1da177e4
LT
119 return IRQ_HANDLED;
120}
121
c4cbe6f9 122static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4 123{
c4cbe6f9
DM
124 struct platform_device *pdev = to_platform_device(dev);
125 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c
KH
126
127 return readb(pdata->ioaddr + ofs);
1da177e4
LT
128}
129
c4cbe6f9 130static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4 131{
c4cbe6f9
DM
132 struct platform_device *pdev = to_platform_device(dev);
133 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c
KH
134
135 writeb(val, pdata->ioaddr + ofs);
1da177e4
LT
136}
137
c4cbe6f9
DM
138static struct m48t59_plat_data m48t59_data = {
139 .read_byte = mostek_read_byte,
140 .write_byte = mostek_write_byte,
141};
142
143/* resource is set at runtime */
144static struct platform_device m48t59_rtc = {
145 .name = "rtc-m48t59",
146 .id = 0,
147 .num_resources = 1,
148 .dev = {
149 .platform_data = &m48t59_data,
150 },
151};
96ba989d 152
ee5caf0e 153static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
1da177e4 154{
ee5caf0e 155 struct device_node *dp = op->node;
8271f042 156 const char *model = of_get_property(dp, "model", NULL);
1da177e4 157
ee5caf0e
DM
158 if (!model)
159 return -ENODEV;
1da177e4 160
c4cbe6f9 161 m48t59_rtc.resource = &op->resource[0];
ee5caf0e 162 if (!strcmp(model, "mk48t02")) {
1da177e4 163 /* Map the clock register io area read-only */
c4cbe6f9
DM
164 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
165 2048, "rtc-m48t59");
166 m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e 167 } else if (!strcmp(model, "mk48t08")) {
c4cbe6f9
DM
168 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
169 8192, "rtc-m48t59");
170 m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e
DM
171 } else
172 return -ENODEV;
1da177e4 173
c4cbe6f9
DM
174 if (platform_device_register(&m48t59_rtc) < 0)
175 printk(KERN_ERR "Registering RTC device failed\n");
96ba989d 176
ee5caf0e
DM
177 return 0;
178}
179
fd098316 180static struct of_device_id __initdata clock_match[] = {
ee5caf0e
DM
181 {
182 .name = "eeprom",
183 },
184 {},
185};
186
187static struct of_platform_driver clock_driver = {
ee5caf0e
DM
188 .match_table = clock_match,
189 .probe = clock_probe,
a2cd1558 190 .driver = {
c4cbe6f9 191 .name = "rtc",
a2cd1558 192 },
ee5caf0e
DM
193};
194
195
196/* Probe for the mostek real time clock chip. */
96ba989d 197static int __init clock_init(void)
ee5caf0e 198{
37b7754a 199 return of_register_driver(&clock_driver, &of_platform_bus_type);
1da177e4 200}
96ba989d
BB
201/* Must be after subsys_initcall() so that busses are probed. Must
202 * be before device_initcall() because things like the RTC driver
203 * need to see the clock registers.
204 */
205fs_initcall(clock_init);
96ba989d 206
1da177e4 207
0299b137 208u32 sbus_do_gettimeoffset(void)
1da177e4 209{
000775c5
DM
210 unsigned long val = *master_l10_counter;
211 unsigned long usec = (val >> 10) & 0x1fffff;
212
213 /* Limit hit? */
214 if (val & 0x80000000)
215 usec += 1000000 / HZ;
216
0299b137 217 return usec * 1000;
1da177e4
LT
218}
219
1da177e4 220
0299b137 221u32 arch_gettimeoffset(void)
1da177e4 222{
0299b137
JS
223 if (unlikely(!do_arch_gettimeoffset))
224 return 0;
225 return do_arch_gettimeoffset();
1da177e4
LT
226}
227
0299b137 228static void __init sbus_time_init(void)
1da177e4 229{
0299b137 230 do_arch_gettimeoffset = sbus_do_gettimeoffset;
1da177e4 231
0299b137 232 btfixup();
1da177e4 233
0299b137
JS
234 sparc_init_timers(timer_interrupt);
235}
1da177e4 236
0299b137
JS
237void __init time_init(void)
238{
239#ifdef CONFIG_PCI
240 extern void pci_time_init(void);
241 if (pcic_present()) {
242 pci_time_init();
243 return;
244 }
245#endif
246 sbus_time_init();
1da177e4
LT
247}
248
0299b137 249
c4cbe6f9 250static int set_rtc_mmss(unsigned long secs)
1da177e4 251{
c4cbe6f9 252 struct rtc_device *rtc = rtc_class_open("rtc0");
ab138c03 253 int err = -1;
1da177e4 254
ab138c03
DM
255 if (rtc) {
256 err = rtc_set_mmss(rtc, secs);
257 rtc_class_close(rtc);
258 }
1da177e4 259
ab138c03 260 return err;
1da177e4 261}