[net-next-2.6.git] / arch / sparc / kernel / sun4m_irq.c

/*  sun4m_irq.c
 *  arch/sparc/kernel/sun4m_irq.c:
 *
 *  djhr: Hacked out of irq.c into a CPU dependent version.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
 *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
 *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
 */

#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/psr.h>
#include <asm/vaddrs.h>
#include <asm/timer.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#include <asm/traps.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/smp.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/cacheflush.h>

#include "irq.h"

struct sun4m_irq_percpu {
	u32		pending;
	u32		clear;
	u32		set;
};

struct sun4m_irq_global {
	u32		pending;
	u32		mask;
	u32		mask_clear;
	u32		mask_set;
	u32		interrupt_target;
};

/* Code in entry.S needs to get at these register mappings.  */
struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
struct sun4m_irq_global __iomem *sun4m_irq_global;

/* Dave Redman (djhr@tadpole.co.uk)
 * The sun4m interrupt registers.
 */
#define SUN4M_INT_ENABLE  	0x80000000
#define SUN4M_INT_E14     	0x00000080
#define SUN4M_INT_E10     	0x00080000

#define SUN4M_HARD_INT(x)	(0x000000001 << (x))
#define SUN4M_SOFT_INT(x)	(0x000010000 << (x))

#define	SUN4M_INT_MASKALL	0x80000000	  /* mask all interrupts */
#define	SUN4M_INT_MODULE_ERR	0x40000000	  /* module error */
#define	SUN4M_INT_M2S_WRITE	0x20000000	  /* write buffer error */
#define	SUN4M_INT_ECC		0x10000000	  /* ecc memory error */
#define	SUN4M_INT_FLOPPY	0x00400000	  /* floppy disk */
#define	SUN4M_INT_MODULE	0x00200000	  /* module interrupt */
#define	SUN4M_INT_VIDEO		0x00100000	  /* onboard video */
#define	SUN4M_INT_REALTIME	0x00080000	  /* system timer */
#define	SUN4M_INT_SCSI		0x00040000	  /* onboard scsi */
#define	SUN4M_INT_AUDIO		0x00020000	  /* audio/isdn */
#define	SUN4M_INT_ETHERNET	0x00010000	  /* onboard ethernet */
#define	SUN4M_INT_SERIAL	0x00008000	  /* serial ports */
#define	SUN4M_INT_KBDMS		0x00004000	  /* keyboard/mouse */
#define	SUN4M_INT_SBUSBITS	0x00003F80	  /* sbus int bits */

#define SUN4M_INT_SBUS(x)	(1 << (x+7))
#define SUN4M_INT_VME(x)	(1 << (x))

/* These tables only apply for interrupts greater than 15..
 * 
 * any intr value below 0x10 is considered to be a soft-int
 * this may be useful or it may not.. but that's how I've done it.
 * and it won't clash with what OBP is telling us about devices.
 *
 * take an encoded intr value and lookup if it's valid
 * then get the mask bits that match from irq_mask
 *
 * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
 */
static unsigned char irq_xlate[32] = {
    /*  0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  a,  b,  c,  d,  e,  f */
	0,  0,  0,  0,  1,  0,  2,  0,  3,  0,  4,  5,  6, 14,  0,  7,
	0,  0,  8,  9,  0, 10,  0, 11,  0, 12,  0, 13,  0, 14,  0,  0
};

static unsigned long irq_mask[] = {
	0,						  /* illegal index */
	SUN4M_INT_SCSI,				  	  /*  1 irq 4 */
	SUN4M_INT_ETHERNET,				  /*  2 irq 6 */
	SUN4M_INT_VIDEO,				  /*  3 irq 8 */
	SUN4M_INT_REALTIME,				  /*  4 irq 10 */
	SUN4M_INT_FLOPPY,				  /*  5 irq 11 */
	(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),	  	  /*  6 irq 12 */
	SUN4M_INT_MODULE_ERR,			  	  /*  7 irq 15 */
	SUN4M_INT_SBUS(0),				  /*  8 irq 2 */
	SUN4M_INT_SBUS(1),				  /*  9 irq 3 */
	SUN4M_INT_SBUS(2),				  /* 10 irq 5 */
	SUN4M_INT_SBUS(3),				  /* 11 irq 7 */
	SUN4M_INT_SBUS(4),				  /* 12 irq 9 */
	SUN4M_INT_SBUS(5),				  /* 13 irq 11 */
	SUN4M_INT_SBUS(6)				  /* 14 irq 13 */
};

static unsigned long sun4m_get_irqmask(unsigned int irq)
{
	unsigned long mask;
    
	if (irq > 0x20) {
		/* OBIO/SBUS interrupts */
		irq &= 0x1f;
		mask = irq_mask[irq_xlate[irq]];
		if (!mask)
			printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
	} else {
		/* Soft Interrupts will come here.
		 * Currently there is no way to trigger them but I'm sure
		 * something could be cooked up.
		 */
		irq &= 0xf;
		mask = SUN4M_SOFT_INT(irq);
	}
	return mask;
}

static void sun4m_disable_irq(unsigned int irq_nr)
{
	unsigned long mask, flags;
	int cpu = smp_processor_id();

	mask = sun4m_get_irqmask(irq_nr);
	local_irq_save(flags);
	if (irq_nr > 15)
		sbus_writel(mask, &sun4m_irq_global->mask_set);
	else
		sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
	local_irq_restore(flags);    
}

static void sun4m_enable_irq(unsigned int irq_nr)
{
	unsigned long mask, flags;
	int cpu = smp_processor_id();

	/* Dreadful floppy hack. When we use 0x2b instead of
         * 0x0b the system blows (it starts to whistle!).
         * So we continue to use 0x0b. Fixme ASAP. --P3
         */
        if (irq_nr != 0x0b) {
		mask = sun4m_get_irqmask(irq_nr);
		local_irq_save(flags);
		if (irq_nr > 15)
			sbus_writel(mask, &sun4m_irq_global->mask_clear);
		else
			sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
		local_irq_restore(flags);    
	} else {
		local_irq_save(flags);
		sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
		local_irq_restore(flags);
	}
}

static unsigned long cpu_pil_to_imask[16] = {
/*0*/	0x00000000,
/*1*/	0x00000000,
/*2*/	SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
/*3*/	SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
/*4*/	SUN4M_INT_SCSI,
/*5*/	SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
/*6*/	SUN4M_INT_ETHERNET,
/*7*/	SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
/*8*/	SUN4M_INT_VIDEO,
/*9*/	SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
/*10*/	SUN4M_INT_REALTIME,
/*11*/	SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
/*12*/	SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
/*13*/	SUN4M_INT_AUDIO,
/*14*/	SUN4M_INT_E14,
/*15*/	0x00000000
};

/* We assume the caller has disabled local interrupts when these are called,
 * or else very bizarre behavior will result.
 */
static void sun4m_disable_pil_irq(unsigned int pil)
{
	sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
}

static void sun4m_enable_pil_irq(unsigned int pil)
{
	sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
}

#ifdef CONFIG_SMP
static void sun4m_send_ipi(int cpu, int level)
{
	unsigned long mask = sun4m_get_irqmask(level);
	sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
}

static void sun4m_clear_ipi(int cpu, int level)
{
	unsigned long mask = sun4m_get_irqmask(level);
	sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
}

static void sun4m_set_udt(int cpu)
{
	sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
}
#endif

struct sun4m_timer_percpu {
	u32		l14_limit;
	u32		l14_count;
	u32		l14_limit_noclear;
	u32		user_timer_start_stop;
};

static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];

struct sun4m_timer_global {
	u32		l10_limit;
	u32		l10_count;
	u32		l10_limit_noclear;
	u32		reserved;
	u32		timer_config;
};

static struct sun4m_timer_global __iomem *timers_global;

#define OBIO_INTR	0x20
#define TIMER_IRQ  	(OBIO_INTR | 10)

unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);

static void sun4m_clear_clock_irq(void)
{
	sbus_readl(&timers_global->l10_limit);
}

/* Exported for sun4m_smp.c */
void sun4m_clear_profile_irq(int cpu)
{
	sbus_readl(&timers_percpu[cpu]->l14_limit);
}

static void sun4m_load_profile_irq(int cpu, unsigned int limit)
{
	sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
}

static void __init sun4m_init_timers(irq_handler_t counter_fn)
{
	struct device_node *dp = of_find_node_by_name(NULL, "counter");
	int i, err, len, num_cpu_timers;
	const u32 *addr;

	if (!dp) {
		printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
		return;
	}

	addr = of_get_property(dp, "address", &len);
	if (!addr) {
		printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
		return;
	}

	num_cpu_timers = (len / sizeof(u32)) - 1;
	for (i = 0; i < num_cpu_timers; i++) {
		timers_percpu[i] = (void __iomem *)
			(unsigned long) addr[i];
	}
	timers_global = (void __iomem *)
		(unsigned long) addr[num_cpu_timers];

	sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);

	master_l10_counter = &timers_global->l10_count;

	err = request_irq(TIMER_IRQ, counter_fn,
			  (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
	if (err) {
		printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
			err);
		return;
	}

	for (i = 0; i < num_cpu_timers; i++)
		sbus_writel(0, &timers_percpu[i]->l14_limit);
	if (num_cpu_timers == 4)
		sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);

#ifdef CONFIG_SMP
	{
		unsigned long flags;
		extern unsigned long lvl14_save[4];
		struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];

		/* For SMP we use the level 14 ticker, however the bootup code
		 * has copied the firmware's level 14 vector into the boot cpu's
		 * trap table, we must fix this now or we get squashed.
		 */
		local_irq_save(flags);
		trap_table->inst_one = lvl14_save[0];
		trap_table->inst_two = lvl14_save[1];
		trap_table->inst_three = lvl14_save[2];
		trap_table->inst_four = lvl14_save[3];
		local_flush_cache_all();
		local_irq_restore(flags);
	}
#endif
}

void __init sun4m_init_IRQ(void)
{
	struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
	int len, i, mid, num_cpu_iregs;
	const u32 *addr;

	if (!dp) {
		printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
		return;
	}

	addr = of_get_property(dp, "address", &len);
	if (!addr) {
		printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
		return;
	}

	num_cpu_iregs = (len / sizeof(u32)) - 1;
	for (i = 0; i < num_cpu_iregs; i++) {
		sun4m_irq_percpu[i] = (void __iomem *)
			(unsigned long) addr[i];
	}
	sun4m_irq_global = (void __iomem *)
		(unsigned long) addr[num_cpu_iregs];

	local_irq_disable();

	sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
	for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
		sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);

	if (num_cpu_iregs == 4)
		sbus_writel(0, &sun4m_irq_global->interrupt_target);

	BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
	sparc_init_timers = sun4m_init_timers;
#ifdef CONFIG_SMP
	BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
#endif

	/* Cannot enable interrupts until OBP ticker is disabled. */
}
Commit	Line	Data
1da177e4 LT	1	/* sun4m_irq.c
	2	* arch/sparc/kernel/sun4m_irq.c:
	3	*
	4	* djhr: Hacked out of irq.c into a CPU dependent version.
	5	*
	6	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	7	* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
	8	* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
	9	* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
	10	*/
	11
1da177e4 LT	12	#include <linux/errno.h>
	13	#include <linux/linkage.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/signal.h>
	16	#include <linux/sched.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/smp.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/slab.h>
	21	#include <linux/init.h>
	22	#include <linux/ioport.h>
454eeb2d DM	23	#include <linux/of.h>
454eeb2d DM	24	#include <linux/of_device.h>
1da177e4 LT	25
	26	#include <asm/ptrace.h>
	27	#include <asm/processor.h>
	28	#include <asm/system.h>
	29	#include <asm/psr.h>
	30	#include <asm/vaddrs.h>
	31	#include <asm/timer.h>
	32	#include <asm/openprom.h>
	33	#include <asm/oplib.h>
	34	#include <asm/traps.h>
	35	#include <asm/pgalloc.h>
	36	#include <asm/pgtable.h>
	37	#include <asm/smp.h>
	38	#include <asm/irq.h>
	39	#include <asm/io.h>
1da177e4 LT	40	#include <asm/cacheflush.h>
1da177e4 LT	41
32231a66 AV	42	#include "irq.h"
32231a66 AV	43
69c010b2 DM	44	struct sun4m_irq_percpu {
	45	u32 pending;
	46	u32 clear;
	47	u32 set;
32231a66 AV	48	};
32231a66 AV	49
69c010b2 DM	50	struct sun4m_irq_global {
	51	u32 pending;
	52	u32 mask;
	53	u32 mask_clear;
	54	u32 mask_set;
	55	u32 interrupt_target;
32231a66 AV	56	};
32231a66 AV	57
69c010b2 DM	58	/* Code in entry.S needs to get at these register mappings. */
	59	struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
	60	struct sun4m_irq_global __iomem *sun4m_irq_global;
1da177e4	61
32231a66 AV	62	/* Dave Redman (djhr@tadpole.co.uk)
	63	* The sun4m interrupt registers.
	64	*/
	65	#define SUN4M_INT_ENABLE 0x80000000
	66	#define SUN4M_INT_E14 0x00000080
	67	#define SUN4M_INT_E10 0x00080000
	68
	69	#define SUN4M_HARD_INT(x) (0x000000001 << (x))
	70	#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
	71
	72	#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
	73	#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
	74	#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
	75	#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
	76	#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
	77	#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
	78	#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
	79	#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
	80	#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
	81	#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
	82	#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
	83	#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
	84	#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
	85	#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
	86
	87	#define SUN4M_INT_SBUS(x) (1 << (x+7))
	88	#define SUN4M_INT_VME(x) (1 << (x))
	89
1da177e4 LT	90	/* These tables only apply for interrupts greater than 15..
	91	*
	92	* any intr value below 0x10 is considered to be a soft-int
	93	* this may be useful or it may not.. but that's how I've done it.
	94	* and it won't clash with what OBP is telling us about devices.
	95	*
	96	* take an encoded intr value and lookup if it's valid
	97	* then get the mask bits that match from irq_mask
	98	*
	99	* P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
	100	*/
	101	static unsigned char irq_xlate[32] = {
	102	/* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
	103	0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
	104	0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
	105	};
	106
	107	static unsigned long irq_mask[] = {
	108	0, /* illegal index */
	109	SUN4M_INT_SCSI, /* 1 irq 4 */
	110	SUN4M_INT_ETHERNET, /* 2 irq 6 */
	111	SUN4M_INT_VIDEO, /* 3 irq 8 */
	112	SUN4M_INT_REALTIME, /* 4 irq 10 */
	113	SUN4M_INT_FLOPPY, /* 5 irq 11 */
	114	(SUN4M_INT_SERIAL \| SUN4M_INT_KBDMS), /* 6 irq 12 */
	115	SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
	116	SUN4M_INT_SBUS(0), /* 8 irq 2 */
	117	SUN4M_INT_SBUS(1), /* 9 irq 3 */
	118	SUN4M_INT_SBUS(2), /* 10 irq 5 */
	119	SUN4M_INT_SBUS(3), /* 11 irq 7 */
	120	SUN4M_INT_SBUS(4), /* 12 irq 9 */
	121	SUN4M_INT_SBUS(5), /* 13 irq 11 */
	122	SUN4M_INT_SBUS(6) /* 14 irq 13 */
	123	};
	124
c61c65cd	125	static unsigned long sun4m_get_irqmask(unsigned int irq)
1da177e4 LT	126	{
	127	unsigned long mask;
	128
	129	if (irq > 0x20) {
	130	/* OBIO/SBUS interrupts */
	131	irq &= 0x1f;
	132	mask = irq_mask[irq_xlate[irq]];
	133	if (!mask)
	134	printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
	135	} else {
	136	/* Soft Interrupts will come here.
	137	* Currently there is no way to trigger them but I'm sure
	138	* something could be cooked up.
	139	*/
	140	irq &= 0xf;
	141	mask = SUN4M_SOFT_INT(irq);
	142	}
	143	return mask;
	144	}
	145
	146	static void sun4m_disable_irq(unsigned int irq_nr)
	147	{
	148	unsigned long mask, flags;
	149	int cpu = smp_processor_id();
	150
	151	mask = sun4m_get_irqmask(irq_nr);
	152	local_irq_save(flags);
	153	if (irq_nr > 15)
69c010b2	154	sbus_writel(mask, &sun4m_irq_global->mask_set);
1da177e4	155	else
69c010b2	156	sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
1da177e4 LT	157	local_irq_restore(flags);
	158	}
	159
	160	static void sun4m_enable_irq(unsigned int irq_nr)
	161	{
	162	unsigned long mask, flags;
	163	int cpu = smp_processor_id();
	164
	165	/* Dreadful floppy hack. When we use 0x2b instead of
	166	* 0x0b the system blows (it starts to whistle!).
	167	* So we continue to use 0x0b. Fixme ASAP. --P3
	168	*/
	169	if (irq_nr != 0x0b) {
	170	mask = sun4m_get_irqmask(irq_nr);
	171	local_irq_save(flags);
	172	if (irq_nr > 15)
69c010b2	173	sbus_writel(mask, &sun4m_irq_global->mask_clear);
1da177e4	174	else
69c010b2	175	sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
1da177e4 LT	176	local_irq_restore(flags);
	177	} else {
	178	local_irq_save(flags);
69c010b2	179	sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
1da177e4 LT	180	local_irq_restore(flags);
	181	}
	182	}
	183
	184	static unsigned long cpu_pil_to_imask[16] = {
	185	/0/ 0x00000000,
	186	/1/ 0x00000000,
	187	/2/ SUN4M_INT_SBUS(0) \| SUN4M_INT_VME(0),
	188	/3/ SUN4M_INT_SBUS(1) \| SUN4M_INT_VME(1),
	189	/4/ SUN4M_INT_SCSI,
	190	/5/ SUN4M_INT_SBUS(2) \| SUN4M_INT_VME(2),
	191	/6/ SUN4M_INT_ETHERNET,
	192	/7/ SUN4M_INT_SBUS(3) \| SUN4M_INT_VME(3),
	193	/8/ SUN4M_INT_VIDEO,
	194	/9/ SUN4M_INT_SBUS(4) \| SUN4M_INT_VME(4) \| SUN4M_INT_MODULE_ERR,
	195	/10/ SUN4M_INT_REALTIME,
	196	/11/ SUN4M_INT_SBUS(5) \| SUN4M_INT_VME(5) \| SUN4M_INT_FLOPPY,
	197	/12/ SUN4M_INT_SERIAL \| SUN4M_INT_KBDMS,
	198	/13/ SUN4M_INT_AUDIO,
	199	/14/ SUN4M_INT_E14,
	200	/15/ 0x00000000
	201	};
	202
	203	/* We assume the caller has disabled local interrupts when these are called,
	204	* or else very bizarre behavior will result.
	205	*/
	206	static void sun4m_disable_pil_irq(unsigned int pil)
	207	{
69c010b2	208	sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
1da177e4 LT	209	}
	210
	211	static void sun4m_enable_pil_irq(unsigned int pil)
	212	{
69c010b2	213	sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
1da177e4 LT	214	}
	215
	216	#ifdef CONFIG_SMP
	217	static void sun4m_send_ipi(int cpu, int level)
	218	{
69c010b2 DM	219	unsigned long mask = sun4m_get_irqmask(level);
69c010b2 DM	220	sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
1da177e4 LT	221	}
	222
	223	static void sun4m_clear_ipi(int cpu, int level)
	224	{
69c010b2 DM	225	unsigned long mask = sun4m_get_irqmask(level);
69c010b2 DM	226	sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
1da177e4 LT	227	}
	228
	229	static void sun4m_set_udt(int cpu)
	230	{
69c010b2	231	sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
1da177e4 LT	232	}
	233	#endif
	234
9b2e43ae DM	235	struct sun4m_timer_percpu {
	236	u32 l14_limit;
	237	u32 l14_count;
	238	u32 l14_limit_noclear;
	239	u32 user_timer_start_stop;
	240	};
	241
	242	static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
	243
	244	struct sun4m_timer_global {
	245	u32 l10_limit;
	246	u32 l10_count;
	247	u32 l10_limit_noclear;
	248	u32 reserved;
	249	u32 timer_config;
	250	};
	251
	252	static struct sun4m_timer_global __iomem *timers_global;
	253
1da177e4 LT	254	#define OBIO_INTR 0x20
1da177e4 LT	255	#define TIMER_IRQ (OBIO_INTR \| 10)
1da177e4	256
1da177e4 LT	257	unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
	258
	259	static void sun4m_clear_clock_irq(void)
	260	{
9b2e43ae	261	sbus_readl(&timers_global->l10_limit);
1da177e4 LT	262	}
1da177e4 LT	263
1de937a5 DM	264	/* Exported for sun4m_smp.c */
1de937a5 DM	265	void sun4m_clear_profile_irq(int cpu)
1da177e4	266	{
9b2e43ae	267	sbus_readl(&timers_percpu[cpu]->l14_limit);
1da177e4 LT	268	}
	269
	270	static void sun4m_load_profile_irq(int cpu, unsigned int limit)
	271	{
9b2e43ae	272	sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
1da177e4 LT	273	}
1da177e4 LT	274
40220c1a	275	static void __init sun4m_init_timers(irq_handler_t counter_fn)
1da177e4	276	{
9b2e43ae DM	277	struct device_node *dp = of_find_node_by_name(NULL, "counter");
	278	int i, err, len, num_cpu_timers;
	279	const u32 *addr;
	280
	281	if (!dp) {
	282	printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
	283	return;
1da177e4	284	}
9b2e43ae DM	285
	286	addr = of_get_property(dp, "address", &len);
	287	if (!addr) {
	288	printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
	289	return;
1da177e4 LT	290	}
1da177e4 LT	291
9b2e43ae DM	292	num_cpu_timers = (len / sizeof(u32)) - 1;
	293	for (i = 0; i < num_cpu_timers; i++) {
	294	timers_percpu[i] = (void __iomem *)
	295	(unsigned long) addr[i];
1da177e4	296	}
9b2e43ae DM	297	timers_global = (void __iomem *)
	298	(unsigned long) addr[num_cpu_timers];
	299
	300	sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
	301
	302	master_l10_counter = &timers_global->l10_count;
9b2e43ae DM	303
	304	err = request_irq(TIMER_IRQ, counter_fn,
	305	(IRQF_DISABLED \| SA_STATIC_ALLOC), "timer", NULL);
	306	if (err) {
	307	printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
	308	err);
	309	return;
1da177e4	310	}
9b2e43ae DM	311
	312	for (i = 0; i < num_cpu_timers; i++)
	313	sbus_writel(0, &timers_percpu[i]->l14_limit);
	314	if (num_cpu_timers == 4)
69c010b2	315	sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
9b2e43ae	316
1da177e4 LT	317	#ifdef CONFIG_SMP
	318	{
	319	unsigned long flags;
	320	extern unsigned long lvl14_save[4];
	321	struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
	322
	323	/* For SMP we use the level 14 ticker, however the bootup code
d1a78c32	324	* has copied the firmware's level 14 vector into the boot cpu's
1da177e4 LT	325	* trap table, we must fix this now or we get squashed.
	326	*/
	327	local_irq_save(flags);
	328	trap_table->inst_one = lvl14_save[0];
	329	trap_table->inst_two = lvl14_save[1];
	330	trap_table->inst_three = lvl14_save[2];
	331	trap_table->inst_four = lvl14_save[3];
	332	local_flush_cache_all();
	333	local_irq_restore(flags);
	334	}
	335	#endif
	336	}
	337
	338	void __init sun4m_init_IRQ(void)
	339	{
69c010b2 DM	340	struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
	341	int len, i, mid, num_cpu_iregs;
	342	const u32 *addr;
	343
	344	if (!dp) {
	345	printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
	346	return;
1da177e4	347	}
69c010b2 DM	348
	349	addr = of_get_property(dp, "address", &len);
	350	if (!addr) {
	351	printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
	352	return;
1da177e4 LT	353	}
1da177e4 LT	354
69c010b2 DM	355	num_cpu_iregs = (len / sizeof(u32)) - 1;
	356	for (i = 0; i < num_cpu_iregs; i++) {
	357	sun4m_irq_percpu[i] = (void __iomem *)
	358	(unsigned long) addr[i];
	359	}
	360	sun4m_irq_global = (void __iomem *)
	361	(unsigned long) addr[num_cpu_iregs];
1da177e4	362
69c010b2	363	local_irq_disable();
1da177e4	364
69c010b2	365	sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
1da177e4	366	for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
69c010b2 DM	367	sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
69c010b2 DM	368
e7913de9	369	if (num_cpu_iregs == 4)
69c010b2	370	sbus_writel(0, &sun4m_irq_global->interrupt_target);
e7913de9	371
1da177e4 LT	372	BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
	373	BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
	374	BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
	375	BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
	376	BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
1da177e4	377	BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
1da177e4 LT	378	sparc_init_timers = sun4m_init_timers;
	379	#ifdef CONFIG_SMP
	380	BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
	381	BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
	382	BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
	383	#endif
69c010b2	384
1da177e4 LT	385	/* Cannot enable interrupts until OBP ticker is disabled. */
1da177e4 LT	386	}