[net-next-2.6.git] / arch / sparc / kernel / sun4c_irq.c

/*  sun4c_irq.c
 *  arch/sparc/kernel/sun4c_irq.c:
 *
 *  djhr: Hacked out of irq.c into a CPU dependent version.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
 *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
 *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
 */

#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include "irq.h"

#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/psr.h>
#include <asm/vaddrs.h>
#include <asm/timer.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#include <asm/traps.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/idprom.h>
#include <asm/machines.h>

/*
 * Bit field defines for the interrupt registers on various
 * Sparc machines.
 */

/* The sun4c interrupt register. */
#define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
#define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
#define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
#define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
#define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
#define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
#define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */

/* Pointer to the interrupt enable byte
 *
 * Dave Redman (djhr@tadpole.co.uk)
 * What you may not be aware of is that entry.S requires this variable.
 *
 *  --- linux_trap_nmi_sun4c --
 *
 * so don't go making it static, like I tried. sigh.
 */
unsigned char __iomem *interrupt_enable = NULL;

static void sun4c_disable_irq(unsigned int irq_nr)
{
	unsigned long flags;
	unsigned char current_mask, new_mask;
    
	local_irq_save(flags);
	irq_nr &= (NR_IRQS - 1);
	current_mask = sbus_readb(interrupt_enable);
	switch(irq_nr) {
	case 1:
		new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
		break;
	case 8:
		new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
		break;
	case 10:
		new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
		break;
	case 14:
		new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
		break;
	default:
		local_irq_restore(flags);
		return;
	}
	sbus_writeb(new_mask, interrupt_enable);
	local_irq_restore(flags);
}

static void sun4c_enable_irq(unsigned int irq_nr)
{
	unsigned long flags;
	unsigned char current_mask, new_mask;
    
	local_irq_save(flags);
	irq_nr &= (NR_IRQS - 1);
	current_mask = sbus_readb(interrupt_enable);
	switch(irq_nr) {
	case 1:
		new_mask = ((current_mask) | SUN4C_INT_E1);
		break;
	case 8:
		new_mask = ((current_mask) | SUN4C_INT_E8);
		break;
	case 10:
		new_mask = ((current_mask) | SUN4C_INT_E10);
		break;
	case 14:
		new_mask = ((current_mask) | SUN4C_INT_E14);
		break;
	default:
		local_irq_restore(flags);
		return;
	}
	sbus_writeb(new_mask, interrupt_enable);
	local_irq_restore(flags);
}

struct sun4c_timer_info {
	u32		l10_count;
	u32		l10_limit;
	u32		l14_count;
	u32		l14_limit;
};

static struct sun4c_timer_info __iomem *sun4c_timers;

static void sun4c_clear_clock_irq(void)
{
	sbus_readl(&sun4c_timers->l10_limit);
}

static void sun4c_load_profile_irq(int cpu, unsigned int limit)
{
	/* Errm.. not sure how to do this.. */
}

static void __init sun4c_init_timers(irq_handler_t counter_fn)
{
	const struct linux_prom_irqs *irq;
	struct device_node *dp;
	const u32 *addr;
	int err;

	dp = of_find_node_by_name(NULL, "counter-timer");
	if (!dp) {
		prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
		prom_halt();
	}

	addr = of_get_property(dp, "address", NULL);
	if (!addr) {
		prom_printf("sun4c_init_timers: No address property\n");
		prom_halt();
	}

	sun4c_timers = (void __iomem *) (unsigned long) addr[0];

	irq = of_get_property(dp, "intr", NULL);
	if (!irq) {
		prom_printf("sun4c_init_timers: No intr property\n");
		prom_halt();
	}

	/* Have the level 10 timer tick at 100HZ.  We don't touch the
	 * level 14 timer limit since we are letting the prom handle
	 * them until we have a real console driver so L1-A works.
	 */
	sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);

	master_l10_counter = &sun4c_timers->l10_count;

	err = request_irq(irq[0].pri, counter_fn,
			  (IRQF_DISABLED | SA_STATIC_ALLOC),
			  "timer", NULL);
	if (err) {
		prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
		prom_halt();
	}
    
	sun4c_disable_irq(irq[1].pri);
}

#ifdef CONFIG_SMP
static void sun4c_nop(void) {}
#endif

void __init sun4c_init_IRQ(void)
{
	struct device_node *dp;
	const u32 *addr;

	dp = of_find_node_by_name(NULL, "interrupt-enable");
	if (!dp) {
		prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
		prom_halt();
	}

	addr = of_get_property(dp, "address", NULL);
	if (!addr) {
		prom_printf("sun4c_init_IRQ: No address property\n");
		prom_halt();
	}

	interrupt_enable = (void __iomem *) (unsigned long) addr[0];

	BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
	sparc_init_timers = sun4c_init_timers;
#ifdef CONFIG_SMP
	BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
	BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
	BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
#endif
	sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
	/* Cannot enable interrupts until OBP ticker is disabled. */
}
Commit	Line	Data
1da177e4 LT	1	/* sun4c_irq.c
	2	* arch/sparc/kernel/sun4c_irq.c:
	3	*
	4	* djhr: Hacked out of irq.c into a CPU dependent version.
	5	*
	6	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	7	* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
	8	* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
	9	* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
	10	*/
	11
1da177e4 LT	12	#include <linux/errno.h>
	13	#include <linux/linkage.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/signal.h>
	16	#include <linux/sched.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/init.h>
454eeb2d DM	21	#include <linux/of.h>
454eeb2d DM	22	#include <linux/of_device.h>
32231a66	23	#include "irq.h"
1da177e4 LT	24
	25	#include <asm/ptrace.h>
	26	#include <asm/processor.h>
	27	#include <asm/system.h>
	28	#include <asm/psr.h>
	29	#include <asm/vaddrs.h>
	30	#include <asm/timer.h>
	31	#include <asm/openprom.h>
	32	#include <asm/oplib.h>
	33	#include <asm/traps.h>
	34	#include <asm/irq.h>
	35	#include <asm/io.h>
1da177e4 LT	36	#include <asm/idprom.h>
1da177e4 LT	37	#include <asm/machines.h>
1da177e4	38
32231a66 AV	39	/*
	40	* Bit field defines for the interrupt registers on various
	41	* Sparc machines.
	42	*/
	43
	44	/* The sun4c interrupt register. */
	45	#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
	46	#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
	47	#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
	48	#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
	49	#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
	50	#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
	51	#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
	52
1da177e4 LT	53	/* Pointer to the interrupt enable byte
	54	*
	55	* Dave Redman (djhr@tadpole.co.uk)
	56	* What you may not be aware of is that entry.S requires this variable.
	57	*
	58	* --- linux_trap_nmi_sun4c --
	59	*
	60	* so don't go making it static, like I tried. sigh.
	61	*/
45bb5a7c	62	unsigned char __iomem *interrupt_enable = NULL;
1da177e4	63
1da177e4 LT	64	static void sun4c_disable_irq(unsigned int irq_nr)
	65	{
	66	unsigned long flags;
	67	unsigned char current_mask, new_mask;
	68
	69	local_irq_save(flags);
	70	irq_nr &= (NR_IRQS - 1);
45bb5a7c	71	current_mask = sbus_readb(interrupt_enable);
1da177e4 LT	72	switch(irq_nr) {
	73	case 1:
	74	new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
	75	break;
	76	case 8:
	77	new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
	78	break;
	79	case 10:
	80	new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
	81	break;
	82	case 14:
	83	new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
	84	break;
	85	default:
	86	local_irq_restore(flags);
	87	return;
	88	}
45bb5a7c	89	sbus_writeb(new_mask, interrupt_enable);
1da177e4 LT	90	local_irq_restore(flags);
	91	}
	92
	93	static void sun4c_enable_irq(unsigned int irq_nr)
	94	{
	95	unsigned long flags;
	96	unsigned char current_mask, new_mask;
	97
	98	local_irq_save(flags);
	99	irq_nr &= (NR_IRQS - 1);
45bb5a7c	100	current_mask = sbus_readb(interrupt_enable);
1da177e4 LT	101	switch(irq_nr) {
	102	case 1:
	103	new_mask = ((current_mask) \| SUN4C_INT_E1);
	104	break;
	105	case 8:
	106	new_mask = ((current_mask) \| SUN4C_INT_E8);
	107	break;
	108	case 10:
	109	new_mask = ((current_mask) \| SUN4C_INT_E10);
	110	break;
	111	case 14:
	112	new_mask = ((current_mask) \| SUN4C_INT_E14);
	113	break;
	114	default:
	115	local_irq_restore(flags);
	116	return;
	117	}
45bb5a7c	118	sbus_writeb(new_mask, interrupt_enable);
1da177e4 LT	119	local_irq_restore(flags);
	120	}
	121
8bd8deea DM	122	struct sun4c_timer_info {
	123	u32 l10_count;
	124	u32 l10_limit;
	125	u32 l14_count;
	126	u32 l14_limit;
	127	};
1da177e4	128
8bd8deea	129	static struct sun4c_timer_info __iomem *sun4c_timers;
1da177e4	130
1da177e4 LT	131	static void sun4c_clear_clock_irq(void)
1da177e4 LT	132	{
8bd8deea	133	sbus_readl(&sun4c_timers->l10_limit);
1da177e4 LT	134	}
1da177e4 LT	135
1da177e4 LT	136	static void sun4c_load_profile_irq(int cpu, unsigned int limit)
	137	{
	138	/* Errm.. not sure how to do this.. */
	139	}
	140
40220c1a	141	static void __init sun4c_init_timers(irq_handler_t counter_fn)
1da177e4	142	{
8bd8deea DM	143	const struct linux_prom_irqs *irq;
	144	struct device_node *dp;
	145	const u32 *addr;
	146	int err;
1da177e4	147
8bd8deea DM	148	dp = of_find_node_by_name(NULL, "counter-timer");
	149	if (!dp) {
	150	prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
	151	prom_halt();
	152	}
	153
	154	addr = of_get_property(dp, "address", NULL);
	155	if (!addr) {
	156	prom_printf("sun4c_init_timers: No address property\n");
	157	prom_halt();
	158	}
	159
	160	sun4c_timers = (void __iomem *) (unsigned long) addr[0];
	161
	162	irq = of_get_property(dp, "intr", NULL);
	163	if (!irq) {
	164	prom_printf("sun4c_init_timers: No intr property\n");
	165	prom_halt();
	166	}
1da177e4 LT	167
	168	/* Have the level 10 timer tick at 100HZ. We don't touch the
	169	* level 14 timer limit since we are letting the prom handle
	170	* them until we have a real console driver so L1-A works.
	171	*/
8bd8deea DM	172	sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
	173
	174	master_l10_counter = &sun4c_timers->l10_count;
1da177e4	175
8bd8deea	176	err = request_irq(irq[0].pri, counter_fn,
67413202	177	(IRQF_DISABLED \| SA_STATIC_ALLOC),
1da177e4	178	"timer", NULL);
8bd8deea DM	179	if (err) {
8bd8deea DM	180	prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
1da177e4 LT	181	prom_halt();
	182	}
	183
8bd8deea	184	sun4c_disable_irq(irq[1].pri);
1da177e4 LT	185	}
	186
	187	#ifdef CONFIG_SMP
	188	static void sun4c_nop(void) {}
	189	#endif
	190
1da177e4 LT	191	void __init sun4c_init_IRQ(void)
1da177e4 LT	192	{
45bb5a7c DM	193	struct device_node *dp;
	194	const u32 *addr;
	195
	196	dp = of_find_node_by_name(NULL, "interrupt-enable");
	197	if (!dp) {
	198	prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
	199	prom_halt();
	200	}
	201
	202	addr = of_get_property(dp, "address", NULL);
	203	if (!addr) {
	204	prom_printf("sun4c_init_IRQ: No address property\n");
	205	prom_halt();
1da177e4	206	}
45bb5a7c DM	207
45bb5a7c DM	208	interrupt_enable = (void __iomem *) (unsigned long) addr[0];
1da177e4	209
1da177e4 LT	210	BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
	211	BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
	212	BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
	213	BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
	214	BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
1da177e4	215	BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
1da177e4 LT	216	sparc_init_timers = sun4c_init_timers;
	217	#ifdef CONFIG_SMP
	218	BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
	219	BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
	220	BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
	221	#endif
45bb5a7c	222	sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
1da177e4 LT	223	/* Cannot enable interrupts until OBP ticker is disabled. */
1da177e4 LT	224	}