[net-next-2.6.git] / arch / sparc / kernel / rtrap_64.S

/*
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#define		RTRAP_PSTATE		(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
#define		RTRAP_PSTATE_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
#define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)

		.text
		.align			32
__handle_softirq:
		call			do_softirq
		 nop
		ba,a,pt			%xcc, __handle_softirq_continue
		 nop
__handle_preemption:
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_preemption_continue
		 andn			%l1, %l4, %l1

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
		 */
		.globl			rtrap_nmi
rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
		ba,pt			%xcc, rtrap_no_irq_enable
		 wrpr			%l4, %pil

		.align			64
		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap:
#ifndef CONFIG_SMP
		sethi			%hi(__cpu_data), %l0
		lduw			[%l0 + %lo(__cpu_data)], %l1
#else
		sethi			%hi(__cpu_data), %l0
		or			%l0, %lo(__cpu_data), %l0
		lduw			[%l0 + %g5], %l1
#endif
		cmp			%l1, 0

		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		bne,pn			%icc, __handle_softirq
		 ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
__handle_softirq_continue:
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 *
		 * It is tempting to put this test and trace_hardirqs_on
		 * call at the 'rt_continue' label, but that will not work
		 * as that path hits unconditionally and we do not want to
		 * execute this in NMI return paths, for example.
		 */
#endif
rtrap_no_irq_enable:
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with user
		 * windows, we have to redo all of these sched+signal checks
		 * with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		bne,pn			%xcc, __handle_signal
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
		sethi			%hi(TSTATE_PEF), %o0
		andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		andn			%l1, TSTATE_SYSCALL, %l1
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup:
		rdpr	%cwp, %g1
		add	%g1, 1, %g1
		wrpr	%g1, 0x0, %cwp

		rdpr	%wstate, %g2
		sll	%g2, 3, %g2
		wrpr	%g2, 0x0, %wstate

		/* We know %canrestore and %otherwin are both zero.  */

		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g2
		mov	PRIMARY_CONTEXT, %g1

661:		stxa	%g2, [%g1] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g2, [%g1] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %g1
		flush	%g1

		or	%g4, FAULT_CODE_WINFIXUP, %g4
		stb	%g4, [%g6 + TI_FAULT_CODE]
		stx	%g5, [%g6 + TI_FAULT_ADDR]

		mov	%g6, %l1
		wrpr	%g0, 0x0, %tl

661:		nop
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(0)
		.previous

		wrpr	%g0, RTRAP_PSTATE, %pstate

		mov	%l1, %g6
		ldx	[%g6 + TI_TASK], %g4
		LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
		call	do_sparc64_fault
		 add	%sp, PTREGS_OFF, %o0
		ba,pt	%xcc, rtrap
		 nop

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 sethi			%hi(PREEMPT_ACTIVE), %l6
		stw			%l6, [%g6 + TI_PRE_COUNT]
		call			schedule
		 nop
		ba,pt			%xcc, rtrap
		 stw			%g0, [%g6 + TI_PRE_COUNT]
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/spitfire.h>
	13	#include <asm/head.h>
	14	#include <asm/visasm.h>
	15	#include <asm/processor.h>
	16
64f2dde3 DM	17	#define RTRAP_PSTATE (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_IE)
	18	#define RTRAP_PSTATE_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV)
	19	#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_AG)
1da177e4	20
1da177e4 LT	21	.text
	22	.align 32
	23	__handle_softirq:
	24	call do_softirq
	25	nop
	26	ba,a,pt %xcc, __handle_softirq_continue
	27	nop
	28	__handle_preemption:
	29	call schedule
	30	wrpr %g0, RTRAP_PSTATE, %pstate
	31	ba,pt %xcc, __handle_preemption_continue
	32	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	33
	34	__handle_user_windows:
	35	call fault_in_user_windows
	36	wrpr %g0, RTRAP_PSTATE, %pstate
caebf910 AV	37	ba,pt %xcc, __handle_preemption_continue
caebf910 AV	38	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4	39
1da177e4 LT	40	__handle_userfpu:
	41	rd %fprs, %l5
	42	andcc %l5, FPRS_FEF, %g0
	43	sethi %hi(TSTATE_PEF), %o0
	44	be,a,pn %icc, __handle_userfpu_continue
	45	andn %l1, %o0, %l1
	46	ba,a,pt %xcc, __handle_userfpu_continue
	47
	48	__handle_signal:
2d7d5f05	49	mov %l5, %o1
2d7d5f05	50	add %sp, PTREGS_OFF, %o0
7697daaa	51	mov %l0, %o2
1da177e4 LT	52	call do_notify_resume
	53	wrpr %g0, RTRAP_PSTATE, %pstate
	54	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	55
	56	/* Signal delivery can modify pt_regs tstate, so we must
	57	* reload it.
	58	*/
	59	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	60	sethi %hi(0xf << 20), %l4
	61	and %l1, %l4, %l4
caebf910	62	ba,pt %xcc, __handle_preemption_continue
1da177e4 LT	63	andn %l1, %l4, %l1
1da177e4 LT	64
5565736e DM	65	/* When returning from a NMI (%pil==15) interrupt we want to
	66	* avoid running softirqs, doing IRQ tracing, preempting, etc.
	67	*/
	68	.globl rtrap_nmi
	69	rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	70	sethi %hi(0xf << 20), %l4
	71	and %l1, %l4, %l4
	72	andn %l1, %l4, %l1
	73	srl %l4, 20, %l4
	74	ba,pt %xcc, rtrap_no_irq_enable
	75	wrpr %l4, %pil
	76
1da177e4	77	.align 64
7697daaa	78	.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4	79	rtrap_irq:
1da177e4	80	rtrap:
d7ce78fd	81	#ifndef CONFIG_SMP
dd17c8f7 RR	82	sethi %hi(__cpu_data), %l0
dd17c8f7 RR	83	lduw [%l0 + %lo(__cpu_data)], %l1
d7ce78fd	84	#else
dd17c8f7 RR	85	sethi %hi(__cpu_data), %l0
dd17c8f7 RR	86	or %l0, %lo(__cpu_data), %l0
d7ce78fd DM	87	lduw [%l0 + %g5], %l1
d7ce78fd DM	88	#endif
1da177e4 LT	89	cmp %l1, 0
	90
	91	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
	92	bne,pn %icc, __handle_softirq
	93	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	94	__handle_softirq_continue:
	95	rtrap_xcall:
	96	sethi %hi(0xf << 20), %l4
1da177e4	97	and %l1, %l4, %l4
10e26723 DM	98	andn %l1, %l4, %l1
	99	srl %l4, 20, %l4
	100	#ifdef CONFIG_TRACE_IRQFLAGS
	101	brnz,pn %l4, rtrap_no_irq_enable
	102	nop
	103	call trace_hardirqs_on
	104	nop
28a1f533 DM	105	/* Do not actually set the %pil here. We will do that
	106	* below after we clear PSTATE_IE in the %pstate register.
	107	* If we re-enable interrupts here, we can recurse down
	108	* the hardirq stack potentially endlessly, causing a
	109	* stack overflow.
	110	*
	111	* It is tempting to put this test and trace_hardirqs_on
	112	* call at the 'rt_continue' label, but that will not work
	113	* as that path hits unconditionally and we do not want to
	114	* execute this in NMI return paths, for example.
	115	*/
10e26723	116	#endif
5565736e	117	rtrap_no_irq_enable:
10e26723	118	andcc %l1, TSTATE_PRIV, %l3
1da177e4	119	bne,pn %icc, to_kernel
10e26723	120	nop
1da177e4 LT	121
	122	/* We must hold IRQs off and atomically test schedule+signal
	123	* state, then hold them off all the way back to userspace.
10e26723 DM	124	* If we are returning to kernel, none of this matters. Note
	125	* that we are disabling interrupts via PSTATE_IE, not using
	126	* %pil.
1da177e4 LT	127	*
	128	* If we do not do this, there is a window where we would do
	129	* the tests, later the signal/resched event arrives but we do
	130	* not process it since we are still in kernel mode. It would
	131	* take until the next local IRQ before the signal/resched
	132	* event would be handled.
	133	*
c7d5a005 DM	134	* This also means that if we have to deal with user
	135	* windows, we have to redo all of these sched+signal checks
	136	* with IRQs disabled.
1da177e4 LT	137	*/
	138	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	139	wrpr 0, %pil
	140	__handle_preemption_continue:
	141	ldx [%g6 + TI_FLAGS], %l0
	142	sethi %hi(_TIF_USER_WORK_MASK), %o0
	143	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	144	andcc %l0, %o0, %g0
	145	sethi %hi(TSTATE_PEF), %o0
	146	be,pt %xcc, user_nowork
	147	andcc %l1, %o0, %g0
	148	andcc %l0, _TIF_NEED_RESCHED, %g0
	149	bne,pn %xcc, __handle_preemption
e35a8925	150	andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4	151	bne,pn %xcc, __handle_signal
1da177e4 LT	152	ldub [%g6 + TI_WSAVED], %o2
	153	brnz,pn %o2, __handle_user_windows
	154	nop
1da177e4	155	sethi %hi(TSTATE_PEF), %o0
c7d5a005	156	andcc %l1, %o0, %g0
1da177e4 LT	157
	158	/* This fpdepth clear is necessary for non-syscall rtraps only */
	159	user_nowork:
	160	bne,pn %xcc, __handle_userfpu
	161	stb %g0, [%g6 + TI_FPDEPTH]
	162	__handle_userfpu_continue:
	163
	164	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	165	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	166
	167	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	168	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	169	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	170	brz,pt %l3, 1f
314981ac DM	171	mov %g6, %l2
314981ac DM	172
56fb4df6	173	/* Must do this before thread reg is clobbered below. */
ffe483d5	174	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	175	1:
74bf4312 DM	176	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	177	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	178
	179	/* Normal globals are restored, go to trap globals. */
	180	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	181	nop
af02bec6 DM	182	.section .sun4v_2insn_patch, "ax"
936f482a	183	.word 661b
af02bec6	184	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	185	SET_GL(1)
	186	.previous
	187
314981ac DM	188	mov %l2, %g6
314981ac DM	189
1da177e4 LT	190	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	191	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	192
	193	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	194	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	195	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	196	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	197	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	198	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	199	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	200	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	201
	202	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	203	wr %o3, %g0, %y
1da177e4 LT	204	wrpr %l4, 0x0, %pil
1da177e4 LT	205	wrpr %g0, 0x1, %tl
28e61036	206	andn %l1, TSTATE_SYSCALL, %l1
1da177e4 LT	207	wrpr %l1, %g0, %tstate
	208	wrpr %l2, %g0, %tpc
	209	wrpr %o2, %g0, %tnpc
	210
	211	brnz,pn %l3, kern_rtt
	212	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	213
	214	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	215	.section .sun4v_1insn_patch, "ax"
	216	.word 661b
	217	ldxa [%l7 + %l7] ASI_MMU, %l0
	218	.previous
	219
0835ae0f DM	220	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	221	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	222	or %l0, %l1, %l0
8b11bd12 DM	223
	224	661: stxa %l0, [%l7] ASI_DMMU
	225	.section .sun4v_1insn_patch, "ax"
	226	.word 661b
	227	stxa %l0, [%l7] ASI_MMU
	228	.previous
	229
4da808c3 DM	230	sethi %hi(KERNBASE), %l7
4da808c3 DM	231	flush %l7
1da177e4 LT	232	rdpr %wstate, %l1
	233	rdpr %otherwin, %l2
	234	srl %l1, 3, %l1
	235
	236	wrpr %l2, %g0, %canrestore
	237	wrpr %l1, %g0, %wstate
314ef685 DM	238	brnz,pt %l2, user_rtt_restore
	239	wrpr %g0, %g0, %otherwin
	240
	241	ldx [%g6 + TI_FLAGS], %g3
	242	wr %g0, ASI_AIUP, %asi
	243	rdpr %cwp, %g1
	244	andcc %g3, _TIF_32BIT, %g0
	245	sub %g1, 1, %g1
	246	bne,pt %xcc, user_rtt_fill_32bit
	247	wrpr %g1, %cwp
	248	ba,a,pt %xcc, user_rtt_fill_64bit
	249
	250	user_rtt_fill_fixup:
	251	rdpr %cwp, %g1
	252	add %g1, 1, %g1
	253	wrpr %g1, 0x0, %cwp
	254
	255	rdpr %wstate, %g2
	256	sll %g2, 3, %g2
	257	wrpr %g2, 0x0, %wstate
	258
	259	/* We know %canrestore and %otherwin are both zero. */
	260
	261	sethi %hi(sparc64_kern_pri_context), %g2
	262	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
	263	mov PRIMARY_CONTEXT, %g1
8b11bd12 DM	264
	265	661: stxa %g2, [%g1] ASI_DMMU
	266	.section .sun4v_1insn_patch, "ax"
	267	.word 661b
	268	stxa %g2, [%g1] ASI_MMU
	269	.previous
	270
314ef685 DM	271	sethi %hi(KERNBASE), %g1
	272	flush %g1
	273
	274	or %g4, FAULT_CODE_WINFIXUP, %g4
	275	stb %g4, [%g6 + TI_FAULT_CODE]
	276	stx %g5, [%g6 + TI_FAULT_ADDR]
	277
	278	mov %g6, %l1
	279	wrpr %g0, 0x0, %tl
936f482a DM	280
936f482a DM	281	661: nop
df7d6aec	282	.section .sun4v_1insn_patch, "ax"
936f482a DM	283	.word 661b
	284	SET_GL(0)
	285	.previous
	286
fc504928 DM	287	wrpr %g0, RTRAP_PSTATE, %pstate
fc504928 DM	288
314ef685 DM	289	mov %l1, %g6
	290	ldx [%g6 + TI_TASK], %g4
	291	LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
	292	call do_sparc64_fault
	293	add %sp, PTREGS_OFF, %o0
	294	ba,pt %xcc, rtrap
	295	nop
	296
	297	user_rtt_pre_restore:
	298	add %g1, 1, %g1
	299	wrpr %g1, 0x0, %cwp
	300
	301	user_rtt_restore:
1da177e4 LT	302	restore
	303	rdpr %canrestore, %g1
	304	wrpr %g1, 0x0, %cleanwin
	305	retry
	306	nop
	307
314ef685 DM	308	kern_rtt: rdpr %canrestore, %g1
	309	brz,pn %g1, kern_rtt_fill
	310	nop
	311	kern_rtt_restore:
ada44a04	312	stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685	313	restore
1da177e4	314	retry
314ef685	315
1da177e4 LT	316	to_kernel:
	317	#ifdef CONFIG_PREEMPT
	318	ldsw [%g6 + TI_PRE_COUNT], %l5
	319	brnz %l5, kern_fpucheck
	320	ldx [%g6 + TI_FLAGS], %l5
	321	andcc %l5, _TIF_NEED_RESCHED, %g0
	322	be,pt %xcc, kern_fpucheck
10e26723 DM	323	nop
10e26723 DM	324	cmp %l4, 0
1da177e4 LT	325	bne,pn %xcc, kern_fpucheck
	326	sethi %hi(PREEMPT_ACTIVE), %l6
	327	stw %l6, [%g6 + TI_PRE_COUNT]
	328	call schedule
	329	nop
	330	ba,pt %xcc, rtrap
	331	stw %g0, [%g6 + TI_PRE_COUNT]
	332	#endif
	333	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	334	brz,pt %l5, rt_continue
	335	srl %l5, 1, %o0
	336	add %g6, TI_FPSAVED, %l6
	337	ldub [%l6 + %o0], %l2
	338	sub %l5, 2, %l5
	339
	340	add %g6, TI_GSR, %o1
	341	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	342	be,pt %icc, 2f
	343	and %l2, FPRS_DL, %l6
	344	andcc %l2, FPRS_FEF, %g0
	345	be,pn %icc, 5f
	346	sll %o0, 3, %o5
	347	rd %fprs, %g1
	348
	349	wr %g1, FPRS_FEF, %fprs
	350	ldx [%o1 + %o5], %g1
	351	add %g6, TI_XFSR, %o1
1da177e4 LT	352	sll %o0, 8, %o2
	353	add %g6, TI_FPREGS, %o3
	354	brz,pn %l6, 1f
	355	add %g6, TI_FPREGS+0x40, %o4
	356
ba639933	357	membar #Sync
1da177e4 LT	358	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	359	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	360	membar #Sync
1da177e4 LT	361	1: andcc %l2, FPRS_DU, %g0
	362	be,pn %icc, 1f
	363	wr %g1, 0, %gsr
	364	add %o2, 0x80, %o2
ba639933	365	membar #Sync
1da177e4 LT	366	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	367	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	368	1: membar #Sync
	369	ldx [%o1 + %o5], %fsr
	370	2: stb %l5, [%g6 + TI_FPDEPTH]
	371	ba,pt %xcc, rt_continue
	372	nop
	373	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	374	sll %o0, 8, %o2
	375
	376	add %g6, TI_FPREGS+0x80, %o3
	377	add %g6, TI_FPREGS+0xc0, %o4
ba639933	378	membar #Sync
1da177e4 LT	379	ldda [%o3 + %o2] ASI_BLK_P, %f32
	380	ldda [%o4 + %o2] ASI_BLK_P, %f48
	381	membar #Sync
	382	wr %g0, FPRS_DU, %fprs
	383	ba,pt %xcc, rt_continue
	384	stb %l5, [%g6 + TI_FPDEPTH]