[net-next-2.6.git] / arch / sparc / kernel / pcr.c

/* pcr.c: Generic sparc64 performance counter infrastructure.
 *
 * Copyright (C) 2009 David S. Miller (davem@davemloft.net)
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>

#include <linux/irq_work.h>
#include <linux/ftrace.h>

#include <asm/pil.h>
#include <asm/pcr.h>
#include <asm/nmi.h>

/* This code is shared between various users of the performance
 * counters.  Users will be oprofile, pseudo-NMI watchdog, and the
 * perf_event support layer.
 */

#define PCR_SUN4U_ENABLE	(PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
#define PCR_N2_ENABLE		(PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
				 PCR_N2_TOE_OV1 | \
				 (2 << PCR_N2_SL1_SHIFT) | \
				 (0xff << PCR_N2_MASK1_SHIFT))

u64 pcr_enable;
unsigned int picl_shift;

/* Performance counter interrupts run unmasked at PIL level 15.
 * Therefore we can't do things like wakeups and other work
 * that expects IRQ disabling to be adhered to in locking etc.
 *
 * Therefore in such situations we defer the work by signalling
 * a lower level cpu IRQ.
 */
void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
{
	struct pt_regs *old_regs;

	clear_softint(1 << PIL_DEFERRED_PCR_WORK);

	old_regs = set_irq_regs(regs);
	irq_enter();
#ifdef CONFIG_IRQ_WORK
	irq_work_run();
#endif
	irq_exit();
	set_irq_regs(old_regs);
}

void arch_irq_work_raise(void)
{
	set_softint(1 << PIL_DEFERRED_PCR_WORK);
}

const struct pcr_ops *pcr_ops;
EXPORT_SYMBOL_GPL(pcr_ops);

static u64 direct_pcr_read(void)
{
	u64 val;

	read_pcr(val);
	return val;
}

static void direct_pcr_write(u64 val)
{
	write_pcr(val);
}

static const struct pcr_ops direct_pcr_ops = {
	.read	= direct_pcr_read,
	.write	= direct_pcr_write,
};

static void n2_pcr_write(u64 val)
{
	unsigned long ret;

	ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
	if (val != HV_EOK)
		write_pcr(val);
}

static const struct pcr_ops n2_pcr_ops = {
	.read	= direct_pcr_read,
	.write	= n2_pcr_write,
};

static unsigned long perf_hsvc_group;
static unsigned long perf_hsvc_major;
static unsigned long perf_hsvc_minor;

static int __init register_perf_hsvc(void)
{
	if (tlb_type == hypervisor) {
		switch (sun4v_chip_type) {
		case SUN4V_CHIP_NIAGARA1:
			perf_hsvc_group = HV_GRP_NIAG_PERF;
			break;

		case SUN4V_CHIP_NIAGARA2:
			perf_hsvc_group = HV_GRP_N2_CPU;
			break;

		default:
			return -ENODEV;
		}


		perf_hsvc_major = 1;
		perf_hsvc_minor = 0;
		if (sun4v_hvapi_register(perf_hsvc_group,
					 perf_hsvc_major,
					 &perf_hsvc_minor)) {
			printk("perfmon: Could not register hvapi.\n");
			return -ENODEV;
		}
	}
	return 0;
}

static void __init unregister_perf_hsvc(void)
{
	if (tlb_type != hypervisor)
		return;
	sun4v_hvapi_unregister(perf_hsvc_group);
}

int __init pcr_arch_init(void)
{
	int err = register_perf_hsvc();

	if (err)
		return err;

	switch (tlb_type) {
	case hypervisor:
		pcr_ops = &n2_pcr_ops;
		pcr_enable = PCR_N2_ENABLE;
		picl_shift = 2;
		break;

	case cheetah:
	case cheetah_plus:
		pcr_ops = &direct_pcr_ops;
		pcr_enable = PCR_SUN4U_ENABLE;
		break;

	case spitfire:
		/* UltraSPARC-I/II and derivatives lack a profile
		 * counter overflow interrupt so we can't make use of
		 * their hardware currently.
		 */
		/* fallthrough */
	default:
		err = -ENODEV;
		goto out_unregister;
	}

	return nmi_init();

out_unregister:
	unregister_perf_hsvc();
	return err;
}

arch_initcall(pcr_arch_init);
Commit	Line	Data
3eb8057b DM	1	/* pcr.c: Generic sparc64 performance counter infrastructure.
	2	*
	3	* Copyright (C) 2009 David S. Miller (davem@davemloft.net)
	4	*/
	5	#include <linux/kernel.h>
	6	#include <linux/module.h>
	7	#include <linux/init.h>
	8	#include <linux/irq.h>
	9
e360adbe	10	#include <linux/irq_work.h>
9960e9e8	11	#include <linux/ftrace.h>
5686f9c3	12
3eb8057b DM	13	#include <asm/pil.h>
3eb8057b DM	14	#include <asm/pcr.h>
e5553a6d	15	#include <asm/nmi.h>
3eb8057b DM	16
	17	/* This code is shared between various users of the performance
	18	* counters. Users will be oprofile, pseudo-NMI watchdog, and the
cdd6c482	19	* perf_event support layer.
3eb8057b DM	20	*/
3eb8057b DM	21
e5553a6d DM	22	#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV \| PCR_STRACE \| PCR_UTRACE)
	23	#define PCR_N2_ENABLE (PCR_PIC_PRIV \| PCR_STRACE \| PCR_UTRACE \| \
	24	PCR_N2_TOE_OV1 \| \
	25	(2 << PCR_N2_SL1_SHIFT) \| \
	26	(0xff << PCR_N2_MASK1_SHIFT))
	27
	28	u64 pcr_enable;
	29	unsigned int picl_shift;
	30
3eb8057b DM	31	/* Performance counter interrupts run unmasked at PIL level 15.
	32	* Therefore we can't do things like wakeups and other work
	33	* that expects IRQ disabling to be adhered to in locking etc.
	34	*
	35	* Therefore in such situations we defer the work by signalling
	36	* a lower level cpu IRQ.
	37	*/
9960e9e8	38	void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
3eb8057b	39	{
5686f9c3 DM	40	struct pt_regs *old_regs;
5686f9c3 DM	41
3eb8057b	42	clear_softint(1 << PIL_DEFERRED_PCR_WORK);
5686f9c3 DM	43
	44	old_regs = set_irq_regs(regs);
	45	irq_enter();
e360adbe PZ	46	#ifdef CONFIG_IRQ_WORK
e360adbe PZ	47	irq_work_run();
5686f9c3 DM	48	#endif
	49	irq_exit();
	50	set_irq_regs(old_regs);
3eb8057b DM	51	}
3eb8057b DM	52
e360adbe	53	void arch_irq_work_raise(void)
3eb8057b DM	54	{
	55	set_softint(1 << PIL_DEFERRED_PCR_WORK);
	56	}
	57
	58	const struct pcr_ops *pcr_ops;
	59	EXPORT_SYMBOL_GPL(pcr_ops);
	60
	61	static u64 direct_pcr_read(void)
	62	{
	63	u64 val;
	64
	65	read_pcr(val);
	66	return val;
	67	}
	68
	69	static void direct_pcr_write(u64 val)
	70	{
	71	write_pcr(val);
	72	}
	73
	74	static const struct pcr_ops direct_pcr_ops = {
	75	.read = direct_pcr_read,
	76	.write = direct_pcr_write,
	77	};
	78
	79	static void n2_pcr_write(u64 val)
	80	{
	81	unsigned long ret;
	82
	83	ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
	84	if (val != HV_EOK)
	85	write_pcr(val);
	86	}
	87
	88	static const struct pcr_ops n2_pcr_ops = {
	89	.read = direct_pcr_read,
	90	.write = n2_pcr_write,
	91	};
	92
	93	static unsigned long perf_hsvc_group;
	94	static unsigned long perf_hsvc_major;
	95	static unsigned long perf_hsvc_minor;
	96
	97	static int __init register_perf_hsvc(void)
	98	{
	99	if (tlb_type == hypervisor) {
	100	switch (sun4v_chip_type) {
	101	case SUN4V_CHIP_NIAGARA1:
	102	perf_hsvc_group = HV_GRP_NIAG_PERF;
	103	break;
	104
	105	case SUN4V_CHIP_NIAGARA2:
	106	perf_hsvc_group = HV_GRP_N2_CPU;
	107	break;
	108
	109	default:
	110	return -ENODEV;
	111	}
	112
	113
	114	perf_hsvc_major = 1;
	115	perf_hsvc_minor = 0;
	116	if (sun4v_hvapi_register(perf_hsvc_group,
	117	perf_hsvc_major,
118	&perf_hsvc_minor)) {
119	printk("perfmon: Could not register hvapi.\n");
120	return -ENODEV;
121	}
122	}
123	return 0;
124	}
125
126	static void __init unregister_perf_hsvc(void)
127	{
128	if (tlb_type != hypervisor)
129	return;
130	sun4v_hvapi_unregister(perf_hsvc_group);
131	}
132
133	int __init pcr_arch_init(void)
134	{
135	int err = register_perf_hsvc();
136
137	if (err)
138	return err;
139
140	switch (tlb_type) {
141	case hypervisor:
142	pcr_ops = &n2_pcr_ops;
e5553a6d DM	143	pcr_enable = PCR_N2_ENABLE;
e5553a6d DM	144	picl_shift = 2;
3eb8057b DM	145	break;
3eb8057b DM	146
3eb8057b DM	147	case cheetah:
	148	case cheetah_plus:
	149	pcr_ops = &direct_pcr_ops;
e5553a6d	150	pcr_enable = PCR_SUN4U_ENABLE;
3eb8057b DM	151	break;
3eb8057b DM	152
1c2f61d4 DM	153	case spitfire:
	154	/* UltraSPARC-I/II and derivatives lack a profile
	155	* counter overflow interrupt so we can't make use of
	156	* their hardware currently.
	157	*/
	158	/* fallthrough */
3eb8057b DM	159	default:
	160	err = -ENODEV;
	161	goto out_unregister;
	162	}
	163
e5553a6d	164	return nmi_init();
3eb8057b DM	165
	166	out_unregister:
	167	unregister_perf_hsvc();
	168	return err;
	169	}
	170
	171	arch_initcall(pcr_arch_init);