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sh: Wire up INTC subgroup splitting for SH7786 SCIF1.
[net-next-2.6.git] / arch / sh / kernel / cpu / sh4a / setup-sh7786.c
CommitLineData
55ba99eb
KM		 1/*
2 * SH7786 Setup
3 *
050d4cc7 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
55ba99eb 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
c3d480de 6 * Paul Mundt <paul.mundt@renesas.com>
55ba99eb
KM		 7 *
8 * Based on SH7785 Setup
9 *
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/serial_sci.h>
20#include <linux/io.h>
21#include <linux/mm.h>
4c3f450b 22#include <linux/dma-mapping.h>
c3d480de 23#include <linux/sh_timer.h>
ed0ad6d3 24#include <linux/sh_dma.h>
43b8774d 25#include <linux/sh_intc.h>
050d4cc7 26#include <cpu/dma-register.h>
55ba99eb
KM		 27#include <asm/mmzone.h>
28
a9571d7b
MD		 29static struct plat_sci_port scif0_platform_data = {
30 .mapbase = 0xffea0000,
31 .flags = UPF_BOOT_AUTOCONF,
32 .type = PORT_SCIF,
33 .irqs = { 40, 41, 43, 42 },
34};
35
36static struct platform_device scif0_device = {
55ba99eb 37 .name = "sh-sci",
a9571d7b
MD		 38 .id = 0,
39 .dev = {
40 .platform_data = &scif0_platform_data,
41 },
42};
43
44/*
45 * The rest of these all have multiplexed IRQs
46 */
47static struct plat_sci_port scif1_platform_data = {
48 .mapbase = 0xffeb0000,
49 .flags = UPF_BOOT_AUTOCONF,
50 .type = PORT_SCIF,
51 .irqs = { 44, 44, 44, 44 },
52};
53
54static struct platform_device scif1_device = {
55 .name = "sh-sci",
56 .id = 1,
57 .dev = {
58 .platform_data = &scif1_platform_data,
59 },
60};
61
62static struct plat_sci_port scif2_platform_data = {
63 .mapbase = 0xffec0000,
64 .flags = UPF_BOOT_AUTOCONF,
65 .type = PORT_SCIF,
66 .irqs = { 50, 50, 50, 50 },
67};
68
69static struct platform_device scif2_device = {
70 .name = "sh-sci",
71 .id = 2,
72 .dev = {
73 .platform_data = &scif2_platform_data,
74 },
75};
76
77static struct plat_sci_port scif3_platform_data = {
78 .mapbase = 0xffed0000,
79 .flags = UPF_BOOT_AUTOCONF,
80 .type = PORT_SCIF,
81 .irqs = { 51, 51, 51, 51 },
82};
83
84static struct platform_device scif3_device = {
85 .name = "sh-sci",
86 .id = 3,
87 .dev = {
88 .platform_data = &scif3_platform_data,
89 },
90};
91
92static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xffee0000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .type = PORT_SCIF,
96 .irqs = { 52, 52, 52, 52 },
97};
98
99static struct platform_device scif4_device = {
100 .name = "sh-sci",
101 .id = 4,
102 .dev = {
103 .platform_data = &scif4_platform_data,
104 },
105};
106
107static struct plat_sci_port scif5_platform_data = {
108 .mapbase = 0xffef0000,
109 .flags = UPF_BOOT_AUTOCONF,
110 .type = PORT_SCIF,
111 .irqs = { 53, 53, 53, 53 },
112};
113
114static struct platform_device scif5_device = {
115 .name = "sh-sci",
116 .id = 5,
55ba99eb 117 .dev = {
a9571d7b 118 .platform_data = &scif5_platform_data,
55ba99eb
KM		 119 },
120};
121
c3d480de 122static struct sh_timer_config tmu0_platform_data = {
c3d480de
PM		 123 .channel_offset = 0x04,
124 .timer_bit = 0,
c3d480de
PM		 125 .clockevent_rating = 200,
126};
127
128static struct resource tmu0_resources[] = {
129 [0] = {
c3d480de
PM		 130 .start = 0xffd80008,
131 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM,
133 },
134 [1] = {
135 .start = 16,
136 .flags = IORESOURCE_IRQ,
137 },
138};
139
140static struct platform_device tmu0_device = {
141 .name = "sh_tmu",
142 .id = 0,
143 .dev = {
144 .platform_data = &tmu0_platform_data,
145 },
146 .resource = tmu0_resources,
147 .num_resources = ARRAY_SIZE(tmu0_resources),
148};
149
150static struct sh_timer_config tmu1_platform_data = {
c3d480de
PM		 151 .channel_offset = 0x10,
152 .timer_bit = 1,
c3d480de
PM		 153 .clocksource_rating = 200,
154};
155
156static struct resource tmu1_resources[] = {
157 [0] = {
c3d480de
PM		 158 .start = 0xffd80014,
159 .end = 0xffd8001f,
160 .flags = IORESOURCE_MEM,
161 },
162 [1] = {
163 .start = 17,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device tmu1_device = {
169 .name = "sh_tmu",
170 .id = 1,
171 .dev = {
172 .platform_data = &tmu1_platform_data,
173 },
174 .resource = tmu1_resources,
175 .num_resources = ARRAY_SIZE(tmu1_resources),
176};
177
178static struct sh_timer_config tmu2_platform_data = {
c3d480de
PM		 179 .channel_offset = 0x1c,
180 .timer_bit = 2,
c3d480de
PM		 181};
182
183static struct resource tmu2_resources[] = {
184 [0] = {
c3d480de
PM		 185 .start = 0xffd80020,
186 .end = 0xffd8002f,
187 .flags = IORESOURCE_MEM,
188 },
189 [1] = {
190 .start = 18,
191 .flags = IORESOURCE_IRQ,
192 },
193};
194
195static struct platform_device tmu2_device = {
196 .name = "sh_tmu",
197 .id = 2,
198 .dev = {
199 .platform_data = &tmu2_platform_data,
200 },
201 .resource = tmu2_resources,
202 .num_resources = ARRAY_SIZE(tmu2_resources),
203};
204
205static struct sh_timer_config tmu3_platform_data = {
c3d480de
PM		 206 .channel_offset = 0x04,
207 .timer_bit = 0,
c3d480de
PM		 208};
209
210static struct resource tmu3_resources[] = {
211 [0] = {
c3d480de
PM		 212 .start = 0xffda0008,
213 .end = 0xffda0013,
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .start = 20,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
222static struct platform_device tmu3_device = {
223 .name = "sh_tmu",
224 .id = 3,
225 .dev = {
226 .platform_data = &tmu3_platform_data,
227 },
228 .resource = tmu3_resources,
229 .num_resources = ARRAY_SIZE(tmu3_resources),
230};
231
232static struct sh_timer_config tmu4_platform_data = {
c3d480de
PM		 233 .channel_offset = 0x10,
234 .timer_bit = 1,
c3d480de
PM		 235};
236
237static struct resource tmu4_resources[] = {
238 [0] = {
c3d480de
PM		 239 .start = 0xffda0014,
240 .end = 0xffda001f,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = 21,
245 .flags = IORESOURCE_IRQ,
246 },
247};
248
249static struct platform_device tmu4_device = {
250 .name = "sh_tmu",
251 .id = 4,
252 .dev = {
253 .platform_data = &tmu4_platform_data,
254 },
255 .resource = tmu4_resources,
256 .num_resources = ARRAY_SIZE(tmu4_resources),
257};
258
259static struct sh_timer_config tmu5_platform_data = {
c3d480de
PM		 260 .channel_offset = 0x1c,
261 .timer_bit = 2,
c3d480de
PM		 262};
263
264static struct resource tmu5_resources[] = {
265 [0] = {
c3d480de
PM		 266 .start = 0xffda0020,
267 .end = 0xffda002b,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = 22,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device tmu5_device = {
277 .name = "sh_tmu",
278 .id = 5,
279 .dev = {
280 .platform_data = &tmu5_platform_data,
281 },
282 .resource = tmu5_resources,
283 .num_resources = ARRAY_SIZE(tmu5_resources),
284};
285
286static struct sh_timer_config tmu6_platform_data = {
c3d480de
PM		 287 .channel_offset = 0x04,
288 .timer_bit = 0,
c3d480de
PM		 289};
290
291static struct resource tmu6_resources[] = {
292 [0] = {
c3d480de
PM		 293 .start = 0xffdc0008,
294 .end = 0xffdc0013,
295 .flags = IORESOURCE_MEM,
296 },
297 [1] = {
298 .start = 45,
299 .flags = IORESOURCE_IRQ,
300 },
301};
302
303static struct platform_device tmu6_device = {
304 .name = "sh_tmu",
305 .id = 6,
306 .dev = {
307 .platform_data = &tmu6_platform_data,
308 },
309 .resource = tmu6_resources,
310 .num_resources = ARRAY_SIZE(tmu6_resources),
311};
312
313static struct sh_timer_config tmu7_platform_data = {
c3d480de
PM		 314 .channel_offset = 0x10,
315 .timer_bit = 1,
c3d480de
PM		 316};
317
318static struct resource tmu7_resources[] = {
319 [0] = {
c3d480de
PM		 320 .start = 0xffdc0014,
321 .end = 0xffdc001f,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
325 .start = 45,
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330static struct platform_device tmu7_device = {
331 .name = "sh_tmu",
332 .id = 7,
333 .dev = {
334 .platform_data = &tmu7_platform_data,
335 },
336 .resource = tmu7_resources,
337 .num_resources = ARRAY_SIZE(tmu7_resources),
338};
339
340static struct sh_timer_config tmu8_platform_data = {
c3d480de
PM		 341 .channel_offset = 0x1c,
342 .timer_bit = 2,
c3d480de
PM		 343};
344
345static struct resource tmu8_resources[] = {
346 [0] = {
c3d480de
PM		 347 .start = 0xffdc0020,
348 .end = 0xffdc002b,
349 .flags = IORESOURCE_MEM,
350 },
351 [1] = {
352 .start = 45,
353 .flags = IORESOURCE_IRQ,
354 },
355};
356
357static struct platform_device tmu8_device = {
358 .name = "sh_tmu",
359 .id = 8,
360 .dev = {
361 .platform_data = &tmu8_platform_data,
362 },
363 .resource = tmu8_resources,
364 .num_resources = ARRAY_SIZE(tmu8_resources),
365};
366
367static struct sh_timer_config tmu9_platform_data = {
c3d480de
PM		 368 .channel_offset = 0x04,
369 .timer_bit = 0,
c3d480de
PM		 370};
371
372static struct resource tmu9_resources[] = {
373 [0] = {
c3d480de
PM		 374 .start = 0xffde0008,
375 .end = 0xffde0013,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = 46,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device tmu9_device = {
385 .name = "sh_tmu",
386 .id = 9,
387 .dev = {
388 .platform_data = &tmu9_platform_data,
389 },
390 .resource = tmu9_resources,
391 .num_resources = ARRAY_SIZE(tmu9_resources),
392};
393
394static struct sh_timer_config tmu10_platform_data = {
c3d480de
PM		 395 .channel_offset = 0x10,
396 .timer_bit = 1,
c3d480de
PM		 397};
398
399static struct resource tmu10_resources[] = {
400 [0] = {
c3d480de
PM		 401 .start = 0xffde0014,
402 .end = 0xffde001f,
403 .flags = IORESOURCE_MEM,
404 },
405 [1] = {
406 .start = 46,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device tmu10_device = {
412 .name = "sh_tmu",
413 .id = 10,
414 .dev = {
415 .platform_data = &tmu10_platform_data,
416 },
417 .resource = tmu10_resources,
418 .num_resources = ARRAY_SIZE(tmu10_resources),
419};
420
421static struct sh_timer_config tmu11_platform_data = {
c3d480de
PM		 422 .channel_offset = 0x1c,
423 .timer_bit = 2,
c3d480de
PM		 424};
425
426static struct resource tmu11_resources[] = {
427 [0] = {
c3d480de
PM		 428 .start = 0xffde0020,
429 .end = 0xffde002b,
430 .flags = IORESOURCE_MEM,
431 },
432 [1] = {
433 .start = 46,
434 .flags = IORESOURCE_IRQ,
435 },
436};
437
438static struct platform_device tmu11_device = {
439 .name = "sh_tmu",
440 .id = 11,
441 .dev = {
442 .platform_data = &tmu11_platform_data,
443 },
444 .resource = tmu11_resources,
445 .num_resources = ARRAY_SIZE(tmu11_resources),
446};
447
5bac942d 448static const struct sh_dmae_channel dmac0_channels[] = {
050d4cc7
PM		 449 {
450 .offset = 0,
451 .dmars = 0,
452 .dmars_bit = 0,
453 }, {
454 .offset = 0x10,
455 .dmars = 0,
456 .dmars_bit = 8,
457 }, {
458 .offset = 0x20,
459 .dmars = 4,
460 .dmars_bit = 0,
461 }, {
462 .offset = 0x30,
463 .dmars = 4,
464 .dmars_bit = 8,
465 }, {
466 .offset = 0x50,
467 .dmars = 8,
468 .dmars_bit = 0,
469 }, {
470 .offset = 0x60,
471 .dmars = 8,
472 .dmars_bit = 8,
473 }
474};
475
5bac942d 476static const unsigned int ts_shift[] = TS_SHIFT;
050d4cc7
PM		 477
478static struct sh_dmae_pdata dma0_platform_data = {
479 .channel = dmac0_channels,
480 .channel_num = ARRAY_SIZE(dmac0_channels),
481 .ts_low_shift = CHCR_TS_LOW_SHIFT,
482 .ts_low_mask = CHCR_TS_LOW_MASK,
483 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
484 .ts_high_mask = CHCR_TS_HIGH_MASK,
485 .ts_shift = ts_shift,
486 .ts_shift_num = ARRAY_SIZE(ts_shift),
487 .dmaor_init = DMAOR_INIT,
488};
489
490/* Resource order important! */
491static struct resource dmac0_resources[] = {
492 {
493 /* Channel registers and DMAOR */
494 .start = 0xfe008020,
495 .end = 0xfe00808f,
496 .flags = IORESOURCE_MEM,
497 }, {
498 /* DMARSx */
499 .start = 0xfe009000,
500 .end = 0xfe00900b,
501 .flags = IORESOURCE_MEM,
502 }, {
503 /* DMA error IRQ */
504 .start = evt2irq(0x5c0),
505 .end = evt2irq(0x5c0),
506 .flags = IORESOURCE_IRQ,
507 }, {
508 /* IRQ for channels 0-5 */
509 .start = evt2irq(0x500),
510 .end = evt2irq(0x5a0),
511 .flags = IORESOURCE_IRQ,
512 },
513};
514
515static struct platform_device dma0_device = {
516 .name = "sh-dma-engine",
517 .id = 0,
518 .resource = dmac0_resources,
519 .num_resources = ARRAY_SIZE(dmac0_resources),
520 .dev = {
521 .platform_data = &dma0_platform_data,
522 },
523};
524
4c3f450b
KM		 525static struct resource usb_ohci_resources[] = {
526 [0] = {
527 .start = 0xffe70400,
528 .end = 0xffe704ff,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = 77,
533 .end = 77,
534 .flags = IORESOURCE_IRQ,
535 },
536};
537
538static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
539static struct platform_device usb_ohci_device = {
540 .name = "sh_ohci",
541 .id = -1,
542 .dev = {
543 .dma_mask = &usb_ohci_dma_mask,
544 .coherent_dma_mask = DMA_BIT_MASK(32),
545 },
546 .num_resources = ARRAY_SIZE(usb_ohci_resources),
547 .resource = usb_ohci_resources,
548};
549
c3d480de 550static struct platform_device *sh7786_early_devices[] __initdata = {
a9571d7b
MD		 551 &scif0_device,
552 &scif1_device,
553 &scif2_device,
554 &scif3_device,
555 &scif4_device,
556 &scif5_device,
c3d480de
PM		 557 &tmu0_device,
558 &tmu1_device,
559 &tmu2_device,
560 &tmu3_device,
561 &tmu4_device,
562 &tmu5_device,
563 &tmu6_device,
564 &tmu7_device,
565 &tmu8_device,
566 &tmu9_device,
567 &tmu10_device,
568 &tmu11_device,
569};
570
55ba99eb 571static struct platform_device *sh7786_devices[] __initdata = {
050d4cc7 572 &dma0_device,
4c3f450b 573 &usb_ohci_device,
55ba99eb
KM		 574};
575
4c3f450b
KM		 576/*
577 * Please call this function if your platform board
578 * use external clock for USB
579 * */
580#define USBCTL0 0xffe70858
581#define CLOCK_MODE_MASK 0xffffff7f
582#define EXT_CLOCK_MODE 0x00000080
dc825b17 583
4c3f450b
KM		 584void __init sh7786_usb_use_exclock(void)
585{
586 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
587 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
588}
589
590#define USBINITREG1 0xffe70094
591#define USBINITREG2 0xffe7009c
592#define USBINITVAL1 0x00ff0040
593#define USBINITVAL2 0x00000001
594
595#define USBPCTL1 0xffe70804
596#define USBST 0xffe70808
597#define PHY_ENB 0x00000001
598#define PLL_ENB 0x00000002
599#define PHY_RST 0x00000004
600#define ACT_PLL_STATUS 0xc0000000
dc825b17 601
4c3f450b
KM		 602static void __init sh7786_usb_setup(void)
603{
604 int i = 1000000;
605
606 /*
607 * USB initial settings
608 *
609 * The following settings are necessary
610 * for using the USB modules.
611 *
612 * see "USB Inital Settings" for detail
613 */
614 __raw_writel(USBINITVAL1, USBINITREG1);
615 __raw_writel(USBINITVAL2, USBINITREG2);
616
617 /*
618 * Set the PHY and PLL enable bit
619 */
620 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
0ee50254
KM		 621 while (i--) {
622 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
623 /* Set the PHY RST bit */
624 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
625 printk(KERN_INFO "sh7786 usb setup done\n");
626 break;
627 }
4c3f450b 628 cpu_relax();
4c3f450b
KM		 629 }
630}
631
55ba99eb
KM		 632enum {
633 UNUSED = 0,
634
635 /* interrupt sources */
55ba99eb
KM		 636 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
637 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
638 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
639 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
640
641 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
642 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
643 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
644 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
645
646 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
647 WDT,
648 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
649 TMU1_0, TMU1_1, TMU1_2,
650 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
651 HUDI1, HUDI0,
652 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
653 HPB_0, HPB_1, HPB_2,
654 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
655 SCIF1,
656 TMU2, TMU3,
657 SCIF2, SCIF3, SCIF4, SCIF5,
658 Eth_0, Eth_1,
659 PCIeC0_0, PCIeC0_1, PCIeC0_2,
660 PCIeC1_0, PCIeC1_1, PCIeC1_2,
661 USB,
662 I2C0, I2C1,
663 DU,
664 SSI0, SSI1, SSI2, SSI3,
665 PCIeC2_0, PCIeC2_1, PCIeC2_2,
666 HAC0, HAC1,
667 FLCTL,
668 HSPI,
669 GPIO0, GPIO1,
670 Thermal,
2eb2a436
PM		 671 INTICI0, INTICI1, INTICI2, INTICI3,
672 INTICI4, INTICI5, INTICI6, INTICI7,
d91ddc25
PM		 673
674 /* Muxed sub-events */
675 TXI1, BRI1, RXI1, ERI1,
55ba99eb
KM		 676};
677
d91ddc25 678static struct intc_vect sh7786_vectors[] __initdata = {
55ba99eb
KM		 679 INTC_VECT(WDT, 0x3e0),
680 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
681 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
682 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
683 INTC_VECT(TMU1_2, 0x4c0),
684 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
685 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
686 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
687 INTC_VECT(DMAC0_6, 0x5c0),
688 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
689 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
690 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
691 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
692 INTC_VECT(HPB_2, 0x6e0),
693 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
694 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
695 INTC_VECT(SCIF1, 0x780),
696 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
697 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
698 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
699 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
700 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
701 INTC_VECT(PCIeC0_2, 0xb20),
702 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
703 INTC_VECT(PCIeC1_2, 0xb80),
704 INTC_VECT(USB, 0xba0),
705 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
706 INTC_VECT(DU, 0xd00),
707 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
708 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
709 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
710 INTC_VECT(PCIeC2_2, 0xde0),
711 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
712 INTC_VECT(FLCTL, 0xe40),
713 INTC_VECT(HSPI, 0xe80),
714 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
715 INTC_VECT(Thermal, 0xee0),
2eb2a436
PM		 716 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
717 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
718 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
719 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
55ba99eb
KM		 720};
721
55ba99eb
KM		 722#define CnINTMSK0 0xfe410030
723#define CnINTMSK1 0xfe410040
724#define CnINTMSKCLR0 0xfe410050
725#define CnINTMSKCLR1 0xfe410060
726#define CnINT2MSKR0 0xfe410a20
727#define CnINT2MSKR1 0xfe410a24
728#define CnINT2MSKR2 0xfe410a28
729#define CnINT2MSKR3 0xfe410a2c
730#define CnINT2MSKCR0 0xfe410a30
731#define CnINT2MSKCR1 0xfe410a34
732#define CnINT2MSKCR2 0xfe410a38
733#define CnINT2MSKCR3 0xfe410a3c
55ba99eb
KM		 734#define INTMSK2 0xfe410068
735#define INTMSKCLR2 0xfe41006c
736
dc825b17
PM		 737#define INTDISTCR0 0xfe4100b0
738#define INTDISTCR1 0xfe4100b4
dc825b17
PM		 739#define INT2DISTCR0 0xfe410900
740#define INT2DISTCR1 0xfe410904
741#define INT2DISTCR2 0xfe410908
742#define INT2DISTCR3 0xfe41090c
743
d91ddc25 744static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
55ba99eb 745 { CnINTMSK0, CnINTMSKCLR0, 32,
dc825b17
PM		 746 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
747 INTC_SMP_BALANCING(INTDISTCR0) },
55ba99eb
KM		 748 { INTMSK2, INTMSKCLR2, 32,
749 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
750 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
751 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
752 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
753 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
754 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
755 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
756 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
757 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
758 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
dc825b17
PM		 759 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
760 INTC_SMP_BALANCING(INT2DISTCR0) },
55ba99eb
KM		 761 { CnINT2MSKR1, CnINT2MSKCR1, 32,
762 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
763 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
764 HUDI1, HUDI0,
765 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
766 HPB_0, HPB_1, HPB_2,
767 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
768 SCIF1,
dc825b17 769 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
55ba99eb
KM		 770 { CnINT2MSKR2, CnINT2MSKCR2, 32,
771 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
772 Eth_0, Eth_1,
773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
774 PCIeC0_0, PCIeC0_1, PCIeC0_2,
775 PCIeC1_0, PCIeC1_1, PCIeC1_2,
dc825b17 776 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
55ba99eb
KM		 777 { CnINT2MSKR3, CnINT2MSKCR3, 32,
778 { 0, 0, 0, 0, 0, 0,
779 I2C0, I2C1,
780 DU, SSI0, SSI1, SSI2, SSI3,
781 PCIeC2_0, PCIeC2_1, PCIeC2_2,
782 HAC0, HAC1,
783 FLCTL, 0,
784 HSPI, GPIO0, GPIO1, Thermal,
dc825b17 785 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
55ba99eb
KM		 786};
787
d91ddc25 788static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
55ba99eb
KM		 789 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
790 IRQ4, IRQ5, IRQ6, IRQ7 } },
791 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
792 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
793 TMU0_2, TMU0_3 } },
794 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
795 TMU1_2, 0 } },
796 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
797 DMAC0_2, DMAC0_3 } },
798 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
799 DMAC0_6, HUDI1 } },
800 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
801 DMAC1_1, DMAC1_2 } },
802 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
803 HPB_1, HPB_2 } },
804 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
805 SCIF0_2, SCIF0_3 } },
806 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
807 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
808 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
809 Eth_0, Eth_1 } },
810 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
811 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
812 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
813 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
814 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
815 PCIeC1_0, PCIeC1_1 } },
816 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
817 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
818 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
819 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
820 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
821 PCIeC2_1, PCIeC2_2 } },
822 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
823 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
824 GPIO1, Thermal } },
825 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
826 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
2eb2a436
PM		 827 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
828 { INTICI7, INTICI6, INTICI5, INTICI4,
829 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
55ba99eb
KM		 830};
831
d91ddc25
PM		 832static struct intc_subgroup sh7786_subgroups[] __initdata = {
833 { 0xfe410c20, 32, SCIF1,
834 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
835 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
836};
55ba99eb 837
d91ddc25
PM		 838static struct intc_desc sh7786_intc_desc __initdata = {
839 .name = "sh7786",
840 .hw = {
841 .vectors = sh7786_vectors,
842 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
843 .mask_regs = sh7786_mask_registers,
844 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
845 .subgroups = sh7786_subgroups,
846 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
847 .prio_regs = sh7786_prio_registers,
848 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
849 },
850};
55ba99eb 851
d91ddc25 852/* Support for external interrupt pins in IRQ mode */
55ba99eb
KM		 853static struct intc_vect vectors_irq0123[] __initdata = {
854 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
855 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
856};
857
858static struct intc_vect vectors_irq4567[] __initdata = {
859 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
860 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
861};
862
d91ddc25 863static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
55ba99eb
KM		 864 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
865 IRQ4, IRQ5, IRQ6, IRQ7 } },
866};
867
d91ddc25 868static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
55ba99eb
KM		 869 { 0xfe410024, 0, 32, /* INTREQ */
870 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
871};
872
873static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
d91ddc25
PM		 874 vectors_irq0123, NULL, sh7786_mask_registers,
875 sh7786_prio_registers, sh7786_sense_registers,
876 sh7786_ack_registers);
55ba99eb
KM		 877
878static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
d91ddc25
PM		 879 vectors_irq4567, NULL, sh7786_mask_registers,
880 sh7786_prio_registers, sh7786_sense_registers,
881 sh7786_ack_registers);
55ba99eb
KM		 882
883/* External interrupt pins in IRL mode */
884
885static struct intc_vect vectors_irl0123[] __initdata = {
886 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
887 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
888 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
889 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
890 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
891 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
892 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
893 INTC_VECT(IRL0_HHHL, 0x3c0),
894};
895
896static struct intc_vect vectors_irl4567[] __initdata = {
897 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
898 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
899 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
900 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
901 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
902 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
903 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
904 INTC_VECT(IRL4_HHHL, 0xac0),
905};
906
907static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
d91ddc25 908 NULL, sh7786_mask_registers, NULL, NULL);
55ba99eb
KM		 909
910static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
d91ddc25 911 NULL, sh7786_mask_registers, NULL, NULL);
55ba99eb
KM		 912
913#define INTC_ICR0 0xfe410000
914#define INTC_INTMSK0 CnINTMSK0
915#define INTC_INTMSK1 CnINTMSK1
916#define INTC_INTMSK2 INTMSK2
917#define INTC_INTMSKCLR1 CnINTMSKCLR1
918#define INTC_INTMSKCLR2 INTMSKCLR2
dc825b17 919
55ba99eb
KM		 920void __init plat_irq_setup(void)
921{
922 /* disable IRQ3-0 + IRQ7-4 */
9d56dd3b 923 __raw_writel(0xff000000, INTC_INTMSK0);
55ba99eb
KM		 924
925 /* disable IRL3-0 + IRL7-4 */
9d56dd3b
PM		 926 __raw_writel(0xc0000000, INTC_INTMSK1);
927 __raw_writel(0xfffefffe, INTC_INTMSK2);
55ba99eb
KM		 928
929 /* select IRL mode for IRL3-0 + IRL7-4 */
9d56dd3b 930 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
55ba99eb 931
d91ddc25 932 register_intc_controller(&sh7786_intc_desc);
55ba99eb
KM		 933}
934
935void __init plat_irq_setup_pins(int mode)
936{
937 switch (mode) {
938 case IRQ_MODE_IRQ7654:
939 /* select IRQ mode for IRL7-4 */
9d56dd3b 940 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
55ba99eb
KM		 941 register_intc_controller(&intc_desc_irq4567);
942 break;
943 case IRQ_MODE_IRQ3210:
944 /* select IRQ mode for IRL3-0 */
9d56dd3b 945 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
55ba99eb
KM		 946 register_intc_controller(&intc_desc_irq0123);
947 break;
948 case IRQ_MODE_IRL7654:
949 /* enable IRL7-4 but don't provide any masking */
9d56dd3b
PM		 950 __raw_writel(0x40000000, INTC_INTMSKCLR1);
951 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
55ba99eb
KM		 952 break;
953 case IRQ_MODE_IRL3210:
954 /* enable IRL0-3 but don't provide any masking */
9d56dd3b
PM		 955 __raw_writel(0x80000000, INTC_INTMSKCLR1);
956 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
55ba99eb
KM		 957 break;
958 case IRQ_MODE_IRL7654_MASK:
959 /* enable IRL7-4 and mask using cpu intc controller */
9d56dd3b 960 __raw_writel(0x40000000, INTC_INTMSKCLR1);
55ba99eb
KM		 961 register_intc_controller(&intc_desc_irl4567);
962 break;
963 case IRQ_MODE_IRL3210_MASK:
964 /* enable IRL0-3 and mask using cpu intc controller */
9d56dd3b 965 __raw_writel(0x80000000, INTC_INTMSKCLR1);
55ba99eb
KM		 966 register_intc_controller(&intc_desc_irl0123);
967 break;
968 default:
969 BUG();
970 }
971}
972
973void __init plat_mem_setup(void)
974{
975}
d91ddc25
PM		 976
977static int __init sh7786_devices_setup(void)
978{
979 int ret, irq;
980
981 sh7786_usb_setup();
982
983 /*
984 * De-mux SCIF1 IRQs if possible
985 */
986 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
987 if (irq > 0) {
988 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
989 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
990 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
991 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
992 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
993 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
994 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
995 }
996
997 ret = platform_add_devices(sh7786_early_devices,
998 ARRAY_SIZE(sh7786_early_devices));
999 if (unlikely(ret != 0))
1000 return ret;
1001
1002 return platform_add_devices(sh7786_devices,
1003 ARRAY_SIZE(sh7786_devices));
1004}
1005arch_initcall(sh7786_devices_setup);
1006
1007void __init plat_early_device_setup(void)
1008{
1009 early_platform_add_devices(sh7786_early_devices,
1010 ARRAY_SIZE(sh7786_early_devices));
1011}
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