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1929cb34 | 1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |
3 | * | |
46e9371c | 4 | * SH7722 clock framework support |
1929cb34 | 5 | * |
46e9371c | 6 | * Copyright (C) 2009 Magnus Damm |
1929cb34 | 7 | * |
46e9371c MD |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1929cb34 | 20 | */ |
21 | #include <linux/init.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
e4e06697 | 24 | #include <asm/clkdev.h> |
1929cb34 | 25 | #include <asm/clock.h> |
a61c1a63 MD |
26 | #include <asm/hwblk.h> |
27 | #include <cpu/sh7722.h> | |
1929cb34 | 28 | |
46e9371c MD |
29 | /* SH7722 registers */ |
30 | #define FRQCR 0xa4150000 | |
31 | #define VCLKCR 0xa4150004 | |
32 | #define SCLKACR 0xa4150008 | |
33 | #define SCLKBCR 0xa415000c | |
34 | #define IRDACLKCR 0xa4150018 | |
35 | #define PLLCR 0xa4150024 | |
46e9371c MD |
36 | #define DLLFRQ 0xa4150050 |
37 | ||
38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | |
39 | static struct clk r_clk = { | |
40 | .name = "rclk", | |
41 | .id = -1, | |
42 | .rate = 32768, | |
1929cb34 | 43 | }; |
44 | ||
1929cb34 | 45 | /* |
46e9371c MD |
46 | * Default rate for the root input clock, reset this with clk_set_rate() |
47 | * from the platform code. | |
1929cb34 | 48 | */ |
46e9371c MD |
49 | struct clk extal_clk = { |
50 | .name = "extal", | |
51 | .id = -1, | |
52 | .rate = 33333333, | |
1929cb34 | 53 | }; |
54 | ||
46e9371c MD |
55 | /* The dll block multiplies the 32khz r_clk, may be used instead of extal */ |
56 | static unsigned long dll_recalc(struct clk *clk) | |
1929cb34 | 57 | { |
46e9371c | 58 | unsigned long mult; |
1929cb34 | 59 | |
46e9371c MD |
60 | if (__raw_readl(PLLCR) & 0x1000) |
61 | mult = __raw_readl(DLLFRQ); | |
1929cb34 | 62 | else |
46e9371c | 63 | mult = 0; |
1929cb34 | 64 | |
46e9371c | 65 | return clk->parent->rate * mult; |
1929cb34 | 66 | } |
67 | ||
46e9371c MD |
68 | static struct clk_ops dll_clk_ops = { |
69 | .recalc = dll_recalc, | |
1312994c MD |
70 | }; |
71 | ||
46e9371c MD |
72 | static struct clk dll_clk = { |
73 | .name = "dll_clk", | |
74 | .id = -1, | |
75 | .ops = &dll_clk_ops, | |
76 | .parent = &r_clk, | |
77 | .flags = CLK_ENABLE_ON_INIT, | |
78 | }; | |
1929cb34 | 79 | |
46e9371c | 80 | static unsigned long pll_recalc(struct clk *clk) |
1929cb34 | 81 | { |
46e9371c MD |
82 | unsigned long mult = 1; |
83 | unsigned long div = 1; | |
1929cb34 | 84 | |
46e9371c MD |
85 | if (__raw_readl(PLLCR) & 0x4000) |
86 | mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); | |
87 | else | |
88 | div = 2; | |
1929cb34 | 89 | |
46e9371c | 90 | return (clk->parent->rate * mult) / div; |
1929cb34 | 91 | } |
92 | ||
46e9371c MD |
93 | static struct clk_ops pll_clk_ops = { |
94 | .recalc = pll_recalc, | |
1929cb34 | 95 | }; |
96 | ||
46e9371c MD |
97 | static struct clk pll_clk = { |
98 | .name = "pll_clk", | |
99 | .id = -1, | |
100 | .ops = &pll_clk_ops, | |
101 | .flags = CLK_ENABLE_ON_INIT, | |
1929cb34 | 102 | }; |
103 | ||
46e9371c MD |
104 | struct clk *main_clks[] = { |
105 | &r_clk, | |
106 | &extal_clk, | |
107 | &dll_clk, | |
108 | &pll_clk, | |
1929cb34 | 109 | }; |
110 | ||
46e9371c MD |
111 | static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; |
112 | static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; | |
1929cb34 | 113 | |
0a5f337e | 114 | static struct clk_div_mult_table div4_div_mult_table = { |
46e9371c MD |
115 | .divisors = divisors, |
116 | .nr_divisors = ARRAY_SIZE(divisors), | |
117 | .multipliers = multipliers, | |
118 | .nr_multipliers = ARRAY_SIZE(multipliers), | |
7c7e02a2 | 119 | }; |
1312994c | 120 | |
0a5f337e MD |
121 | static struct clk_div4_table div4_table = { |
122 | .div_mult_table = &div4_div_mult_table, | |
123 | }; | |
124 | ||
46e9371c MD |
125 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ |
126 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | |
1929cb34 | 127 | |
31c3af50 GL |
128 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; |
129 | ||
46e9371c MD |
130 | struct clk div4_clks[DIV4_NR] = { |
131 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), | |
132 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), | |
133 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), | |
134 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), | |
135 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), | |
136 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), | |
31c3af50 GL |
137 | }; |
138 | ||
139 | enum { DIV4_IRDA, DIV4_ENABLE_NR }; | |
140 | ||
141 | struct clk div4_enable_clks[DIV4_ENABLE_NR] = { | |
142 | [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), | |
143 | }; | |
144 | ||
145 | enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; | |
146 | ||
147 | struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { | |
46e9371c MD |
148 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), |
149 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), | |
1929cb34 | 150 | }; |
151 | ||
098ec49b MD |
152 | enum { DIV6_V, DIV6_NR }; |
153 | ||
154 | struct clk div6_clks[DIV6_NR] = { | |
9e1985e1 | 155 | [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), |
1929cb34 | 156 | }; |
157 | ||
f3d51e13 | 158 | static struct clk mstp_clks[HWBLK_NR] = { |
08134c3c MD |
159 | SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT), |
160 | SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), | |
161 | SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0), | |
162 | SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), | |
163 | SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), | |
164 | SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), | |
165 | SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), | |
166 | SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), | |
167 | SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), | |
168 | ||
169 | SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), | |
170 | SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), | |
171 | ||
172 | SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0), | |
173 | SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), | |
174 | SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0), | |
175 | SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), | |
176 | SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), | |
177 | SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), | |
178 | SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), | |
179 | SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), | |
180 | SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), | |
181 | SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0), | |
182 | SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), | |
183 | SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0), | |
1929cb34 | 184 | }; |
185 | ||
fd30401b MD |
186 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
187 | ||
e4e06697 | 188 | static struct clk_lookup lookups[] = { |
098ec49b MD |
189 | /* DIV6 clocks */ |
190 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | |
191 | ||
fd30401b MD |
192 | /* MSTP clocks */ |
193 | CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]), | |
194 | CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]), | |
e4e06697 MD |
195 | { |
196 | /* TMU0 */ | |
197 | .dev_id = "sh_tmu.0", | |
198 | .con_id = "tmu_fck", | |
199 | .clk = &mstp_clks[HWBLK_TMU], | |
200 | }, { | |
201 | /* TMU1 */ | |
202 | .dev_id = "sh_tmu.1", | |
203 | .con_id = "tmu_fck", | |
204 | .clk = &mstp_clks[HWBLK_TMU], | |
205 | }, { | |
206 | /* TMU2 */ | |
207 | .dev_id = "sh_tmu.2", | |
208 | .con_id = "tmu_fck", | |
209 | .clk = &mstp_clks[HWBLK_TMU], | |
fd30401b MD |
210 | }, |
211 | CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), | |
212 | CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), | |
213 | CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), | |
214 | { | |
e4e06697 MD |
215 | /* SCIF0 */ |
216 | .dev_id = "sh-sci.0", | |
217 | .con_id = "sci_fck", | |
218 | .clk = &mstp_clks[HWBLK_SCIF0], | |
219 | }, { | |
220 | /* SCIF1 */ | |
221 | .dev_id = "sh-sci.1", | |
222 | .con_id = "sci_fck", | |
223 | .clk = &mstp_clks[HWBLK_SCIF1], | |
224 | }, { | |
225 | /* SCIF2 */ | |
226 | .dev_id = "sh-sci.2", | |
227 | .con_id = "sci_fck", | |
228 | .clk = &mstp_clks[HWBLK_SCIF2], | |
229 | }, | |
fd30401b MD |
230 | CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]), |
231 | CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), | |
232 | CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]), | |
233 | CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), | |
234 | CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]), | |
235 | CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), | |
236 | CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), | |
237 | CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), | |
238 | CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), | |
239 | CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), | |
240 | CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), | |
241 | CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]), | |
242 | CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), | |
243 | CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), | |
e4e06697 MD |
244 | }; |
245 | ||
dfbbbe92 | 246 | int __init arch_clk_init(void) |
1929cb34 | 247 | { |
46e9371c | 248 | int k, ret = 0; |
1929cb34 | 249 | |
46e9371c MD |
250 | /* autodetect extal or dll configuration */ |
251 | if (__raw_readl(PLLCR) & 0x1000) | |
252 | pll_clk.parent = &dll_clk; | |
253 | else | |
254 | pll_clk.parent = &extal_clk; | |
253b0887 | 255 | |
46e9371c MD |
256 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) |
257 | ret = clk_register(main_clks[k]); | |
7c7e02a2 | 258 | |
e4e06697 MD |
259 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
260 | ||
46e9371c MD |
261 | if (!ret) |
262 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | |
7c7e02a2 | 263 | |
31c3af50 GL |
264 | if (!ret) |
265 | ret = sh_clk_div4_enable_register(div4_enable_clks, | |
266 | DIV4_ENABLE_NR, &div4_table); | |
267 | ||
268 | if (!ret) | |
269 | ret = sh_clk_div4_reparent_register(div4_reparent_clks, | |
270 | DIV4_REPARENT_NR, &div4_table); | |
271 | ||
46e9371c | 272 | if (!ret) |
098ec49b | 273 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); |
aea167cb | 274 | |
46e9371c | 275 | if (!ret) |
f3d51e13 | 276 | ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); |
0c0daec7 | 277 | |
46e9371c | 278 | return ret; |
1929cb34 | 279 | } |