[net-next-2.6.git] / arch / sh / kernel / cpu / irq / intc.c

/*
 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
 *
 * Copyright (C) 2007 Magnus Damm
 *
 * Based on intc2.c and ipr.c
 *
 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
 * Copyright (C) 2000  Kazumoto Kojima
 * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
 * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
 * Copyright (C) 2005, 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>

#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
	((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
	 ((addr_e) << 16) | ((addr_d << 24)))

#define _INTC_SHIFT(h) (h & 0x1f)
#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
#define _INTC_FN(h) ((h >> 9) & 0xf)
#define _INTC_MODE(h) ((h >> 13) & 0x7)
#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)

struct intc_handle_int {
	unsigned int irq;
	unsigned long handle;
};

struct intc_desc_int {
	unsigned long *reg;
	unsigned int nr_reg;
	struct intc_handle_int *prio;
	unsigned int nr_prio;
	struct intc_handle_int *sense;
	unsigned int nr_sense;
	struct irq_chip chip;
};

static unsigned int intc_prio_level[NR_IRQS]; /* for now */

static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
{
	struct irq_chip *chip = get_irq_chip(irq);
	return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
}

static inline unsigned int set_field(unsigned int value,
				     unsigned int field_value,
				     unsigned int handle)
{
	unsigned int width = _INTC_WIDTH(handle);
	unsigned int shift = _INTC_SHIFT(handle);

	value &= ~(((1 << width) - 1) << shift);
	value |= field_value << shift;
	return value;
}

static void write_8(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outb(set_field(0, data, h), addr);
}

static void write_16(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outw(set_field(0, data, h), addr);
}

static void write_32(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outl(set_field(0, data, h), addr);
}

static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
}

static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
}

static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
}

enum {	REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };

static void (*intc_reg_fns[])(unsigned long addr,
			      unsigned long h,
			      unsigned long data) = {
	[REG_FN_WRITE_BASE + 0] = write_8,
	[REG_FN_WRITE_BASE + 1] = write_16,
	[REG_FN_WRITE_BASE + 3] = write_32,
	[REG_FN_MODIFY_BASE + 0] = modify_8,
	[REG_FN_MODIFY_BASE + 1] = modify_16,
	[REG_FN_MODIFY_BASE + 3] = modify_32,
};

enum {	MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
	MODE_MASK_REG,       /* Bit(s) set -> interrupt disabled */
	MODE_DUAL_REG,       /* Two registers, set bit to enable / disable */
	MODE_PRIO_REG,       /* Priority value written to enable interrupt */
	MODE_PCLR_REG,       /* Above plus all bits set to disable interrupt */
};

static void intc_mode_field(unsigned long addr,
			    unsigned long handle,
			    void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			    unsigned int irq)
{
	fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
}

static void intc_mode_zero(unsigned long addr,
			   unsigned long handle,
			   void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			   unsigned int irq)
{
	fn(addr, handle, 0);
}

static void intc_mode_prio(unsigned long addr,
			   unsigned long handle,
			   void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			   unsigned int irq)
{
	fn(addr, handle, intc_prio_level[irq]);
}

static void (*intc_enable_fns[])(unsigned long addr,
				 unsigned long handle,
				 void (*fn)(unsigned long,
					    unsigned long,
					    unsigned long),
				 unsigned int irq) = {
	[MODE_ENABLE_REG] = intc_mode_field,
	[MODE_MASK_REG] = intc_mode_zero,
	[MODE_DUAL_REG] = intc_mode_field,
	[MODE_PRIO_REG] = intc_mode_prio,
	[MODE_PCLR_REG] = intc_mode_prio,
};

static void (*intc_disable_fns[])(unsigned long addr,
				  unsigned long handle,
				  void (*fn)(unsigned long,
					     unsigned long,
					     unsigned long),
				  unsigned int irq) = {
	[MODE_ENABLE_REG] = intc_mode_zero,
	[MODE_MASK_REG] = intc_mode_field,
	[MODE_DUAL_REG] = intc_mode_field,
	[MODE_PRIO_REG] = intc_mode_zero,
	[MODE_PCLR_REG] = intc_mode_field,
};

static inline void _intc_enable(unsigned int irq, unsigned long handle)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned long addr = d->reg[_INTC_ADDR_E(handle)];

	intc_enable_fns[_INTC_MODE(handle)](addr, handle,
					    intc_reg_fns[_INTC_FN(handle)],
					    irq);
}

static void intc_enable(unsigned int irq)
{
	_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
}

static void intc_disable(unsigned int irq)
{
	struct intc_desc_int *desc = get_intc_desc(irq);
	unsigned long handle = (unsigned long) get_irq_chip_data(irq);
	unsigned long addr = desc->reg[_INTC_ADDR_D(handle)];

	intc_disable_fns[_INTC_MODE(handle)](addr, handle,
					     intc_reg_fns[_INTC_FN(handle)],
					     irq);
}

static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
					     unsigned int nr_hp,
					     unsigned int irq)
{
	int i;

	/* this doesn't scale well, but...
	 *
	 * this function should only be used for cerain uncommon
	 * operations such as intc_set_priority() and intc_set_sense()
	 * and in those rare cases performance doesn't matter that much.
	 * keeping the memory footprint low is more important.
	 *
	 * one rather simple way to speed this up and still keep the
	 * memory footprint down is to make sure the array is sorted
	 * and then perform a bisect to lookup the irq.
	 */

	for (i = 0; i < nr_hp; i++) {
		if ((hp + i)->irq != irq)
			continue;

		return hp + i;
	}

	return NULL;
}

int intc_set_priority(unsigned int irq, unsigned int prio)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	struct intc_handle_int *ihp;

	if (!intc_prio_level[irq] || prio <= 1)
		return -EINVAL;

	ihp = intc_find_irq(d->prio, d->nr_prio, irq);
	if (ihp) {
		if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
			return -EINVAL;

		intc_prio_level[irq] = prio;

		/*
		 * only set secondary masking method directly
		 * primary masking method is using intc_prio_level[irq]
		 * priority level will be set during next enable()
		 */

		if (_INTC_FN(ihp->handle) != REG_FN_ERR)
			_intc_enable(irq, ihp->handle);
	}
	return 0;
}

#define VALID(x) (x | 0x80)

static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = VALID(0),
	[IRQ_TYPE_EDGE_RISING] = VALID(1),
	[IRQ_TYPE_LEVEL_LOW] = VALID(2),
	[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
};

static int intc_set_sense(unsigned int irq, unsigned int type)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
	struct intc_handle_int *ihp;
	unsigned long addr;

	if (!value)
		return -EINVAL;

	ihp = intc_find_irq(d->sense, d->nr_sense, irq);
	if (ihp) {
		addr = d->reg[_INTC_ADDR_E(ihp->handle)];
		intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
	}
	return 0;
}

static unsigned int __init intc_get_reg(struct intc_desc_int *d,
				 unsigned long address)
{
	unsigned int k;

	for (k = 0; k < d->nr_reg; k++) {
		if (d->reg[k] == address)
			return k;
	}

	BUG();
	return 0;
}

static intc_enum __init intc_grp_id(struct intc_desc *desc,
				    intc_enum enum_id)
{
	struct intc_group *g = desc->groups;
	unsigned int i, j;

	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
		g = desc->groups + i;

		for (j = 0; g->enum_ids[j]; j++) {
			if (g->enum_ids[j] != enum_id)
				continue;

			return g->enum_id;
		}
	}

	return 0;
}

static unsigned int __init intc_prio_value(struct intc_desc *desc,
					   intc_enum enum_id, int do_grps)
{
	struct intc_prio *p = desc->priorities;
	unsigned int i;

	for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
		p = desc->priorities + i;

		if (p->enum_id != enum_id)
			continue;

		return p->priority;
	}

	if (do_grps)
		return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);

	/* default to the lowest priority possible if no priority is set
	 * - this needs to be at least 2 for 5-bit priorities on 7780
	 */

	return 2;
}

static unsigned int __init intc_mask_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id, int do_grps)
{
	struct intc_mask_reg *mr = desc->mask_regs;
	unsigned int i, j, fn, mode;
	unsigned long reg_e, reg_d;

	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
		mr = desc->mask_regs + i;

		for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
			if (mr->enum_ids[j] != enum_id)
				continue;

			if (mr->set_reg && mr->clr_reg) {
				fn = REG_FN_WRITE_BASE;
				mode = MODE_DUAL_REG;
				reg_e = mr->clr_reg;
				reg_d = mr->set_reg;
			} else {
				fn = REG_FN_MODIFY_BASE;
				if (mr->set_reg) {
					mode = MODE_ENABLE_REG;
					reg_e = mr->set_reg;
					reg_d = mr->set_reg;
				} else {
					mode = MODE_MASK_REG;
					reg_e = mr->clr_reg;
					reg_d = mr->clr_reg;
				}
			}

			fn += (mr->reg_width >> 3) - 1;
			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					1,
					(mr->reg_width - 1) - j);
		}
	}

	if (do_grps)
		return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);

	return 0;
}

static unsigned int __init intc_prio_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id, int do_grps)
{
	struct intc_prio_reg *pr = desc->prio_regs;
	unsigned int i, j, fn, mode, bit;
	unsigned long reg_e, reg_d;

	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
		pr = desc->prio_regs + i;

		for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
			if (pr->enum_ids[j] != enum_id)
				continue;

			if (pr->set_reg && pr->clr_reg) {
				fn = REG_FN_WRITE_BASE;
				mode = MODE_PCLR_REG;
				reg_e = pr->set_reg;
				reg_d = pr->clr_reg;
			} else {
				fn = REG_FN_MODIFY_BASE;
				mode = MODE_PRIO_REG;
				if (!pr->set_reg)
					BUG();
				reg_e = pr->set_reg;
				reg_d = pr->set_reg;
			}

			fn += (pr->reg_width >> 3) - 1;
			bit = pr->reg_width - ((j + 1) * pr->field_width);

			BUG_ON(bit < 0);

			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					pr->field_width, bit);
		}
	}

	if (do_grps)
		return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);

	return 0;
}

static unsigned int __init intc_sense_data(struct intc_desc *desc,
					   struct intc_desc_int *d,
					   intc_enum enum_id)
{
	struct intc_sense_reg *sr = desc->sense_regs;
	unsigned int i, j, fn, bit;

	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
		sr = desc->sense_regs + i;

		for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
			if (sr->enum_ids[j] != enum_id)
				continue;

			fn = REG_FN_MODIFY_BASE;
			fn += (sr->reg_width >> 3) - 1;
			bit = sr->reg_width - ((j + 1) * sr->field_width);

			BUG_ON(bit < 0);

			return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
					0, sr->field_width, bit);
		}
	}

	return 0;
}

static void __init intc_register_irq(struct intc_desc *desc,
				     struct intc_desc_int *d,
				     intc_enum enum_id,
				     unsigned int irq)
{
	struct intc_handle_int *hp;
	unsigned int data[2], primary;

	/* Prefer single interrupt source bitmap over other combinations:
	 * 1. bitmap, single interrupt source
	 * 2. priority, single interrupt source
	 * 3. bitmap, multiple interrupt sources (groups)
	 * 4. priority, multiple interrupt sources (groups)
	 */

	data[0] = intc_mask_data(desc, d, enum_id, 0);
	data[1] = intc_prio_data(desc, d, enum_id, 0);

	primary = 0;
	if (!data[0] && data[1])
		primary = 1;

	data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
	data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);

	if (!data[primary])
		primary ^= 1;

	BUG_ON(!data[primary]); /* must have primary masking method */

	disable_irq_nosync(irq);
	set_irq_chip_and_handler_name(irq, &d->chip,
				      handle_level_irq, "level");
	set_irq_chip_data(irq, (void *)data[primary]);

	/* record the desired priority level */
	intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);

	/* enable secondary masking method if present */
	if (data[!primary])
		_intc_enable(irq, data[!primary]);

	/* add irq to d->prio list if priority is available */
	if (data[1]) {
		hp = d->prio + d->nr_prio;
		hp->irq = irq;
		hp->handle = data[1];

		if (primary) {
			/*
			 * only secondary priority should access registers, so
			 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
			 */

			hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
			hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
		}
		d->nr_prio++;
	}

	/* add irq to d->sense list if sense is available */
	data[0] = intc_sense_data(desc, d, enum_id);
	if (data[0]) {
		(d->sense + d->nr_sense)->irq = irq;
		(d->sense + d->nr_sense)->handle = data[0];
		d->nr_sense++;
	}

	/* irq should be disabled by default */
	d->chip.mask(irq);
}

void __init register_intc_controller(struct intc_desc *desc)
{
	unsigned int i, k;
	struct intc_desc_int *d;

	d = alloc_bootmem(sizeof(*d));

	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;

	d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
	k = 0;

	if (desc->mask_regs) {
		for (i = 0; i < desc->nr_mask_regs; i++) {
			if (desc->mask_regs[i].set_reg)
				d->reg[k++] = desc->mask_regs[i].set_reg;
			if (desc->mask_regs[i].clr_reg)
				d->reg[k++] = desc->mask_regs[i].clr_reg;
		}
	}

	if (desc->prio_regs) {
		d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));

		for (i = 0; i < desc->nr_prio_regs; i++) {
			if (desc->prio_regs[i].set_reg)
				d->reg[k++] = desc->prio_regs[i].set_reg;
			if (desc->prio_regs[i].clr_reg)
				d->reg[k++] = desc->prio_regs[i].clr_reg;
		}
	}

	if (desc->sense_regs) {
		d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));

		for (i = 0; i < desc->nr_sense_regs; i++) {
			if (desc->sense_regs[i].reg)
				d->reg[k++] = desc->sense_regs[i].reg;
		}
	}

	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */

	d->chip.name = desc->name;
	d->chip.mask = intc_disable;
	d->chip.unmask = intc_enable;
	d->chip.mask_ack = intc_disable;
	d->chip.set_type = intc_set_sense;

	for (i = 0; i < desc->nr_vectors; i++) {
		struct intc_vect *vect = desc->vectors + i;

		intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
	}
}
Commit	Line	Data
02ab3f70 MD	1	/*
	2	* Shared interrupt handling code for IPR and INTC2 types of IRQs.
	3	*
	4	* Copyright (C) 2007 Magnus Damm
	5	*
	6	* Based on intc2.c and ipr.c
	7	*
	8	* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
	9	* Copyright (C) 2000 Kazumoto Kojima
	10	* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
	11	* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
	12	* Copyright (C) 2005, 2006 Paul Mundt
	13	*
	14	* This file is subject to the terms and conditions of the GNU General Public
	15	* License. See the file "COPYING" in the main directory of this archive
	16	* for more details.
	17	*/
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/module.h>
	21	#include <linux/io.h>
	22	#include <linux/interrupt.h>
73505b44 MD	23	#include <linux/bootmem.h>
	24
	25	#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
	26	((shift) \| ((width) << 5) \| ((fn) << 9) \| ((mode) << 13) \| \
	27	((addr_e) << 16) \| ((addr_d << 24)))
	28
	29	#define _INTC_SHIFT(h) (h & 0x1f)
	30	#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
	31	#define _INTC_FN(h) ((h >> 9) & 0xf)
	32	#define _INTC_MODE(h) ((h >> 13) & 0x7)
	33	#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
	34	#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
	35
	36	struct intc_handle_int {
	37	unsigned int irq;
	38	unsigned long handle;
	39	};
02ab3f70	40
73505b44 MD	41	struct intc_desc_int {
	42	unsigned long *reg;
	43	unsigned int nr_reg;
	44	struct intc_handle_int *prio;
	45	unsigned int nr_prio;
	46	struct intc_handle_int *sense;
	47	unsigned int nr_sense;
	48	struct irq_chip chip;
	49	};
02ab3f70	50
73505b44	51	static unsigned int intc_prio_level[NR_IRQS]; /* for now */
02ab3f70	52
73505b44	53	static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
02ab3f70 MD	54	{
02ab3f70 MD	55	struct irq_chip *chip = get_irq_chip(irq);
73505b44	56	return (void )((char )chip - offsetof(struct intc_desc_int, chip));
02ab3f70 MD	57	}
	58
	59	static inline unsigned int set_field(unsigned int value,
	60	unsigned int field_value,
73505b44	61	unsigned int handle)
02ab3f70	62	{
73505b44 MD	63	unsigned int width = _INTC_WIDTH(handle);
	64	unsigned int shift = _INTC_SHIFT(handle);
	65
02ab3f70 MD	66	value &= ~(((1 << width) - 1) << shift);
	67	value \|= field_value << shift;
	68	return value;
	69	}
	70
73505b44	71	static void write_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	72	{
73505b44	73	ctrl_outb(set_field(0, data, h), addr);
02ab3f70 MD	74	}
02ab3f70 MD	75
73505b44	76	static void write_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	77	{
73505b44	78	ctrl_outw(set_field(0, data, h), addr);
02ab3f70 MD	79	}
02ab3f70 MD	80
73505b44	81	static void write_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	82	{
73505b44	83	ctrl_outl(set_field(0, data, h), addr);
02ab3f70 MD	84	}
02ab3f70 MD	85
73505b44	86	static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	87	{
73505b44	88	ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
02ab3f70 MD	89	}
02ab3f70 MD	90
73505b44	91	static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	92	{
73505b44	93	ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
02ab3f70 MD	94	}
02ab3f70 MD	95
73505b44	96	static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	97	{
73505b44	98	ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
02ab3f70 MD	99	}
02ab3f70 MD	100
73505b44 MD	101	enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
	102
	103	static void (*intc_reg_fns[])(unsigned long addr,
	104	unsigned long h,
	105	unsigned long data) = {
	106	[REG_FN_WRITE_BASE + 0] = write_8,
	107	[REG_FN_WRITE_BASE + 1] = write_16,
	108	[REG_FN_WRITE_BASE + 3] = write_32,
	109	[REG_FN_MODIFY_BASE + 0] = modify_8,
	110	[REG_FN_MODIFY_BASE + 1] = modify_16,
	111	[REG_FN_MODIFY_BASE + 3] = modify_32,
	112	};
02ab3f70	113
73505b44 MD	114	enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
	115	MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
	116	MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
	117	MODE_PRIO_REG, /* Priority value written to enable interrupt */
	118	MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
	119	};
02ab3f70	120
73505b44 MD	121	static void intc_mode_field(unsigned long addr,
	122	unsigned long handle,
	123	void (*fn)(unsigned long,
	124	unsigned long,
	125	unsigned long),
	126	unsigned int irq)
02ab3f70	127	{
73505b44	128	fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
02ab3f70 MD	129	}
02ab3f70 MD	130
73505b44 MD	131	static void intc_mode_zero(unsigned long addr,
	132	unsigned long handle,
	133	void (*fn)(unsigned long,
	134	unsigned long,
	135	unsigned long),
	136	unsigned int irq)
51da6426	137	{
73505b44	138	fn(addr, handle, 0);
51da6426 MD	139	}
51da6426 MD	140
73505b44 MD	141	static void intc_mode_prio(unsigned long addr,
	142	unsigned long handle,
	143	void (*fn)(unsigned long,
	144	unsigned long,
	145	unsigned long),
	146	unsigned int irq)
51da6426	147	{
73505b44	148	fn(addr, handle, intc_prio_level[irq]);
51da6426 MD	149	}
51da6426 MD	150
73505b44 MD	151	static void (*intc_enable_fns[])(unsigned long addr,
	152	unsigned long handle,
	153	void (*fn)(unsigned long,
	154	unsigned long,
	155	unsigned long),
	156	unsigned int irq) = {
	157	[MODE_ENABLE_REG] = intc_mode_field,
	158	[MODE_MASK_REG] = intc_mode_zero,
	159	[MODE_DUAL_REG] = intc_mode_field,
	160	[MODE_PRIO_REG] = intc_mode_prio,
	161	[MODE_PCLR_REG] = intc_mode_prio,
	162	};
51da6426	163
73505b44 MD	164	static void (*intc_disable_fns[])(unsigned long addr,
	165	unsigned long handle,
	166	void (*fn)(unsigned long,
	167	unsigned long,
	168	unsigned long),
	169	unsigned int irq) = {
	170	[MODE_ENABLE_REG] = intc_mode_zero,
	171	[MODE_MASK_REG] = intc_mode_field,
	172	[MODE_DUAL_REG] = intc_mode_field,
	173	[MODE_PRIO_REG] = intc_mode_zero,
	174	[MODE_PCLR_REG] = intc_mode_field,
	175	};
51da6426	176
73505b44	177	static inline void _intc_enable(unsigned int irq, unsigned long handle)
51da6426	178	{
73505b44 MD	179	struct intc_desc_int *d = get_intc_desc(irq);
73505b44 MD	180	unsigned long addr = d->reg[_INTC_ADDR_E(handle)];
51da6426	181
73505b44 MD	182	intc_enable_fns[_INTC_MODE(handle)](addr, handle,
	183	intc_reg_fns[_INTC_FN(handle)],
	184	irq);
51da6426 MD	185	}
51da6426 MD	186
02ab3f70 MD	187	static void intc_enable(unsigned int irq)
02ab3f70 MD	188	{
73505b44	189	_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
02ab3f70 MD	190	}
	191
	192	static void intc_disable(unsigned int irq)
	193	{
73505b44 MD	194	struct intc_desc_int *desc = get_intc_desc(irq);
	195	unsigned long handle = (unsigned long) get_irq_chip_data(irq);
	196	unsigned long addr = desc->reg[_INTC_ADDR_D(handle)];
02ab3f70	197
73505b44 MD	198	intc_disable_fns[_INTC_MODE(handle)](addr, handle,
	199	intc_reg_fns[_INTC_FN(handle)],
	200	irq);
02ab3f70 MD	201	}
02ab3f70 MD	202
73505b44 MD	203	static struct intc_handle_int intc_find_irq(struct intc_handle_int hp,
	204	unsigned int nr_hp,
	205	unsigned int irq)
02ab3f70	206	{
73505b44 MD	207	int i;
73505b44 MD	208
3d37d94e MD	209	/* this doesn't scale well, but...
	210	*
	211	* this function should only be used for cerain uncommon
	212	* operations such as intc_set_priority() and intc_set_sense()
	213	* and in those rare cases performance doesn't matter that much.
	214	* keeping the memory footprint low is more important.
	215	*
	216	* one rather simple way to speed this up and still keep the
	217	* memory footprint down is to make sure the array is sorted
	218	* and then perform a bisect to lookup the irq.
	219	*/
	220
73505b44 MD	221	for (i = 0; i < nr_hp; i++) {
	222	if ((hp + i)->irq != irq)
	223	continue;
	224
	225	return hp + i;
	226	}
02ab3f70	227
73505b44	228	return NULL;
02ab3f70 MD	229	}
02ab3f70 MD	230
73505b44	231	int intc_set_priority(unsigned int irq, unsigned int prio)
02ab3f70	232	{
73505b44 MD	233	struct intc_desc_int *d = get_intc_desc(irq);
	234	struct intc_handle_int *ihp;
	235
	236	if (!intc_prio_level[irq] \|\| prio <= 1)
	237	return -EINVAL;
	238
	239	ihp = intc_find_irq(d->prio, d->nr_prio, irq);
	240	if (ihp) {
3d37d94e	241	if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
73505b44	242	return -EINVAL;
02ab3f70	243
73505b44 MD	244	intc_prio_level[irq] = prio;
	245
	246	/*
	247	* only set secondary masking method directly
	248	* primary masking method is using intc_prio_level[irq]
	249	* priority level will be set during next enable()
	250	*/
	251
3d37d94e	252	if (_INTC_FN(ihp->handle) != REG_FN_ERR)
73505b44 MD	253	_intc_enable(irq, ihp->handle);
	254	}
	255	return 0;
02ab3f70 MD	256	}
	257
	258	#define VALID(x) (x \| 0x80)
	259
	260	static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	261	[IRQ_TYPE_EDGE_FALLING] = VALID(0),
	262	[IRQ_TYPE_EDGE_RISING] = VALID(1),
	263	[IRQ_TYPE_LEVEL_LOW] = VALID(2),
	264	[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
	265	};
	266
	267	static int intc_set_sense(unsigned int irq, unsigned int type)
	268	{
73505b44	269	struct intc_desc_int *d = get_intc_desc(irq);
02ab3f70	270	unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
73505b44 MD	271	struct intc_handle_int *ihp;
73505b44 MD	272	unsigned long addr;
02ab3f70	273
73505b44	274	if (!value)
02ab3f70 MD	275	return -EINVAL;
02ab3f70 MD	276
73505b44 MD	277	ihp = intc_find_irq(d->sense, d->nr_sense, irq);
	278	if (ihp) {
	279	addr = d->reg[_INTC_ADDR_E(ihp->handle)];
	280	intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
02ab3f70	281	}
73505b44	282	return 0;
02ab3f70 MD	283	}
02ab3f70 MD	284
73505b44 MD	285	static unsigned int __init intc_get_reg(struct intc_desc_int *d,
73505b44 MD	286	unsigned long address)
02ab3f70	287	{
73505b44	288	unsigned int k;
02ab3f70	289
73505b44 MD	290	for (k = 0; k < d->nr_reg; k++) {
	291	if (d->reg[k] == address)
	292	return k;
51da6426 MD	293	}
	294
	295	BUG();
73505b44	296	return 0;
51da6426 MD	297	}
51da6426 MD	298
73505b44 MD	299	static intc_enum __init intc_grp_id(struct intc_desc *desc,
73505b44 MD	300	intc_enum enum_id)
680c4598 MD	301	{
	302	struct intc_group *g = desc->groups;
	303	unsigned int i, j;
	304
	305	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
	306	g = desc->groups + i;
	307
	308	for (j = 0; g->enum_ids[j]; j++) {
	309	if (g->enum_ids[j] != enum_id)
	310	continue;
	311
	312	return g->enum_id;
	313	}
	314	}
	315
	316	return 0;
	317	}
	318
02ab3f70	319	static unsigned int __init intc_prio_value(struct intc_desc *desc,
680c4598	320	intc_enum enum_id, int do_grps)
02ab3f70	321	{
680c4598	322	struct intc_prio *p = desc->priorities;
02ab3f70 MD	323	unsigned int i;
02ab3f70 MD	324
680c4598 MD	325	for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
680c4598 MD	326	p = desc->priorities + i;
02ab3f70 MD	327
	328	if (p->enum_id != enum_id)
	329	continue;
	330
	331	return p->priority;
	332	}
	333
680c4598 MD	334	if (do_grps)
	335	return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
	336
	337	/* default to the lowest priority possible if no priority is set
	338	* - this needs to be at least 2 for 5-bit priorities on 7780
	339	*/
	340
	341	return 2;
02ab3f70 MD	342	}
	343
	344	static unsigned int __init intc_mask_data(struct intc_desc *desc,
73505b44	345	struct intc_desc_int *d,
680c4598	346	intc_enum enum_id, int do_grps)
02ab3f70	347	{
680c4598	348	struct intc_mask_reg *mr = desc->mask_regs;
73505b44 MD	349	unsigned int i, j, fn, mode;
73505b44 MD	350	unsigned long reg_e, reg_d;
02ab3f70	351
680c4598 MD	352	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
680c4598 MD	353	mr = desc->mask_regs + i;
02ab3f70 MD	354
	355	for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
	356	if (mr->enum_ids[j] != enum_id)
	357	continue;
	358
73505b44 MD	359	if (mr->set_reg && mr->clr_reg) {
	360	fn = REG_FN_WRITE_BASE;
	361	mode = MODE_DUAL_REG;
	362	reg_e = mr->clr_reg;
	363	reg_d = mr->set_reg;
	364	} else {
	365	fn = REG_FN_MODIFY_BASE;
	366	if (mr->set_reg) {
	367	mode = MODE_ENABLE_REG;
	368	reg_e = mr->set_reg;
	369	reg_d = mr->set_reg;
	370	} else {
	371	mode = MODE_MASK_REG;
	372	reg_e = mr->clr_reg;
	373	reg_d = mr->clr_reg;
	374	}
51da6426 MD	375	}
51da6426 MD	376
73505b44 MD	377	fn += (mr->reg_width >> 3) - 1;
	378	return _INTC_MK(fn, mode,
	379	intc_get_reg(d, reg_e),
	380	intc_get_reg(d, reg_d),
	381	1,
	382	(mr->reg_width - 1) - j);
02ab3f70 MD	383	}
	384	}
	385
680c4598	386	if (do_grps)
73505b44	387	return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
680c4598	388
02ab3f70 MD	389	return 0;
	390	}
	391
	392	static unsigned int __init intc_prio_data(struct intc_desc *desc,
73505b44	393	struct intc_desc_int *d,
680c4598	394	intc_enum enum_id, int do_grps)
02ab3f70	395	{
680c4598	396	struct intc_prio_reg *pr = desc->prio_regs;
73505b44 MD	397	unsigned int i, j, fn, mode, bit;
73505b44 MD	398	unsigned long reg_e, reg_d;
02ab3f70	399
680c4598 MD	400	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
680c4598 MD	401	pr = desc->prio_regs + i;
02ab3f70 MD	402
	403	for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
	404	if (pr->enum_ids[j] != enum_id)
	405	continue;
	406
73505b44 MD	407	if (pr->set_reg && pr->clr_reg) {
	408	fn = REG_FN_WRITE_BASE;
	409	mode = MODE_PCLR_REG;
	410	reg_e = pr->set_reg;
	411	reg_d = pr->clr_reg;
	412	} else {
	413	fn = REG_FN_MODIFY_BASE;
	414	mode = MODE_PRIO_REG;
	415	if (!pr->set_reg)
	416	BUG();
	417	reg_e = pr->set_reg;
	418	reg_d = pr->set_reg;
	419	}
02ab3f70	420
73505b44	421	fn += (pr->reg_width >> 3) - 1;
02ab3f70 MD	422	bit = pr->reg_width - ((j + 1) * pr->field_width);
	423
	424	BUG_ON(bit < 0);
	425
73505b44 MD	426	return _INTC_MK(fn, mode,
	427	intc_get_reg(d, reg_e),
	428	intc_get_reg(d, reg_d),
	429	pr->field_width, bit);
02ab3f70 MD	430	}
	431	}
	432
680c4598	433	if (do_grps)
73505b44 MD	434	return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
	435
	436	return 0;
	437	}
	438
	439	static unsigned int __init intc_sense_data(struct intc_desc *desc,
	440	struct intc_desc_int *d,
	441	intc_enum enum_id)
	442	{
	443	struct intc_sense_reg *sr = desc->sense_regs;
	444	unsigned int i, j, fn, bit;
	445
	446	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
	447	sr = desc->sense_regs + i;
	448
	449	for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
	450	if (sr->enum_ids[j] != enum_id)
	451	continue;
	452
	453	fn = REG_FN_MODIFY_BASE;
	454	fn += (sr->reg_width >> 3) - 1;
	455	bit = sr->reg_width - ((j + 1) * sr->field_width);
	456
	457	BUG_ON(bit < 0);
	458
	459	return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
	460	0, sr->field_width, bit);
	461	}
	462	}
680c4598	463
02ab3f70 MD	464	return 0;
	465	}
	466
73505b44 MD	467	static void __init intc_register_irq(struct intc_desc *desc,
	468	struct intc_desc_int *d,
	469	intc_enum enum_id,
02ab3f70 MD	470	unsigned int irq)
02ab3f70 MD	471	{
3d37d94e	472	struct intc_handle_int *hp;
680c4598 MD	473	unsigned int data[2], primary;
	474
	475	/* Prefer single interrupt source bitmap over other combinations:
	476	* 1. bitmap, single interrupt source
	477	* 2. priority, single interrupt source
	478	* 3. bitmap, multiple interrupt sources (groups)
	479	* 4. priority, multiple interrupt sources (groups)
	480	*/
02ab3f70	481
73505b44 MD	482	data[0] = intc_mask_data(desc, d, enum_id, 0);
73505b44 MD	483	data[1] = intc_prio_data(desc, d, enum_id, 0);
680c4598 MD	484
	485	primary = 0;
	486	if (!data[0] && data[1])
	487	primary = 1;
	488
73505b44 MD	489	data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
73505b44 MD	490	data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
680c4598 MD	491
	492	if (!data[primary])
	493	primary ^= 1;
	494
	495	BUG_ON(!data[primary]); /* must have primary masking method */
02ab3f70 MD	496
02ab3f70 MD	497	disable_irq_nosync(irq);
73505b44	498	set_irq_chip_and_handler_name(irq, &d->chip,
02ab3f70	499	handle_level_irq, "level");
680c4598	500	set_irq_chip_data(irq, (void *)data[primary]);
02ab3f70	501
73505b44 MD	502	/* record the desired priority level */
	503	intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
	504
680c4598 MD	505	/* enable secondary masking method if present */
680c4598 MD	506	if (data[!primary])
73505b44 MD	507	_intc_enable(irq, data[!primary]);
	508
	509	/* add irq to d->prio list if priority is available */
	510	if (data[1]) {
3d37d94e MD	511	hp = d->prio + d->nr_prio;
	512	hp->irq = irq;
	513	hp->handle = data[1];
	514
	515	if (primary) {
	516	/*
	517	* only secondary priority should access registers, so
	518	* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
	519	*/
	520
	521	hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
	522	hp->handle \|= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
	523	}
73505b44 MD	524	d->nr_prio++;
	525	}
	526
	527	/* add irq to d->sense list if sense is available */
	528	data[0] = intc_sense_data(desc, d, enum_id);
	529	if (data[0]) {
	530	(d->sense + d->nr_sense)->irq = irq;
	531	(d->sense + d->nr_sense)->handle = data[0];
	532	d->nr_sense++;
	533	}
02ab3f70 MD	534
02ab3f70 MD	535	/* irq should be disabled by default */
73505b44	536	d->chip.mask(irq);
02ab3f70 MD	537	}
	538
	539	void __init register_intc_controller(struct intc_desc *desc)
	540	{
73505b44 MD	541	unsigned int i, k;
	542	struct intc_desc_int *d;
	543
	544	d = alloc_bootmem(sizeof(*d));
	545
	546	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
	547	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
	548	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
	549
	550	d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
	551	k = 0;
	552
	553	if (desc->mask_regs) {
	554	for (i = 0; i < desc->nr_mask_regs; i++) {
	555	if (desc->mask_regs[i].set_reg)
	556	d->reg[k++] = desc->mask_regs[i].set_reg;
	557	if (desc->mask_regs[i].clr_reg)
	558	d->reg[k++] = desc->mask_regs[i].clr_reg;
	559	}
	560	}
	561
	562	if (desc->prio_regs) {
	563	d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
	564
	565	for (i = 0; i < desc->nr_prio_regs; i++) {
	566	if (desc->prio_regs[i].set_reg)
	567	d->reg[k++] = desc->prio_regs[i].set_reg;
	568	if (desc->prio_regs[i].clr_reg)
	569	d->reg[k++] = desc->prio_regs[i].clr_reg;
	570	}
	571	}
	572
	573	if (desc->sense_regs) {
	574	d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
	575
	576	for (i = 0; i < desc->nr_sense_regs; i++) {
	577	if (desc->sense_regs[i].reg)
	578	d->reg[k++] = desc->sense_regs[i].reg;
	579	}
	580	}
	581
	582	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
02ab3f70	583
73505b44 MD	584	d->chip.name = desc->name;
	585	d->chip.mask = intc_disable;
	586	d->chip.unmask = intc_enable;
	587	d->chip.mask_ack = intc_disable;
	588	d->chip.set_type = intc_set_sense;
02ab3f70 MD	589
	590	for (i = 0; i < desc->nr_vectors; i++) {
	591	struct intc_vect *vect = desc->vectors + i;
	592
73505b44	593	intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
02ab3f70 MD	594	}
02ab3f70 MD	595	}