[net-next-2.6.git] / arch / sh / include / asm / processor.h

#ifndef __ASM_SH_PROCESSOR_H
#define __ASM_SH_PROCESSOR_H

#include <asm/cpu-features.h>
#include <asm/segment.h>
#include <asm/cache.h>

#ifndef __ASSEMBLY__
/*
 *  CPU type and hardware bug flags. Kept separately for each CPU.
 *
 *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
 *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
 *  for parsing the subtype in get_cpu_subtype().
 */
enum cpu_type {
	/* SH-2 types */
	CPU_SH7619,

	/* SH-2A types */
	CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,

	/* SH-3 types */
	CPU_SH7705, CPU_SH7706, CPU_SH7707,
	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
	CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
	CPU_SH7720, CPU_SH7721, CPU_SH7729,

	/* SH-4 types */
	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
	CPU_SH7760, CPU_SH4_202, CPU_SH4_501,

	/* SH-4A types */
	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
	CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,

	/* SH4AL-DSP types */
	CPU_SH7343, CPU_SH7722, CPU_SH7366,

	/* SH-5 types */
        CPU_SH5_101, CPU_SH5_103,

	/* Unknown subtype */
	CPU_SH_NONE
};

enum cpu_family {
	CPU_FAMILY_SH2,
	CPU_FAMILY_SH2A,
	CPU_FAMILY_SH3,
	CPU_FAMILY_SH4,
	CPU_FAMILY_SH4A,
	CPU_FAMILY_SH4AL_DSP,
	CPU_FAMILY_SH5,
	CPU_FAMILY_UNKNOWN,
};

/*
 * TLB information structure
 *
 * Defined for both I and D tlb, per-processor.
 */
struct tlb_info {
	unsigned long long next;
	unsigned long long first;
	unsigned long long last;

	unsigned int entries;
	unsigned int step;

	unsigned long flags;
};

struct sh_cpuinfo {
	unsigned int type, family;
	int cut_major, cut_minor;
	unsigned long loops_per_jiffy;
	unsigned long asid_cache;

	struct cache_info icache;	/* Primary I-cache */
	struct cache_info dcache;	/* Primary D-cache */
	struct cache_info scache;	/* Secondary cache */

	/* TLB info */
	struct tlb_info itlb;
	struct tlb_info dtlb;

#ifdef CONFIG_SMP
	struct task_struct *idle;
#endif

	unsigned int phys_bits;
	unsigned long flags;
} __attribute__ ((aligned(L1_CACHE_BYTES)));

extern struct sh_cpuinfo cpu_data[];
#define boot_cpu_data cpu_data[0]
#define current_cpu_data cpu_data[smp_processor_id()]
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]

#define cpu_sleep()	__asm__ __volatile__ ("sleep" : : : "memory")
#define cpu_relax()	barrier()

/* Forward decl */
struct seq_operations;
struct task_struct;

extern struct pt_regs fake_swapper_regs;

extern void cpu_init(void);
extern void cpu_probe(void);

/* arch/sh/kernel/process.c */
extern unsigned int xstate_size;
extern void free_thread_xstate(struct task_struct *);
extern struct kmem_cache *task_xstate_cachep;

/* arch/sh/mm/alignment.c */
extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
extern int set_unalign_ctl(struct task_struct *, unsigned int val);

#define GET_UNALIGN_CTL(tsk, addr)	get_unalign_ctl((tsk), (addr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

/* arch/sh/mm/init.c */
extern unsigned int mem_init_done;

/* arch/sh/kernel/setup.c */
const char *get_cpu_subtype(struct sh_cpuinfo *c);
extern const struct seq_operations cpuinfo_op;

/* thread_struct flags */
#define SH_THREAD_UAC_NOPRINT	(1 << 0)
#define SH_THREAD_UAC_SIGBUS	(1 << 1)
#define SH_THREAD_UAC_MASK	(SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)

/* processor boot mode configuration */
#define MODE_PIN0 (1 << 0)
#define MODE_PIN1 (1 << 1)
#define MODE_PIN2 (1 << 2)
#define MODE_PIN3 (1 << 3)
#define MODE_PIN4 (1 << 4)
#define MODE_PIN5 (1 << 5)
#define MODE_PIN6 (1 << 6)
#define MODE_PIN7 (1 << 7)
#define MODE_PIN8 (1 << 8)
#define MODE_PIN9 (1 << 9)
#define MODE_PIN10 (1 << 10)
#define MODE_PIN11 (1 << 11)
#define MODE_PIN12 (1 << 12)
#define MODE_PIN13 (1 << 13)
#define MODE_PIN14 (1 << 14)
#define MODE_PIN15 (1 << 15)

int generic_mode_pins(void);
int test_mode_pin(int pin);

#ifdef CONFIG_VSYSCALL
int vsyscall_init(void);
#else
#define vsyscall_init() do { } while (0)
#endif

#endif /* __ASSEMBLY__ */

#ifdef CONFIG_SUPERH32
# include "processor_32.h"
#else
# include "processor_64.h"
#endif

#endif /* __ASM_SH_PROCESSOR_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_PROCESSOR_H
1da177e4 LT	2	#define __ASM_SH_PROCESSOR_H
1da177e4	3
76168c21	4	#include <asm/cpu-features.h>
02f7e627	5	#include <asm/segment.h>
81b66995	6	#include <asm/cache.h>
76168c21	7
343ac722	8	#ifndef __ASSEMBLY__
1da177e4 LT	9	/*
	10	* CPU type and hardware bug flags. Kept separately for each CPU.
	11	*
	12	* Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
de02797a	13	* in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
1da177e4 LT	14	* for parsing the subtype in get_cpu_subtype().
	15	*/
	16	enum cpu_type {
	17	/* SH-2 types */
b9601c5e	18	CPU_SH7619,
b229632a YS	19
b229632a YS	20	/* SH-2A types */
2825999e	21	CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
1da177e4 LT	22
1da177e4 LT	23	/* SH-3 types */
e5723e0e PM	24	CPU_SH7705, CPU_SH7706, CPU_SH7707,
e5723e0e PM	25	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
9465a54f	26	CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
31a49c4b	27	CPU_SH7720, CPU_SH7721, CPU_SH7729,
1da177e4 LT	28
	29	/* SH-4 types */
	30	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
f9669187	31	CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
b552c7e8 PM	32
b552c7e8 PM	33	/* SH-4A types */
55ba99eb	34	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
c01f0f1a	35	CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
41504c39 PM	36
41504c39 PM	37	/* SH4AL-DSP types */
9109a30e	38	CPU_SH7343, CPU_SH7722, CPU_SH7366,
1da177e4	39
af3c7dfe PM	40	/* SH-5 types */
	41	CPU_SH5_101, CPU_SH5_103,
	42
1da177e4 LT	43	/* Unknown subtype */
	44	CPU_SH_NONE
	45	};
	46
e82da214 PM	47	enum cpu_family {
	48	CPU_FAMILY_SH2,
	49	CPU_FAMILY_SH2A,
	50	CPU_FAMILY_SH3,
	51	CPU_FAMILY_SH4,
	52	CPU_FAMILY_SH4A,
	53	CPU_FAMILY_SH4AL_DSP,
	54	CPU_FAMILY_SH5,
	55	CPU_FAMILY_UNKNOWN,
	56	};
	57
81b66995 PM	58	/*
	59	* TLB information structure
	60	*
	61	* Defined for both I and D tlb, per-processor.
	62	*/
	63	struct tlb_info {
	64	unsigned long long next;
	65	unsigned long long first;
	66	unsigned long long last;
	67
	68	unsigned int entries;
	69	unsigned int step;
	70
	71	unsigned long flags;
	72	};
	73
	74	struct sh_cpuinfo {
e82da214	75	unsigned int type, family;
81b66995 PM	76	int cut_major, cut_minor;
	77	unsigned long loops_per_jiffy;
	78	unsigned long asid_cache;
	79
	80	struct cache_info icache; /* Primary I-cache */
	81	struct cache_info dcache; /* Primary D-cache */
	82	struct cache_info scache; /* Secondary cache */
	83
	84	/* TLB info */
	85	struct tlb_info itlb;
	86	struct tlb_info dtlb;
	87
8db2bc45 PM	88	#ifdef CONFIG_SMP
	89	struct task_struct *idle;
	90	#endif
	91
2f98492c	92	unsigned int phys_bits;
81b66995 PM	93	unsigned long flags;
	94	} __attribute__ ((aligned(L1_CACHE_BYTES)));
	95
	96	extern struct sh_cpuinfo cpu_data[];
	97	#define boot_cpu_data cpu_data[0]
	98	#define current_cpu_data cpu_data[smp_processor_id()]
	99	#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
	100
eb67cf14 PM	101	#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
	102	#define cpu_relax() barrier()
	103
343ac722	104	/* Forward decl */
fa43972f	105	struct seq_operations;
3ef2932b	106	struct task_struct;
fa43972f PM	107
fa43972f PM	108	extern struct pt_regs fake_swapper_regs;
19f9a34f	109
4a6feab0	110	extern void cpu_init(void);
a9079ca0 PM	111	extern void cpu_probe(void);
a9079ca0 PM	112
3ef2932b PM	113	/* arch/sh/kernel/process.c */
	114	extern unsigned int xstate_size;
	115	extern void free_thread_xstate(struct task_struct *);
	116	extern struct kmem_cache *task_xstate_cachep;
	117
94ea5e44 PM	118	/* arch/sh/mm/alignment.c */
	119	extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
	120	extern int set_unalign_ctl(struct task_struct *, unsigned int val);
	121
	122	#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
	123	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	124
d9b9487a PM	125	/* arch/sh/mm/init.c */
	126	extern unsigned int mem_init_done;
	127
11c19656 PM	128	/* arch/sh/kernel/setup.c */
11c19656 PM	129	const char get_cpu_subtype(struct sh_cpuinfo c);
fa43972f	130	extern const struct seq_operations cpuinfo_op;
11c19656	131
94ea5e44 PM	132	/* thread_struct flags */
	133	#define SH_THREAD_UAC_NOPRINT (1 << 0)
	134	#define SH_THREAD_UAC_SIGBUS (1 << 1)
	135	#define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT \| SH_THREAD_UAC_SIGBUS)
	136
eb9b9b56	137	/* processor boot mode configuration */
0d4fdbb6 MD	138	#define MODE_PIN0 (1 << 0)
	139	#define MODE_PIN1 (1 << 1)
	140	#define MODE_PIN2 (1 << 2)
	141	#define MODE_PIN3 (1 << 3)
	142	#define MODE_PIN4 (1 << 4)
	143	#define MODE_PIN5 (1 << 5)
	144	#define MODE_PIN6 (1 << 6)
	145	#define MODE_PIN7 (1 << 7)
	146	#define MODE_PIN8 (1 << 8)
	147	#define MODE_PIN9 (1 << 9)
	148	#define MODE_PIN10 (1 << 10)
	149	#define MODE_PIN11 (1 << 11)
	150	#define MODE_PIN12 (1 << 12)
	151	#define MODE_PIN13 (1 << 13)
	152	#define MODE_PIN14 (1 << 14)
	153	#define MODE_PIN15 (1 << 15)
	154
eb9b9b56 MD	155	int generic_mode_pins(void);
	156	int test_mode_pin(int pin);
	157
acb499f0 PM	158	#ifdef CONFIG_VSYSCALL
	159	int vsyscall_init(void);
	160	#else
	161	#define vsyscall_init() do { } while (0)
	162	#endif
	163
343ac722 PM	164	#endif /* __ASSEMBLY__ */
	165
	166	#ifdef CONFIG_SUPERH32
	167	# include "processor_32.h"
	168	#else
	169	# include "processor_64.h"
	170	#endif
	171
1da177e4	172	#endif /* __ASM_SH_PROCESSOR_H */