[net-next-2.6.git] / arch / sh / include / asm / pgtable.h

/*
 * This file contains the functions and defines necessary to modify and
 * use the SuperH page table tree.
 *
 * Copyright (C) 1999 Niibe Yutaka
 * Copyright (C) 2002 - 2007 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License.  See the file "COPYING" in the main directory of this
 * archive for more details.
 */
#ifndef __ASM_SH_PGTABLE_H
#define __ASM_SH_PGTABLE_H

#ifdef CONFIG_X2TLB
#include <asm/pgtable-3level.h>
#else
#include <asm/pgtable-2level.h>
#endif
#include <asm/page.h>

#ifndef __ASSEMBLY__
#include <asm/addrspace.h>
#include <asm/fixmap.h>

/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

#endif /* !__ASSEMBLY__ */

/*
 * Effective and physical address definitions, to aid with sign
 * extension.
 */
#define NEFF		32
#define	NEFF_SIGN	(1LL << (NEFF - 1))
#define	NEFF_MASK	(-1LL << NEFF)

static inline unsigned long long neff_sign_extend(unsigned long val)
{
	unsigned long long extended = val;
	return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
}

#ifdef CONFIG_29BIT
#define NPHYS		29
#else
#define NPHYS		32
#endif

#define	NPHYS_SIGN	(1LL << (NPHYS - 1))
#define	NPHYS_MASK	(-1LL << NPHYS)

#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/* Entries per level */
#define PTRS_PER_PTE	(PAGE_SIZE / (1 << PTE_MAGNITUDE))

#define FIRST_USER_ADDRESS	0

#define PHYS_ADDR_MASK29		0x1fffffff
#define PHYS_ADDR_MASK32		0xffffffff

static inline unsigned long phys_addr_mask(void)
{
	/* Is the MMU in 29bit mode? */
	if (__in_29bit_mode())
		return PHYS_ADDR_MASK29;

	return PHYS_ADDR_MASK32;
}

#define PTE_PHYS_MASK		(phys_addr_mask() & PAGE_MASK)
#define PTE_FLAGS_MASK		(~(PTE_PHYS_MASK) << PAGE_SHIFT)

#ifdef CONFIG_SUPERH32
#define VMALLOC_START	(P3SEG)
#else
#define VMALLOC_START	(0xf0000000)
#endif
#define VMALLOC_END	(FIXADDR_START-2*PAGE_SIZE)

#if defined(CONFIG_SUPERH32)
#include <asm/pgtable_32.h>
#else
#include <asm/pgtable_64.h>
#endif

/*
 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
 * protection for execute, and considers it the same as a read. Also, write
 * permission implies read permission. This is the closest we can get..
 *
 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
 * not only supporting separate execute, read, and write bits, but having
 * completely separate permission bits for user and kernel space.
 */
	 /*xwr*/
#define __P000	PAGE_NONE
#define __P001	PAGE_READONLY
#define __P010	PAGE_COPY
#define __P011	PAGE_COPY
#define __P100	PAGE_EXECREAD
#define __P101	PAGE_EXECREAD
#define __P110	PAGE_COPY
#define __P111	PAGE_COPY

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_WRITEONLY
#define __S011	PAGE_SHARED
#define __S100	PAGE_EXECREAD
#define __S101	PAGE_EXECREAD
#define __S110	PAGE_RWX
#define __S111	PAGE_RWX

typedef pte_t *pte_addr_t;

#define kern_addr_valid(addr)	(1)

#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)		\
		remap_pfn_range(vma, vaddr, pfn, size, prot)

#define pte_pfn(x)		((unsigned long)(((x).pte_low >> PAGE_SHIFT)))

/*
 * Initialise the page table caches
 */
extern void pgtable_cache_init(void);

struct vm_area_struct;

extern void __update_cache(struct vm_area_struct *vma,
			   unsigned long address, pte_t pte);
extern void __update_tlb(struct vm_area_struct *vma,
			 unsigned long address, pte_t pte);

static inline void
update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
{
	pte_t pte = *ptep;
	__update_cache(vma, address, pte);
	__update_tlb(vma, address, pte);
}

extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
extern void paging_init(void);
extern void page_table_range_init(unsigned long start, unsigned long end,
				  pgd_t *pgd);

/* arch/sh/mm/mmap.c */
#define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN

#define __HAVE_ARCH_PTE_SPECIAL

#include <asm-generic/pgtable.h>

#endif /* __ASM_SH_PGTABLE_H */
Commit	Line	Data
1da177e4	1	/*
26ff6c11 PM	2	* This file contains the functions and defines necessary to modify and
	3	* use the SuperH page table tree.
	4	*
1da177e4	5	* Copyright (C) 1999 Niibe Yutaka
249cfea9	6	* Copyright (C) 2002 - 2007 Paul Mundt
26ff6c11 PM	7	*
	8	* This file is subject to the terms and conditions of the GNU General
	9	* Public License. See the file "COPYING" in the main directory of this
	10	* archive for more details.
1da177e4	11	*/
26ff6c11 PM	12	#ifndef __ASM_SH_PGTABLE_H
26ff6c11 PM	13	#define __ASM_SH_PGTABLE_H
1da177e4	14
782bb5a5	15	#ifdef CONFIG_X2TLB
e44d6c40	16	#include <asm/pgtable-3level.h>
5d9b4b19	17	#else
e44d6c40	18	#include <asm/pgtable-2level.h>
5d9b4b19	19	#endif
26ff6c11 PM	20	#include <asm/page.h>
26ff6c11 PM	21
1da177e4	22	#ifndef __ASSEMBLY__
1da177e4 LT	23	#include <asm/addrspace.h>
1da177e4 LT	24	#include <asm/fixmap.h>
1da177e4	25
1da177e4 LT	26	/*
	27	* ZERO_PAGE is a global shared page that is always zero: used
	28	* for zero-mapped memory areas etc..
	29	*/
26ff6c11	30	extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
1da177e4 LT	31	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	32
	33	#endif /* !__ASSEMBLY__ */
	34
36bcd39d PM	35	/*
	36	* Effective and physical address definitions, to aid with sign
	37	* extension.
	38	*/
	39	#define NEFF 32
	40	#define NEFF_SIGN (1LL << (NEFF - 1))
	41	#define NEFF_MASK (-1LL << NEFF)
	42
c7914834 PM	43	static inline unsigned long long neff_sign_extend(unsigned long val)
	44	{
	45	unsigned long long extended = val;
	46	return (extended & NEFF_SIGN) ? (extended \| NEFF_MASK) : extended;
	47	}
	48
36bcd39d PM	49	#ifdef CONFIG_29BIT
	50	#define NPHYS 29
	51	#else
	52	#define NPHYS 32
	53	#endif
	54
	55	#define NPHYS_SIGN (1LL << (NPHYS - 1))
	56	#define NPHYS_MASK (-1LL << NPHYS)
	57
db2e1fa3	58	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
1da177e4 LT	59	#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4 LT	60
21440cf0	61	/* Entries per level */
7a847f81	62	#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
21440cf0	63
d455a369	64	#define FIRST_USER_ADDRESS 0
1da177e4	65
1f69b6af MF	66	#define PHYS_ADDR_MASK29 0x1fffffff
	67	#define PHYS_ADDR_MASK32 0xffffffff
	68
1f69b6af MF	69	static inline unsigned long phys_addr_mask(void)
	70	{
	71	/* Is the MMU in 29bit mode? */
	72	if (__in_29bit_mode())
	73	return PHYS_ADDR_MASK29;
	74
	75	return PHYS_ADDR_MASK32;
	76	}
d02b08f6	77
1f69b6af	78	#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
cb700aa4	79	#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
1da177e4	80
0468b4bb	81	#ifdef CONFIG_SUPERH32
f0b859e3	82	#define VMALLOC_START (P3SEG)
0468b4bb PM	83	#else
	84	#define VMALLOC_START (0xf0000000)
	85	#endif
1da177e4 LT	86	#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
1da177e4 LT	87
249cfea9 PM	88	#if defined(CONFIG_SUPERH32)
249cfea9 PM	89	#include <asm/pgtable_32.h>
21440cf0	90	#else
249cfea9	91	#include <asm/pgtable_64.h>
1da177e4 LT	92	#endif
	93
	94	/*
21440cf0 PM	95	* SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
	96	* protection for execute, and considers it the same as a read. Also, write
	97	* permission implies read permission. This is the closest we can get..
	98	*
	99	* SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
	100	* not only supporting separate execute, read, and write bits, but having
	101	* completely separate permission bits for user and kernel space.
1da177e4	102	*/
21440cf0	103	/xwr/
1da177e4 LT	104	#define __P000 PAGE_NONE
	105	#define __P001 PAGE_READONLY
	106	#define __P010 PAGE_COPY
	107	#define __P011 PAGE_COPY
21440cf0 PM	108	#define __P100 PAGE_EXECREAD
21440cf0 PM	109	#define __P101 PAGE_EXECREAD
1da177e4 LT	110	#define __P110 PAGE_COPY
	111	#define __P111 PAGE_COPY
	112
	113	#define __S000 PAGE_NONE
	114	#define __S001 PAGE_READONLY
21440cf0	115	#define __S010 PAGE_WRITEONLY
1da177e4	116	#define __S011 PAGE_SHARED
21440cf0 PM	117	#define __S100 PAGE_EXECREAD
	118	#define __S101 PAGE_EXECREAD
	119	#define __S110 PAGE_RWX
	120	#define __S111 PAGE_RWX
1da177e4	121
1da177e4 LT	122	typedef pte_t *pte_addr_t;
1da177e4 LT	123
1da177e4 LT	124	#define kern_addr_valid(addr) (1)
1da177e4 LT	125
1da177e4 LT	126	#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
	127	remap_pfn_range(vma, vaddr, pfn, size, prot)
	128
249cfea9	129	#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
8c65b4a6	130
1da177e4	131	/*
2a5eacca	132	* Initialise the page table caches
1da177e4	133	*/
2a5eacca	134	extern void pgtable_cache_init(void);
1da177e4	135
249cfea9	136	struct vm_area_struct;
9cef7492 PM	137
	138	extern void __update_cache(struct vm_area_struct *vma,
	139	unsigned long address, pte_t pte);
	140	extern void __update_tlb(struct vm_area_struct *vma,
	141	unsigned long address, pte_t pte);
	142
	143	static inline void
4b3073e1	144	update_mmu_cache(struct vm_area_struct vma, unsigned long address, pte_t ptep)
9cef7492	145	{
4b3073e1	146	pte_t pte = *ptep;
9cef7492 PM	147	__update_cache(vma, address, pte);
	148	__update_tlb(vma, address, pte);
	149	}
	150
21440cf0 PM	151	extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
21440cf0 PM	152	extern void paging_init(void);
9acb98fb PM	153	extern void page_table_range_init(unsigned long start, unsigned long end,
9acb98fb PM	154	pgd_t *pgd);
21440cf0	155
ee1acbfa PM	156	/* arch/sh/mm/mmap.c */
	157	#define HAVE_ARCH_UNMAPPED_AREA
	158	#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
	159
a16382ce PM	160	#define __HAVE_ARCH_PTE_SPECIAL
a16382ce PM	161
1da177e4 LT	162	#include <asm-generic/pgtable.h>
1da177e4 LT	163
249cfea9	164	#endif /* __ASM_SH_PGTABLE_H */