[net-next-2.6.git] / arch / sh / include / asm / dma-sh.h

/*
 * arch/sh/include/asm/dma-sh.h
 *
 * Copyright (C) 2000  Takashi YOSHII
 * Copyright (C) 2003  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#ifndef __DMA_SH_H
#define __DMA_SH_H

#include <asm/dma.h>
#include <cpu/dma.h>

/* DMAOR contorl: The DMAOR access size is different by CPU.*/
#if defined(CONFIG_CPU_SUBTYPE_SH7723)	|| \
    defined(CONFIG_CPU_SUBTYPE_SH7724)	|| \
    defined(CONFIG_CPU_SUBTYPE_SH7780)	|| \
    defined(CONFIG_CPU_SUBTYPE_SH7785)
#define dmaor_read_reg(n) \
    (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
	: __raw_readw(SH_DMAC_BASE0 + DMAOR))
#define dmaor_write_reg(n, data) \
    (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
    : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
#else /* Other CPU */
#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
#endif

static int dmte_irq_map[] __maybe_unused = {
#if (MAX_DMA_CHANNELS >= 4)
    DMTE0_IRQ,
    DMTE0_IRQ + 1,
    DMTE0_IRQ + 2,
    DMTE0_IRQ + 3,
#endif
#if (MAX_DMA_CHANNELS >= 6)
    DMTE4_IRQ,
    DMTE4_IRQ + 1,
#endif
#if (MAX_DMA_CHANNELS >= 8)
    DMTE6_IRQ,
    DMTE6_IRQ + 1,
#endif
#if (MAX_DMA_CHANNELS >= 12)
    DMTE8_IRQ,
    DMTE9_IRQ,
    DMTE10_IRQ,
    DMTE11_IRQ,
#endif
};

/* Definitions for the SuperH DMAC */
#define REQ_L	0x00000000
#define REQ_E	0x00080000
#define RACK_H	0x00000000
#define RACK_L	0x00040000
#define ACK_R	0x00000000
#define ACK_W	0x00020000
#define ACK_H	0x00000000
#define ACK_L	0x00010000
#define DM_INC	0x00004000
#define DM_DEC	0x00008000
#define DM_FIX	0x0000c000
#define SM_INC	0x00001000
#define SM_DEC	0x00002000
#define SM_FIX	0x00003000
#define RS_IN	0x00000200
#define RS_OUT	0x00000300
#define TS_BLK	0x00000040
#define TM_BUR	0x00000020
#define CHCR_DE 0x00000001
#define CHCR_TE 0x00000002
#define CHCR_IE 0x00000004

/* DMAOR definitions */
#define DMAOR_AE	0x00000004
#define DMAOR_NMIF	0x00000002
#define DMAOR_DME	0x00000001

/*
 * Define the default configuration for dual address memory-memory transfer.
 * The 0x400 value represents auto-request, external->external.
 */
#define RS_DUAL	(DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))

/* DMA base address */
static u32 dma_base_addr[] __maybe_unused = {
#if (MAX_DMA_CHANNELS >= 4)
	SH_DMAC_BASE0 + 0x00,	/* channel 0 */
	SH_DMAC_BASE0 + 0x10,
	SH_DMAC_BASE0 + 0x20,
	SH_DMAC_BASE0 + 0x30,
#endif
#if (MAX_DMA_CHANNELS >= 6)
	SH_DMAC_BASE0 + 0x50,
	SH_DMAC_BASE0 + 0x60,
#endif
#if (MAX_DMA_CHANNELS >= 8)
	SH_DMAC_BASE1 + 0x00,
	SH_DMAC_BASE1 + 0x10,
#endif
#if (MAX_DMA_CHANNELS >= 12)
	SH_DMAC_BASE1 + 0x20,
	SH_DMAC_BASE1 + 0x30,
	SH_DMAC_BASE1 + 0x50,
	SH_DMAC_BASE1 + 0x60, /* channel 11 */
#endif
};

/* DMA register */
#define SAR     0x00
#define DAR     0x04
#define TCR     0x08
#define CHCR    0x0C
#define DMAOR	0x40

/*
 * for dma engine
 *
 * SuperH DMA mode
 */
#define SHDMA_MIX_IRQ	(1 << 1)
#define SHDMA_DMAOR1	(1 << 2)
#define SHDMA_DMAE1	(1 << 3)

enum sh_dmae_slave_chan_id {
	SHDMA_SLAVE_SCIF0_TX,
	SHDMA_SLAVE_SCIF0_RX,
	SHDMA_SLAVE_SCIF1_TX,
	SHDMA_SLAVE_SCIF1_RX,
	SHDMA_SLAVE_SCIF2_TX,
	SHDMA_SLAVE_SCIF2_RX,
	SHDMA_SLAVE_SCIF3_TX,
	SHDMA_SLAVE_SCIF3_RX,
	SHDMA_SLAVE_SCIF4_TX,
	SHDMA_SLAVE_SCIF4_RX,
	SHDMA_SLAVE_SCIF5_TX,
	SHDMA_SLAVE_SCIF5_RX,
	SHDMA_SLAVE_SIUA_TX,
	SHDMA_SLAVE_SIUA_RX,
	SHDMA_SLAVE_SIUB_TX,
	SHDMA_SLAVE_SIUB_RX,
	SHDMA_SLAVE_NUMBER,	/* Must stay last */
};

struct sh_dmae_slave_config {
	enum sh_dmae_slave_chan_id	slave_id;
	dma_addr_t			addr;
	u32				chcr;
	char				mid_rid;
};

struct sh_dmae_channel {
	unsigned int	offset;
	unsigned int	dmars;
	unsigned int	dmars_bit;
};

struct sh_dmae_pdata {
	struct sh_dmae_slave_config *slave;
	int slave_num;
	struct sh_dmae_channel *channel;
	int channel_num;
};

struct device;

struct sh_dmae_slave {
	enum sh_dmae_slave_chan_id	slave_id; /* Set by the platform */
	struct device			*dma_dev; /* Set by the platform */
	struct sh_dmae_slave_config	*config;  /* Set by the driver */
};

#endif /* __DMA_SH_H */
Commit	Line	Data
71b973a4 NI	1	/*
	2	* arch/sh/include/asm/dma-sh.h
	3	*
	4	* Copyright (C) 2000 Takashi YOSHII
	5	* Copyright (C) 2003 Paul Mundt
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11	#ifndef __DMA_SH_H
	12	#define __DMA_SH_H
	13
039a718e	14	#include <asm/dma.h>
71b973a4 NI	15	#include <cpu/dma.h>
	16
	17	/* DMAOR contorl: The DMAOR access size is different by CPU.*/
	18	#if defined(CONFIG_CPU_SUBTYPE_SH7723) \|\| \
edc67b29	19	defined(CONFIG_CPU_SUBTYPE_SH7724) \|\| \
71b973a4 NI	20	defined(CONFIG_CPU_SUBTYPE_SH7780) \|\| \
	21	defined(CONFIG_CPU_SUBTYPE_SH7785)
	22	#define dmaor_read_reg(n) \
9d56dd3b PM	23	(n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
9d56dd3b PM	24	: __raw_readw(SH_DMAC_BASE0 + DMAOR))
71b973a4	25	#define dmaor_write_reg(n, data) \
9d56dd3b PM	26	(n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
9d56dd3b PM	27	: __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
71b973a4	28	#else /* Other CPU */
9d56dd3b PM	29	#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
9d56dd3b PM	30	#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
71b973a4 NI	31	#endif
	32
	33	static int dmte_irq_map[] __maybe_unused = {
039a718e	34	#if (MAX_DMA_CHANNELS >= 4)
71b973a4 NI	35	DMTE0_IRQ,
	36	DMTE0_IRQ + 1,
	37	DMTE0_IRQ + 2,
	38	DMTE0_IRQ + 3,
	39	#endif
039a718e	40	#if (MAX_DMA_CHANNELS >= 6)
71b973a4 NI	41	DMTE4_IRQ,
	42	DMTE4_IRQ + 1,
	43	#endif
039a718e	44	#if (MAX_DMA_CHANNELS >= 8)
71b973a4 NI	45	DMTE6_IRQ,
	46	DMTE6_IRQ + 1,
	47	#endif
039a718e	48	#if (MAX_DMA_CHANNELS >= 12)
71b973a4 NI	49	DMTE8_IRQ,
	50	DMTE9_IRQ,
	51	DMTE10_IRQ,
	52	DMTE11_IRQ,
	53	#endif
	54	};
	55
	56	/* Definitions for the SuperH DMAC */
	57	#define REQ_L 0x00000000
	58	#define REQ_E 0x00080000
	59	#define RACK_H 0x00000000
	60	#define RACK_L 0x00040000
	61	#define ACK_R 0x00000000
	62	#define ACK_W 0x00020000
	63	#define ACK_H 0x00000000
	64	#define ACK_L 0x00010000
	65	#define DM_INC 0x00004000
	66	#define DM_DEC 0x00008000
cfefe997	67	#define DM_FIX 0x0000c000
71b973a4 NI	68	#define SM_INC 0x00001000
71b973a4 NI	69	#define SM_DEC 0x00002000
cfefe997	70	#define SM_FIX 0x00003000
71b973a4 NI	71	#define RS_IN 0x00000200
	72	#define RS_OUT 0x00000300
	73	#define TS_BLK 0x00000040
	74	#define TM_BUR 0x00000020
	75	#define CHCR_DE 0x00000001
	76	#define CHCR_TE 0x00000002
	77	#define CHCR_IE 0x00000004
	78
	79	/* DMAOR definitions */
	80	#define DMAOR_AE 0x00000004
	81	#define DMAOR_NMIF 0x00000002
	82	#define DMAOR_DME 0x00000001
	83
	84	/*
	85	* Define the default configuration for dual address memory-memory transfer.
	86	* The 0x400 value represents auto-request, external->external.
	87	*/
623b4ac4	88	#define RS_DUAL (DM_INC \| SM_INC \| 0x400 \| TS_INDEX2VAL(XMIT_SZ_32BIT))
71b973a4 NI	89
	90	/* DMA base address */
	91	static u32 dma_base_addr[] __maybe_unused = {
039a718e	92	#if (MAX_DMA_CHANNELS >= 4)
71b973a4 NI	93	SH_DMAC_BASE0 + 0x00, /* channel 0 */
	94	SH_DMAC_BASE0 + 0x10,
	95	SH_DMAC_BASE0 + 0x20,
	96	SH_DMAC_BASE0 + 0x30,
	97	#endif
039a718e	98	#if (MAX_DMA_CHANNELS >= 6)
71b973a4 NI	99	SH_DMAC_BASE0 + 0x50,
	100	SH_DMAC_BASE0 + 0x60,
	101	#endif
039a718e	102	#if (MAX_DMA_CHANNELS >= 8)
71b973a4 NI	103	SH_DMAC_BASE1 + 0x00,
	104	SH_DMAC_BASE1 + 0x10,
	105	#endif
039a718e	106	#if (MAX_DMA_CHANNELS >= 12)
71b973a4 NI	107	SH_DMAC_BASE1 + 0x20,
	108	SH_DMAC_BASE1 + 0x30,
	109	SH_DMAC_BASE1 + 0x50,
	110	SH_DMAC_BASE1 + 0x60, /* channel 11 */
	111	#endif
	112	};
	113
	114	/* DMA register */
	115	#define SAR 0x00
	116	#define DAR 0x04
	117	#define TCR 0x08
	118	#define CHCR 0x0C
	119	#define DMAOR 0x40
	120
d8902adc NI	121	/*
	122	* for dma engine
	123	*
	124	* SuperH DMA mode
	125	*/
	126	#define SHDMA_MIX_IRQ (1 << 1)
	127	#define SHDMA_DMAOR1 (1 << 2)
cfefe997 GL	128	#define SHDMA_DMAE1 (1 << 3)
	129
	130	enum sh_dmae_slave_chan_id {
	131	SHDMA_SLAVE_SCIF0_TX,
	132	SHDMA_SLAVE_SCIF0_RX,
	133	SHDMA_SLAVE_SCIF1_TX,
	134	SHDMA_SLAVE_SCIF1_RX,
	135	SHDMA_SLAVE_SCIF2_TX,
	136	SHDMA_SLAVE_SCIF2_RX,
	137	SHDMA_SLAVE_SCIF3_TX,
	138	SHDMA_SLAVE_SCIF3_RX,
	139	SHDMA_SLAVE_SCIF4_TX,
	140	SHDMA_SLAVE_SCIF4_RX,
	141	SHDMA_SLAVE_SCIF5_TX,
	142	SHDMA_SLAVE_SCIF5_RX,
	143	SHDMA_SLAVE_SIUA_TX,
	144	SHDMA_SLAVE_SIUA_RX,
	145	SHDMA_SLAVE_SIUB_TX,
	146	SHDMA_SLAVE_SIUB_RX,
	147	SHDMA_SLAVE_NUMBER, /* Must stay last */
	148	};
	149
	150	struct sh_dmae_slave_config {
	151	enum sh_dmae_slave_chan_id slave_id;
	152	dma_addr_t addr;
	153	u32 chcr;
	154	char mid_rid;
	155	};
d8902adc	156
027811b9 GL	157	struct sh_dmae_channel {
	158	unsigned int offset;
	159	unsigned int dmars;
	160	unsigned int dmars_bit;
	161	};
	162
d8902adc	163	struct sh_dmae_pdata {
027811b9 GL	164	struct sh_dmae_slave_config *slave;
	165	int slave_num;
	166	struct sh_dmae_channel *channel;
	167	int channel_num;
cfefe997 GL	168	};
	169
	170	struct device;
	171
	172	struct sh_dmae_slave {
	173	enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
	174	struct device dma_dev; / Set by the platform */
	175	struct sh_dmae_slave_config config; / Set by the driver */
d8902adc NI	176	};
d8902adc NI	177
71b973a4	178	#endif /* __DMA_SH_H */