[net-next-2.6.git] / arch / sh / drivers / pci / pcie-sh7786.c

/*
 * Low-Level PCI Express Support for the SH7786
 *
 *  Copyright (C) 2009 - 2010  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include "pcie-sh7786.h"
#include <asm/sizes.h>

struct sh7786_pcie_port {
	struct pci_channel	*hose;
	unsigned int		index;
	int			endpoint;
	int			link;
};

static struct sh7786_pcie_port *sh7786_pcie_ports;
static unsigned int nr_ports;

static struct sh7786_pcie_hwops {
	int (*core_init)(void);
	int (*port_init_hw)(struct sh7786_pcie_port *port);
} *sh7786_pcie_hwops;

static struct resource sh7786_pci0_resources[] = {
	{
		.name	= "PCIe0 IO",
		.start	= 0xfd000000,
		.end	= 0xfd000000 + SZ_8M - 1,
		.flags	= IORESOURCE_IO,
	}, {
		.name	= "PCIe0 MEM 0",
		.start	= 0xc0000000,
		.end	= 0xc0000000 + SZ_512M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe0 MEM 1",
		.start	= 0x10000000,
		.end	= 0x10000000 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "PCIe0 MEM 2",
		.start	= 0xfe100000,
		.end	= 0xfe100000 + SZ_1M - 1,
	},
};

static struct resource sh7786_pci1_resources[] = {
	{
		.name	= "PCIe1 IO",
		.start	= 0xfd800000,
		.end	= 0xfd800000 + SZ_8M - 1,
		.flags	= IORESOURCE_IO,
	}, {
		.name	= "PCIe1 MEM 0",
		.start	= 0xa0000000,
		.end	= 0xa0000000 + SZ_512M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe1 MEM 1",
		.start	= 0x30000000,
		.end	= 0x30000000 + SZ_256M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe1 MEM 2",
		.start	= 0xfe300000,
		.end	= 0xfe300000 + SZ_1M - 1,
	},
};

static struct resource sh7786_pci2_resources[] = {
	{
		.name	= "PCIe2 IO",
		.start	= 0xfc800000,
		.end	= 0xfc800000 + SZ_4M - 1,
		.flags	= IORESOURCE_IO,
	}, {
		.name	= "PCIe2 MEM 0",
		.start	= 0x80000000,
		.end	= 0x80000000 + SZ_512M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe2 MEM 1",
		.start	= 0x20000000,
		.end	= 0x20000000 + SZ_256M - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
	}, {
		.name	= "PCIe2 MEM 2",
		.start	= 0xfcd00000,
		.end	= 0xfcd00000 + SZ_1M - 1,
	},
};

extern struct pci_ops sh7786_pci_ops;

#define DEFINE_CONTROLLER(start, idx)					\
{									\
	.pci_ops	= &sh7786_pci_ops,				\
	.resources	= sh7786_pci##idx##_resources,			\
	.nr_resources	= ARRAY_SIZE(sh7786_pci##idx##_resources),	\
	.reg_base	= start,					\
	.mem_offset	= 0,						\
	.io_offset	= 0,						\
}

static struct pci_channel sh7786_pci_channels[] = {
	DEFINE_CONTROLLER(0xfe000000, 0),
	DEFINE_CONTROLLER(0xfe200000, 1),
	DEFINE_CONTROLLER(0xfcc00000, 2),
};

static int phy_wait_for_ack(struct pci_channel *chan)
{
	unsigned int timeout = 100;

	while (timeout--) {
		if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
			return 0;

		udelay(100);
	}

	return -ETIMEDOUT;
}

static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
{
	unsigned int timeout = 100;

	while (timeout--) {
		if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
			return 0;

		udelay(100);
	}

	return -ETIMEDOUT;
}

static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
			  unsigned int lane, unsigned int data)
{
	unsigned long phyaddr;

	phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
			((addr & 0xff) << BITS_ADR);

	/* Set write data */
	pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
	pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);

	phy_wait_for_ack(chan);

	/* Clear command */
	pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
	pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);

	phy_wait_for_ack(chan);
}

static int phy_init(struct pci_channel *chan)
{
	unsigned long ctrl;
	unsigned int timeout = 100;

	/* Enable clock */
	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	ctrl |= (1 << BITS_CKE);
	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);

	/* Initialize the phy */
	phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
	phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
	phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
	phy_write_reg(chan, 0x65, 0xf, 0x09070907);
	phy_write_reg(chan, 0x66, 0xf, 0x00000010);
	phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
	phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
	phy_write_reg(chan, 0xb0, 0xf, 0x00000610);

	/* Deassert Standby */
	phy_write_reg(chan, 0x67, 0x1, 0x00000400);

	/* Disable clock */
	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	ctrl &= ~(1 << BITS_CKE);
	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);

	while (timeout--) {
		if (pci_read_reg(chan, SH4A_PCIEPHYSR))
			return 0;

		udelay(100);
	}

	return -ETIMEDOUT;
}

static void pcie_reset(struct sh7786_pcie_port *port)
{
	struct pci_channel *chan = port->hose;

	pci_write_reg(chan, 1, SH4A_PCIESRSTR);
	pci_write_reg(chan, 0, SH4A_PCIETCTLR);
	pci_write_reg(chan, 0, SH4A_PCIESRSTR);
	pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
}

static int pcie_init(struct sh7786_pcie_port *port)
{
	struct pci_channel *chan = port->hose;
	unsigned int data;
	phys_addr_t memphys;
	size_t memsize;
	int ret, i, win;

	/* Begin initialization */
	pcie_reset(port);

	/* Initialize as type1. */
	data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
	data &= ~(0x7f << 16);
	data |= PCI_HEADER_TYPE_BRIDGE << 16;
	pci_write_reg(chan, data, SH4A_PCIEPCICONF3);

	/* Initialize default capabilities. */
	data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
	data &= ~(PCI_EXP_FLAGS_TYPE << 16);

	if (port->endpoint)
		data |= PCI_EXP_TYPE_ENDPOINT << 20;
	else
		data |= PCI_EXP_TYPE_ROOT_PORT << 20;

	data |= PCI_CAP_ID_EXP;
	pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);

	/* Enable data link layer active state reporting */
	pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);

	/* Enable extended sync and ASPM L0s support */
	data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
	data &= ~PCI_EXP_LNKCTL_ASPMC;
	data |= PCI_EXP_LNKCTL_ES | 1;
	pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);

	/* Write out the physical slot number */
	data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
	data &= ~PCI_EXP_SLTCAP_PSN;
	data |= (port->index + 1) << 19;
	pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);

	/* Set the completion timer timeout to the maximum 32ms. */
	data = pci_read_reg(chan, SH4A_PCIETLCTLR);
	data &= ~0x3f00;
	data |= 0x32 << 8;
	pci_write_reg(chan, data, SH4A_PCIETLCTLR);

	/*
	 * Set fast training sequences to the maximum 255,
	 * and enable MAC data scrambling.
	 */
	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	data &= ~PCIEMACCTLR_SCR_DIS;
	data |= (0xff << 16);
	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);

	memphys = __pa(memory_start);
	memsize = roundup_pow_of_two(memory_end - memory_start);

	/*
	 * If there's more than 512MB of memory, we need to roll over to
	 * LAR1/LAMR1.
	 */
	if (memsize > SZ_512M) {
		__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
		__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
			     chan->reg_base + SH4A_PCIELAMR1);
		memsize = SZ_512M;
	} else {
		/*
		 * Otherwise just zero it out and disable it.
		 */
		__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
		__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
	}

	/*
	 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
	 * cover all of lowmem on most platforms.
	 */
	__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
	__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);

	__raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
	__raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);

	/* Finish initialization */
	data = pci_read_reg(chan, SH4A_PCIETCTLR);
	data |= 0x1;
	pci_write_reg(chan, data, SH4A_PCIETCTLR);

	/* Enable DL_Active Interrupt generation */
	data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
	data |= PCIEDLINTENR_DLL_ACT_ENABLE;
	pci_write_reg(chan, data, SH4A_PCIEDLINTENR);

	/* Disable MAC data scrambling. */
	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);

	ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
	if (unlikely(ret != 0))
		return -ENODEV;

	data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
	data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
	data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
		(PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
	pci_write_reg(chan, data, SH4A_PCIEPCICONF1);

	pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
	pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);

	wmb();

	data = pci_read_reg(chan, SH4A_PCIEMACSR);
	printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
	       port->index, (data >> 20) & 0x3f);

	for (i = win = 0; i < chan->nr_resources; i++) {
		struct resource *res = chan->resources + i;
		resource_size_t size;
		u32 enable_mask;

		/*
		 * We can't use the 32-bit mode windows in legacy 29-bit
		 * mode, so just skip them entirely.
		 */
		if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
			continue;

		pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));

		size = resource_size(res);

		/*
		 * The PAMR mask is calculated in units of 256kB, which
		 * keeps things pretty simple.
		 */
		__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
			     chan->reg_base + SH4A_PCIEPAMR(win));

		pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
		pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));

		enable_mask = MASK_PARE;
		if (res->flags & IORESOURCE_IO)
			enable_mask |= MASK_SPC;

		pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));

		win++;
	}

	return 0;
}

int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
        return 71;
}

static int sh7786_pcie_core_init(void)
{
	/* Return the number of ports */
	return test_mode_pin(MODE_PIN12) ? 3 : 2;
}

static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
{
	int ret;

	ret = phy_init(port->hose);
	if (unlikely(ret < 0))
		return ret;

	/*
	 * Check if we are configured in endpoint or root complex mode,
	 * this is a fixed pin setting that applies to all PCIe ports.
	 */
	port->endpoint = test_mode_pin(MODE_PIN11);

	ret = pcie_init(port);
	if (unlikely(ret < 0))
		return ret;

	return register_pci_controller(port->hose);
}

static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
	.core_init	= sh7786_pcie_core_init,
	.port_init_hw	= sh7786_pcie_init_hw,
};

static int __init sh7786_pcie_init(void)
{
	int ret = 0, i;

	printk(KERN_NOTICE "PCI: Starting intialization.\n");

	sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;

	nr_ports = sh7786_pcie_hwops->core_init();
	BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));

	if (unlikely(nr_ports == 0))
		return -ENODEV;

	sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
				    GFP_KERNEL);
	if (unlikely(!sh7786_pcie_ports))
		return -ENOMEM;

	printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);

	for (i = 0; i < nr_ports; i++) {
		struct sh7786_pcie_port *port = sh7786_pcie_ports + i;

		port->index		= i;
		port->hose		= sh7786_pci_channels + i;
		port->hose->io_map_base	= port->hose->resources[0].start;

		ret |= sh7786_pcie_hwops->port_init_hw(port);
	}

	if (unlikely(ret))
		return ret;

	return 0;
}
arch_initcall(sh7786_pcie_init);
Commit	Line	Data
5713e602 PM	1	/*
	2	* Low-Level PCI Express Support for the SH7786
	3	*
7561f2dd	4	* Copyright (C) 2009 - 2010 Paul Mundt
5713e602 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/pci.h>
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/io.h>
	14	#include <linux/delay.h>
5a0e3ad6	15	#include <linux/slab.h>
5713e602 PM	16	#include "pcie-sh7786.h"
	17	#include <asm/sizes.h>
	18
	19	struct sh7786_pcie_port {
	20	struct pci_channel *hose;
	21	unsigned int index;
	22	int endpoint;
	23	int link;
	24	};
	25
	26	static struct sh7786_pcie_port *sh7786_pcie_ports;
	27	static unsigned int nr_ports;
	28
	29	static struct sh7786_pcie_hwops {
	30	int (*core_init)(void);
	31	int (port_init_hw)(struct sh7786_pcie_port port);
	32	} *sh7786_pcie_hwops;
	33
7561f2dd	34	static struct resource sh7786_pci0_resources[] = {
5713e602	35	{
7561f2dd PM	36	.name = "PCIe0 IO",
	37	.start = 0xfd000000,
	38	.end = 0xfd000000 + SZ_8M - 1,
	39	.flags = IORESOURCE_IO,
5713e602	40	}, {
7561f2dd PM	41	.name = "PCIe0 MEM 0",
	42	.start = 0xc0000000,
	43	.end = 0xc0000000 + SZ_512M - 1,
	44	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
5713e602	45	}, {
7561f2dd PM	46	.name = "PCIe0 MEM 1",
	47	.start = 0x10000000,
	48	.end = 0x10000000 + SZ_64M - 1,
5713e602	49	.flags = IORESOURCE_MEM,
7561f2dd PM	50	}, {
	51	.name = "PCIe0 MEM 2",
	52	.start = 0xfe100000,
	53	.end = 0xfe100000 + SZ_1M - 1,
5713e602 PM	54	},
	55	};
	56
7561f2dd PM	57	static struct resource sh7786_pci1_resources[] = {
	58	{
	59	.name = "PCIe1 IO",
	60	.start = 0xfd800000,
	61	.end = 0xfd800000 + SZ_8M - 1,
	62	.flags = IORESOURCE_IO,
	63	}, {
	64	.name = "PCIe1 MEM 0",
	65	.start = 0xa0000000,
	66	.end = 0xa0000000 + SZ_512M - 1,
	67	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	68	}, {
	69	.name = "PCIe1 MEM 1",
	70	.start = 0x30000000,
	71	.end = 0x30000000 + SZ_256M - 1,
	72	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	73	}, {
	74	.name = "PCIe1 MEM 2",
	75	.start = 0xfe300000,
	76	.end = 0xfe300000 + SZ_1M - 1,
	77	},
5713e602 PM	78	};
5713e602 PM	79
7561f2dd	80	static struct resource sh7786_pci2_resources[] = {
5713e602	81	{
7561f2dd PM	82	.name = "PCIe2 IO",
	83	.start = 0xfc800000,
	84	.end = 0xfc800000 + SZ_4M - 1,
f0485193	85	.flags = IORESOURCE_IO,
5713e602	86	}, {
7561f2dd PM	87	.name = "PCIe2 MEM 0",
	88	.start = 0x80000000,
	89	.end = 0x80000000 + SZ_512M - 1,
	90	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
5713e602	91	}, {
7561f2dd PM	92	.name = "PCIe2 MEM 1",
	93	.start = 0x20000000,
	94	.end = 0x20000000 + SZ_256M - 1,
	95	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_32BIT,
	96	}, {
	97	.name = "PCIe2 MEM 2",
	98	.start = 0xfcd00000,
	99	.end = 0xfcd00000 + SZ_1M - 1,
5713e602 PM	100	},
	101	};
	102
	103	extern struct pci_ops sh7786_pci_ops;
	104
7561f2dd PM	105	#define DEFINE_CONTROLLER(start, idx) \
	106	{ \
	107	.pci_ops = &sh7786_pci_ops, \
	108	.resources = sh7786_pci##idx##_resources, \
	109	.nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
	110	.reg_base = start, \
	111	.mem_offset = 0, \
	112	.io_offset = 0, \
5713e602 PM	113	}
	114
	115	static struct pci_channel sh7786_pci_channels[] = {
	116	DEFINE_CONTROLLER(0xfe000000, 0),
	117	DEFINE_CONTROLLER(0xfe200000, 1),
	118	DEFINE_CONTROLLER(0xfcc00000, 2),
	119	};
	120
	121	static int phy_wait_for_ack(struct pci_channel *chan)
	122	{
	123	unsigned int timeout = 100;
	124
	125	while (timeout--) {
	126	if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
	127	return 0;
	128
	129	udelay(100);
	130	}
	131
	132	return -ETIMEDOUT;
	133	}
	134
	135	static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
	136	{
	137	unsigned int timeout = 100;
	138
	139	while (timeout--) {
	140	if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
	141	return 0;
	142
	143	udelay(100);
	144	}
	145
	146	return -ETIMEDOUT;
	147	}
	148
	149	static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
	150	unsigned int lane, unsigned int data)
	151	{
53178d71	152	unsigned long phyaddr;
5713e602 PM	153
	154	phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
	155	((addr & 0xff) << BITS_ADR);
	156
5713e602 PM	157	/* Set write data */
	158	pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
	159	pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
	160
	161	phy_wait_for_ack(chan);
	162
	163	/* Clear command */
53178d71	164	pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
5713e602 PM	165	pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
	166
	167	phy_wait_for_ack(chan);
5713e602 PM	168	}
	169
	170	static int phy_init(struct pci_channel *chan)
	171	{
53178d71	172	unsigned long ctrl;
5713e602 PM	173	unsigned int timeout = 100;
5713e602 PM	174
53178d71 PM	175	/* Enable clock */
	176	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	177	ctrl \|= (1 << BITS_CKE);
	178	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
	179
5713e602 PM	180	/* Initialize the phy */
	181	phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
	182	phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
	183	phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
	184	phy_write_reg(chan, 0x65, 0xf, 0x09070907);
	185	phy_write_reg(chan, 0x66, 0xf, 0x00000010);
	186	phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
	187	phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
53178d71	188	phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
5713e602 PM	189
5713e602 PM	190	/* Deassert Standby */
53178d71 PM	191	phy_write_reg(chan, 0x67, 0x1, 0x00000400);
	192
	193	/* Disable clock */
	194	ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
	195	ctrl &= ~(1 << BITS_CKE);
	196	pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
5713e602 PM	197
	198	while (timeout--) {
	199	if (pci_read_reg(chan, SH4A_PCIEPHYSR))
	200	return 0;
	201
	202	udelay(100);
	203	}
	204
	205	return -ETIMEDOUT;
	206	}
	207
2dbfa1e3 PM	208	static void pcie_reset(struct sh7786_pcie_port *port)
	209	{
	210	struct pci_channel *chan = port->hose;
	211
	212	pci_write_reg(chan, 1, SH4A_PCIESRSTR);
	213	pci_write_reg(chan, 0, SH4A_PCIETCTLR);
	214	pci_write_reg(chan, 0, SH4A_PCIESRSTR);
	215	pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
	216	}
	217
5713e602 PM	218	static int pcie_init(struct sh7786_pcie_port *port)
	219	{
	220	struct pci_channel *chan = port->hose;
	221	unsigned int data;
7578a4c6 PM	222	phys_addr_t memphys;
7578a4c6 PM	223	size_t memsize;
da03a63a	224	int ret, i, win;
5713e602 PM	225
5713e602 PM	226	/* Begin initialization */
2dbfa1e3	227	pcie_reset(port);
5713e602 PM	228
	229	/* Initialize as type1. */
	230	data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
	231	data &= ~(0x7f << 16);
	232	data \|= PCI_HEADER_TYPE_BRIDGE << 16;
	233	pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
	234
	235	/* Initialize default capabilities. */
	236	data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
	237	data &= ~(PCI_EXP_FLAGS_TYPE << 16);
	238
	239	if (port->endpoint)
	240	data \|= PCI_EXP_TYPE_ENDPOINT << 20;
	241	else
	242	data \|= PCI_EXP_TYPE_ROOT_PORT << 20;
	243
	244	data \|= PCI_CAP_ID_EXP;
	245	pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
	246
7578a4c6 PM	247	/* Enable data link layer active state reporting */
	248	pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
	249
	250	/* Enable extended sync and ASPM L0s support */
5713e602	251	data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
7578a4c6 PM	252	data &= ~PCI_EXP_LNKCTL_ASPMC;
7578a4c6 PM	253	data \|= PCI_EXP_LNKCTL_ES \| 1;
5713e602 PM	254	pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
5713e602 PM	255
7578a4c6 PM	256	/* Write out the physical slot number */
	257	data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
	258	data &= ~PCI_EXP_SLTCAP_PSN;
	259	data \|= (port->index + 1) << 19;
	260	pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
	261
5713e602 PM	262	/* Set the completion timer timeout to the maximum 32ms. */
5713e602 PM	263	data = pci_read_reg(chan, SH4A_PCIETLCTLR);
7578a4c6	264	data &= ~0x3f00;
5713e602 PM	265	data \|= 0x32 << 8;
	266	pci_write_reg(chan, data, SH4A_PCIETLCTLR);
	267
	268	/*
	269	* Set fast training sequences to the maximum 255,
	270	* and enable MAC data scrambling.
	271	*/
	272	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	273	data &= ~PCIEMACCTLR_SCR_DIS;
	274	data \|= (0xff << 16);
	275	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
	276
7578a4c6 PM	277	memphys = __pa(memory_start);
	278	memsize = roundup_pow_of_two(memory_end - memory_start);
	279
	280	/*
	281	* If there's more than 512MB of memory, we need to roll over to
	282	* LAR1/LAMR1.
	283	*/
	284	if (memsize > SZ_512M) {
	285	__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
	286	__raw_writel(((memsize - SZ_512M) - SZ_256) \| 1,
	287	chan->reg_base + SH4A_PCIELAMR1);
	288	memsize = SZ_512M;
	289	} else {
	290	/*
	291	* Otherwise just zero it out and disable it.
	292	*/
	293	__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
	294	__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
	295	}
	296
	297	/*
	298	* LAR0/LAMR0 covers up to the first 512MB, which is enough to
	299	* cover all of lowmem on most platforms.
	300	*/
	301	__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
	302	__raw_writel((memsize - SZ_256) \| 1, chan->reg_base + SH4A_PCIELAMR0);
	303
53178d71 PM	304	__raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
	305	__raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
	306
5713e602 PM	307	/* Finish initialization */
	308	data = pci_read_reg(chan, SH4A_PCIETCTLR);
	309	data \|= 0x1;
	310	pci_write_reg(chan, data, SH4A_PCIETCTLR);
	311
	312	/* Enable DL_Active Interrupt generation */
	313	data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
	314	data \|= PCIEDLINTENR_DLL_ACT_ENABLE;
	315	pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
	316
	317	/* Disable MAC data scrambling. */
	318	data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
	319	data \|= PCIEMACCTLR_SCR_DIS \| (0xff << 16);
	320	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
	321
	322	ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
	323	if (unlikely(ret != 0))
	324	return -ENODEV;
	325
7578a4c6 PM	326	data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
	327	data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
	328	data \|= PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \|
	329	(PCI_STATUS_CAP_LIST \| PCI_STATUS_DEVSEL_FAST) << 16;
	330	pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
	331
5713e602 PM	332	pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
5713e602 PM	333	pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
5713e602 PM	334
	335	wmb();
	336
	337	data = pci_read_reg(chan, SH4A_PCIEMACSR);
	338	printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
	339	port->index, (data >> 20) & 0x3f);
	340
da03a63a	341	for (i = win = 0; i < chan->nr_resources; i++) {
7578a4c6 PM	342	struct resource *res = chan->resources + i;
	343	resource_size_t size;
	344	u32 enable_mask;
	345
da03a63a PM	346	/*
	347	* We can't use the 32-bit mode windows in legacy 29-bit
	348	* mode, so just skip them entirely.
	349	*/
	350	if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
	351	continue;
	352
	353	pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
7578a4c6 PM	354
	355	size = resource_size(res);
	356
	357	/*
	358	* The PAMR mask is calculated in units of 256kB, which
	359	* keeps things pretty simple.
	360	*/
	361	__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
da03a63a	362	chan->reg_base + SH4A_PCIEPAMR(win));
7578a4c6	363
da03a63a PM	364	pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
da03a63a PM	365	pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
7578a4c6 PM	366
	367	enable_mask = MASK_PARE;
	368	if (res->flags & IORESOURCE_IO)
	369	enable_mask \|= MASK_SPC;
	370
da03a63a PM	371	pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
	372
	373	win++;
7578a4c6	374	}
5713e602 PM	375
	376	return 0;
	377	}
	378
	379	int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
	380	{
	381	return 71;
	382	}
	383
	384	static int sh7786_pcie_core_init(void)
	385	{
	386	/* Return the number of ports */
	387	return test_mode_pin(MODE_PIN12) ? 3 : 2;
	388	}
	389
	390	static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
	391	{
	392	int ret;
	393
	394	ret = phy_init(port->hose);
	395	if (unlikely(ret < 0))
	396	return ret;
	397
	398	/*
	399	* Check if we are configured in endpoint or root complex mode,
	400	* this is a fixed pin setting that applies to all PCIe ports.
	401	*/
	402	port->endpoint = test_mode_pin(MODE_PIN11);
	403
	404	ret = pcie_init(port);
	405	if (unlikely(ret < 0))
	406	return ret;
	407
bcf39352	408	return register_pci_controller(port->hose);
5713e602 PM	409	}
	410
	411	static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
	412	.core_init = sh7786_pcie_core_init,
	413	.port_init_hw = sh7786_pcie_init_hw,
	414	};
	415
	416	static int __init sh7786_pcie_init(void)
	417	{
	418	int ret = 0, i;
	419
	420	printk(KERN_NOTICE "PCI: Starting intialization.\n");
	421
	422	sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
	423
	424	nr_ports = sh7786_pcie_hwops->core_init();
	425	BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
	426
	427	if (unlikely(nr_ports == 0))
	428	return -ENODEV;
	429
	430	sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
	431	GFP_KERNEL);
	432	if (unlikely(!sh7786_pcie_ports))
	433	return -ENOMEM;
	434
	435	printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
	436
	437	for (i = 0; i < nr_ports; i++) {
	438	struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
	439
	440	port->index = i;
	441	port->hose = sh7786_pci_channels + i;
7561f2dd	442	port->hose->io_map_base = port->hose->resources[0].start;
5713e602 PM	443
	444	ret \|= sh7786_pcie_hwops->port_init_hw(port);
	445	}
	446
	447	if (unlikely(ret))
	448	return ret;
	449
	450	return 0;
	451	}
	452	arch_initcall(sh7786_pcie_init);